diff --git a/design_introspection-plugin/get_cells.cc b/design_introspection-plugin/get_cells.cc
index 3cdc0b4..ba414de 100644
--- a/design_introspection-plugin/get_cells.cc
+++ b/design_introspection-plugin/get_cells.cc
@@ -19,11 +19,11 @@
 		}
 	    }
 	    std::string object_name(RTLIL::unescape_id(cell->name));
-	    if (!args.is_quiet) {
-		log("%s ", object_name.c_str());
-	    }
 	    selected_objects.push_back(object_name);
 	}
     }
+    if (selected_objects.size() == 0 and !args.is_quiet) {
+	log_warning("Couldn't find matching cell.\n");
+    }
     return selected_objects;
 }
diff --git a/design_introspection-plugin/get_nets.cc b/design_introspection-plugin/get_nets.cc
index 504bb87..15cdb1d 100644
--- a/design_introspection-plugin/get_nets.cc
+++ b/design_introspection-plugin/get_nets.cc
@@ -20,11 +20,11 @@
 		}
 	    }
 	    std::string object_name(RTLIL::unescape_id(wire->name));
-	    if (!args.is_quiet) {
-		log("%s ", object_name.c_str());
-	    }
 	    selected_objects.push_back(object_name);
 	}
     }
+    if (selected_objects.size() == 0 and !args.is_quiet) {
+	log_warning("Couldn't find matching net.\n");
+    }
     return selected_objects;
 }
diff --git a/design_introspection-plugin/get_pins.cc b/design_introspection-plugin/get_pins.cc
index aa557e8..3bedf62 100644
--- a/design_introspection-plugin/get_pins.cc
+++ b/design_introspection-plugin/get_pins.cc
@@ -11,7 +11,7 @@
 }
 
 GetPins::SelectionObjects GetPins::ExtractSelection(RTLIL::Design* design, const CommandArgs& args) {
-    SelectionObjects selection_objects;
+    SelectionObjects selected_objects;
     for (auto obj : args.selection_objects) {
 	size_t port_separator = obj.find_last_of("/");
 	std::string cell = obj.substr(0, port_separator);
@@ -19,12 +19,12 @@
 	SelectionObjects selection{RTLIL::unescape_id(design->top_module()->name) + "/" +
 	       SelectionType() + ":" + cell};
 	extra_args(selection, 0, design);
-	ExtractSingleSelection(selection_objects, design, port, args);
+	ExtractSingleSelection(selected_objects, design, port, args);
     }
-    if (!args.is_quiet) {
-	log("\n");
+    if (selected_objects.size() == 0 and !args.is_quiet) {
+	log_warning("Couldn't find matching pin.\n");
     }
-    return selection_objects;
+    return selected_objects;
 }
 
 void GetPins::ExtractSingleSelection(SelectionObjects& objects, RTLIL::Design* design,
@@ -50,9 +50,6 @@
 		}
 	    }
 	    std::string pin_name(RTLIL::unescape_id(cell->name) + "/" + port_name);
-	    if (!args.is_quiet) {
-		log("%s ", pin_name.c_str());
-	    }
 	    objects.push_back(pin_name);
 	}
     }
diff --git a/design_introspection-plugin/get_ports.cc b/design_introspection-plugin/get_ports.cc
index be9e7f3..d6f326f 100644
--- a/design_introspection-plugin/get_ports.cc
+++ b/design_introspection-plugin/get_ports.cc
@@ -27,14 +27,11 @@
 	    if (bit >= wire->start_offset &&
 	        bit < wire->start_offset + wire->width) {
 		objects.push_back(port_name);
-		if (!args.is_quiet) {
-		    log("%s ", port_name.c_str());
-		}
 	    }
 	}
     }
     if (objects.size() == 0 and !args.is_quiet) {
-	log_error("Couldn't find port %s\n", port_name.c_str());
+	log_warning("Couldn't find port matching %s\n", port_name.c_str());
     }
     return objects;
 }