Merge pull request #292 from hzeller/20220406-make-dsp-ff-test-location-independent
Make access to nexus-dsp_rules.txt in tests location indpenedent.
diff --git a/dsp-ff-plugin/dsp_ff.cc b/dsp-ff-plugin/dsp_ff.cc
index 26e5acd..d0ecd8e 100644
--- a/dsp-ff-plugin/dsp_ff.cc
+++ b/dsp-ff-plugin/dsp_ff.cc
@@ -289,7 +289,7 @@
log("Loading rules from '%s'...\n", a_FileName.c_str());
if (!file) {
- log_error(" Error opening file!\n");
+ log_error(" Error opening file '%s'!\n", a_FileName.c_str());
}
// Parse each port as if it was associated with its own DSP register.
diff --git a/dsp-ff-plugin/tests/nexus_conn_conflict/nexus_conn_conflict.tcl b/dsp-ff-plugin/tests/nexus_conn_conflict/nexus_conn_conflict.tcl
index 87486f9..2bce1d4 100644
--- a/dsp-ff-plugin/tests/nexus_conn_conflict/nexus_conn_conflict.tcl
+++ b/dsp-ff-plugin/tests/nexus_conn_conflict/nexus_conn_conflict.tcl
@@ -2,6 +2,8 @@
if { [info procs dsp_ff] == {} } { plugin -i dsp-ff }
yosys -import ;# ingest plugin commands
+set DSP_RULES [file dirname $::env(DESIGN_TOP)]/../../nexus-dsp_rules.txt
+
read_verilog $::env(DESIGN_TOP).v
design -save read
@@ -10,7 +12,7 @@
hierarchy -top ${TOP}
synth_nexus -flatten
techmap -map +/nexus/cells_sim.v t:VLO t:VHI %u ;# Unmap VHI and VLO
-equiv_opt -assert -async2sync -map +/nexus/cells_sim.v debug dsp_ff -rules ../../nexus-dsp_rules.txt
+equiv_opt -assert -async2sync -map +/nexus/cells_sim.v debug dsp_ff -rules ${DSP_RULES}
design -load postopt
yosys cd ${TOP}
stat
@@ -22,7 +24,7 @@
hierarchy -top ${TOP}
synth_nexus -flatten
techmap -map +/nexus/cells_sim.v t:VLO t:VHI %u ;# Unmap VHI and VLO
-debug dsp_ff -rules ../../nexus-dsp_rules.txt
+debug dsp_ff -rules ${DSP_RULES}
stat
select -assert-count 1 t:MULT9X9
select -assert-count 18 t:FD1P3IX
@@ -32,7 +34,7 @@
hierarchy -top ${TOP}
synth_nexus -flatten
techmap -map +/nexus/cells_sim.v t:VLO t:VHI %u ;# Unmap VHI and VLO
-debug dsp_ff -rules ../../nexus-dsp_rules.txt
+debug dsp_ff -rules ${DSP_RULES}
stat
select -assert-count 1 t:MULT9X9
select -assert-count 18 t:FD1P3DX
@@ -42,7 +44,7 @@
hierarchy -top ${TOP}
synth_nexus -flatten
techmap -map +/nexus/cells_sim.v t:VLO t:VHI %u ;# Unmap VHI and VLO
-debug dsp_ff -rules ../../nexus-dsp_rules.txt
+debug dsp_ff -rules ${DSP_RULES}
stat
select -assert-count 1 t:MULT9X9
select -assert-count 18 t:FD1P3IX
@@ -52,7 +54,7 @@
hierarchy -top ${TOP}
synth_nexus -flatten
techmap -map +/nexus/cells_sim.v t:VLO t:VHI %u ;# Unmap VHI and VLO
-debug dsp_ff -rules ../../nexus-dsp_rules.txt
+debug dsp_ff -rules ${DSP_RULES}
stat
select -assert-count 1 t:MULT9X9
select -assert-count 9 t:FD1P3IX
diff --git a/dsp-ff-plugin/tests/nexus_conn_share/nexus_conn_share.tcl b/dsp-ff-plugin/tests/nexus_conn_share/nexus_conn_share.tcl
index 2f13e67..673131d 100644
--- a/dsp-ff-plugin/tests/nexus_conn_share/nexus_conn_share.tcl
+++ b/dsp-ff-plugin/tests/nexus_conn_share/nexus_conn_share.tcl
@@ -2,6 +2,8 @@
if { [info procs dsp_ff] == {} } { plugin -i dsp-ff }
yosys -import ;# ingest plugin commands
+set DSP_RULES [file dirname $::env(DESIGN_TOP)]/../../nexus-dsp_rules.txt
+
read_verilog $::env(DESIGN_TOP).v
design -save read
@@ -10,7 +12,7 @@
hierarchy -top ${TOP}
synth_nexus -flatten
techmap -map +/nexus/cells_sim.v t:VLO t:VHI %u ;# Unmap VHI and VLO
-debug dsp_ff -rules ../../nexus-dsp_rules.txt
+debug dsp_ff -rules ${DSP_RULES}
stat
select -assert-count 1 t:MULT9X9
select -assert-count 18 t:FD1P3IX
@@ -20,7 +22,7 @@
hierarchy -top ${TOP}
synth_nexus -flatten
techmap -map +/nexus/cells_sim.v t:VLO t:VHI %u ;# Unmap VHI and VLO
-debug dsp_ff -rules ../../nexus-dsp_rules.txt
+debug dsp_ff -rules ${DSP_RULES}
stat
select -assert-count 1 t:MULT9X9
select -assert-count 18 t:FD1P3IX
@@ -30,7 +32,7 @@
hierarchy -top ${TOP}
synth_nexus -flatten
techmap -map +/nexus/cells_sim.v t:VLO t:VHI %u ;# Unmap VHI and VLO
-debug dsp_ff -rules ../../nexus-dsp_rules.txt
+debug dsp_ff -rules ${DSP_RULES}
stat
select -assert-count 1 t:MULT9X9
select -assert-count 9 t:FD1P3IX
@@ -40,9 +42,7 @@
hierarchy -top ${TOP}
synth_nexus -flatten
techmap -map +/nexus/cells_sim.v t:VLO t:VHI %u ;# Unmap VHI and VLO
-debug dsp_ff -rules ../../nexus-dsp_rules.txt
+debug dsp_ff -rules ${DSP_RULES}
stat
select -assert-count 1 t:MULT9X9
select -assert-count 9 t:FD1P3IX
-
-
diff --git a/dsp-ff-plugin/tests/nexus_fftypes/nexus_fftypes.tcl b/dsp-ff-plugin/tests/nexus_fftypes/nexus_fftypes.tcl
index fa006c8..d394e04 100644
--- a/dsp-ff-plugin/tests/nexus_fftypes/nexus_fftypes.tcl
+++ b/dsp-ff-plugin/tests/nexus_fftypes/nexus_fftypes.tcl
@@ -2,6 +2,8 @@
if { [info procs dsp_ff] == {} } { plugin -i dsp-ff }
yosys -import ;# ingest plugin commands
+set DSP_RULES [file dirname $::env(DESIGN_TOP)]/../../nexus-dsp_rules.txt
+
read_verilog $::env(DESIGN_TOP).v
design -save read
@@ -10,7 +12,7 @@
hierarchy -top ${TOP}
synth_nexus -flatten
techmap -map +/nexus/cells_sim.v t:VLO t:VHI %u ;# Unmap VHI and VLO
-equiv_opt -assert -async2sync -map +/nexus/cells_sim.v debug dsp_ff -rules ../../nexus-dsp_rules.txt
+equiv_opt -assert -async2sync -map +/nexus/cells_sim.v debug dsp_ff -rules ${DSP_RULES}
design -load postopt
yosys cd ${TOP}
stat
@@ -23,7 +25,7 @@
hierarchy -top ${TOP}
synth_nexus -flatten
techmap -map +/nexus/cells_sim.v t:VLO t:VHI %u ;# Unmap VHI and VLO
-equiv_opt -assert -async2sync -map +/nexus/cells_sim.v debug dsp_ff -rules ../../nexus-dsp_rules.txt
+equiv_opt -assert -async2sync -map +/nexus/cells_sim.v debug dsp_ff -rules ${DSP_RULES}
design -load postopt
yosys cd ${TOP}
stat
@@ -36,7 +38,7 @@
hierarchy -top ${TOP}
synth_nexus -flatten
techmap -map +/nexus/cells_sim.v t:VLO t:VHI %u ;# Unmap VHI and VLO
-equiv_opt -assert -async2sync -map +/nexus/cells_sim.v debug dsp_ff -rules ../../nexus-dsp_rules.txt
+equiv_opt -assert -async2sync -map +/nexus/cells_sim.v debug dsp_ff -rules ${DSP_RULES}
design -load postopt
yosys cd ${TOP}
stat
@@ -49,7 +51,7 @@
hierarchy -top ${TOP}
synth_nexus -flatten
techmap -map +/nexus/cells_sim.v t:VLO t:VHI %u ;# Unmap VHI and VLO
-equiv_opt -assert -async2sync -map +/nexus/cells_sim.v debug dsp_ff -rules ../../nexus-dsp_rules.txt
+equiv_opt -assert -async2sync -map +/nexus/cells_sim.v debug dsp_ff -rules ${DSP_RULES}
design -load postopt
yosys cd ${TOP}
stat
@@ -62,7 +64,7 @@
hierarchy -top ${TOP}
synth_nexus -flatten
techmap -map +/nexus/cells_sim.v t:VLO t:VHI %u ;# Unmap VHI and VLO
-equiv_opt -assert -async2sync -map +/nexus/cells_sim.v debug dsp_ff -rules ../../nexus-dsp_rules.txt
+equiv_opt -assert -async2sync -map +/nexus/cells_sim.v debug dsp_ff -rules ${DSP_RULES}
design -load postopt
yosys cd ${TOP}
stat
diff --git a/dsp-ff-plugin/tests/nexus_mult/nexus_mult.tcl b/dsp-ff-plugin/tests/nexus_mult/nexus_mult.tcl
index 1eef04a..3e52fbf 100644
--- a/dsp-ff-plugin/tests/nexus_mult/nexus_mult.tcl
+++ b/dsp-ff-plugin/tests/nexus_mult/nexus_mult.tcl
@@ -2,6 +2,8 @@
if { [info procs dsp_ff] == {} } { plugin -i dsp-ff }
yosys -import ;# ingest plugin commands
+set DSP_RULES [file dirname $::env(DESIGN_TOP)]/../../nexus-dsp_rules.txt
+
read_verilog $::env(DESIGN_TOP).v
design -save read
@@ -10,7 +12,7 @@
hierarchy -top ${TOP}
synth_nexus -flatten
techmap -map +/nexus/cells_sim.v t:VLO t:VHI %u ;# Unmap VHI and VLO
-equiv_opt -assert -async2sync -map +/nexus/cells_sim.v debug dsp_ff -rules ../../nexus-dsp_rules.txt
+equiv_opt -assert -async2sync -map +/nexus/cells_sim.v debug dsp_ff -rules ${DSP_RULES}
design -load postopt
yosys cd ${TOP}
stat
@@ -22,7 +24,7 @@
hierarchy -top ${TOP}
synth_nexus -flatten
techmap -map +/nexus/cells_sim.v t:VLO t:VHI %u ;# Unmap VHI and VLO
-equiv_opt -assert -async2sync -map +/nexus/cells_sim.v debug dsp_ff -rules ../../nexus-dsp_rules.txt
+equiv_opt -assert -async2sync -map +/nexus/cells_sim.v debug dsp_ff -rules ${DSP_RULES}
design -load postopt
yosys cd ${TOP}
stat
@@ -34,7 +36,7 @@
hierarchy -top ${TOP}
synth_nexus -flatten
techmap -map +/nexus/cells_sim.v t:VLO t:VHI %u ;# Unmap VHI and VLO
-equiv_opt -assert -async2sync -map +/nexus/cells_sim.v debug dsp_ff -rules ../../nexus-dsp_rules.txt
+equiv_opt -assert -async2sync -map +/nexus/cells_sim.v debug dsp_ff -rules ${DSP_RULES}
design -load postopt
yosys cd ${TOP}
stat
@@ -50,7 +52,7 @@
#hierarchy -top ${TOP}
#synth_nexus -flatten
#techmap -map +/nexus/cells_sim.v t:VLO t:VHI %u ;# Unmap VHI and VLO
-#equiv_opt -assert -async2sync -map +/nexus/cells_sim.v debug dsp_ff -rules ../../nexus-dsp_rules.txt
+#equiv_opt -assert -async2sync -map +/nexus/cells_sim.v debug dsp_ff -rules ${DSP_RULES}
#design -load postopt
#yosys cd ${TOP}
#stat
diff --git a/dsp-ff-plugin/tests/nexus_mult_wide/nexus_mult_wide.tcl b/dsp-ff-plugin/tests/nexus_mult_wide/nexus_mult_wide.tcl
index 70f5a61..3697177 100644
--- a/dsp-ff-plugin/tests/nexus_mult_wide/nexus_mult_wide.tcl
+++ b/dsp-ff-plugin/tests/nexus_mult_wide/nexus_mult_wide.tcl
@@ -2,6 +2,8 @@
if { [info procs dsp_ff] == {} } { plugin -i dsp-ff }
yosys -import ;# ingest plugin commands
+set DSP_RULES [file dirname $::env(DESIGN_TOP)]/../../nexus-dsp_rules.txt
+
read_verilog $::env(DESIGN_TOP).v
design -save read
@@ -10,7 +12,7 @@
hierarchy -top ${TOP}
synth_nexus -flatten
techmap -map +/nexus/cells_sim.v t:VLO t:VHI %u ;# Unmap VHI and VLO
-equiv_opt -assert -async2sync -map +/nexus/cells_sim.v debug dsp_ff -rules ../../nexus-dsp_rules.txt
+equiv_opt -assert -async2sync -map +/nexus/cells_sim.v debug dsp_ff -rules ${DSP_RULES}
design -load postopt
yosys cd ${TOP}
stat
diff --git a/dsp-ff-plugin/tests/nexus_param_conflict/nexus_param_conflict.tcl b/dsp-ff-plugin/tests/nexus_param_conflict/nexus_param_conflict.tcl
index ff46e0b..27dff3a 100644
--- a/dsp-ff-plugin/tests/nexus_param_conflict/nexus_param_conflict.tcl
+++ b/dsp-ff-plugin/tests/nexus_param_conflict/nexus_param_conflict.tcl
@@ -2,6 +2,8 @@
if { [info procs dsp_ff] == {} } { plugin -i dsp-ff }
yosys -import ;# ingest plugin commands
+set DSP_RULES [file dirname $::env(DESIGN_TOP)]/../../nexus-dsp_rules.txt
+
read_verilog $::env(DESIGN_TOP).v
design -save read
@@ -10,7 +12,7 @@
hierarchy -top ${TOP}
synth_nexus -flatten
techmap -map +/nexus/cells_sim.v t:VLO t:VHI %u ;# Unmap VHI and VLO
-debug dsp_ff -rules ../../nexus-dsp_rules.txt
+debug dsp_ff -rules ${DSP_RULES}
stat
select -assert-count 1 t:MULT9X9
select -assert-count 18 t:FD1P3IX
@@ -20,7 +22,7 @@
hierarchy -top ${TOP}
synth_nexus -flatten
techmap -map +/nexus/cells_sim.v t:VLO t:VHI %u ;# Unmap VHI and VLO
-equiv_opt -assert -async2sync -map +/nexus/cells_sim.v debug dsp_ff -rules ../../nexus-dsp_rules.txt
+equiv_opt -assert -async2sync -map +/nexus/cells_sim.v debug dsp_ff -rules ${DSP_RULES}
design -load postopt
yosys cd ${TOP}
stat
@@ -32,9 +34,8 @@
hierarchy -top ${TOP}
synth_nexus -flatten
techmap -map +/nexus/cells_sim.v t:VLO t:VHI %u ;# Unmap VHI and VLO
-debug dsp_ff -rules ../../nexus-dsp_rules.txt
+debug dsp_ff -rules ${DSP_RULES}
stat
select -assert-count 1 t:MULT9X9
select -assert-count 4 t:FD1P3IX
select -assert-count 5 t:FD1P3DX
-
