)]}'
{
  "commit": "6689e20e5fdb0b8d6f494acd65b08fd4646edc0e",
  "tree": "1a028583251255c848b1d115e0b0de41933a1fda",
  "parents": [
    "188555fc0648c0a3623e84dd28a8cd61e169bc6d",
    "c12a4b81e2536cb70001f730e68beb01a39a02a8"
  ],
  "author": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Wed Jun 07 10:58:14 2023 +0200"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Wed Jun 07 10:58:14 2023 +0200"
  },
  "message": "Merge pull request #529 from antmicro/kr/fix_multirange_with_dot\n\nyosys-systemverilog: fix multirange with dot usage",
  "tree_diff": []
}