| commit | 67119f51357e0f4403f3d93131119040e59389a6 | [log] [tgz] |
|---|---|---|
| author | Wojciech Sipak <wsipak@antmicro.com> | Fri Mar 31 13:20:43 2023 +0200 |
| committer | Wojciech Sipak <wsipak@antmicro.com> | Tue Apr 04 17:38:24 2023 +0200 |
| tree | 11818ed10cb8879c2feba9c880f60fedf3c62976 | |
| parent | cbd00f0cec6e966f6ad73936dea857b8e68f8ae3 [diff] |
clear scope before setting it up again
diff --git a/systemverilog-plugin/UhdmAst.cc b/systemverilog-plugin/UhdmAst.cc index a3484d6..c226ab5 100644 --- a/systemverilog-plugin/UhdmAst.cc +++ b/systemverilog-plugin/UhdmAst.cc
@@ -1853,6 +1853,7 @@ continue; if (pair.second->type == AST::AST_PACKAGE) { check_memories(pair.second); + clear_current_scope(); setup_current_scope(shared.top_nodes, pair.second); simplify(pair.second, nullptr); clear_current_scope();