)]}'
{
  "commit": "67119f51357e0f4403f3d93131119040e59389a6",
  "tree": "11818ed10cb8879c2feba9c880f60fedf3c62976",
  "parents": [
    "cbd00f0cec6e966f6ad73936dea857b8e68f8ae3"
  ],
  "author": {
    "name": "Wojciech Sipak",
    "email": "wsipak@antmicro.com",
    "time": "Fri Mar 31 13:20:43 2023 +0200"
  },
  "committer": {
    "name": "Wojciech Sipak",
    "email": "wsipak@antmicro.com",
    "time": "Tue Apr 04 17:38:24 2023 +0200"
  },
  "message": "clear scope before setting it up again\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "a3484d62577c1c66c0ae366d67b2ad49d51a664e",
      "old_mode": 33188,
      "old_path": "systemverilog-plugin/UhdmAst.cc",
      "new_id": "c226ab5d25594bc79470e221a2d050bdcdd06139",
      "new_mode": 33188,
      "new_path": "systemverilog-plugin/UhdmAst.cc"
    }
  ]
}