)]}'
{
  "commit": "67537a21261d08a334376d10f3a53e1ed7a75c74",
  "tree": "ef13925fa8e2748594577c3f4554dcbc5c0f23f1",
  "parents": [
    "932ef09b440db9c7f1c0418a51d0f401d2a30d3e"
  ],
  "author": {
    "name": "Wojciech Sipak",
    "email": "wsipak@antmicro.com",
    "time": "Wed Apr 12 13:21:07 2023 +0200"
  },
  "committer": {
    "name": "Wojciech Sipak",
    "email": "wsipak@antmicro.com",
    "time": "Wed Apr 12 14:16:19 2023 +0200"
  },
  "message": "Warn about invalidvalue in reduceExpr\n\nSigned-off-by: Wojciech Sipak \u003cwsipak@antmicro.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "3a2524e0adc1012830c954358bf007cc65e6797f",
      "old_mode": 33188,
      "old_path": "systemverilog-plugin/UhdmAst.cc",
      "new_id": "e7d264e68c147c3ab8fd6f75c0f52462004dac77",
      "new_mode": 33188,
      "new_path": "systemverilog-plugin/UhdmAst.cc"
    }
  ]
}