diff --git a/design_introspection-plugin/get_ports.cc b/design_introspection-plugin/get_ports.cc
index ccc422a..0476ef1 100644
--- a/design_introspection-plugin/get_ports.cc
+++ b/design_introspection-plugin/get_ports.cc
@@ -6,28 +6,6 @@
 
 std::string GetPorts::SelectionType() { return "x"; }
 
-void GetPorts::ExtractSelection(Tcl_Obj* tcl_list, RTLIL::Module* module,
-                                const CommandArgs& args) {
-    for (auto wire : module->selected_wires()) {
-	if (!wire->port_input and !wire->port_output) {
-	    continue;
-	}
-	if (args.filters.size() > 0) {
-	    Filter filter = args.filters.at(0);
-	    std::string attr_value = wire->get_string_attribute(
-	        RTLIL::IdString(RTLIL::escape_id(filter.first)));
-	    if (attr_value.compare(filter.second)) {
-		continue;
-	    }
-	}
-	if (!args.is_quiet) {
-	    log("%s ", id2cstr(wire->name));
-	}
-	Tcl_Obj* value_obj = Tcl_NewStringObj(id2cstr(wire->name), -1);
-	Tcl_ListObjAppendElement(yosys_get_tcl_interp(), tcl_list, value_obj);
-    }
-}
-
 void GetPorts::execute(std::vector<std::string> args, RTLIL::Design* design) {
     if (args.size() < 2) {
 	log_cmd_error("No port specified.\n");
diff --git a/design_introspection-plugin/get_ports.h b/design_introspection-plugin/get_ports.h
index 70c4996..a06bc53 100644
--- a/design_introspection-plugin/get_ports.h
+++ b/design_introspection-plugin/get_ports.h
@@ -10,8 +10,6 @@
 
     std::string TypeName() override;
     std::string SelectionType() override;
-    void ExtractSelection(Tcl_Obj* tcl_list, RTLIL::Module* module,
-                          const CommandArgs& args) override;
     void execute(std::vector<std::string> args, RTLIL::Design* design) override;
 };