)]}'
{
  "commit": "67deb91dfd4e77f084102669db67d6d88d9d491a",
  "tree": "368d72e1733265398bc08a71dba0be57ec7538a3",
  "parents": [
    "a20c6a96d9fd4b8989940a6608501784e02e78b1"
  ],
  "author": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Mon Feb 06 16:54:32 2023 +0100"
  },
  "committer": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Wed Feb 08 10:03:15 2023 +0100"
  },
  "message": "systemverilog: add support for list op with low and high bound\n\nSigned-off-by: Kamil Rakoczy \u003ckrakoczy@antmicro.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "3c2ae3ed82ce2f18371efffd4a4d5de350575e81",
      "old_mode": 33188,
      "old_path": "systemverilog-plugin/UhdmAst.cc",
      "new_id": "aa9812bc05f95a519c5f9ada37a162840a1b97c6",
      "new_mode": 33188,
      "new_path": "systemverilog-plugin/UhdmAst.cc"
    }
  ]
}