)]}'
{
  "commit": "681aa553c80b3a0daa00c49a421f8316ac2c3d56",
  "tree": "aeca45e3021e0011ee270a51393f15f57a8eef5a",
  "parents": [
    "0af8e42609be2602ab0d8083853b44b7bcd79ced"
  ],
  "author": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Wed Feb 08 12:11:45 2023 +0100"
  },
  "committer": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Wed Feb 08 12:11:45 2023 +0100"
  },
  "message": "systemverilog-plugin: add support for case type in process_value\n\nSigned-off-by: Kamil Rakoczy \u003ckrakoczy@antmicro.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "3eb0e30d9339c2ba458d77a498851d71aebb0f1c",
      "old_mode": 33188,
      "old_path": "systemverilog-plugin/UhdmAst.cc",
      "new_id": "5c845af0bc48a3f63352ec1ed26578e92e0d413c",
      "new_mode": 33188,
      "new_path": "systemverilog-plugin/UhdmAst.cc"
    }
  ]
}