diff --git a/sdc-plugin/clocks.cc b/sdc-plugin/clocks.cc
index 4147174..865dd37 100644
--- a/sdc-plugin/clocks.cc
+++ b/sdc-plugin/clocks.cc
@@ -30,7 +30,7 @@
     wire->set_bool_attribute(RTLIL::escape_id("IS_PROPAGATED"), type == PROPAGATED);
     wire->set_string_attribute(RTLIL::escape_id("CLASS"), "clock");
     wire->set_string_attribute(RTLIL::escape_id("NAME"), name);
-    wire->set_string_attribute(RTLIL::escape_id("SOURCE_PINS"),
+    wire->set_string_attribute(RTLIL::escape_id("SOURCE_WIRES"),
                                Clock::WireName(wire));
     wire->set_string_attribute(RTLIL::escape_id("PERIOD"),
                                std::to_string(period));
@@ -124,9 +124,9 @@
     return AddEscaping(RTLIL::unescape_id(clock_wire->name));
 }
 
-std::string Clock::SourcePinName(RTLIL::Wire* clock_wire) {
-    if (clock_wire->has_attribute(RTLIL::escape_id("SOURCE_PINS"))) {
-	return clock_wire->get_string_attribute(RTLIL::escape_id("SOURCE_PINS"));
+std::string Clock::SourceWireName(RTLIL::Wire* clock_wire) {
+    if (clock_wire->has_attribute(RTLIL::escape_id("SOURCE_WIRES"))) {
+	return clock_wire->get_string_attribute(RTLIL::escape_id("SOURCE_WIRES"));
     }
     return Name(clock_wire);
 }
diff --git a/sdc-plugin/clocks.h b/sdc-plugin/clocks.h
index d9208e0..5d3d9af 100644
--- a/sdc-plugin/clocks.h
+++ b/sdc-plugin/clocks.h
@@ -47,7 +47,7 @@
     static std::string AddEscaping(const std::string& name) {
 	return std::regex_replace(name, std::regex{"\\$"}, "\\$");
     }
-    static std::string SourcePinName(RTLIL::Wire* clock_wire);
+    static std::string SourceWireName(RTLIL::Wire* clock_wire);
     static bool IsPropagated(RTLIL::Wire* wire) {
 	return GetClockWireBoolAttribute(wire, "IS_PROPAGATED");
     }
diff --git a/sdc-plugin/sdc_writer.cc b/sdc-plugin/sdc_writer.cc
index 4c3e093..b73e242 100644
--- a/sdc-plugin/sdc_writer.cc
+++ b/sdc-plugin/sdc_writer.cc
@@ -58,7 +58,7 @@
 	file << "create_clock -period " << Clock::Period(clock_wire);
 	file << " -waveform {" << Clock::RisingEdge(clock_wire) << " "
 	     << Clock::FallingEdge(clock_wire) << "}";
-	file << " " << Clock::SourcePinName(clock_wire);
+	file << " " << Clock::SourceWireName(clock_wire);
 	file << std::endl;
     }
 }