diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
index a98124e..4ab1814 100644
--- a/.github/workflows/ci.yml
+++ b/.github/workflows/ci.yml
@@ -21,7 +21,7 @@
 jobs:
 
   Run-tests:
-    runs-on: ubuntu-latest
+    runs-on: ubuntu-20.04
 
     steps:
 
diff --git a/.gitignore b/.gitignore
index 56d3484..a299974 100644
--- a/.gitignore
+++ b/.gitignore
@@ -3,4 +3,4 @@
 *.so
 *.swp
 *.log
-ql-qlf-plugin/pmgen/*
+/*/build
diff --git a/Makefile b/Makefile
index 044fe00..70433f7 100644
--- a/Makefile
+++ b/Makefile
@@ -20,6 +20,7 @@
 PLUGINS_CLEAN := $(foreach plugin,$(PLUGIN_LIST),clean_$(plugin))
 PLUGINS_TEST := $(foreach plugin,$(PLUGIN_LIST),test_$(plugin))
 
+.PHONY: all
 all: plugins
 
 TOP_DIR := $(realpath $(dir $(lastword $(MAKEFILE_LIST))))
@@ -29,15 +30,19 @@
 -include third_party/make-env/conda.mk
 
 define install_plugin =
+.PHONY: $(1).so
 $(1).so:
 	$$(MAKE) -C $(1)-plugin $$@
 
+.PHONY: install_$(1)
 install_$(1):
 	$$(MAKE) -C $(1)-plugin install
 
+.PHONY: clean_$(1)
 clean_$(1):
 	$$(MAKE) -C $(1)-plugin clean
 
+.PHONY: test_$(1)
 test_$(1):
 	@$$(MAKE) --no-print-directory -C $(1)-plugin test
 endef
@@ -47,21 +52,28 @@
 pmgen.py:
 	wget -nc -O $@ https://raw.githubusercontent.com/YosysHQ/yosys/master/passes/pmgen/pmgen.py
 
+.PHONY: plugins
 plugins: $(PLUGINS)
 
+.PHONY: install
 install: $(PLUGINS_INSTALL)
 
+.PHONY: test
 test: $(PLUGINS_TEST)
 
+.PHONY: plugins_clean
 plugins_clean: $(PLUGINS_CLEAN)
 
+.PHONY: clean
 clean:: plugins_clean
 	rm -rf pmgen.py
 
 CLANG_FORMAT ?= clang-format-8
+.PHONY: format
 format:
-	find . \( -name "*.h" -o -name "*.cc" \) -and -not -path './third_party/*' -print0 | xargs -0 -P $$(nproc) ${CLANG_FORMAT} -style=file -i
+	find . \( -name "*.h" -o -name "*.cc" \) -and -not -path '*/third_party/*' -print0 | xargs -0 -P $$(nproc) ${CLANG_FORMAT} -style=file -i
 
 VERIBLE_FORMAT ?= verible-verilog-format
+.PHONY: format-verilog
 format-verilog:
-	find */tests \( -name "*.v" -o -name "*.sv" \) -and -not -path './third_party/*' -print0 | xargs -0 $(VERIBLE_FORMAT) --inplace
+	find */tests \( -name "*.v" -o -name "*.sv" \) -and -not -path '*/third_party/*' -print0 | xargs -0 $(VERIBLE_FORMAT) --inplace
diff --git a/Makefile_plugin.common b/Makefile_plugin.common
index b26a7e0..45c2640 100644
--- a/Makefile_plugin.common
+++ b/Makefile_plugin.common
@@ -5,6 +5,7 @@
 # This shared object can be imported to Yosys with `plugin -i` command.
 #
 # Below is an example of a plugin Makefile that uses this template:
+# PLUGIN_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
 # NAME = plugin_name
 # SOURCES = source1.cc source2.cc
 # include ../Makefile_plugin.common
@@ -38,8 +39,15 @@
 # |-- example2-plugin
 # |-- ...
 
+SHELL := /usr/bin/env bash
+
+# Directory containing this Makefile
+TOP_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
+
+_MAKEFILES := $(abspath $(filter-out %.d,$(MAKEFILE_LIST)))
+
 # Either find yosys in system and use its path or use the given path
-YOSYS_PATH ?= $(realpath $(dir $(shell which yosys))/..)
+YOSYS_PATH ?= $(realpath $(dir $(shell command -v yosys))/..)
 
 # Find yosys-config, throw an error if not found
 YOSYS_CONFIG = $(YOSYS_PATH)/bin/yosys-config
@@ -53,35 +61,94 @@
 LDLIBS := $(shell $(YOSYS_CONFIG) --ldlibs) $(LDLIBS)
 EXTRA_FLAGS ?=
 
-DATA_DIR = $(DESTDIR)$(shell $(YOSYS_CONFIG) --datdir)
-PLUGINS_DIR = $(DATA_DIR)/plugins
+YOSYS_DATA_DIR = $(DESTDIR)$(shell $(YOSYS_CONFIG) --datdir)
+YOSYS_PLUGINS_DIR = $(YOSYS_DATA_DIR)/plugins
 
-OBJS := $(patsubst %.cc,%.o,$(SOURCES))
-DEPS ?=
+BUILD_DIR := $(PLUGIN_DIR)/build
 
-$(PLUGINS_DIR):
-	@mkdir -p $@
+# Filled below with all object file paths
+_ALL_OBJECTS :=
+# Filled below with all build directory paths
+_ALL_BUILD_SUBDIRS :=
 
+# Default rule
+
+.PHONY: all
 all: $(NAME).so
 
-$(OBJS): %.o: %.cc $(DEPS)
-	$(CXX) $(CXXFLAGS) $(CPPFLAGS) $(EXTRA_FLAGS) -c -o $@ $(filter %.cc, $^)
+# Object files
 
-$(NAME).so: $(OBJS)
-	$(CXX) $(CXXFLAGS) $(LDFLAGS) -shared -o $@ $^ $(LDLIBS)
+define _process-single-source-file
+_source_abs := $(abspath $(addprefix $(PLUGIN_DIR)/,$(source)))
+_object_abs := $(abspath $(addprefix $(BUILD_DIR)/,$(source).o))
+_object_dir := $(abspath $(dir $(_object_abs)))
+_ALL_OBJECTS += $(_object_abs)
+_ALL_BUILD_SUBDIRS += $(_object_dir)
 
-../pmgen.py:
-	@$(MAKE) -C .. pmgen.py
+-include $(abspath $(addprefix $(BUILD_DIR)/,$(source).d))
 
-install_plugin: $(NAME).so | $(PLUGINS_DIR)
-	install -D $< $(PLUGINS_DIR)/$<
+$(_object_abs): TARGET_SOURCES := $(_source_abs)
+$(_object_abs): $(_source_abs) | $(_object_dir)
+endef
+$(foreach source,$(SOURCES),$(eval $(value _process-single-source-file)))
 
+$(_ALL_OBJECTS): $(_MAKEFILES)
+	$(CXX) $(CXXFLAGS) $(CPPFLAGS) $(EXTRA_FLAGS) -MMD -c -o $@ $(TARGET_SOURCES)
+
+# Objects list for the purpose of adding extra dependencies after inclusion.
+# Example use: `$(OBJECTS): $(BUILD_DIR)/some-file.h`
+OBJECTS := $(_ALL_OBJECTS)
+
+# Shared library
+
+_SO_LIB := $(BUILD_DIR)/$(NAME).so
+_ALL_BUILD_SUBDIRS += $(abspath $(dir $(_SO_LIB)))
+
+$(_SO_LIB): $(_ALL_OBJECTS) $(_MAKEFILES) | $(abspath $(dir $(_SO_LIB)))
+	$(CXX) $(CXXFLAGS) $(LDFLAGS) -shared -o $@ $(_ALL_OBJECTS) $(LDLIBS)
+
+.PHONY: $(NAME).so
+$(NAME).so: $(_SO_LIB)
+
+# Tests
+
+.PHONY: test test_clean
+ifneq ($(wildcard $(PLUGIN_DIR)/tests/Makefile),)
 test:
 	@$(MAKE) -C tests all
+test_clean:
+	$(MAKE) -C tests clean
+else
+test:
+test_clean:
+endif
+
+# Installation
+
+$(YOSYS_PLUGINS_DIR)/$(NAME).so: $(_SO_LIB) | $(YOSYS_PLUGINS_DIR)
+	install -D $(_SO_LIB) $@
+
+.PHONY: install_plugin
+install_plugin: $(YOSYS_PLUGINS_DIR)/$(NAME).so
 
 .PHONY: install
 install: install_plugin
 
-clean:
-	rm -f *.d *.o *.so
-	$(MAKE) -C tests clean
+# Cleanup
+
+clean: test_clean
+	rm -rf $(BUILD_DIR)
+
+# Other
+
+$(sort $(_ALL_BUILD_SUBDIRS)):
+	mkdir -p $@
+
+$(YOSYS_PLUGINS_DIR):
+	@mkdir -p $@
+
+PMGEN_PY := $(TOP_DIR)/pmgen.py
+
+$(PMGEN_PY):
+	@$(MAKE) -C $(TOP_DIR) pmgen.py
+
diff --git a/Makefile_test.common b/Makefile_test.common
index ca6ec18..5d72327 100644
--- a/Makefile_test.common
+++ b/Makefile_test.common
@@ -14,8 +14,10 @@
 # test2_verify = $(call diff_test,test2,ext)
 #
 
+SHELL := /usr/bin/env bash
+
 # Either find yosys in system and use its path or use the given path
-YOSYS_PATH ?= $(realpath $(dir $(shell which yosys))/..)
+YOSYS_PATH ?= $(realpath $(dir $(shell command -v yosys))/..)
 
 # Find yosys-config, throw an error if not found
 YOSYS_CONFIG = $(YOSYS_PATH)/bin/yosys-config
diff --git a/design_introspection-plugin/Makefile b/design_introspection-plugin/Makefile
index 604254e..178d5f3 100644
--- a/design_introspection-plugin/Makefile
+++ b/design_introspection-plugin/Makefile
@@ -14,6 +14,8 @@
 #
 # SPDX-License-Identifier: Apache-2.0
 
+PLUGIN_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
+
 NAME = design_introspection
 SOURCES = design_introspection.cc \
 	  get_cmd.cc \
diff --git a/dsp-ff-plugin/Makefile b/dsp-ff-plugin/Makefile
index 9cd9800..0466d85 100644
--- a/dsp-ff-plugin/Makefile
+++ b/dsp-ff-plugin/Makefile
@@ -14,11 +14,13 @@
 #
 # SPDX-License-Identifier: Apache-2.0
 
+PLUGIN_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
+
 NAME = dsp-ff
 SOURCES = dsp_ff.cc 
 
 include ../Makefile_plugin.common
 
 install:
-	install -D nexus-dsp_rules.txt $(DATA_DIR)/nexus/dsp_rules.txt
+	install -D nexus-dsp_rules.txt $(YOSYS_DATA_DIR)/nexus/dsp_rules.txt
 
diff --git a/environment.yml b/environment.yml
index a4cf46c..dc51454 100644
--- a/environment.yml
+++ b/environment.yml
@@ -20,5 +20,5 @@
   - litex-hub
 dependencies:
   - litex-hub::yosys=0.17_7_g990c9b8e1=20220512_085338_py37
-  - litex-hub::surelog
+  - litex-hub::surelog=0.0_5519_g900fb2499=20221223_060448_py37
   - litex-hub::iverilog
diff --git a/fasm-plugin/Makefile b/fasm-plugin/Makefile
index b149198..3ce41d5 100644
--- a/fasm-plugin/Makefile
+++ b/fasm-plugin/Makefile
@@ -14,6 +14,8 @@
 #
 # SPDX-License-Identifier: Apache-2.0
 
+PLUGIN_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
+
 NAME = fasm
 SOURCES = fasm.cc
 include ../Makefile_plugin.common
diff --git a/integrateinv-plugin/Makefile b/integrateinv-plugin/Makefile
index f93225a..21b75ca 100644
--- a/integrateinv-plugin/Makefile
+++ b/integrateinv-plugin/Makefile
@@ -14,6 +14,8 @@
 #
 # SPDX-License-Identifier: Apache-2.0
 
+PLUGIN_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
+
 NAME = integrateinv
 SOURCES = integrateinv.cc
 include ../Makefile_plugin.common
diff --git a/params-plugin/Makefile b/params-plugin/Makefile
index 9740c7b..b4e2d29 100644
--- a/params-plugin/Makefile
+++ b/params-plugin/Makefile
@@ -14,6 +14,8 @@
 #
 # SPDX-License-Identifier: Apache-2.0
 
+PLUGIN_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
+
 NAME = params
 SOURCES = params.cc
 include ../Makefile_plugin.common
diff --git a/ql-iob-plugin/Makefile b/ql-iob-plugin/Makefile
index dc89757..4091a6a 100644
--- a/ql-iob-plugin/Makefile
+++ b/ql-iob-plugin/Makefile
@@ -14,6 +14,8 @@
 #
 # SPDX-License-Identifier: Apache-2.0
 
+PLUGIN_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
+
 NAME = ql-iob
 SOURCES = ql-iob.cc pcf_parser.cc pinmap_parser.cc
 include ../Makefile_plugin.common
diff --git a/ql-qlf-plugin/Makefile b/ql-qlf-plugin/Makefile
index b0411b8..d546b16 100644
--- a/ql-qlf-plugin/Makefile
+++ b/ql-qlf-plugin/Makefile
@@ -14,6 +14,8 @@
 #
 # SPDX-License-Identifier: Apache-2.0
 
+PLUGIN_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
+
 NAME = ql-qlf
 SOURCES = synth_quicklogic.cc \
           ql-dsp.cc \
@@ -26,13 +28,11 @@
           ql-dsp-io-regs.cc \
           ql-bram-asymmetric.cc
 
-DEPS = pmgen/ql-dsp-pm.h \
-       pmgen/ql-dsp-macc.h \
-       pmgen/ql-bram-asymmetric-wider-write.h \
-       pmgen/ql-bram-asymmetric-wider-read.h
-
 include ../Makefile_plugin.common
 
+# For pmgen/*.h
+CXXFLAGS += -I$(BUILD_DIR)
+
 COMMON          = common
 QLF_K4N8_DIR    = qlf_k4n8
 QLF_K6N10_DIR   = qlf_k6n10
@@ -55,6 +55,8 @@
                   $(QLF_K6N10F_DIR)/brams.txt   \
                   $(QLF_K6N10F_DIR)/cells_sim.v \
                   $(QLF_K6N10F_DIR)/dsp_sim.v \
+                  $(QLF_K6N10F_DIR)/primitives_sim.v \
+                  $(QLF_K6N10F_DIR)/brams_sim.v \
                   $(QLF_K6N10F_DIR)/sram1024x18.v \
                   $(QLF_K6N10F_DIR)/TDP18K_FIFO.v \
                   $(QLF_K6N10F_DIR)/ufifo_ctl.v \
@@ -77,28 +79,35 @@
                   $(PP3_DIR)/bram_init_32.vh   \
                   $(PP3_DIR)/qlal4s3b_sim.v    \
                   $(PP3_DIR)/mult_sim.v        \
-                  $(PP3_DIR)/qlal3_sim.v       \
+                  $(PP3_DIR)/qlal3_sim.v
 
-pmgen:
-	mkdir -p pmgen
+PMGEN_OUT_DIR := $(BUILD_DIR)/pmgen
 
-pmgen/ql-dsp-pm.h: ../pmgen.py ql_dsp.pmg | pmgen
-	python3 ../pmgen.py -o $@ -p ql_dsp ql_dsp.pmg
+$(PMGEN_OUT_DIR):
+	mkdir -p $@
 
-pmgen/ql-dsp-macc.h: ../pmgen.py ql-dsp-macc.pmg | pmgen
-	python3 ../pmgen.py -o $@ -p ql_dsp_macc ql-dsp-macc.pmg
+DEPS := $(PMGEN_OUT_DIR)/ql-dsp-pm.h \
+        $(PMGEN_OUT_DIR)/ql-dsp-macc.h \
+        $(PMGEN_OUT_DIR)/ql-bram-asymmetric-wider-write.h \
+        $(PMGEN_OUT_DIR)/ql-bram-asymmetric-wider-read.h
 
-pmgen/ql-bram-asymmetric-wider-write.h: ../pmgen.py ql-bram-asymmetric-wider-write.pmg | pmgen
-	python3 ../pmgen.py -o $@ -p ql_bram_asymmetric_wider_write ql-bram-asymmetric-wider-write.pmg
+$(DEPS): $(PMGEN_PY) | $(PMGEN_OUT_DIR)
 
-pmgen/ql-bram-asymmetric-wider-read.h: ../pmgen.py ql-bram-asymmetric-wider-read.pmg | pmgen
-	python3 ../pmgen.py -o $@ -p ql_bram_asymmetric_wider_read ql-bram-asymmetric-wider-read.pmg
+$(OBJECTS): $(DEPS)
+
+$(PMGEN_OUT_DIR)/ql-dsp-pm.h: ql_dsp.pmg
+	python3 $(PMGEN_PY) -o $@ -p ql_dsp ql_dsp.pmg
+
+$(PMGEN_OUT_DIR)/ql-dsp-macc.h: ql-dsp-macc.pmg
+	python3 $(PMGEN_PY) -o $@ -p ql_dsp_macc ql-dsp-macc.pmg
+
+$(PMGEN_OUT_DIR)/ql-bram-asymmetric-wider-write.h: ql-bram-asymmetric-wider-write.pmg
+	python3 $(PMGEN_PY) -o $@ -p ql_bram_asymmetric_wider_write ql-bram-asymmetric-wider-write.pmg
+
+$(PMGEN_OUT_DIR)/ql-bram-asymmetric-wider-read.h: ql-bram-asymmetric-wider-read.pmg
+	python3 $(PMGEN_PY) -o $@ -p ql_bram_asymmetric_wider_read ql-bram-asymmetric-wider-read.pmg
 
 install_modules: $(VERILOG_MODULES)
-	$(foreach f,$^,install -D $(f) $(DATA_DIR)/quicklogic/$(f);)
+	$(foreach f,$^,install -D $(f) $(YOSYS_DATA_DIR)/quicklogic/$(f);)
 
 install: install_modules
-
-clean:
-	$(MAKE) -f ../Makefile_plugin.common $@
-	rm -rf pmgen
diff --git a/ql-qlf-plugin/ql-bram-split.cc b/ql-qlf-plugin/ql-bram-split.cc
index f699ee5..6a7d2f9 100644
--- a/ql-qlf-plugin/ql-bram-split.cc
+++ b/ql-qlf-plugin/ql-bram-split.cc
@@ -129,6 +129,97 @@
         }
     }
 
+    void map_pairs(std::vector<RTLIL::Cell *> group, BramConfig config, std::vector<const RTLIL::Cell *> *cellsToRemove, RTLIL::Module *module)
+    {
+        // Ensure an even number
+        size_t count = group.size();
+        if (count & 1)
+            count--;
+
+        // Map SIMD pairs
+        for (size_t i = 0; i < count; i += 2) {
+            const RTLIL::Cell *bram_0 = group[i];
+            const RTLIL::Cell *bram_1 = group[i + 1];
+
+            if (bram_0->type != bram_1->type)
+                log_error("Unsupported BRAM configuration: one half of TDP36K is TDP, second SDP");
+
+            std::vector<std::pair<std::string, std::string>> m_BramDataPorts_0;
+            std::vector<std::pair<std::string, std::string>> m_BramDataPorts_1;
+            std::string m_Bram1x18Type;
+            std::string m_Bram2x18Type;
+            // Distinguish between TDP and SDP
+            if (bram_0->type == RTLIL::escape_id(m_Bram1x18TDPType)) {
+                m_BramDataPorts_0 = m_BramTDPDataPorts_0;
+                m_BramDataPorts_1 = m_BramTDPDataPorts_1;
+                m_Bram1x18Type = m_Bram1x18TDPType;
+                m_Bram2x18Type = m_Bram2x18TDPType;
+            } else {
+                m_BramDataPorts_0 = m_BramSDPDataPorts_0;
+                m_BramDataPorts_1 = m_BramSDPDataPorts_1;
+                m_Bram1x18Type = m_Bram1x18SDPType;
+                m_Bram2x18Type = m_Bram2x18SDPType;
+            }
+
+            std::string name = stringf("bram_%s_%s", RTLIL::unescape_id(bram_0->name).c_str(), RTLIL::unescape_id(bram_1->name).c_str());
+
+            log(" BRAM: %s (%s) + %s (%s) => %s (%s)\n", RTLIL::unescape_id(bram_0->name).c_str(), RTLIL::unescape_id(bram_0->type).c_str(),
+                RTLIL::unescape_id(bram_1->name).c_str(), RTLIL::unescape_id(bram_1->type).c_str(), RTLIL::unescape_id(name).c_str(),
+                m_Bram2x18Type.c_str());
+
+            // Create the new cell
+            RTLIL::Cell *bram_2x18 = module->addCell(RTLIL::escape_id(name), RTLIL::escape_id(m_Bram2x18Type));
+
+            // Check if the target cell is known (important to know
+            // its port widths)
+            if (!bram_2x18->known()) {
+                log_error(" The target cell type '%s' is not known!", m_Bram2x18Type.c_str());
+            }
+
+            // Connect shared ports
+            for (const auto &it : m_BramSharedPorts) {
+                auto src = RTLIL::escape_id(it.first);
+                auto dst = RTLIL::escape_id(it.second);
+
+                bram_2x18->setPort(dst, config.connections.at(src));
+            }
+
+            // Connect data ports
+            // Connect first bram
+            map_ports(m_BramDataPorts_0, bram_0, bram_2x18);
+            // Connect second bram
+            map_ports(m_BramDataPorts_1, bram_1, bram_2x18);
+
+            // Set bram parameters
+            for (const auto &it : m_BramParams) {
+                auto val = bram_0->getParam(RTLIL::escape_id(it));
+                bram_2x18->setParam(RTLIL::escape_id(it), val);
+            }
+
+            // Setting manual parameters
+            if (bram_0->type == RTLIL::escape_id(m_Bram1x18TDPType)) {
+                bram_2x18->setParam(RTLIL::escape_id("CFG_ENABLE_B"), bram_0->getParam(RTLIL::escape_id("CFG_ENABLE_B")));
+                bram_2x18->setParam(RTLIL::escape_id("CFG_ENABLE_D"), bram_0->getParam(RTLIL::escape_id("CFG_ENABLE_D")));
+                bram_2x18->setParam(RTLIL::escape_id("CFG_ENABLE_F"), bram_1->getParam(RTLIL::escape_id("CFG_ENABLE_B")));
+                bram_2x18->setParam(RTLIL::escape_id("CFG_ENABLE_H"), bram_1->getParam(RTLIL::escape_id("CFG_ENABLE_D")));
+            } else {
+                bram_2x18->setParam(RTLIL::escape_id("CFG_ENABLE_B"), bram_0->getParam(RTLIL::escape_id("CFG_ENABLE_B")));
+                bram_2x18->setParam(RTLIL::escape_id("CFG_ENABLE_D"), bram_1->getParam(RTLIL::escape_id("CFG_ENABLE_B")));
+            }
+            if (bram_0->hasParam(RTLIL::escape_id("INIT")))
+                bram_2x18->setParam(RTLIL::escape_id("INIT0"), bram_0->getParam(RTLIL::escape_id("INIT")));
+            if (bram_1->hasParam(RTLIL::escape_id("INIT")))
+                bram_2x18->setParam(RTLIL::escape_id("INIT1"), bram_1->getParam(RTLIL::escape_id("INIT")));
+
+            // Since in this pass we are mapping the inferred cell directly then mark it as inferred
+            bram_2x18->set_bool_attribute(RTLIL::escape_id("is_inferred"), true);
+
+            // Mark BRAM parts for removal
+            cellsToRemove->push_back(bram_0);
+            cellsToRemove->push_back(bram_1);
+        }
+    }
+
     void execute(std::vector<std::string> a_Args, RTLIL::Design *a_Design) override
     {
         log_header(a_Design, "Executing QL_BRAM_Split pass.\n");
@@ -144,115 +235,37 @@
             m_SigMap.set(module);
 
             // Assemble BRAM cell groups
-            dict<BramConfig, std::vector<RTLIL::Cell *>> groups;
+            dict<BramConfig, std::vector<RTLIL::Cell *>> sdp_groups, tdp_groups;
             for (auto cell : module->selected_cells()) {
 
-                // Check if this is a BRAM cell
-                if (cell->type != RTLIL::escape_id(m_Bram1x18TDPType) && cell->type != RTLIL::escape_id(m_Bram1x18SDPType)) {
-                    continue;
-                }
-
                 // Skip if it has the (* keep *) attribute set
                 if (cell->has_keep_attr()) {
                     continue;
                 }
 
-                // Add to a group
+                // Check if this is a BRAM cell and add to a group
                 const auto key = getBramConfig(cell);
-                groups[key].push_back(cell);
+                if (cell->type == RTLIL::escape_id(m_Bram1x18TDPType)) {
+                    tdp_groups[key].push_back(cell);
+                } else if (cell->type == RTLIL::escape_id(m_Bram1x18SDPType)) {
+                    sdp_groups[key].push_back(cell);
+                } else {
+                    continue;
+                }
             }
 
             std::vector<const RTLIL::Cell *> cellsToRemove;
 
             // Map cell pairs to the target BRAM 2x18 cell
-            for (const auto &it : groups) {
+            for (const auto &it : sdp_groups) {
                 const auto &group = it.second;
                 const auto &config = it.first;
-
-                // Ensure an even number
-                size_t count = group.size();
-                if (count & 1)
-                    count--;
-
-                // Map SIMD pairs
-                for (size_t i = 0; i < count; i += 2) {
-                    const RTLIL::Cell *bram_0 = group[i];
-                    const RTLIL::Cell *bram_1 = group[i + 1];
-
-                    if (bram_0->type != bram_1->type)
-                        log_error("Unsupported BRAM configuration: one half of TDP36K is TDP, second SDP");
-
-                    std::vector<std::pair<std::string, std::string>> m_BramDataPorts_0;
-                    std::vector<std::pair<std::string, std::string>> m_BramDataPorts_1;
-                    std::string m_Bram1x18Type;
-                    std::string m_Bram2x18Type;
-                    // Distinguish between TDP and SDP
-                    if (bram_0->type == RTLIL::escape_id(m_Bram1x18TDPType)) {
-                        m_BramDataPorts_0 = m_BramTDPDataPorts_0;
-                        m_BramDataPorts_1 = m_BramTDPDataPorts_1;
-                        m_Bram1x18Type = m_Bram1x18TDPType;
-                        m_Bram2x18Type = m_Bram2x18TDPType;
-                    } else {
-                        m_BramDataPorts_0 = m_BramSDPDataPorts_0;
-                        m_BramDataPorts_1 = m_BramSDPDataPorts_1;
-                        m_Bram1x18Type = m_Bram1x18SDPType;
-                        m_Bram2x18Type = m_Bram2x18SDPType;
-                    }
-
-                    std::string name = stringf("bram_%s_%s", RTLIL::unescape_id(bram_0->name).c_str(), RTLIL::unescape_id(bram_1->name).c_str());
-
-                    log(" BRAM: %s (%s) + %s (%s) => %s (%s)\n", RTLIL::unescape_id(bram_0->name).c_str(), RTLIL::unescape_id(bram_0->type).c_str(),
-                        RTLIL::unescape_id(bram_1->name).c_str(), RTLIL::unescape_id(bram_1->type).c_str(), RTLIL::unescape_id(name).c_str(),
-                        m_Bram2x18Type.c_str());
-
-                    // Create the new cell
-                    RTLIL::Cell *bram_2x18 = module->addCell(RTLIL::escape_id(name), RTLIL::escape_id(m_Bram2x18Type));
-
-                    // Check if the target cell is known (important to know
-                    // its port widths)
-                    if (!bram_2x18->known()) {
-                        log_error(" The target cell type '%s' is not known!", m_Bram2x18Type.c_str());
-                    }
-
-                    // Connect shared ports
-                    for (const auto &it : m_BramSharedPorts) {
-                        auto src = RTLIL::escape_id(it.first);
-                        auto dst = RTLIL::escape_id(it.second);
-
-                        bram_2x18->setPort(dst, config.connections.at(src));
-                    }
-
-                    // Connect data ports
-                    // Connect first bram
-                    map_ports(m_BramDataPorts_0, bram_0, bram_2x18);
-                    // Connect second bram
-                    map_ports(m_BramDataPorts_1, bram_1, bram_2x18);
-
-                    // Set bram parameters
-                    for (const auto &it : m_BramParams) {
-                        auto val = bram_0->getParam(RTLIL::escape_id(it));
-                        bram_2x18->setParam(RTLIL::escape_id(it), val);
-                    }
-
-                    // Setting manual parameters
-                    if (bram_0->type == RTLIL::escape_id(m_Bram1x18TDPType)) {
-                        bram_2x18->setParam(RTLIL::escape_id("CFG_ENABLE_B"), bram_0->getParam(RTLIL::escape_id("CFG_ENABLE_B")));
-                        bram_2x18->setParam(RTLIL::escape_id("CFG_ENABLE_D"), bram_0->getParam(RTLIL::escape_id("CFG_ENABLE_D")));
-                        bram_2x18->setParam(RTLIL::escape_id("CFG_ENABLE_F"), bram_1->getParam(RTLIL::escape_id("CFG_ENABLE_B")));
-                        bram_2x18->setParam(RTLIL::escape_id("CFG_ENABLE_H"), bram_1->getParam(RTLIL::escape_id("CFG_ENABLE_D")));
-                    } else {
-                        bram_2x18->setParam(RTLIL::escape_id("CFG_ENABLE_B"), bram_0->getParam(RTLIL::escape_id("CFG_ENABLE_B")));
-                        bram_2x18->setParam(RTLIL::escape_id("CFG_ENABLE_D"), bram_1->getParam(RTLIL::escape_id("CFG_ENABLE_B")));
-                    }
-                    if (bram_0->hasParam(RTLIL::escape_id("INIT")))
-                        bram_2x18->setParam(RTLIL::escape_id("INIT0"), bram_0->getParam(RTLIL::escape_id("INIT")));
-                    if (bram_1->hasParam(RTLIL::escape_id("INIT")))
-                        bram_2x18->setParam(RTLIL::escape_id("INIT1"), bram_1->getParam(RTLIL::escape_id("INIT")));
-
-                    // Mark BRAM parts for removal
-                    cellsToRemove.push_back(bram_0);
-                    cellsToRemove.push_back(bram_1);
-                }
+                map_pairs(group, config, &cellsToRemove, module);
+            }
+            for (const auto &it : tdp_groups) {
+                const auto &group = it.second;
+                const auto &config = it.first;
+                map_pairs(group, config, &cellsToRemove, module);
             }
 
             // Remove old cells
diff --git a/ql-qlf-plugin/ql-dsp-simd.cc b/ql-qlf-plugin/ql-dsp-simd.cc
index 7893eb4..2528879 100644
--- a/ql-qlf-plugin/ql-dsp-simd.cc
+++ b/ql-qlf-plugin/ql-dsp-simd.cc
@@ -162,7 +162,7 @@
                     const RTLIL::Cell *dsp_a = group[i];
                     const RTLIL::Cell *dsp_b = group[i + 1];
 
-                    std::string name = stringf("simd_%s_%s", RTLIL::unescape_id(dsp_a->name).c_str(), RTLIL::unescape_id(dsp_b->name).c_str());
+                    std::string name = stringf("simd%ld", i / 2);
                     std::string SimdDspType;
 
                     if (use_cfg_params)
diff --git a/ql-qlf-plugin/qlf_k6n10f/brams_final_map.v b/ql-qlf-plugin/qlf_k6n10f/brams_final_map.v
index aa4bb5d..cc0e272 100644
--- a/ql-qlf-plugin/qlf_k6n10f/brams_final_map.v
+++ b/ql-qlf-plugin/qlf_k6n10f/brams_final_map.v
@@ -227,6 +227,9 @@
 	wire PORT_B2_WEN = H1EN[0];
 	wire [CFG_ENABLE_H-1:0] PORT_B2_BE = {H1EN[1],H1EN[0]};
 
+    (* is_split = 1 *)
+    (* rd_data_width = CFG_DBITS *)
+    (* wr_data_width = CFG_DBITS *)
 	TDP36K  _TECHMAP_REPLACE_ (
 		.WDATA_A1_i(PORT_A1_WDATA),
 		.RDATA_A1_o(PORT_A1_RDATA),
@@ -443,6 +446,1280 @@
 	wire PORT_B2_WEN = D1EN[0];
 	wire [CFG_ENABLE_D-1:0] PORT_B2_BE = {D1EN[1],D1EN[0]};
 
+    (* is_split = 1 *)
+    (* rd_data_width = CFG_DBITS *)
+    (* wr_data_width = CFG_DBITS *)
+	TDP36K  _TECHMAP_REPLACE_ (
+		.WDATA_A1_i(PORT_A1_WDATA),
+		.RDATA_A1_o(PORT_A1_RDATA),
+		.ADDR_A1_i(PORT_A1_ADDR),
+		.CLK_A1_i(PORT_A1_CLK),
+		.REN_A1_i(PORT_A1_REN),
+		.WEN_A1_i(PORT_A1_WEN),
+		.BE_A1_i(PORT_A1_BE),
+
+		.WDATA_A2_i(PORT_A2_WDATA),
+		.RDATA_A2_o(PORT_A2_RDATA),
+		.ADDR_A2_i(PORT_A2_ADDR),
+		.CLK_A2_i(PORT_A2_CLK),
+		.REN_A2_i(PORT_A2_REN),
+		.WEN_A2_i(PORT_A2_WEN),
+		.BE_A2_i(PORT_A2_BE),
+
+		.WDATA_B1_i(PORT_B1_WDATA),
+		.RDATA_B1_o(PORT_B1_RDATA),
+		.ADDR_B1_i(PORT_B1_ADDR),
+		.CLK_B1_i(PORT_B1_CLK),
+		.REN_B1_i(PORT_B1_REN),
+		.WEN_B1_i(PORT_B1_WEN),
+		.BE_B1_i(PORT_B1_BE),
+
+		.WDATA_B2_i(PORT_B2_WDATA),
+		.RDATA_B2_o(PORT_B2_RDATA),
+		.ADDR_B2_i(PORT_B2_ADDR),
+		.CLK_B2_i(PORT_B2_CLK),
+		.REN_B2_i(PORT_B2_REN),
+		.WEN_B2_i(PORT_B2_WEN),
+		.BE_B2_i(PORT_B2_BE),
+
+		.FLUSH1_i(FLUSH1),
+		.FLUSH2_i(FLUSH2)
+	);
+endmodule
+
+module BRAM2x18_SFIFO (
+    DIN1,
+    PUSH1,
+    POP1,
+    CLK1,
+    Async_Flush1,
+    Overrun_Error1,
+    Full_Watermark1,
+    Almost_Full1,
+    Full1,
+    Underrun_Error1,
+    Empty_Watermark1,
+    Almost_Empty1,
+    Empty1,
+    DOUT1,
+    
+    DIN2,
+    PUSH2,
+    POP2,
+    CLK2,
+    Async_Flush2,
+    Overrun_Error2,
+    Full_Watermark2,
+    Almost_Full2,
+    Full2,
+    Underrun_Error2,
+    Empty_Watermark2,
+    Almost_Empty2,
+    Empty2,
+    DOUT2
+);
+
+  parameter WR_DATA_WIDTH = 18;
+  parameter RD_DATA_WIDTH = 18;
+
+  
+  parameter UPAE_DBITS1 = 11'd10;
+  parameter UPAF_DBITS1 = 11'd10;
+  
+  parameter UPAE_DBITS2 = 11'd10;
+  parameter UPAF_DBITS2 = 11'd10;
+
+  input CLK1;
+  input PUSH1, POP1;
+  input [WR_DATA_WIDTH-1:0] DIN1;
+  input Async_Flush1;
+  output [RD_DATA_WIDTH-1:0] DOUT1;
+  output Almost_Full1, Almost_Empty1;
+  output Full1, Empty1;
+  output Full_Watermark1, Empty_Watermark1;
+  output Overrun_Error1, Underrun_Error1;
+  
+  input CLK2;
+  input PUSH2, POP2;
+  input [WR_DATA_WIDTH-1:0] DIN2;
+  input Async_Flush2;
+  output [RD_DATA_WIDTH-1:0] DOUT2;
+  output Almost_Full2, Almost_Empty2;
+  output Full2, Empty2;
+  output Full_Watermark2, Empty_Watermark2;
+  output Overrun_Error2, Underrun_Error2;
+  
+  wire [17:0] in_reg1;
+  wire [17:0] out_reg1;
+  wire [17:0] fifo1_flags;
+  
+  wire [17:0] in_reg2;
+  wire [17:0] out_reg2;
+  wire [17:0] fifo2_flags;
+  
+  wire Push_Clk1, Pop_Clk1;
+  wire Push_Clk2, Pop_Clk2;
+  assign Push_Clk1 = CLK1;
+  assign Pop_Clk1 = CLK1;
+  assign Push_Clk2 = CLK2;
+  assign Pop_Clk2 = CLK2;
+  
+  assign Overrun_Error1 = fifo1_flags[0];
+  assign Full_Watermark1 = fifo1_flags[1];
+  assign Almost_Full1 = fifo1_flags[2];
+  assign Full1 = fifo1_flags[3];
+  assign Underrun_Error1 = fifo1_flags[4];
+  assign Empty_Watermark1 = fifo1_flags[5];
+  assign Almost_Empty1 = fifo1_flags[6];
+  assign Empty1 = fifo1_flags[7];
+  
+  assign Overrun_Error2 = fifo2_flags[0];
+  assign Full_Watermark2 = fifo2_flags[1];
+  assign Almost_Full2 = fifo2_flags[2];
+  assign Full2 = fifo2_flags[3];
+  assign Underrun_Error2 = fifo2_flags[4];
+  assign Empty_Watermark2 = fifo2_flags[5];
+  assign Almost_Empty2 = fifo2_flags[6];
+  assign Empty2 = fifo2_flags[7];
+  
+  generate
+    if (WR_DATA_WIDTH == 18) begin
+      assign in_reg1[17:0] = DIN1[17:0];
+      assign in_reg2[17:0] = DIN2[17:0];
+    end else if (WR_DATA_WIDTH == 9) begin
+      assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]};
+      assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]};
+    end else begin
+      assign in_reg1[17:WR_DATA_WIDTH]  = 0;
+      assign in_reg1[WR_DATA_WIDTH-1:0] = DIN1[WR_DATA_WIDTH-1:0];
+      assign in_reg2[17:WR_DATA_WIDTH]  = 0;
+      assign in_reg2[WR_DATA_WIDTH-1:0] = DIN2[WR_DATA_WIDTH-1:0];
+    end
+  endgenerate     
+  
+ case (RD_DATA_WIDTH)
+	8, 9: begin
+		case (WR_DATA_WIDTH)
+			8, 9: begin
+				defparam U1.MODE_BITS = { 1'b1,
+					UPAF_DBITS2, UPAE_DBITS2, 4'h1, `MODE_9, `MODE_9, `MODE_9, `MODE_9, 1'b1,
+					1'b0, UPAF_DBITS1, 1'b0, UPAE_DBITS1, 4'h1, `MODE_9, `MODE_9, `MODE_9, `MODE_9, 1'b1
+				};
+			end
+			16, 18: begin
+				defparam U1.MODE_BITS = { 1'b1,
+					UPAF_DBITS2, UPAE_DBITS2, 4'h1, `MODE_9, `MODE_18, `MODE_9, `MODE_18, 1'b1,
+					1'b0, UPAF_DBITS1, 1'b0, UPAE_DBITS1, 4'h1, `MODE_9, `MODE_18, `MODE_9, `MODE_18, 1'b1
+				};
+			end
+			default: begin
+				defparam U1.MODE_BITS = { 1'b1,
+					UPAF_DBITS2, UPAE_DBITS2, 4'h1, `MODE_9, `MODE_9, `MODE_9, `MODE_9, 1'b1,
+					1'b0, UPAF_DBITS1, 1'b0, UPAE_DBITS1, 4'h1, `MODE_9, `MODE_9, `MODE_9, `MODE_9, 1'b1
+				};
+			end
+		endcase
+	end
+	16, 18: begin
+		case (WR_DATA_WIDTH)
+			8, 9: begin
+				defparam U1.MODE_BITS = { 1'b1,
+					UPAF_DBITS2, UPAE_DBITS2, 4'h1, `MODE_18, `MODE_9, `MODE_18, `MODE_9, 1'b1,
+					1'b0, UPAF_DBITS1, 1'b0, UPAE_DBITS1, 4'h1, `MODE_18, `MODE_9, `MODE_18, `MODE_9, 1'b1
+				};
+			end
+			16, 18: begin
+				defparam U1.MODE_BITS = { 1'b1,
+					UPAF_DBITS2, UPAE_DBITS2, 4'h1, `MODE_18, `MODE_18, `MODE_18, `MODE_18, 1'b1,
+					1'b0, UPAF_DBITS1, 1'b0, UPAE_DBITS1, 4'h1, `MODE_18, `MODE_18, `MODE_18, `MODE_18, 1'b1
+				};
+			end
+			default: begin
+				defparam U1.MODE_BITS = { 1'b1,
+					UPAF_DBITS2, UPAE_DBITS2, 4'h1, `MODE_18, `MODE_18, `MODE_18, `MODE_18, 1'b1,
+					1'b0, UPAF_DBITS1, 1'b0, UPAE_DBITS1, 4'h1, `MODE_18, `MODE_18, `MODE_18, `MODE_18, 1'b1
+				};
+			end
+		endcase
+	end
+	default: begin
+		case (WR_DATA_WIDTH)
+			8, 9: begin
+				defparam U1.MODE_BITS = { 1'b1,
+					UPAF_DBITS2, UPAE_DBITS2, 4'h1, `MODE_9, `MODE_9, `MODE_9, `MODE_9, 1'b1,
+					1'b0, UPAF_DBITS1, 1'b0, UPAE_DBITS1, 4'h1, `MODE_9, `MODE_9, `MODE_9, `MODE_9, 1'b1
+				};
+			end
+			16, 18: begin
+				defparam U1.MODE_BITS = { 1'b1,
+					UPAF_DBITS2, UPAE_DBITS2, 4'h1, `MODE_18, `MODE_18, `MODE_18, `MODE_18, 1'b1,
+					1'b0, UPAF_DBITS1, 1'b0, UPAE_DBITS1, 4'h1, `MODE_18, `MODE_18, `MODE_18, `MODE_18, 1'b1
+				};
+			end
+			default: begin
+				defparam U1.MODE_BITS = { 1'b1,
+					UPAF_DBITS2, UPAE_DBITS2, 4'h1, `MODE_18, `MODE_18, `MODE_18, `MODE_18, 1'b1,
+					1'b0, UPAF_DBITS1, 1'b0, UPAE_DBITS1, 4'h1, `MODE_18, `MODE_18, `MODE_18, `MODE_18, 1'b1
+				};
+			end
+		endcase
+	end
+  endcase
+
+  (* is_fifo = 1 *) 
+  (* sync_fifo = 1 *) 
+  (* is_split = 1 *)
+  (* rd_data_width = RD_DATA_WIDTH *)
+  (* wr_data_width = WR_DATA_WIDTH *) 
+ 	TDP36K U1 (
+		.RESET_ni(1'b1),
+		.WDATA_A1_i(in_reg1[17:0]),
+		.WDATA_A2_i(in_reg2[17:0]),
+		.RDATA_A1_o(fifo1_flags),
+		.RDATA_A2_o(fifo2_flags),
+		.ADDR_A1_i(14'h0),
+		.ADDR_A2_i(14'h0),
+		.CLK_A1_i(Push_Clk1),
+		.CLK_A2_i(Push_Clk2),
+		.REN_A1_i(1'b1),
+		.REN_A2_i(1'b1),
+		.WEN_A1_i(PUSH1),
+		.WEN_A2_i(PUSH2),
+		.BE_A1_i(2'b11),
+		.BE_A2_i(2'b11),
+
+		.WDATA_B1_i(18'h0),
+		.WDATA_B2_i(18'h0),
+		.RDATA_B1_o(out_reg1[17:0]),
+		.RDATA_B2_o(out_reg2[17:0]),
+		.ADDR_B1_i(14'h0),
+		.ADDR_B2_i(14'h0),
+		.CLK_B1_i(Pop_Clk1),
+		.CLK_B2_i(Pop_Clk2),
+		.REN_B1_i(POP1),
+		.REN_B2_i(POP2),
+		.WEN_B1_i(1'b0),
+		.WEN_B2_i(1'b0),
+		.BE_B1_i(2'b11),
+		.BE_B2_i(2'b11),
+
+		.FLUSH1_i(Async_Flush1),
+		.FLUSH2_i(Async_Flush2)
+	);
+
+  generate
+    if (RD_DATA_WIDTH == 9) begin
+      assign DOUT1[RD_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]};
+      assign DOUT2[RD_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]};
+    end else begin
+      assign DOUT1[RD_DATA_WIDTH-1:0] = out_reg1[RD_DATA_WIDTH-1:0];
+      assign DOUT2[RD_DATA_WIDTH-1:0] = out_reg2[RD_DATA_WIDTH-1:0];
+    end
+  endgenerate 
+
+endmodule
+
+module BRAM2x18_AFIFO (
+    DIN1,
+    PUSH1,
+    POP1,
+    Push_Clk1,
+    Pop_Clk1,
+    Async_Flush1,
+    Overrun_Error1,
+    Full_Watermark1,
+    Almost_Full1,
+    Full1,
+    Underrun_Error1,
+    Empty_Watermark1,
+    Almost_Empty1,
+    Empty1,
+    DOUT1,
+    
+    DIN2,
+    PUSH2,
+    POP2,
+    Push_Clk2,
+    Pop_Clk2,
+    Async_Flush2,
+    Overrun_Error2,
+    Full_Watermark2,
+    Almost_Full2,
+    Full2,
+    Underrun_Error2,
+    Empty_Watermark2,
+    Almost_Empty2,
+    Empty2,
+    DOUT2
+);
+
+  parameter WR_DATA_WIDTH = 18;
+  parameter RD_DATA_WIDTH = 18;
+
+  
+  parameter UPAE_DBITS1 = 11'd10;
+  parameter UPAF_DBITS1 = 11'd10;
+  
+  parameter UPAE_DBITS2 = 11'd10;
+  parameter UPAF_DBITS2 = 11'd10;
+
+  input Push_Clk1, Pop_Clk1;
+  input PUSH1, POP1;
+  input [WR_DATA_WIDTH-1:0] DIN1;
+  input Async_Flush1;
+  output [RD_DATA_WIDTH-1:0] DOUT1;
+  output Almost_Full1, Almost_Empty1;
+  output Full1, Empty1;
+  output Full_Watermark1, Empty_Watermark1;
+  output Overrun_Error1, Underrun_Error1;
+  
+  input Push_Clk2, Pop_Clk2;
+  input PUSH2, POP2;
+  input [WR_DATA_WIDTH-1:0] DIN2;
+  input Async_Flush2;
+  output [RD_DATA_WIDTH-1:0] DOUT2;
+  output Almost_Full2, Almost_Empty2;
+  output Full2, Empty2;
+  output Full_Watermark2, Empty_Watermark2;
+  output Overrun_Error2, Underrun_Error2;
+  
+  wire [17:0] in_reg1;
+  wire [17:0] out_reg1;
+  wire [17:0] fifo1_flags;
+  
+  wire [17:0] in_reg2;
+  wire [17:0] out_reg2;
+  wire [17:0] fifo2_flags;
+  
+  assign Overrun_Error1 = fifo1_flags[0];
+  assign Full_Watermark1 = fifo1_flags[1];
+  assign Almost_Full1 = fifo1_flags[2];
+  assign Full1 = fifo1_flags[3];
+  assign Underrun_Error1 = fifo1_flags[4];
+  assign Empty_Watermark1 = fifo1_flags[5];
+  assign Almost_Empty1 = fifo1_flags[6];
+  assign Empty1 = fifo1_flags[7];
+  
+  assign Overrun_Error2 = fifo2_flags[0];
+  assign Full_Watermark2 = fifo2_flags[1];
+  assign Almost_Full2 = fifo2_flags[2];
+  assign Full2 = fifo2_flags[3];
+  assign Underrun_Error2 = fifo2_flags[4];
+  assign Empty_Watermark2 = fifo2_flags[5];
+  assign Almost_Empty2 = fifo2_flags[6];
+  assign Empty2 = fifo2_flags[7];
+  
+  generate
+    if (WR_DATA_WIDTH == 18) begin
+      assign in_reg1[17:0] = DIN1[17:0];
+      assign in_reg2[17:0] = DIN2[17:0];
+    end else if (WR_DATA_WIDTH == 9) begin
+      assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]};
+      assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]};
+    end else begin
+      assign in_reg1[17:WR_DATA_WIDTH]  = 0;
+      assign in_reg1[WR_DATA_WIDTH-1:0] = DIN1[WR_DATA_WIDTH-1:0];
+      assign in_reg2[17:WR_DATA_WIDTH]  = 0;
+      assign in_reg2[WR_DATA_WIDTH-1:0] = DIN2[WR_DATA_WIDTH-1:0];
+    end
+  endgenerate     
+  
+ case (RD_DATA_WIDTH)
+	8, 9: begin
+		case (WR_DATA_WIDTH)
+			8, 9: begin
+				defparam U1.MODE_BITS = { 1'b1,
+					UPAF_DBITS2, UPAE_DBITS2, 4'h1, `MODE_9, `MODE_9, `MODE_9, `MODE_9, 1'b0,
+					1'b0, UPAF_DBITS1, 1'b0, UPAE_DBITS1, 4'h1, `MODE_9, `MODE_9, `MODE_9, `MODE_9, 1'b0
+				};
+			end
+			16, 18: begin
+				defparam U1.MODE_BITS = { 1'b1,
+					UPAF_DBITS2, UPAE_DBITS2, 4'h1, `MODE_9, `MODE_18, `MODE_9, `MODE_18, 1'b0,
+					1'b0, UPAF_DBITS1, 1'b0, UPAE_DBITS1, 4'h1, `MODE_9, `MODE_18, `MODE_9, `MODE_18, 1'b0
+				};
+			end
+			default: begin
+				defparam U1.MODE_BITS = { 1'b1,
+					UPAF_DBITS2, UPAE_DBITS2, 4'h1, `MODE_9, `MODE_9, `MODE_9, `MODE_9, 1'b0,
+					1'b0, UPAF_DBITS1, 1'b0, UPAE_DBITS1, 4'h1, `MODE_9, `MODE_9, `MODE_9, `MODE_9, 1'b0
+				};
+			end
+		endcase
+	end
+	16, 18: begin
+		case (WR_DATA_WIDTH)
+			8, 9: begin
+				defparam U1.MODE_BITS = { 1'b1,
+					UPAF_DBITS2, UPAE_DBITS2, 4'h1, `MODE_18, `MODE_9, `MODE_18, `MODE_9, 1'b0,
+					1'b0, UPAF_DBITS1, 1'b0, UPAE_DBITS1, 4'h1, `MODE_18, `MODE_9, `MODE_18, `MODE_9, 1'b0
+				};
+			end
+			16, 18: begin
+				defparam U1.MODE_BITS = { 1'b1,
+					UPAF_DBITS2, UPAE_DBITS2, 4'h1, `MODE_18, `MODE_18, `MODE_18, `MODE_18, 1'b0,
+					1'b0, UPAF_DBITS1, 1'b0, UPAE_DBITS1, 4'h1, `MODE_18, `MODE_18, `MODE_18, `MODE_18, 1'b0
+				};
+			end
+			default: begin
+				defparam U1.MODE_BITS = { 1'b1,
+					UPAF_DBITS2, UPAE_DBITS2, 4'h1, `MODE_18, `MODE_18, `MODE_18, `MODE_18, 1'b0,
+					1'b0, UPAF_DBITS1, 1'b0, UPAE_DBITS1, 4'h1, `MODE_18, `MODE_18, `MODE_18, `MODE_18, 1'b0
+				};
+			end
+		endcase
+	end
+	default: begin
+		case (WR_DATA_WIDTH)
+			8, 9: begin
+				defparam U1.MODE_BITS = { 1'b1,
+					UPAF_DBITS2, UPAE_DBITS2, 4'h1, `MODE_9, `MODE_9, `MODE_9, `MODE_9, 1'b0,
+					1'b0, UPAF_DBITS1, 1'b0, UPAE_DBITS1, 4'h1, `MODE_9, `MODE_9, `MODE_9, `MODE_9, 1'b0
+				};
+			end
+			16, 18: begin
+				defparam U1.MODE_BITS = { 1'b1,
+					UPAF_DBITS2, UPAE_DBITS2, 4'h1, `MODE_18, `MODE_18, `MODE_18, `MODE_18, 1'b0,
+					1'b0, UPAF_DBITS1, 1'b0, UPAE_DBITS1, 4'h1, `MODE_18, `MODE_18, `MODE_18, `MODE_18, 1'b0
+				};
+			end
+			default: begin
+				defparam U1.MODE_BITS = { 1'b1,
+					UPAF_DBITS2, UPAE_DBITS2, 4'h1, `MODE_18, `MODE_18, `MODE_18, `MODE_18, 1'b0,
+					1'b0, UPAF_DBITS1, 1'b0, UPAE_DBITS1, 4'h1, `MODE_18, `MODE_18, `MODE_18, `MODE_18, 1'b0
+				};
+			end
+		endcase
+	end
+  endcase
+
+  (* is_fifo = 1 *) 
+  (* sync_fifo = 0 *) 
+  (* is_split = 1 *)
+  (* rd_data_width = RD_DATA_WIDTH *)
+  (* wr_data_width = WR_DATA_WIDTH *) 
+ 	TDP36K U1 (
+		.RESET_ni(1'b1),
+		.WDATA_A1_i(in_reg1[17:0]),
+		.WDATA_A2_i(in_reg2[17:0]),
+		.RDATA_A1_o(fifo1_flags),
+		.RDATA_A2_o(fifo2_flags),
+		.ADDR_A1_i(14'h0),
+		.ADDR_A2_i(14'h0),
+		.CLK_A1_i(Push_Clk1),
+		.CLK_A2_i(Push_Clk2),
+		.REN_A1_i(1'b1),
+		.REN_A2_i(1'b1),
+		.WEN_A1_i(PUSH1),
+		.WEN_A2_i(PUSH2),
+		.BE_A1_i(2'b11),
+		.BE_A2_i(2'b11),
+
+		.WDATA_B1_i(18'h0),
+		.WDATA_B2_i(18'h0),
+		.RDATA_B1_o(out_reg1[17:0]),
+		.RDATA_B2_o(out_reg2[17:0]),
+		.ADDR_B1_i(14'h0),
+		.ADDR_B2_i(14'h0),
+		.CLK_B1_i(Pop_Clk1),
+		.CLK_B2_i(Pop_Clk2),
+		.REN_B1_i(POP1),
+		.REN_B2_i(POP2),
+		.WEN_B1_i(1'b0),
+		.WEN_B2_i(1'b0),
+		.BE_B1_i(2'b11),
+		.BE_B2_i(2'b11),
+
+		.FLUSH1_i(Async_Flush1),
+		.FLUSH2_i(Async_Flush2)
+	);
+
+  generate
+    if (RD_DATA_WIDTH == 9) begin
+      assign DOUT1[RD_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]};
+      assign DOUT2[RD_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]};
+    end else begin
+      assign DOUT1[RD_DATA_WIDTH-1:0] = out_reg1[RD_DATA_WIDTH-1:0];
+      assign DOUT2[RD_DATA_WIDTH-1:0] = out_reg2[RD_DATA_WIDTH-1:0];
+    end
+  endgenerate  
+
+endmodule
+
+module BRAM2x18_SP (
+    RESET_ni,
+    
+    WEN1_i,
+    REN1_i,
+    WR1_CLK_i,
+    RD1_CLK_i,
+    WR1_BE_i,
+    WR1_ADDR_i,
+    RD1_ADDR_i,
+    WDATA1_i,
+    RDATA1_o,
+    
+    WEN2_i,
+    REN2_i,
+    WR2_CLK_i,
+    RD2_CLK_i,
+    WR2_BE_i,
+    WR2_ADDR_i,
+    RD2_ADDR_i,
+    WDATA2_i,
+    RDATA2_o
+);
+
+parameter WR_ADDR_WIDTH = 10;
+parameter RD_ADDR_WIDTH = 10;
+parameter WR_DATA_WIDTH = 18;
+parameter RD_DATA_WIDTH = 18;
+parameter BE1_WIDTH = 2;
+parameter BE2_WIDTH = 2;
+
+input wire RESET_ni;
+
+input wire WEN1_i;
+input wire REN1_i;
+input wire WR1_CLK_i;
+input wire RD1_CLK_i;
+input wire [BE1_WIDTH-1:0] WR1_BE_i;
+input wire [WR_ADDR_WIDTH-1 :0] WR1_ADDR_i;
+input wire [RD_ADDR_WIDTH-1 :0] RD1_ADDR_i;
+input wire [WR_DATA_WIDTH-1 :0] WDATA1_i;
+output wire [RD_DATA_WIDTH-1 :0] RDATA1_o;
+
+input wire WEN2_i;
+input wire REN2_i;
+input wire WR2_CLK_i;
+input wire RD2_CLK_i;
+input wire [BE2_WIDTH-1:0] WR2_BE_i;
+input wire [WR_ADDR_WIDTH-1 :0] WR2_ADDR_i;
+input wire [RD_ADDR_WIDTH-1 :0] RD2_ADDR_i;
+input wire [WR_DATA_WIDTH-1 :0] WDATA2_i;
+output wire [RD_DATA_WIDTH-1 :0] RDATA2_o;
+
+//localparam READ_DATA_BITS_TO_SKIP = 18 - RD_DATA_WIDTH;
+
+wire [14:RD_ADDR_WIDTH] RD1_ADDR_CMPL;
+wire [14:WR_ADDR_WIDTH] WR1_ADDR_CMPL;
+wire [17:RD_DATA_WIDTH] RD1_DATA_CMPL;
+wire [17:WR_DATA_WIDTH] WR1_DATA_CMPL;
+           
+wire [14:RD_ADDR_WIDTH] RD2_ADDR_CMPL;
+wire [14:WR_ADDR_WIDTH] WR2_ADDR_CMPL;
+wire [17:RD_DATA_WIDTH] RD2_DATA_CMPL;
+wire [17:WR_DATA_WIDTH] WR2_DATA_CMPL;
+
+wire [14:0] RD1_ADDR_TOTAL;
+wire [14:0] WR1_ADDR_TOTAL;
+
+wire [14:0] RD2_ADDR_TOTAL;
+wire [14:0] WR2_ADDR_TOTAL;
+
+wire [14:0] RD1_ADDR_SHIFTED;
+wire [14:0] WR1_ADDR_SHIFTED;
+
+wire [14:0] RD2_ADDR_SHIFTED;
+wire [14:0] WR2_ADDR_SHIFTED;
+
+wire [1:0] WR1_BE;
+wire [1:0] WR2_BE;
+
+wire FLUSH1;
+wire FLUSH2;
+
+generate
+  if (WR_ADDR_WIDTH == 15) begin
+    assign WR1_ADDR_TOTAL = WR1_ADDR_i;
+    assign WR2_ADDR_TOTAL = WR2_ADDR_i;
+  end else begin
+    assign WR1_ADDR_TOTAL[14:WR_ADDR_WIDTH] = 0;
+    assign WR1_ADDR_TOTAL[WR_ADDR_WIDTH-1:0] = WR1_ADDR_i;
+    assign WR2_ADDR_TOTAL[14:WR_ADDR_WIDTH] = 0;
+    assign WR2_ADDR_TOTAL[WR_ADDR_WIDTH-1:0] = WR2_ADDR_i;
+  end
+endgenerate
+
+generate
+  if (RD_ADDR_WIDTH == 15) begin
+    assign RD1_ADDR_TOTAL = RD1_ADDR_i;
+    assign RD2_ADDR_TOTAL = RD2_ADDR_i;
+  end else begin
+    assign RD1_ADDR_TOTAL[14:RD_ADDR_WIDTH] = 0;
+    assign RD1_ADDR_TOTAL[RD_ADDR_WIDTH-1:0] = RD1_ADDR_i;
+    assign RD2_ADDR_TOTAL[14:RD_ADDR_WIDTH] = 0;
+    assign RD2_ADDR_TOTAL[RD_ADDR_WIDTH-1:0] = RD2_ADDR_i;
+  end
+endgenerate
+
+// Assign parameters
+case (RD_DATA_WIDTH)
+	1: begin
+		case (WR_DATA_WIDTH)
+			1: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, `MODE_1, `MODE_1, `MODE_1, `MODE_1, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_1, `MODE_1, `MODE_1, `MODE_1, 1'd0
+				};
+			end
+			2: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, `MODE_1, `MODE_2, `MODE_1, `MODE_2, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_1, `MODE_2, `MODE_1, `MODE_2, 1'd0
+				};
+			end
+			4: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, `MODE_1, `MODE_4, `MODE_1, `MODE_4, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_1, `MODE_4, `MODE_1, `MODE_4, 1'd0
+				};
+			end
+			8, 9: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, `MODE_1, `MODE_9, `MODE_1, `MODE_9, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_1, `MODE_9, `MODE_1, `MODE_9, 1'd0
+				};
+			end
+			16, 18: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, `MODE_1, `MODE_18, `MODE_1, `MODE_18, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_1, `MODE_18, `MODE_1, `MODE_18, 1'd0
+				};
+			end
+			default: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, `MODE_1, `MODE_1, `MODE_1, `MODE_1, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_1, `MODE_1, `MODE_1, `MODE_1, 1'd0
+				};
+			end
+		endcase
+	end
+	2: begin
+		case (WR_DATA_WIDTH)
+			1: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, `MODE_2, `MODE_1, `MODE_2, `MODE_1, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_2, `MODE_1, `MODE_2, `MODE_1, 1'd0
+				};
+			end
+			2: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, `MODE_2, `MODE_2, `MODE_2, `MODE_2, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_2, `MODE_2, `MODE_2, `MODE_2, 1'd0
+				};
+			end
+			4: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, `MODE_2, `MODE_4, `MODE_2, `MODE_4, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_2, `MODE_4, `MODE_2, `MODE_4, 1'd0
+				};
+			end
+			8, 9: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, `MODE_2, `MODE_9, `MODE_2, `MODE_9, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_2, `MODE_9, `MODE_2, `MODE_9, 1'd0
+				};
+			end
+			16, 18: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, `MODE_2, `MODE_18, `MODE_2, `MODE_18, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_2, `MODE_18, `MODE_2, `MODE_18, 1'd0
+				};
+			end
+			default: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, `MODE_2, `MODE_1, `MODE_2, `MODE_1, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_2, `MODE_1, `MODE_2, `MODE_1, 1'd0
+				};
+			end
+		endcase
+	end
+	4: begin
+		case (WR_DATA_WIDTH)
+			1: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, `MODE_4, `MODE_1, `MODE_4, `MODE_1, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_4, `MODE_1, `MODE_4, `MODE_1, 1'd0
+				};
+			end
+			2: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, `MODE_4, `MODE_2, `MODE_4, `MODE_2, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_4, `MODE_2, `MODE_4, `MODE_2, 1'd0
+				};
+			end
+			4: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, `MODE_4, `MODE_4, `MODE_4, `MODE_4, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_4, `MODE_4, `MODE_4, `MODE_4, 1'd0
+				};
+			end
+			8, 9: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, `MODE_4, `MODE_9, `MODE_4, `MODE_9, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_4, `MODE_9, `MODE_4, `MODE_9, 1'd0
+				};
+			end
+			16, 18: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, `MODE_4, `MODE_18, `MODE_4, `MODE_18, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_4, `MODE_18, `MODE_4, `MODE_18, 1'd0
+				};
+			end
+			default: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, `MODE_4, `MODE_1, `MODE_4, `MODE_1, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_4, `MODE_1, `MODE_4, `MODE_1, 1'd0
+				};
+			end
+		endcase
+	end
+	8, 9: begin
+		case (WR_DATA_WIDTH)
+			1: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, `MODE_9, `MODE_1, `MODE_9, `MODE_1, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_9, `MODE_1, `MODE_9, `MODE_1, 1'd0
+				};
+			end
+			2: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, `MODE_9, `MODE_2, `MODE_9, `MODE_2, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_9, `MODE_2, `MODE_9, `MODE_2, 1'd0
+				};
+			end
+			4: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, `MODE_9, `MODE_4, `MODE_9, `MODE_4, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_9, `MODE_4, `MODE_9, `MODE_4, 1'd0
+				};
+			end
+			8, 9: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, `MODE_9, `MODE_9, `MODE_9, `MODE_9, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_9, `MODE_9, `MODE_9, `MODE_9, 1'd0
+				};
+			end
+			16, 18: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, `MODE_9, `MODE_18, `MODE_9, `MODE_18, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_9, `MODE_18, `MODE_9, `MODE_18, 1'd0
+				};
+			end
+			default: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, `MODE_9, `MODE_1, `MODE_9, `MODE_1, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_9, `MODE_1, `MODE_9, `MODE_1, 1'd0
+				};
+			end
+		endcase
+	end
+	16, 18: begin
+		case (WR_DATA_WIDTH)
+			1: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, `MODE_18, `MODE_1, `MODE_18, `MODE_1, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_18, `MODE_1, `MODE_18, `MODE_1, 1'd0
+				};
+			end
+			2: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, `MODE_18, `MODE_2, `MODE_18, `MODE_2, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_18, `MODE_2, `MODE_18, `MODE_2, 1'd0
+				};
+			end
+			4: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, `MODE_18, `MODE_4, `MODE_18, `MODE_4, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_18, `MODE_4, `MODE_18, `MODE_4, 1'd0
+				};
+			end
+			8, 9: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, `MODE_18, `MODE_9, `MODE_18, `MODE_9, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_18, `MODE_9, `MODE_18, `MODE_9, 1'd0
+				};
+			end
+			16, 18: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, `MODE_18, `MODE_18, `MODE_18, `MODE_18, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_18, `MODE_18, `MODE_18, `MODE_18, 1'd0
+				};
+			end
+			default: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, `MODE_18, `MODE_1, `MODE_18, `MODE_1, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_18, `MODE_1, `MODE_18, `MODE_1, 1'd0
+				};
+			end
+		endcase
+	end
+	default: begin
+		case (WR_DATA_WIDTH)
+			1: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, `MODE_1, `MODE_1, `MODE_1, `MODE_1, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_1, `MODE_1, `MODE_1, `MODE_1, 1'd0
+				};
+			end
+			2: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, `MODE_1, `MODE_2, `MODE_1, `MODE_2, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_1, `MODE_2, `MODE_1, `MODE_2, 1'd0
+				};
+			end
+			4: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, `MODE_1, `MODE_4, `MODE_1, `MODE_4, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_1, `MODE_4, `MODE_1, `MODE_4, 1'd0
+				};
+			end
+			8, 9: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, `MODE_1, `MODE_9, `MODE_1, `MODE_9, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_1, `MODE_9, `MODE_1, `MODE_9, 1'd0
+				};
+			end
+			16, 18: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, `MODE_1, `MODE_18, `MODE_1, `MODE_18, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_1, `MODE_18, `MODE_1, `MODE_18, 1'd0
+				};
+			end
+			default: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, `MODE_1, `MODE_1, `MODE_1, `MODE_1, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_1, `MODE_1, `MODE_1, `MODE_1, 1'd0
+				};
+			end
+		endcase
+	end
+endcase
+
+// Apply shift
+case (RD_DATA_WIDTH)
+	1: begin
+		assign RD1_ADDR_SHIFTED = RD1_ADDR_TOTAL;
+	end
+	2: begin
+		assign RD1_ADDR_SHIFTED = RD1_ADDR_TOTAL << 1;
+	end
+	4: begin
+		assign RD1_ADDR_SHIFTED = RD1_ADDR_TOTAL << 2;
+	end
+	8, 9: begin
+		assign RD1_ADDR_SHIFTED = RD1_ADDR_TOTAL << 3;
+	end
+	16, 18: begin
+		assign RD1_ADDR_SHIFTED = RD1_ADDR_TOTAL << 4;
+	end
+	default: begin
+		assign RD1_ADDR_SHIFTED = RD1_ADDR_TOTAL;
+	end
+endcase
+
+case (WR_DATA_WIDTH)
+	1: begin
+		assign WR1_ADDR_SHIFTED = WR1_ADDR_TOTAL;
+	end
+	2: begin
+		assign WR1_ADDR_SHIFTED = WR1_ADDR_TOTAL << 1;
+	end
+	4: begin
+		assign WR1_ADDR_SHIFTED = WR1_ADDR_TOTAL << 2;
+	end
+	8, 9: begin
+		assign WR1_ADDR_SHIFTED = WR1_ADDR_TOTAL << 3;
+	end
+	16, 18: begin
+		assign WR1_ADDR_SHIFTED = WR1_ADDR_TOTAL << 4;
+	end
+	default: begin
+		assign WR1_ADDR_SHIFTED = WR1_ADDR_TOTAL;
+	end
+endcase
+
+case (RD_DATA_WIDTH)
+	1: begin
+		assign RD2_ADDR_SHIFTED = RD2_ADDR_TOTAL;
+	end
+	2: begin
+		assign RD2_ADDR_SHIFTED = RD2_ADDR_TOTAL << 1;
+	end
+	4: begin
+		assign RD2_ADDR_SHIFTED = RD2_ADDR_TOTAL << 2;
+	end
+	8, 9: begin
+		assign RD2_ADDR_SHIFTED = RD2_ADDR_TOTAL << 3;
+	end
+	16, 18: begin
+		assign RD2_ADDR_SHIFTED = RD2_ADDR_TOTAL << 4;
+	end
+	default: begin
+		assign RD2_ADDR_SHIFTED = RD2_ADDR_TOTAL;
+	end
+endcase
+
+case (WR_DATA_WIDTH)
+	1: begin
+		assign WR2_ADDR_SHIFTED = WR2_ADDR_TOTAL;
+	end
+	2: begin
+		assign WR2_ADDR_SHIFTED = WR2_ADDR_TOTAL << 1;
+	end
+	4: begin
+		assign WR2_ADDR_SHIFTED = WR2_ADDR_TOTAL << 2;
+	end
+	8, 9: begin
+		assign WR2_ADDR_SHIFTED = WR2_ADDR_TOTAL << 3;
+	end
+	16, 18: begin
+		assign WR2_ADDR_SHIFTED = WR2_ADDR_TOTAL << 4;
+	end
+	default: begin
+		assign WR2_ADDR_SHIFTED = WR2_ADDR_TOTAL;
+	end
+endcase
+
+case (BE1_WIDTH)
+	2: begin
+		assign WR1_BE = WR1_BE_i[BE1_WIDTH-1 :0];
+	end
+	default: begin
+		assign WR1_BE[1:BE1_WIDTH] = 0;
+    assign WR1_BE[BE1_WIDTH-1 :0] = WR1_BE_i[BE1_WIDTH-1 :0];
+	end
+endcase
+
+case (BE2_WIDTH)
+	2: begin
+		assign WR2_BE = WR2_BE_i[BE2_WIDTH-1 :0];
+	end
+	default: begin
+		assign WR2_BE[1:BE2_WIDTH] = 0;
+    assign WR2_BE[BE2_WIDTH-1 :0] = WR2_BE_i[BE2_WIDTH-1 :0];
+	end
+endcase
+
+assign FLUSH1 = 1'b0;
+assign FLUSH2 = 1'b0;
+
+// TODO configure per width
+wire [17:0] PORT_B1_RDATA;
+wire [17:0] PORT_B2_RDATA;
+wire [17:0] PORT_A1_WDATA;
+wire [17:0] PORT_A2_WDATA;
+
+generate
+  if (WR_DATA_WIDTH == 18) begin
+    assign PORT_A1_WDATA[WR_DATA_WIDTH-1:0] = WDATA1_i[WR_DATA_WIDTH-1:0];
+    assign PORT_A2_WDATA[WR_DATA_WIDTH-1:0] = WDATA2_i[WR_DATA_WIDTH-1:0];
+  end else if (WR_DATA_WIDTH == 9) begin
+    assign PORT_A1_WDATA = {19'h0, WDATA1_i[8], 8'h0, WDATA1_i[7:0]};
+    assign PORT_A2_WDATA = {19'h0, WDATA2_i[8], 8'h0, WDATA2_i[7:0]};
+  end else begin
+    assign PORT_A1_WDATA[17:WR_DATA_WIDTH] = 0;
+    assign PORT_A1_WDATA[WR_DATA_WIDTH-1:0] = WDATA1_i[WR_DATA_WIDTH-1:0];
+    assign PORT_A2_WDATA[17:WR_DATA_WIDTH] = 0;
+    assign PORT_A2_WDATA[WR_DATA_WIDTH-1:0] = WDATA2_i[WR_DATA_WIDTH-1:0];
+  end
+endgenerate
+
+case (RD_DATA_WIDTH)
+	9: begin
+		assign RDATA1_o = {PORT_B1_RDATA[16], PORT_B1_RDATA[7:0]};
+    assign RDATA2_o = {PORT_B2_RDATA[16], PORT_B2_RDATA[7:0]};
+	end
+	default: begin
+		assign RDATA1_o = PORT_B1_RDATA[RD_DATA_WIDTH-1:0];
+    assign RDATA2_o = PORT_B2_RDATA[RD_DATA_WIDTH-1:0];
+	end
+endcase
+
+(* is_inferred = 1 *)
+(* is_split = 1 *)
+(* rd_data_width = RD_DATA_WIDTH *)
+(* wr_data_width = WR_DATA_WIDTH *)
+TDP36K BRAM_BLK (
+	.RESET_ni(RESET_ni),
+
+  .WDATA_A1_i(PORT_A1_WDATA),
+  .RDATA_A1_o(),
+  .ADDR_A1_i(WR1_ADDR_SHIFTED),
+  .CLK_A1_i(WR1_CLK_i),
+  .REN_A1_i(),
+  .WEN_A1_i(WEN1_i),
+  .BE_A1_i(WR1_BE[1:0]),
+  
+  .WDATA_B1_i(18'h0),
+  .RDATA_B1_o(PORT_B1_RDATA),
+  .ADDR_B1_i(RD1_ADDR_SHIFTED),
+  .CLK_B1_i(RD1_CLK_i),
+  .REN_B1_i(REN1_i),
+  .WEN_B1_i(1'b0),
+  .BE_B1_i({REN1_i,REN1_i}),
+  
+  .WDATA_A2_i(PORT_A2_WDATA),
+  .RDATA_A2_o(),
+  .ADDR_A2_i(WR2_ADDR_SHIFTED),
+  .CLK_A2_i(WR2_CLK_i),
+  .REN_A2_i(1'b0),
+  .WEN_A2_i(WEN2_i),
+  .BE_A2_i(WR2_BE[1:0]),
+  
+  .WDATA_B2_i(18'h0),
+  .RDATA_B2_o(PORT_B2_RDATA),
+  .ADDR_B2_i(RD2_ADDR_SHIFTED),
+  .CLK_B2_i(RD2_CLK_i),
+  .REN_B2_i(REN2_i),
+  .WEN_B2_i(1'b0),
+  .BE_B2_i({REN2_i,REN2_i}),
+
+	.FLUSH1_i(FLUSH1),
+	.FLUSH2_i(FLUSH2)
+);
+
+endmodule
+
+module BRAM2x18_DP (A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN, C1ADDR, C1DATA, C1EN, CLK1, CLK2, CLK3, CLK4, D1ADDR, D1DATA, D1EN, E1ADDR, E1DATA, E1EN, F1ADDR, F1DATA, F1EN, G1ADDR, G1DATA, G1EN, H1ADDR, H1DATA, H1EN);
+	parameter CFG_ABITS = 11;
+	parameter CFG_DBITS = 18;
+	parameter CFG_ENABLE_B = 4;
+	parameter CFG_ENABLE_D = 4;
+	parameter CFG_ENABLE_F = 4;
+	parameter CFG_ENABLE_H = 4;
+
+	parameter CLKPOL2 = 1;
+	parameter CLKPOL3 = 1;
+	parameter [18431:0] INIT0 = 18432'bx;
+	parameter [18431:0] INIT1 = 18432'bx;
+
+	input CLK1;
+	input CLK2;
+	input CLK3;
+	input CLK4;
+
+	input [CFG_ABITS-1:0] A1ADDR;
+	output [CFG_DBITS-1:0] A1DATA;
+	input A1EN;
+
+	input [CFG_ABITS-1:0] B1ADDR;
+	input [CFG_DBITS-1:0] B1DATA;
+	input [CFG_ENABLE_B-1:0] B1EN;
+
+	input [CFG_ABITS-1:0] C1ADDR;
+	output [CFG_DBITS-1:0] C1DATA;
+	input C1EN;
+
+	input [CFG_ABITS-1:0] D1ADDR;
+	input [CFG_DBITS-1:0] D1DATA;
+	input [CFG_ENABLE_D-1:0] D1EN;
+
+	input [CFG_ABITS-1:0] E1ADDR;
+	output [CFG_DBITS-1:0] E1DATA;
+	input E1EN;
+
+	input [CFG_ABITS-1:0] F1ADDR;
+	input [CFG_DBITS-1:0] F1DATA;
+	input [CFG_ENABLE_F-1:0] F1EN;
+
+	input [CFG_ABITS-1:0] G1ADDR;
+	output [CFG_DBITS-1:0] G1DATA;
+	input G1EN;
+
+	input [CFG_ABITS-1:0] H1ADDR;
+	input [CFG_DBITS-1:0] H1DATA;
+	input [CFG_ENABLE_H-1:0] H1EN;
+
+	wire FLUSH1;
+	wire FLUSH2;
+
+	wire [14:0] A1ADDR_TOTAL;
+	wire [14:0] B1ADDR_TOTAL;
+	wire [14:0] C1ADDR_TOTAL;
+	wire [14:0] D1ADDR_TOTAL;
+	wire [14:0] E1ADDR_TOTAL;
+	wire [14:0] F1ADDR_TOTAL;
+	wire [14:0] G1ADDR_TOTAL;
+	wire [14:0] H1ADDR_TOTAL;
+  
+  generate
+    if (CFG_ABITS == 15) begin
+      assign A1ADDR_TOTAL = A1ADDR;
+      assign B1ADDR_TOTAL = B1ADDR;
+      assign C1ADDR_TOTAL = C1ADDR;
+      assign D1ADDR_TOTAL = D1ADDR;
+      assign E1ADDR_TOTAL = E1ADDR;
+      assign F1ADDR_TOTAL = F1ADDR;
+      assign G1ADDR_TOTAL = G1ADDR;
+      assign H1ADDR_TOTAL = H1ADDR;
+    end else begin
+      assign A1ADDR_TOTAL[14:CFG_ABITS] = 0;
+      assign A1ADDR_TOTAL[CFG_ABITS-1:0] = A1ADDR;
+      assign B1ADDR_TOTAL[14:CFG_ABITS] = 0;
+      assign B1ADDR_TOTAL[CFG_ABITS-1:0] = B1ADDR;
+      assign C1ADDR_TOTAL[14:CFG_ABITS] = 0;
+      assign C1ADDR_TOTAL[CFG_ABITS-1:0] = C1ADDR;
+      assign D1ADDR_TOTAL[14:CFG_ABITS] = 0;
+      assign D1ADDR_TOTAL[CFG_ABITS-1:0] = D1ADDR;
+      assign E1ADDR_TOTAL[14:CFG_ABITS] = 0;
+      assign E1ADDR_TOTAL[CFG_ABITS-1:0] = E1ADDR;
+      assign F1ADDR_TOTAL[14:CFG_ABITS] = 0;
+      assign F1ADDR_TOTAL[CFG_ABITS-1:0] = F1ADDR;
+      assign G1ADDR_TOTAL[14:CFG_ABITS] = 0;
+      assign G1ADDR_TOTAL[CFG_ABITS-1:0] = G1ADDR;
+      assign H1ADDR_TOTAL[14:CFG_ABITS] = 0;
+      assign H1ADDR_TOTAL[CFG_ABITS-1:0] = H1ADDR;
+    end
+  endgenerate
+
+	wire [17:CFG_DBITS] A1_RDATA_CMPL;
+	wire [17:CFG_DBITS] C1_RDATA_CMPL;
+	wire [17:CFG_DBITS] E1_RDATA_CMPL;
+	wire [17:CFG_DBITS] G1_RDATA_CMPL;
+
+	wire [17:CFG_DBITS] B1_WDATA_CMPL = {17-CFG_DBITS{1'b0}};
+	wire [17:CFG_DBITS] D1_WDATA_CMPL = {17-CFG_DBITS{1'b0}};
+	wire [17:CFG_DBITS] F1_WDATA_CMPL = {17-CFG_DBITS{1'b0}};
+	wire [17:CFG_DBITS] H1_WDATA_CMPL = {17-CFG_DBITS{1'b0}};
+
+	wire [14:0] PORT_A1_ADDR;
+	wire [14:0] PORT_A2_ADDR;
+	wire [14:0] PORT_B1_ADDR;
+	wire [14:0] PORT_B2_ADDR;
+
+	case (CFG_DBITS)
+		1: begin
+			assign PORT_A1_ADDR = A1EN ? A1ADDR_TOTAL : (B1EN ? B1ADDR_TOTAL : 14'd0);
+			assign PORT_B1_ADDR = C1EN ? C1ADDR_TOTAL : (D1EN ? D1ADDR_TOTAL : 14'd0);
+			assign PORT_A2_ADDR = E1EN ? E1ADDR_TOTAL : (F1EN ? F1ADDR_TOTAL : 14'd0);
+			assign PORT_B2_ADDR = G1EN ? G1ADDR_TOTAL : (H1EN ? H1ADDR_TOTAL : 14'd0);
+			defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1,
+				11'd10, 11'd10, 4'd0, `MODE_1, `MODE_1, `MODE_1, `MODE_1, 1'd0,
+				12'd10, 12'd10, 4'd0, `MODE_1, `MODE_1, `MODE_1, `MODE_1, 1'd0
+			};
+		end
+
+		2: begin
+			assign PORT_A1_ADDR = A1EN ? (A1ADDR_TOTAL << 1) : (B1EN ? (B1ADDR_TOTAL << 1) : 14'd0);
+			assign PORT_B1_ADDR = C1EN ? (C1ADDR_TOTAL << 1) : (D1EN ? (D1ADDR_TOTAL << 1) : 14'd0);
+			assign PORT_A2_ADDR = E1EN ? (E1ADDR_TOTAL << 1) : (F1EN ? (F1ADDR_TOTAL << 1) : 14'd0);
+			assign PORT_B2_ADDR = G1EN ? (G1ADDR_TOTAL << 1) : (H1EN ? (H1ADDR_TOTAL << 1) : 14'd0);
+			defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1,
+				11'd10, 11'd10, 4'd0, `MODE_2, `MODE_2, `MODE_2, `MODE_2, 1'd0,
+				12'd10, 12'd10, 4'd0, `MODE_2, `MODE_2, `MODE_2, `MODE_2, 1'd0
+			};
+		end
+
+		4: begin
+			assign PORT_A1_ADDR = A1EN ? (A1ADDR_TOTAL << 2) : (B1EN ? (B1ADDR_TOTAL << 2) : 14'd0);
+			assign PORT_B1_ADDR = C1EN ? (C1ADDR_TOTAL << 2) : (D1EN ? (D1ADDR_TOTAL << 2) : 14'd0);
+			assign PORT_A2_ADDR = E1EN ? (E1ADDR_TOTAL << 2) : (F1EN ? (F1ADDR_TOTAL << 2) : 14'd0);
+			assign PORT_B2_ADDR = G1EN ? (G1ADDR_TOTAL << 2) : (H1EN ? (H1ADDR_TOTAL << 2) : 14'd0);
+			defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1,
+				11'd10, 11'd10, 4'd0, `MODE_4, `MODE_4, `MODE_4, `MODE_4, 1'd0,
+				12'd10, 12'd10, 4'd0, `MODE_4, `MODE_4, `MODE_4, `MODE_4, 1'd0
+			};
+		end
+
+		8, 9: begin
+			assign PORT_A1_ADDR = A1EN ? (A1ADDR_TOTAL << 3) : (B1EN ? (B1ADDR_TOTAL << 3) : 14'd0);
+			assign PORT_B1_ADDR = C1EN ? (C1ADDR_TOTAL << 3) : (D1EN ? (D1ADDR_TOTAL << 3) : 14'd0);
+			assign PORT_A2_ADDR = E1EN ? (E1ADDR_TOTAL << 3) : (F1EN ? (F1ADDR_TOTAL << 3) : 14'd0);
+			assign PORT_B2_ADDR = G1EN ? (G1ADDR_TOTAL << 3) : (H1EN ? (H1ADDR_TOTAL << 3) : 14'd0);
+			defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1,
+				11'd10, 11'd10, 4'd0, `MODE_9, `MODE_9, `MODE_9, `MODE_9, 1'd0,
+				12'd10, 12'd10, 4'd0, `MODE_9, `MODE_9, `MODE_9, `MODE_9, 1'd0
+			};
+		end
+
+		16, 18: begin
+			assign PORT_A1_ADDR = A1EN ? (A1ADDR_TOTAL << 4) : (B1EN ? (B1ADDR_TOTAL << 4) : 14'd0);
+			assign PORT_B1_ADDR = C1EN ? (C1ADDR_TOTAL << 4) : (D1EN ? (D1ADDR_TOTAL << 4) : 14'd0);
+			assign PORT_A2_ADDR = E1EN ? (E1ADDR_TOTAL << 4) : (F1EN ? (F1ADDR_TOTAL << 4) : 14'd0);
+			assign PORT_B2_ADDR = G1EN ? (G1ADDR_TOTAL << 4) : (H1EN ? (H1ADDR_TOTAL << 4) : 14'd0);
+			defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1,
+				11'd10, 11'd10, 4'd0, `MODE_18, `MODE_18, `MODE_18, `MODE_18, 1'd0,
+				12'd10, 12'd10, 4'd0, `MODE_18, `MODE_18, `MODE_18, `MODE_18, 1'd0
+			};
+		end
+
+		default: begin
+			assign PORT_A1_ADDR = A1EN ? A1ADDR_TOTAL : (B1EN ? B1ADDR_TOTAL : 14'd0);
+			assign PORT_B1_ADDR = C1EN ? C1ADDR_TOTAL : (D1EN ? D1ADDR_TOTAL : 14'd0);
+			assign PORT_A2_ADDR = E1EN ? E1ADDR_TOTAL : (F1EN ? F1ADDR_TOTAL : 14'd0);
+			assign PORT_B2_ADDR = G1EN ? G1ADDR_TOTAL : (H1EN ? H1ADDR_TOTAL : 14'd0);
+			defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1,
+				11'd10, 11'd10, 4'd0, `MODE_36, `MODE_36, `MODE_36, `MODE_36, 1'd0,
+				12'd10, 12'd10, 4'd0, `MODE_36, `MODE_36, `MODE_36, `MODE_36, 1'd0
+			};
+		end
+	endcase
+
+	assign FLUSH1 = 1'b0;
+	assign FLUSH2 = 1'b0;
+
+	wire [17:0] PORT_A1_RDATA;
+	wire [17:0] PORT_B1_RDATA;
+	wire [17:0] PORT_A2_RDATA;
+	wire [17:0] PORT_B2_RDATA;
+
+	wire [17:0] PORT_A1_WDATA;
+	wire [17:0] PORT_B1_WDATA;
+	wire [17:0] PORT_A2_WDATA;
+	wire [17:0] PORT_B2_WDATA;
+
+	// Assign read/write data - handle special case for 9bit mode
+	// parity bit for 9bit mode is placed in R/W port on bit #16
+	case (CFG_DBITS)
+		9: begin
+			assign A1DATA = {PORT_A1_RDATA[16], PORT_A1_RDATA[7:0]};
+			assign C1DATA = {PORT_B1_RDATA[16], PORT_B1_RDATA[7:0]};
+			assign E1DATA = {PORT_A2_RDATA[16], PORT_A2_RDATA[7:0]};
+			assign G1DATA = {PORT_B2_RDATA[16], PORT_B2_RDATA[7:0]};
+			assign PORT_A1_WDATA = {B1_WDATA_CMPL[17], B1DATA[8], B1_WDATA_CMPL[16:9], B1DATA[7:0]};
+			assign PORT_B1_WDATA = {D1_WDATA_CMPL[17], D1DATA[8], D1_WDATA_CMPL[16:9], D1DATA[7:0]};
+			assign PORT_A2_WDATA = {F1_WDATA_CMPL[17], F1DATA[8], F1_WDATA_CMPL[16:9], F1DATA[7:0]};
+			assign PORT_B2_WDATA = {H1_WDATA_CMPL[17], H1DATA[8], H1_WDATA_CMPL[16:9], H1DATA[7:0]};
+		end
+		default: begin
+			assign A1DATA = PORT_A1_RDATA[CFG_DBITS-1:0];
+			assign C1DATA = PORT_B1_RDATA[CFG_DBITS-1:0];
+			assign E1DATA = PORT_A2_RDATA[CFG_DBITS-1:0];
+			assign G1DATA = PORT_B2_RDATA[CFG_DBITS-1:0];
+			assign PORT_A1_WDATA = {B1_WDATA_CMPL, B1DATA};
+			assign PORT_B1_WDATA = {D1_WDATA_CMPL, D1DATA};
+			assign PORT_A2_WDATA = {F1_WDATA_CMPL, F1DATA};
+			assign PORT_B2_WDATA = {H1_WDATA_CMPL, H1DATA};
+
+		end
+	endcase
+
+	wire PORT_A1_CLK = CLK1;
+	wire PORT_A2_CLK = CLK3;
+	wire PORT_B1_CLK = CLK2;
+	wire PORT_B2_CLK = CLK4;
+
+	wire PORT_A1_REN = A1EN;
+	wire PORT_A1_WEN = B1EN[0];
+	wire [CFG_ENABLE_B-1:0] PORT_A1_BE = {B1EN[1],B1EN[0]};
+
+	wire PORT_A2_REN = E1EN;
+	wire PORT_A2_WEN = F1EN[0];
+	wire [CFG_ENABLE_F-1:0] PORT_A2_BE = {F1EN[1],F1EN[0]};
+
+	wire PORT_B1_REN = C1EN;
+	wire PORT_B1_WEN = D1EN[0];
+	wire [CFG_ENABLE_D-1:0] PORT_B1_BE = {D1EN[1],D1EN[0]};
+
+	wire PORT_B2_REN = G1EN;
+	wire PORT_B2_WEN = H1EN[0];
+	wire [CFG_ENABLE_H-1:0] PORT_B2_BE = {H1EN[1],H1EN[0]};
+
+    (* is_split = 1 *)
+    (* rd_data_width = CFG_DBITS *)
+    (* wr_data_width = CFG_DBITS *)
 	TDP36K  _TECHMAP_REPLACE_ (
 		.WDATA_A1_i(PORT_A1_WDATA),
 		.RDATA_A1_o(PORT_A1_RDATA),
diff --git a/ql-qlf-plugin/qlf_k6n10f/brams_map.v b/ql-qlf-plugin/qlf_k6n10f/brams_map.v
index 873a5d7..1c97e8f 100644
--- a/ql-qlf-plugin/qlf_k6n10f/brams_map.v
+++ b/ql-qlf-plugin/qlf_k6n10f/brams_map.v
@@ -163,6 +163,9 @@
 	assign FLUSH1 = 1'b0;
 	assign FLUSH2 = 1'b0;
 
+    (* is_inferred = 1 *)
+    (* rd_data_width = CFG_DBITS *)
+    (* wr_data_width = CFG_DBITS *)
 	TDP36K _TECHMAP_REPLACE_ (
 		.RESET_ni(1'b1),
 		.WDATA_A1_i(B1DATA_TOTAL[17:0]),
@@ -233,6 +236,7 @@
 	input [CFG_DBITS-1:0] D1DATA;
 	input [CFG_ENABLE_D-1:0] D1EN;
 
+    (* is_inferred = 1 *)
 	BRAM2x18_TDP #(
 		.CFG_ABITS(CFG_ABITS),
 		.CFG_DBITS(CFG_DBITS),
@@ -240,7 +244,7 @@
 		.CFG_ENABLE_D(CFG_ENABLE_D),
 		.CLKPOL2(CLKPOL2),
 		.CLKPOL3(CLKPOL3),
-		.INIT0(INIT),
+		.INIT0(INIT)
 	) _TECHMAP_REPLACE_ (
 		.A1ADDR(A1ADDR),
 		.A1DATA(A1DATA),
@@ -296,13 +300,14 @@
 	input [CFG_DBITS-1:0] B1DATA;
 	input [CFG_ENABLE_B-1:0] B1EN;
 
+    (* is_inferred = 1 *)
 	BRAM2x18_SDP #(
 		.CFG_ABITS(CFG_ABITS),
 		.CFG_DBITS(CFG_DBITS),
 		.CFG_ENABLE_B(CFG_ENABLE_B),
 		.CLKPOL2(CLKPOL2),
 		.CLKPOL3(CLKPOL3),
-		.INIT0(INIT),
+		.INIT0(INIT)
 	) _TECHMAP_REPLACE_ (
 		.A1ADDR(A1ADDR),
 		.A1DATA(A1DATA),
@@ -446,6 +451,9 @@
 	assign FLUSH1 = 1'b0;
 	assign FLUSH2 = 1'b0;
 
+    (* is_inferred = 1 *)
+    (* rd_data_width = CFG_DBITS *)
+    (* wr_data_width = CFG_DBITS *)
 	TDP36K _TECHMAP_REPLACE_ (
 		.RESET_ni(1'b1),
 		.WDATA_A1_i(18'h3FFFF),
@@ -534,7 +542,7 @@
 	input RD_SRST;
 
 	input [RD_ADDR_WIDTH-1:0] RD_ADDR;
-	output [RD_DATA_WIDTH-1:0] RD_DATA;
+	output reg [RD_DATA_WIDTH-1:0] RD_DATA;
 	input RD_EN;
 
 	input [WR_ADDR_WIDTH-1:0] WR_ADDR;
@@ -543,7 +551,7 @@
 
 	wire [14:RD_ADDR_WIDTH] RD_ADDR_CMPL;
 	wire [14:WR_ADDR_WIDTH] WR_ADDR_CMPL;
-	wire [35:RD_DATA_WIDTH] RD_DATA_CMPL;
+	reg [35:RD_DATA_WIDTH] RD_DATA_CMPL;
 	wire [35:WR_DATA_WIDTH] WR_DATA_CMPL;
 
 	wire [14:0] RD_ADDR_TOTAL;
@@ -968,6 +976,9 @@
 	wire PORT_A2_WEN = WR_EN;
 	wire [1:0] PORT_A2_BE = {PORT_A2_WEN, PORT_A2_WEN};
 
+    (* is_inferred = 1 *)
+    (* rd_data_width = RD_DATA_WIDTH *)
+    (* wr_data_width = WR_DATA_WIDTH *)
 	TDP36K _TECHMAP_REPLACE_ (
 		.RESET_ni(1'b1),
 
@@ -1008,3 +1019,1522 @@
 	);
 endmodule
 
+module SFIFO_36K_BLK (
+    DIN,
+    PUSH,
+    POP,
+    CLK,
+    Async_Flush,
+    Overrun_Error,
+    Full_Watermark,
+    Almost_Full,
+    Full,
+    Underrun_Error,
+    Empty_Watermark,
+    Almost_Empty,
+    Empty,
+    DOUT
+);
+
+  parameter WR_DATA_WIDTH = 36;
+  parameter RD_DATA_WIDTH = 36;
+  parameter UPAE_DBITS = 12'd10;
+  parameter UPAF_DBITS = 12'd10;
+
+  input wire CLK;
+  input wire PUSH, POP;
+  input wire [WR_DATA_WIDTH-1:0] DIN;
+  input wire Async_Flush;
+  output wire [RD_DATA_WIDTH-1:0] DOUT;
+  output wire Almost_Full, Almost_Empty;
+  output wire Full, Empty;
+  output wire Full_Watermark, Empty_Watermark;
+  output wire Overrun_Error, Underrun_Error;
+  
+  wire [35:0] in_reg;
+  wire [35:0] out_reg;
+  wire [17:0] fifo_flags;
+  
+  wire [35:0] RD_DATA_CMPL;
+  wire [35:WR_DATA_WIDTH] WR_DATA_CMPL;
+  
+  wire Push_Clk, Pop_Clk;
+  
+  assign Push_Clk = CLK;
+  assign Pop_Clk = CLK;
+  
+  assign Overrun_Error = fifo_flags[0];
+  assign Full_Watermark = fifo_flags[1];
+  assign Almost_Full = fifo_flags[2];
+  assign Full = fifo_flags[3];
+  assign Underrun_Error = fifo_flags[4];
+  assign Empty_Watermark = fifo_flags[5];
+  assign Almost_Empty = fifo_flags[6];
+  assign Empty = fifo_flags[7];
+   
+  generate
+    if (WR_DATA_WIDTH == 36) begin
+      assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0];
+    end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin
+      assign in_reg[WR_DATA_WIDTH+1:18] = DIN[WR_DATA_WIDTH-1:16];
+      assign in_reg[17:0] = {2'b00,DIN[15:0]};
+    end else if (WR_DATA_WIDTH == 9) begin
+      assign in_reg[35:0] = {19'h0, DIN[8], 8'h0, DIN[7:0]};
+    end else begin
+      assign in_reg[35:WR_DATA_WIDTH]  = 0;
+      assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0];
+    end
+  endgenerate
+  
+  generate
+    if (RD_DATA_WIDTH == 36) begin
+      assign RD_DATA_CMPL = out_reg;
+    end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin
+      assign RD_DATA_CMPL  = {2'b00,out_reg[35:18],out_reg[15:0]};
+    end else if (RD_DATA_WIDTH == 9) begin
+      assign RD_DATA_CMPL = { 27'h0, out_reg[16], out_reg[7:0]};
+    end else begin
+      assign RD_DATA_CMPL = {18'h0, out_reg[17:0]};
+    end
+  endgenerate
+  
+  case (RD_DATA_WIDTH)
+	8, 9: begin
+		case (WR_DATA_WIDTH)
+			8, 9: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_9, `MODE_9, `MODE_9, `MODE_9, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, `MODE_9, `MODE_9, `MODE_9, `MODE_9, 1'b1
+				};
+			end
+			16, 18: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_9, `MODE_18, `MODE_9, `MODE_18, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, `MODE_9, `MODE_18, `MODE_9, `MODE_18, 1'b1
+				};
+			end
+			32, 36: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_9, `MODE_36, `MODE_9, `MODE_36, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, `MODE_9, `MODE_36, `MODE_9, `MODE_36, 1'b1
+				};
+			end
+			default: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_9, `MODE_9, `MODE_9, `MODE_9, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, `MODE_9, `MODE_9, `MODE_9, `MODE_9, 1'b1
+				};
+			end
+		endcase
+	end
+	16, 18: begin
+		case (WR_DATA_WIDTH)
+			8, 9: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_18, `MODE_9, `MODE_18, `MODE_9, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, `MODE_18, `MODE_9, `MODE_18, `MODE_9, 1'b1
+				};
+			end
+			16, 18: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_18, `MODE_18, `MODE_18, `MODE_18, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, `MODE_18, `MODE_18, `MODE_18, `MODE_18, 1'b1
+				};
+			end
+			32, 36: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_18, `MODE_36, `MODE_18, `MODE_36, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, `MODE_18, `MODE_36, `MODE_18, `MODE_36, 1'b1
+				};
+			end
+			default: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_18, `MODE_18, `MODE_18, `MODE_18, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, `MODE_18, `MODE_18, `MODE_18, `MODE_18, 1'b1
+				};
+			end
+		endcase
+	end
+	32, 36: begin
+		case (WR_DATA_WIDTH)
+			8, 9: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_36, `MODE_9, `MODE_36, `MODE_9, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, `MODE_36, `MODE_9, `MODE_36, `MODE_9, 1'b1
+				};
+			end
+			16, 18: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_36, `MODE_18, `MODE_36, `MODE_18, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, `MODE_36, `MODE_18, `MODE_36, `MODE_18, 1'b1
+				};
+			end
+			32, 36: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_36, `MODE_36, `MODE_36, `MODE_36, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, `MODE_36, `MODE_36, `MODE_36, `MODE_36, 1'b1
+				};
+			end
+			default: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_36, `MODE_36, `MODE_36, `MODE_36, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, `MODE_36, `MODE_36, `MODE_36, `MODE_36, 1'b1
+				};
+			end
+		endcase
+	end
+	default: begin
+		case (WR_DATA_WIDTH)
+			8, 9: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_9, `MODE_9, `MODE_9, `MODE_9, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, `MODE_9, `MODE_9, `MODE_9, `MODE_9, 1'b1
+				};
+			end
+			16, 18: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_18, `MODE_18, `MODE_18, `MODE_18, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, `MODE_18, `MODE_18, `MODE_18, `MODE_18, 1'b1
+				};
+			end
+			32, 36: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_36, `MODE_36, `MODE_36, `MODE_36, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, `MODE_36, `MODE_36, `MODE_36, `MODE_36, 1'b1
+				};
+			end
+			default: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_36, `MODE_36, `MODE_36, `MODE_36, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, `MODE_36, `MODE_36, `MODE_36, `MODE_36, 1'b1
+				};
+			end
+		endcase
+	end
+ endcase
+ 
+  (* is_fifo = 1 *)
+  (* sync_fifo = 1 *)
+  (* rd_data_width = RD_DATA_WIDTH *) 
+  (* wr_data_width = WR_DATA_WIDTH *)
+ 	TDP36K U1 (
+		.RESET_ni(1'b1),
+		.WDATA_A1_i(in_reg[17:0]),
+		.WDATA_A2_i(in_reg[35:18]),
+		.RDATA_A1_o(fifo_flags),
+		.RDATA_A2_o(),
+		.ADDR_A1_i(14'h0),
+		.ADDR_A2_i(14'h0),
+		.CLK_A1_i(Push_Clk),
+		.CLK_A2_i(1'b0),
+		.REN_A1_i(1'b1),
+		.REN_A2_i(1'b0),
+		.WEN_A1_i(PUSH),
+		.WEN_A2_i(1'b0),
+		.BE_A1_i(2'b11),
+		.BE_A2_i(2'b11),
+
+		.WDATA_B1_i(18'h0),
+		.WDATA_B2_i(18'h0),
+		.RDATA_B1_o(out_reg[17:0]),
+		.RDATA_B2_o(out_reg[35:18]),
+		.ADDR_B1_i(14'h0),
+		.ADDR_B2_i(14'h0),
+		.CLK_B1_i(Pop_Clk),
+		.CLK_B2_i(1'b0),
+		.REN_B1_i(POP),
+		.REN_B2_i(1'b0),
+		.WEN_B1_i(1'b0),
+		.WEN_B2_i(1'b0),
+		.BE_B1_i(2'b11),
+		.BE_B2_i(2'b11),
+
+		.FLUSH1_i(Async_Flush),
+		.FLUSH2_i(1'b0)
+	);
+
+  assign DOUT[RD_DATA_WIDTH-1 : 0] = RD_DATA_CMPL[RD_DATA_WIDTH-1 : 0];
+
+endmodule 
+
+module AFIFO_36K_BLK (
+    DIN,
+    PUSH,
+    POP,
+    Push_Clk,
+    Pop_Clk,
+    Async_Flush,
+    Overrun_Error,
+    Full_Watermark,
+    Almost_Full,
+    Full,
+    Underrun_Error,
+    Empty_Watermark,
+    Almost_Empty,
+    Empty,
+    DOUT
+);
+
+  parameter WR_DATA_WIDTH = 36;
+  parameter RD_DATA_WIDTH = 36;
+  parameter UPAE_DBITS = 12'd10;
+  parameter UPAF_DBITS = 12'd10;
+
+  input wire Push_Clk, Pop_Clk;
+  input wire PUSH, POP;
+  input wire [WR_DATA_WIDTH-1:0] DIN;
+  input wire Async_Flush;
+  output wire [RD_DATA_WIDTH-1:0] DOUT;
+  output wire Almost_Full, Almost_Empty;
+  output wire Full, Empty;
+  output wire Full_Watermark, Empty_Watermark;
+  output wire Overrun_Error, Underrun_Error;
+  
+  wire [35:0] in_reg;
+  wire [35:0] out_reg;
+  wire [17:0] fifo_flags;
+  
+  wire [35:0] RD_DATA_CMPL;
+  wire [35:WR_DATA_WIDTH] WR_DATA_CMPL;
+  
+  assign Overrun_Error = fifo_flags[0];
+  assign Full_Watermark = fifo_flags[1];
+  assign Almost_Full = fifo_flags[2];
+  assign Full = fifo_flags[3];
+  assign Underrun_Error = fifo_flags[4];
+  assign Empty_Watermark = fifo_flags[5];
+  assign Almost_Empty = fifo_flags[6];
+  assign Empty = fifo_flags[7];
+   
+  generate
+    if (WR_DATA_WIDTH == 36) begin
+      assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0];
+    end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin
+      assign in_reg[WR_DATA_WIDTH+1:18] = DIN[WR_DATA_WIDTH-1:16];
+      assign in_reg[17:0] = {2'b00,DIN[15:0]};
+    end else if (WR_DATA_WIDTH == 9) begin
+      assign in_reg[35:0] = {19'h0, DIN[8], 8'h0, DIN[7:0]};
+    end else begin
+      assign in_reg[35:WR_DATA_WIDTH]  = 0;
+      assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0];
+    end
+  endgenerate
+  
+  generate
+    if (RD_DATA_WIDTH == 36) begin
+      assign RD_DATA_CMPL = out_reg;
+    end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin
+      assign RD_DATA_CMPL  = {2'b00,out_reg[35:18],out_reg[15:0]};
+    end else if (RD_DATA_WIDTH == 9) begin
+      assign RD_DATA_CMPL = { 27'h0, out_reg[16], out_reg[7:0]};
+    end else begin
+      assign RD_DATA_CMPL = {18'h0, out_reg[17:0]};
+    end
+  endgenerate
+  
+  case (RD_DATA_WIDTH)
+	8, 9: begin
+		case (WR_DATA_WIDTH)
+			8, 9: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_9, `MODE_9, `MODE_9, `MODE_9, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, `MODE_9, `MODE_9, `MODE_9, `MODE_9, 1'b0
+				};
+			end
+			16, 18: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_9, `MODE_18, `MODE_9, `MODE_18, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, `MODE_9, `MODE_18, `MODE_9, `MODE_18, 1'b0
+				};
+			end
+			32, 36: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_9, `MODE_36, `MODE_9, `MODE_36, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, `MODE_9, `MODE_36, `MODE_9, `MODE_36, 1'b0
+				};
+			end
+			default: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_9, `MODE_9, `MODE_9, `MODE_9, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, `MODE_9, `MODE_9, `MODE_9, `MODE_9, 1'b0
+				};
+			end
+		endcase
+	end
+	16, 18: begin
+		case (WR_DATA_WIDTH)
+			8, 9: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_18, `MODE_9, `MODE_18, `MODE_9, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, `MODE_18, `MODE_9, `MODE_18, `MODE_9, 1'b0
+				};
+			end
+			16, 18: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_18, `MODE_18, `MODE_18, `MODE_18, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, `MODE_18, `MODE_18, `MODE_18, `MODE_18, 1'b0
+				};
+			end
+			32, 36: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_18, `MODE_36, `MODE_18, `MODE_36, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, `MODE_18, `MODE_36, `MODE_18, `MODE_36, 1'b0
+				};
+			end
+			default: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_18, `MODE_18, `MODE_18, `MODE_18, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, `MODE_18, `MODE_18, `MODE_18, `MODE_18, 1'b0
+				};
+			end
+		endcase
+	end
+	32, 36: begin
+		case (WR_DATA_WIDTH)
+			8, 9: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_36, `MODE_9, `MODE_36, `MODE_9, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, `MODE_36, `MODE_9, `MODE_36, `MODE_9, 1'b0
+				};
+			end
+			16, 18: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_36, `MODE_18, `MODE_36, `MODE_18, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, `MODE_36, `MODE_18, `MODE_36, `MODE_18, 1'b0
+				};
+			end
+			32, 36: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_36, `MODE_36, `MODE_36, `MODE_36, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, `MODE_36, `MODE_36, `MODE_36, `MODE_36, 1'b0
+				};
+			end
+			default: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_36, `MODE_36, `MODE_36, `MODE_36, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, `MODE_36, `MODE_36, `MODE_36, `MODE_36, 1'b0
+				};
+			end
+		endcase
+	end
+	default: begin
+		case (WR_DATA_WIDTH)
+			8, 9: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_9, `MODE_9, `MODE_9, `MODE_9, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, `MODE_9, `MODE_9, `MODE_9, `MODE_9, 1'b0
+				};
+			end
+			16, 18: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_18, `MODE_18, `MODE_18, `MODE_18, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, `MODE_18, `MODE_18, `MODE_18, `MODE_18, 1'b0
+				};
+			end
+			32, 36: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_36, `MODE_36, `MODE_36, `MODE_36, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, `MODE_36, `MODE_36, `MODE_36, `MODE_36, 1'b0
+				};
+			end
+			default: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_36, `MODE_36, `MODE_36, `MODE_36, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, `MODE_36, `MODE_36, `MODE_36, `MODE_36, 1'b0
+				};
+			end
+		endcase
+	end
+ endcase
+ 
+  (* is_fifo = 1 *)
+  (* sync_fifo = 0 *)
+  (* rd_data_width = RD_DATA_WIDTH *) 
+  (* wr_data_width = WR_DATA_WIDTH *)
+ 	TDP36K U1 (
+		.RESET_ni(1'b1),
+		.WDATA_A1_i(in_reg[17:0]),
+		.WDATA_A2_i(in_reg[35:18]),
+		.RDATA_A1_o(fifo_flags),
+		.RDATA_A2_o(),
+		.ADDR_A1_i(14'h0),
+		.ADDR_A2_i(14'h0),
+		.CLK_A1_i(Push_Clk),
+		.CLK_A2_i(1'b0),
+		.REN_A1_i(1'b1),
+		.REN_A2_i(1'b0),
+		.WEN_A1_i(PUSH),
+		.WEN_A2_i(1'b0),
+		.BE_A1_i(2'b11),
+		.BE_A2_i(2'b11),
+
+		.WDATA_B1_i(18'h0),
+		.WDATA_B2_i(18'h0),
+		.RDATA_B1_o(out_reg[17:0]),
+		.RDATA_B2_o(out_reg[35:18]),
+		.ADDR_B1_i(14'h0),
+		.ADDR_B2_i(14'h0),
+		.CLK_B1_i(Pop_Clk),
+		.CLK_B2_i(1'b0),
+		.REN_B1_i(POP),
+		.REN_B2_i(1'b0),
+		.WEN_B1_i(1'b0),
+		.WEN_B2_i(1'b0),
+		.BE_B1_i(2'b11),
+		.BE_B2_i(2'b11),
+
+		.FLUSH1_i(Async_Flush),
+		.FLUSH2_i(1'b0)
+	);
+
+  assign DOUT[RD_DATA_WIDTH-1 : 0] = RD_DATA_CMPL[RD_DATA_WIDTH-1 : 0];
+
+endmodule 
+
+module SFIFO_18K_BLK (
+    DIN,
+    PUSH,
+    POP,
+    CLK,
+    Async_Flush,
+    Overrun_Error,
+    Full_Watermark,
+    Almost_Full,
+    Full,
+    Underrun_Error,
+    Empty_Watermark,
+    Almost_Empty,
+    Empty,
+    DOUT
+);
+  
+  parameter WR_DATA_WIDTH = 18;
+  parameter RD_DATA_WIDTH = 18;
+  parameter UPAE_DBITS = 11'd10;
+  parameter UPAF_DBITS = 11'd10;
+
+  input wire CLK;
+  input wire PUSH, POP;
+  input wire [WR_DATA_WIDTH-1:0] DIN;
+  input wire Async_Flush;
+  output wire [RD_DATA_WIDTH-1:0] DOUT;
+  output wire Almost_Full, Almost_Empty;
+  output wire Full, Empty;
+  output wire Full_Watermark, Empty_Watermark;
+  output wire Overrun_Error, Underrun_Error;
+ 
+ 	BRAM2x18_SFIFO  #(
+      .WR_DATA_WIDTH(WR_DATA_WIDTH), 
+      .RD_DATA_WIDTH(RD_DATA_WIDTH),
+      .UPAE_DBITS1(UPAE_DBITS),
+      .UPAF_DBITS1(UPAF_DBITS),
+      .UPAE_DBITS2(),
+      .UPAF_DBITS2()   
+       ) U1
+      (
+      .DIN1(DIN),
+      .PUSH1(PUSH),
+      .POP1(POP),
+      .CLK1(CLK),
+      .Async_Flush1(Async_Flush),
+      .Overrun_Error1(Overrun_Error),
+      .Full_Watermark1(Full_Watermark),
+      .Almost_Full1(Almost_Full),
+      .Full1(Full),
+      .Underrun_Error1(Underrun_Error),
+      .Empty_Watermark1(Empty_Watermark),
+      .Almost_Empty1(Almost_Empty),
+      .Empty1(Empty),
+      .DOUT1(DOUT),
+      
+      .DIN2(),
+      .PUSH2(),
+      .POP2(),
+      .CLK2(),
+      .Async_Flush2(),
+      .Overrun_Error2(),
+      .Full_Watermark2(),
+      .Almost_Full2(),
+      .Full2(),
+      .Underrun_Error2(),
+      .Empty_Watermark2(),
+      .Almost_Empty2(),
+      .Empty2(),
+      .DOUT2()
+	);
+
+endmodule
+
+module AFIFO_18K_BLK (
+    DIN,
+    PUSH,
+    POP,
+    Push_Clk,
+    Pop_Clk,
+    Async_Flush,
+    Overrun_Error,
+    Full_Watermark,
+    Almost_Full,
+    Full,
+    Underrun_Error,
+    Empty_Watermark,
+    Almost_Empty,
+    Empty,
+    DOUT
+);
+  
+  parameter WR_DATA_WIDTH = 18;
+  parameter RD_DATA_WIDTH = 18;
+  parameter UPAE_DBITS = 11'd10;
+  parameter UPAF_DBITS = 11'd10;
+
+  input wire Push_Clk, Pop_Clk;
+  input wire PUSH, POP;
+  input wire [WR_DATA_WIDTH-1:0] DIN;
+  input wire Async_Flush;
+  output wire [RD_DATA_WIDTH-1:0] DOUT;
+  output wire Almost_Full, Almost_Empty;
+  output wire Full, Empty;
+  output wire Full_Watermark, Empty_Watermark;
+  output wire Overrun_Error, Underrun_Error;
+ 
+ 	BRAM2x18_AFIFO  #(
+      .WR_DATA_WIDTH(WR_DATA_WIDTH), 
+      .RD_DATA_WIDTH(RD_DATA_WIDTH),
+      .UPAE_DBITS1(UPAE_DBITS),
+      .UPAF_DBITS1(UPAF_DBITS),
+      .UPAE_DBITS2(),
+      .UPAF_DBITS2()
+       ) U1
+      (
+      .DIN1(DIN),
+      .PUSH1(PUSH),
+      .POP1(POP),
+      .Push_Clk1(Push_Clk),
+      .Pop_Clk1(Pop_Clk),
+      .Async_Flush1(Async_Flush),
+      .Overrun_Error1(Overrun_Error),
+      .Full_Watermark1(Full_Watermark),
+      .Almost_Full1(Almost_Full),
+      .Full1(Full),
+      .Underrun_Error1(Underrun_Error),
+      .Empty_Watermark1(Empty_Watermark),
+      .Almost_Empty1(Almost_Empty),
+      .Empty1(Empty),
+      .DOUT1(DOUT),
+      
+      .DIN2(),
+      .PUSH2(),
+      .POP2(),
+      .Push_Clk2(),
+      .Pop_Clk2(),
+      .Async_Flush2(),
+      .Overrun_Error2(),
+      .Full_Watermark2(),
+      .Almost_Full2(),
+      .Full2(),
+      .Underrun_Error2(),
+      .Empty_Watermark2(),
+      .Almost_Empty2(),
+      .Empty2(),
+      .DOUT2()
+	);
+
+endmodule
+
+module RAM_36K_BLK (
+    WEN_i,
+    REN_i,
+    WR_CLK_i,
+    RD_CLK_i,
+    WR_BE_i,
+    WR_ADDR_i,
+    RD_ADDR_i,
+    WDATA_i,
+    RDATA_o
+);
+
+parameter WR_ADDR_WIDTH = 10;
+parameter RD_ADDR_WIDTH = 10;
+parameter WR_DATA_WIDTH = 36;
+parameter RD_DATA_WIDTH = 36;
+parameter BE_WIDTH = 4;
+
+input wire WEN_i;
+input wire REN_i;
+input wire WR_CLK_i;
+input wire RD_CLK_i;
+input wire [BE_WIDTH-1:0] WR_BE_i;
+input wire [WR_ADDR_WIDTH-1 :0] WR_ADDR_i;
+input wire [RD_ADDR_WIDTH-1 :0] RD_ADDR_i;
+input wire [WR_DATA_WIDTH-1 :0] WDATA_i;
+output wire [RD_DATA_WIDTH-1 :0] RDATA_o;
+
+wire [14:RD_ADDR_WIDTH] RD_ADDR_CMPL;
+wire [14:WR_ADDR_WIDTH] WR_ADDR_CMPL;
+wire [35:0] RD_DATA_CMPL;
+wire [35:WR_DATA_WIDTH] WR_DATA_CMPL;
+
+wire [14:0] RD_ADDR_TOTAL;
+wire [14:0] WR_ADDR_TOTAL;
+
+wire [14:0] RD_ADDR_SHIFTED;
+wire [14:0] WR_ADDR_SHIFTED;
+
+wire [3:0] WR_BE;
+
+wire FLUSH1;
+wire FLUSH2;
+
+generate
+  if (WR_ADDR_WIDTH == 15) begin
+    assign WR_ADDR_TOTAL = WR_ADDR_i;
+  end else begin
+    assign WR_ADDR_TOTAL[14:WR_ADDR_WIDTH] = 0;
+    assign WR_ADDR_TOTAL[WR_ADDR_WIDTH-1:0] = WR_ADDR_i;
+  end
+endgenerate
+
+generate
+  if (RD_ADDR_WIDTH == 15) begin
+    assign RD_ADDR_TOTAL = RD_ADDR_i;
+  end else begin
+    assign RD_ADDR_TOTAL[14:RD_ADDR_WIDTH] = 0;
+    assign RD_ADDR_TOTAL[RD_ADDR_WIDTH-1:0] = RD_ADDR_i;
+  end
+endgenerate
+
+// Assign parameters
+case (RD_DATA_WIDTH)
+	1: begin
+		case (WR_DATA_WIDTH)
+			1: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_1, `MODE_1, `MODE_1, `MODE_1, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_1, `MODE_1, `MODE_1, `MODE_1, 1'd0
+				};
+			end
+			2: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_1, `MODE_2, `MODE_1, `MODE_2, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_1, `MODE_2, `MODE_1, `MODE_2, 1'd0
+				};
+			end
+			4: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_1, `MODE_4, `MODE_1, `MODE_4, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_1, `MODE_4, `MODE_1, `MODE_4, 1'd0
+				};
+			end
+			8, 9: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_1, `MODE_9, `MODE_1, `MODE_9, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_1, `MODE_9, `MODE_1, `MODE_9, 1'd0
+				};
+			end
+			16, 18: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_1, `MODE_18, `MODE_1, `MODE_18, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_1, `MODE_18, `MODE_1, `MODE_18, 1'd0
+				};
+			end
+			32, 36: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_1, `MODE_36, `MODE_1, `MODE_36, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_1, `MODE_36, `MODE_1, `MODE_36, 1'd0
+				};
+			end
+			default: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_1, `MODE_1, `MODE_1, `MODE_1, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_1, `MODE_1, `MODE_1, `MODE_1, 1'd0
+				};
+			end
+		endcase
+	end
+	2: begin
+		case (WR_DATA_WIDTH)
+			1: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_2, `MODE_1, `MODE_2, `MODE_1, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_2, `MODE_1, `MODE_2, `MODE_1, 1'd0
+				};
+			end
+			2: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_2, `MODE_2, `MODE_2, `MODE_2, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_2, `MODE_2, `MODE_2, `MODE_2, 1'd0
+				};
+			end
+			4: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_2, `MODE_4, `MODE_2, `MODE_4, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_2, `MODE_4, `MODE_2, `MODE_4, 1'd0
+				};
+			end
+			8, 9: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_2, `MODE_9, `MODE_2, `MODE_9, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_2, `MODE_9, `MODE_2, `MODE_9, 1'd0
+				};
+			end
+			16, 18: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_2, `MODE_18, `MODE_2, `MODE_18, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_2, `MODE_18, `MODE_2, `MODE_18, 1'd0
+				};
+			end
+			32, 36: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_2, `MODE_36, `MODE_2, `MODE_36, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_2, `MODE_36, `MODE_2, `MODE_36, 1'd0
+				};
+			end
+			default: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_2, `MODE_1, `MODE_2, `MODE_1, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_2, `MODE_1, `MODE_2, `MODE_1, 1'd0
+				};
+			end
+		endcase
+	end
+	4: begin
+		case (WR_DATA_WIDTH)
+			1: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_4, `MODE_1, `MODE_4, `MODE_1, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_4, `MODE_1, `MODE_4, `MODE_1, 1'd0
+				};
+			end
+			2: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_4, `MODE_2, `MODE_4, `MODE_2, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_4, `MODE_2, `MODE_4, `MODE_2, 1'd0
+				};
+			end
+			4: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_4, `MODE_4, `MODE_4, `MODE_4, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_4, `MODE_4, `MODE_4, `MODE_4, 1'd0
+				};
+			end
+			8, 9: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_4, `MODE_9, `MODE_4, `MODE_9, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_4, `MODE_9, `MODE_4, `MODE_9, 1'd0
+				};
+			end
+			16, 18: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_4, `MODE_18, `MODE_4, `MODE_18, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_4, `MODE_18, `MODE_4, `MODE_18, 1'd0
+				};
+			end
+			32, 36: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_4, `MODE_36, `MODE_4, `MODE_36, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_4, `MODE_36, `MODE_4, `MODE_36, 1'd0
+				};
+			end
+			default: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_4, `MODE_1, `MODE_4, `MODE_1, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_4, `MODE_1, `MODE_4, `MODE_1, 1'd0
+				};
+			end
+		endcase
+	end
+	8, 9: begin
+		case (WR_DATA_WIDTH)
+			1: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_9, `MODE_1, `MODE_9, `MODE_1, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_9, `MODE_1, `MODE_9, `MODE_1, 1'd0
+				};
+			end
+			2: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_9, `MODE_2, `MODE_9, `MODE_2, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_9, `MODE_2, `MODE_9, `MODE_2, 1'd0
+				};
+			end
+			4: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_9, `MODE_4, `MODE_9, `MODE_4, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_9, `MODE_4, `MODE_9, `MODE_4, 1'd0
+				};
+			end
+			8, 9: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_9, `MODE_9, `MODE_9, `MODE_9, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_9, `MODE_9, `MODE_9, `MODE_9, 1'd0
+				};
+			end
+			16, 18: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_9, `MODE_18, `MODE_9, `MODE_18, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_9, `MODE_18, `MODE_9, `MODE_18, 1'd0
+				};
+			end
+			32, 36: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_9, `MODE_36, `MODE_9, `MODE_36, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_9, `MODE_36, `MODE_9, `MODE_36, 1'd0
+				};
+			end
+			default: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_9, `MODE_1, `MODE_9, `MODE_1, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_9, `MODE_1, `MODE_9, `MODE_1, 1'd0
+				};
+			end
+		endcase
+	end
+	16, 18: begin
+		case (WR_DATA_WIDTH)
+			1: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_18, `MODE_1, `MODE_18, `MODE_1, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_18, `MODE_1, `MODE_18, `MODE_1, 1'd0
+				};
+			end
+			2: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_18, `MODE_2, `MODE_18, `MODE_2, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_18, `MODE_2, `MODE_18, `MODE_2, 1'd0
+				};
+			end
+			4: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_18, `MODE_4, `MODE_18, `MODE_4, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_18, `MODE_4, `MODE_18, `MODE_4, 1'd0
+				};
+			end
+			8, 9: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_18, `MODE_9, `MODE_18, `MODE_9, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_18, `MODE_9, `MODE_18, `MODE_9, 1'd0
+				};
+			end
+			16, 18: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_18, `MODE_18, `MODE_18, `MODE_18, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_18, `MODE_18, `MODE_18, `MODE_18, 1'd0
+				};
+			end
+			32, 36: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_18, `MODE_36, `MODE_18, `MODE_36, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_18, `MODE_36, `MODE_18, `MODE_36, 1'd0
+				};
+			end
+			default: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_18, `MODE_1, `MODE_18, `MODE_1, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_18, `MODE_1, `MODE_18, `MODE_1, 1'd0
+				};
+			end
+		endcase
+	end
+	32, 36: begin
+		case (WR_DATA_WIDTH)
+			1: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_36, `MODE_1, `MODE_36, `MODE_1, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_36, `MODE_1, `MODE_36, `MODE_1, 1'd0
+				};
+			end
+			2: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_36, `MODE_2, `MODE_36, `MODE_2, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_36, `MODE_2, `MODE_36, `MODE_2, 1'd0
+				};
+			end
+			4: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_36, `MODE_4, `MODE_36, `MODE_4, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_36, `MODE_4, `MODE_36, `MODE_4, 1'd0
+				};
+			end
+			8, 9: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_36, `MODE_9, `MODE_36, `MODE_9, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_36, `MODE_9, `MODE_36, `MODE_9, 1'd0
+				};
+			end
+			16, 18: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_36, `MODE_18, `MODE_36, `MODE_18, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_36, `MODE_18, `MODE_36, `MODE_18, 1'd0
+				};
+			end
+			32, 36: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_36, `MODE_36, `MODE_36, `MODE_36, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_36, `MODE_36, `MODE_36, `MODE_36, 1'd0
+				};
+			end
+			default: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_36, `MODE_1, `MODE_36, `MODE_1, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_36, `MODE_1, `MODE_36, `MODE_1, 1'd0
+				};
+			end
+		endcase
+	end
+	default: begin
+		case (WR_DATA_WIDTH)
+			1: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_1, `MODE_1, `MODE_1, `MODE_1, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_1, `MODE_1, `MODE_1, `MODE_1, 1'd0
+				};
+			end
+			2: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_1, `MODE_2, `MODE_1, `MODE_2, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_1, `MODE_2, `MODE_1, `MODE_2, 1'd0
+				};
+			end
+			4: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_1, `MODE_4, `MODE_1, `MODE_4, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_1, `MODE_4, `MODE_1, `MODE_4, 1'd0
+				};
+			end
+			8, 9: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_1, `MODE_9, `MODE_1, `MODE_9, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_1, `MODE_9, `MODE_1, `MODE_9, 1'd0
+				};
+			end
+			16, 18: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_1, `MODE_18, `MODE_1, `MODE_18, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_1, `MODE_18, `MODE_1, `MODE_18, 1'd0
+				};
+			end
+			32, 36: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_1, `MODE_36, `MODE_1, `MODE_36, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_1, `MODE_36, `MODE_1, `MODE_36, 1'd0
+				};
+			end
+			default: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, `MODE_1, `MODE_1, `MODE_1, `MODE_1, 1'd0,
+					12'd10, 12'd10, 4'd0, `MODE_1, `MODE_1, `MODE_1, `MODE_1, 1'd0
+				};
+			end
+		endcase
+	end
+endcase
+
+// Apply shift
+case (RD_DATA_WIDTH)
+	1: begin
+		assign RD_ADDR_SHIFTED = RD_ADDR_TOTAL;
+	end
+	2: begin
+		assign RD_ADDR_SHIFTED = RD_ADDR_TOTAL << 1;
+	end
+	4: begin
+		assign RD_ADDR_SHIFTED = RD_ADDR_TOTAL << 2;
+	end
+	8, 9: begin
+		assign RD_ADDR_SHIFTED = RD_ADDR_TOTAL << 3;
+	end
+	16, 18: begin
+		assign RD_ADDR_SHIFTED = RD_ADDR_TOTAL << 4;
+	end
+	32, 36: begin
+		assign RD_ADDR_SHIFTED = RD_ADDR_TOTAL << 5;
+	end
+	default: begin
+		assign RD_ADDR_SHIFTED = RD_ADDR_TOTAL;
+	end
+endcase
+
+case (WR_DATA_WIDTH)
+	1: begin
+		assign WR_ADDR_SHIFTED = WR_ADDR_TOTAL;
+	end
+	2: begin
+		assign WR_ADDR_SHIFTED = WR_ADDR_TOTAL << 1;
+	end
+	4: begin
+		assign WR_ADDR_SHIFTED = WR_ADDR_TOTAL << 2;
+	end
+	8, 9: begin
+		assign WR_ADDR_SHIFTED = WR_ADDR_TOTAL << 3;
+	end
+	16, 18: begin
+		assign WR_ADDR_SHIFTED = WR_ADDR_TOTAL << 4;
+	end
+	32, 36: begin
+		assign WR_ADDR_SHIFTED = WR_ADDR_TOTAL << 5;
+	end
+	default: begin
+		assign WR_ADDR_SHIFTED = WR_ADDR_TOTAL;
+	end
+endcase
+
+case (BE_WIDTH)
+	4: begin
+		assign WR_BE = WR_BE_i[BE_WIDTH-1 :0];
+	end
+	default: begin
+		assign WR_BE[3:BE_WIDTH] = 0;
+    assign WR_BE[BE_WIDTH-1 :0] = WR_BE_i[BE_WIDTH-1 :0];
+	end
+endcase
+
+assign FLUSH1 = 1'b0;
+assign FLUSH2 = 1'b0;
+
+// TODO configure per width
+wire [17:0] PORT_B1_RDATA;
+wire [17:0] PORT_B2_RDATA;
+wire [35:0] PORT_A_WDATA;
+
+generate
+  if (WR_DATA_WIDTH == 36) begin
+    assign PORT_A_WDATA[WR_DATA_WIDTH-1:0] = WDATA_i[WR_DATA_WIDTH-1:0];
+  end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin
+    assign PORT_A_WDATA[WR_DATA_WIDTH+1:18]  = WDATA_i[WR_DATA_WIDTH-1:16];
+    assign PORT_A_WDATA[17:0] = {2'b00,WDATA_i[15:0]};
+  end else if (WR_DATA_WIDTH == 9) begin
+    assign PORT_A_WDATA = {19'h0, WDATA_i[8], 8'h0, WDATA_i[7:0]};
+  end else begin
+    assign PORT_A_WDATA[35:WR_DATA_WIDTH] = 0;
+    assign PORT_A_WDATA[WR_DATA_WIDTH-1:0] = WDATA_i[WR_DATA_WIDTH-1:0];
+  end
+endgenerate
+
+generate
+  if (RD_DATA_WIDTH == 36) begin
+    assign RD_DATA_CMPL = {PORT_B2_RDATA, PORT_B1_RDATA};
+  end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin
+    assign RD_DATA_CMPL  = {2'b00,PORT_B2_RDATA[17:0],PORT_B1_RDATA[15:0]};
+  end else if (RD_DATA_WIDTH == 9) begin
+    assign RD_DATA_CMPL = { 27'h0, PORT_B1_RDATA[16], PORT_B1_RDATA[7:0]};
+  end else begin
+    assign RD_DATA_CMPL = {18'h0, PORT_B1_RDATA};
+  end
+endgenerate
+
+assign RDATA_o = RD_DATA_CMPL[RD_DATA_WIDTH-1:0];
+
+(* is_inferred = 1 *)
+(* rd_data_width = RD_DATA_WIDTH *)
+(* wr_data_width = WR_DATA_WIDTH *)
+TDP36K BRAM_BLK (
+	.RESET_ni(1'b1),
+
+	.WDATA_A1_i(PORT_A_WDATA[17:0]),
+	.RDATA_A1_o(),
+	.ADDR_A1_i(WR_ADDR_SHIFTED),
+	.CLK_A1_i(WR_CLK_i),
+	.REN_A1_i(1'b0),
+	.WEN_A1_i(WEN_i),
+	.BE_A1_i(WR_BE[1:0]),
+
+	.WDATA_B1_i(18'h0),
+	.RDATA_B1_o(PORT_B1_RDATA[17:0]),
+	.ADDR_B1_i(RD_ADDR_SHIFTED),
+	.CLK_B1_i(RD_CLK_i),
+	.REN_B1_i(REN_i),
+	.WEN_B1_i(1'b0),
+	.BE_B1_i({REN_i,REN_i}),
+
+	.WDATA_A2_i(PORT_A_WDATA[35:18]),
+	.RDATA_A2_o(),
+	.ADDR_A2_i(WR_ADDR_SHIFTED),
+	.CLK_A2_i(WR_CLK_i),
+	.REN_A2_i(1'b0),
+	.WEN_A2_i(WEN_i),
+	.BE_A2_i(WR_BE[3:2]),
+
+	.WDATA_B2_i(18'h0),
+	.RDATA_B2_o(PORT_B2_RDATA[17:0]),
+	.ADDR_B2_i(RD_ADDR_SHIFTED),
+	.CLK_B2_i(RD_CLK_i),
+	.REN_B2_i(REN_i),
+	.WEN_B2_i(1'b0),
+	.BE_B2_i({REN_i,REN_i}),
+
+	.FLUSH1_i(FLUSH1),
+	.FLUSH2_i(FLUSH2)
+);
+
+endmodule
+
+module RAM_18K_BLK (
+    WEN_i,
+    REN_i,
+    WR_CLK_i,
+    RD_CLK_i,
+    WR_BE_i,
+    WR_ADDR_i,
+    RD_ADDR_i,
+    WDATA_i,
+    RDATA_o
+);
+
+parameter WR_ADDR_WIDTH = 10;
+parameter RD_ADDR_WIDTH = 10;
+parameter WR_DATA_WIDTH = 18;
+parameter RD_DATA_WIDTH = 18;
+parameter BE_WIDTH = 2;
+
+input wire WEN_i;
+input wire REN_i;
+input wire WR_CLK_i;
+input wire RD_CLK_i;
+input wire [BE_WIDTH-1:0] WR_BE_i;
+input wire [WR_ADDR_WIDTH-1 :0] WR_ADDR_i;
+input wire [RD_ADDR_WIDTH-1 :0] RD_ADDR_i;
+input wire [WR_DATA_WIDTH-1 :0] WDATA_i;
+output wire [RD_DATA_WIDTH-1 :0] RDATA_o;
+
+  BRAM2x18_SP  #(
+      .WR_ADDR_WIDTH(WR_ADDR_WIDTH), 
+      .RD_ADDR_WIDTH(RD_ADDR_WIDTH),
+      .WR_DATA_WIDTH(WR_DATA_WIDTH), 
+      .RD_DATA_WIDTH(RD_DATA_WIDTH),
+      .BE1_WIDTH(BE_WIDTH),
+      .BE2_WIDTH()      
+       ) U1
+      (
+      .RESET_ni(1'b1),
+      
+      .WEN1_i(WEN_i),
+      .REN1_i(REN_i),
+      .WR1_CLK_i(WR_CLK_i),
+      .RD1_CLK_i(RD_CLK_i),
+      .WR1_BE_i(WR_BE_i),
+      .WR1_ADDR_i(WR_ADDR_i),
+      .RD1_ADDR_i(RD_ADDR_i),
+      .WDATA1_i(WDATA_i),
+      .RDATA1_o(RDATA_o),
+      
+      .WEN2_i(),
+      .REN2_i(),
+      .WR2_CLK_i(),
+      .RD2_CLK_i(),
+      .WR2_BE_i(),
+      .WR2_ADDR_i(),
+      .RD2_ADDR_i(),
+      .WDATA2_i(),
+      .RDATA2_o()
+      );
+    
+endmodule
+
+module DPRAM_36K_BLK (   
+    CLK1_i,
+    WEN1_i,
+    WR1_BE_i,
+    REN1_i,
+    WR1_ADDR_i,
+    RD1_ADDR_i,
+    WDATA1_i,
+    RDATA1_o,
+    
+    CLK2_i,
+    WEN2_i,
+    WR2_BE_i,
+    REN2_i,
+    WR2_ADDR_i,
+    RD2_ADDR_i,
+    WDATA2_i,
+    RDATA2_o
+);
+
+parameter ADDR_WIDTH = 10;
+parameter DATA_WIDTH = 36;
+parameter BE1_WIDTH = 4;
+parameter BE2_WIDTH = 4;
+
+input wire CLK1_i;
+input wire WEN1_i;
+input wire [BE1_WIDTH-1 :0] WR1_BE_i;
+input wire REN1_i;
+input wire [ADDR_WIDTH-1 :0] WR1_ADDR_i;
+input wire [ADDR_WIDTH-1 :0] RD1_ADDR_i;
+input wire [DATA_WIDTH-1 :0] WDATA1_i;
+output wire [DATA_WIDTH-1 :0] RDATA1_o;
+
+input wire CLK2_i;
+input wire WEN2_i;
+input wire [BE2_WIDTH-1 :0] WR2_BE_i;
+input wire REN2_i;
+input wire [ADDR_WIDTH-1 :0] WR2_ADDR_i;
+input wire [ADDR_WIDTH-1 :0] RD2_ADDR_i;
+input wire [DATA_WIDTH-1 :0] WDATA2_i;
+output wire [DATA_WIDTH-1 :0] RDATA2_o;
+
+wire FLUSH1;
+wire FLUSH2;
+
+wire [14:0] A1ADDR_TOTAL;
+wire [14:0] B1ADDR_TOTAL;
+wire [14:0] C1ADDR_TOTAL;
+wire [14:0] D1ADDR_TOTAL;
+
+generate
+  if (ADDR_WIDTH == 15) begin
+    assign A1ADDR_TOTAL = RD1_ADDR_i;
+    assign B1ADDR_TOTAL = WR1_ADDR_i;
+    assign C1ADDR_TOTAL = RD2_ADDR_i;
+    assign D1ADDR_TOTAL = WR2_ADDR_i;
+  end else begin
+    assign A1ADDR_TOTAL[14:ADDR_WIDTH] = 0;
+    assign A1ADDR_TOTAL[ADDR_WIDTH-1:0] = RD1_ADDR_i;
+    assign B1ADDR_TOTAL[14:ADDR_WIDTH] = 0;
+    assign B1ADDR_TOTAL[ADDR_WIDTH-1:0] = WR1_ADDR_i;
+    assign C1ADDR_TOTAL[14:ADDR_WIDTH] = 0;
+    assign C1ADDR_TOTAL[ADDR_WIDTH-1:0] = RD2_ADDR_i;
+    assign D1ADDR_TOTAL[14:ADDR_WIDTH] = 0;
+    assign D1ADDR_TOTAL[ADDR_WIDTH-1:0] = WR2_ADDR_i;
+  end
+endgenerate
+
+wire [35:DATA_WIDTH] A1DATA_CMPL;
+wire [35:DATA_WIDTH] B1DATA_CMPL;
+wire [35:DATA_WIDTH] C1DATA_CMPL;
+wire [35:DATA_WIDTH] D1DATA_CMPL;
+
+wire [35:0] A1DATA_TOTAL;
+wire [35:0] B1DATA_TOTAL;
+wire [35:0] C1DATA_TOTAL;
+wire [35:0] D1DATA_TOTAL;
+
+wire [14:0] PORT_A_ADDR;
+wire [14:0] PORT_B_ADDR;
+
+wire [3:0] WR1_BE;
+wire [3:0] WR2_BE;
+
+generate
+  if (BE1_WIDTH == 4) begin
+    assign WR1_BE = WR1_BE_i;
+  end else begin
+    assign WR1_BE[3:BE1_WIDTH] = 0;
+    assign WR1_BE[BE1_WIDTH-1:0] = WR1_BE_i[BE1_WIDTH-1:0];
+  end
+endgenerate
+
+generate
+  if (BE2_WIDTH == 4) begin
+    assign WR2_BE = WR2_BE_i;
+  end else begin
+    assign WR2_BE[3:BE2_WIDTH] = 0;
+    assign WR2_BE[BE2_WIDTH-1:0] = WR2_BE_i[BE2_WIDTH-1:0];
+  end
+endgenerate
+
+// Assign read/write data - handle special case for 9bit mode
+// parity bit for 9bit mode is placed in R/W port on bit #16
+case (DATA_WIDTH)
+	9: begin
+		assign RDATA1_o = {A1DATA_TOTAL[16], A1DATA_TOTAL[7:0]};
+		assign RDATA2_o = {C1DATA_TOTAL[16], C1DATA_TOTAL[7:0]};
+		assign B1DATA_TOTAL = {B1DATA_CMPL[35:17], WDATA1_i[8], B1DATA_CMPL[16:9], WDATA1_i[7:0]};
+		assign D1DATA_TOTAL = {D1DATA_CMPL[35:17], WDATA2_i[8], D1DATA_CMPL[16:9], WDATA2_i[7:0]};
+	end
+	default: begin
+		assign RDATA1_o = A1DATA_TOTAL[DATA_WIDTH-1:0];
+		assign RDATA2_o = C1DATA_TOTAL[DATA_WIDTH-1:0];
+		assign B1DATA_TOTAL = {B1DATA_CMPL, WDATA1_i};
+		assign D1DATA_TOTAL = {D1DATA_CMPL, WDATA2_i};
+	end
+endcase
+
+case (DATA_WIDTH)
+	1: begin
+		assign PORT_A_ADDR = REN1_i ? A1ADDR_TOTAL : (WEN1_i ? B1ADDR_TOTAL : 15'd0);
+		assign PORT_B_ADDR = REN2_i ? C1ADDR_TOTAL : (WEN2_i ? D1ADDR_TOTAL : 15'd0);
+          defparam U1.MODE_BITS = { 1'b0,
+              11'd10, 11'd10, 4'd0, `MODE_1, `MODE_1, `MODE_1, `MODE_1, 1'd0,
+              12'd10, 12'd10, 4'd0, `MODE_1, `MODE_1, `MODE_1, `MODE_1, 1'd0
+          };
+	end
+
+	2: begin
+		assign PORT_A_ADDR = REN1_i ? (A1ADDR_TOTAL << 1) : (WEN1_i ? (B1ADDR_TOTAL << 1) : 15'd0);
+		assign PORT_B_ADDR = REN2_i ? (C1ADDR_TOTAL << 1) : (WEN2_i ? (D1ADDR_TOTAL << 1) : 15'd0);
+          defparam U1.MODE_BITS = { 1'b0,
+              11'd10, 11'd10, 4'd0, `MODE_2, `MODE_2, `MODE_2, `MODE_2, 1'd0,
+              12'd10, 12'd10, 4'd0, `MODE_2, `MODE_2, `MODE_2, `MODE_2, 1'd0
+          };
+	end
+
+	4: begin
+		assign PORT_A_ADDR = REN1_i ? (A1ADDR_TOTAL << 2) : (WEN1_i ? (B1ADDR_TOTAL << 2) : 15'd0);
+		assign PORT_B_ADDR = REN2_i ? (C1ADDR_TOTAL << 2) : (WEN2_i ? (D1ADDR_TOTAL << 2) : 15'd0);
+          defparam U1.MODE_BITS = { 1'b0,
+              11'd10, 11'd10, 4'd0, `MODE_4, `MODE_4, `MODE_4, `MODE_4, 1'd0,
+              12'd10, 12'd10, 4'd0, `MODE_4, `MODE_4, `MODE_4, `MODE_4, 1'd0
+          };
+	end
+
+	8, 9: begin
+		assign PORT_A_ADDR = REN1_i ? (A1ADDR_TOTAL << 3) : (WEN1_i ? (B1ADDR_TOTAL << 3) : 15'd0);
+		assign PORT_B_ADDR = REN2_i ? (C1ADDR_TOTAL << 3) : (WEN2_i ? (D1ADDR_TOTAL << 3) : 15'd0);
+          defparam U1.MODE_BITS = { 1'b0,
+              11'd10, 11'd10, 4'd0, `MODE_9, `MODE_9, `MODE_9, `MODE_9, 1'd0,
+              12'd10, 12'd10, 4'd0, `MODE_9, `MODE_9, `MODE_9, `MODE_9, 1'd0
+          };
+	end
+
+	16, 18: begin
+		assign PORT_A_ADDR = REN1_i ? (A1ADDR_TOTAL << 4) : (WEN1_i ? (B1ADDR_TOTAL << 4) : 15'd0);
+		assign PORT_B_ADDR = REN2_i ? (C1ADDR_TOTAL << 4) : (WEN2_i ? (D1ADDR_TOTAL << 4) : 15'd0);
+          defparam U1.MODE_BITS = { 1'b0,
+              11'd10, 11'd10, 4'd0, `MODE_18, `MODE_18, `MODE_18, `MODE_18, 1'd0,
+              12'd10, 12'd10, 4'd0, `MODE_18, `MODE_18, `MODE_18, `MODE_18, 1'd0
+          };
+	end
+
+	32, 36: begin
+		assign PORT_A_ADDR = REN1_i ? (A1ADDR_TOTAL << 5) : (WEN1_i ? (B1ADDR_TOTAL << 5) : 15'd0);
+		assign PORT_B_ADDR = REN2_i ? (C1ADDR_TOTAL << 5) : (WEN2_i ? (D1ADDR_TOTAL << 5) : 15'd0);
+          defparam U1.MODE_BITS = { 1'b0,
+              11'd10, 11'd10, 4'd0, `MODE_36, `MODE_36, `MODE_36, `MODE_36, 1'd0,
+              12'd10, 12'd10, 4'd0, `MODE_36, `MODE_36, `MODE_36, `MODE_36, 1'd0
+          };
+	end
+	default: begin
+		assign PORT_A_ADDR = REN1_i ? (A1ADDR_TOTAL << 5) : (WEN1_i ? (B1ADDR_TOTAL << 5) : 15'd0);
+		assign PORT_B_ADDR = REN2_i ? (C1ADDR_TOTAL << 5) : (WEN2_i ? (D1ADDR_TOTAL << 5) : 15'd0);
+          defparam U1.MODE_BITS = { 1'b0,
+              11'd10, 11'd10, 4'd0, `MODE_36, `MODE_36, `MODE_36, `MODE_36, 1'd0,
+              12'd10, 12'd10, 4'd0, `MODE_36, `MODE_36, `MODE_36, `MODE_36, 1'd0
+          };
+	end
+endcase
+
+assign FLUSH1 = 1'b0;
+assign FLUSH2 = 1'b0;
+
+(* is_inferred = 1 *)
+(* rd_data_width = DATA_WIDTH *)
+(* wr_data_width = DATA_WIDTH *)
+TDP36K U1 (
+	.RESET_ni(1'b1),
+	.WDATA_A1_i(B1DATA_TOTAL[17:0]),
+	.WDATA_A2_i(B1DATA_TOTAL[35:18]),
+	.RDATA_A1_o(A1DATA_TOTAL[17:0]),
+	.RDATA_A2_o(A1DATA_TOTAL[35:18]),
+	.ADDR_A1_i(PORT_A_ADDR),
+	.ADDR_A2_i(PORT_A_ADDR),
+	.CLK_A1_i(CLK1_i),
+	.CLK_A2_i(CLK1_i),
+	.REN_A1_i(REN1_i),
+	.REN_A2_i(REN1_i),
+	.WEN_A1_i(WEN1_i),
+	.WEN_A2_i(WEN1_i),
+	.BE_A1_i(WR1_BE[1:0]),
+	.BE_A2_i(WR1_BE[3:0]),
+
+	.WDATA_B1_i(D1DATA_TOTAL[17:0]),
+	.WDATA_B2_i(D1DATA_TOTAL[35:18]),
+	.RDATA_B1_o(C1DATA_TOTAL[17:0]),
+	.RDATA_B2_o(C1DATA_TOTAL[35:18]),
+	.ADDR_B1_i(PORT_B_ADDR),
+	.ADDR_B2_i(PORT_B_ADDR),
+	.CLK_B1_i(CLK2_i),
+	.CLK_B2_i(CLK2_i),
+	.REN_B1_i(REN2_i),
+	.REN_B2_i(REN2_i),
+	.WEN_B1_i(WEN2_i),
+	.WEN_B2_i(WEN2_i),
+	.BE_B1_i(WR2_BE[1:0]),
+	.BE_B2_i(WR2_BE[3:0]),
+
+	.FLUSH1_i(FLUSH1),
+	.FLUSH2_i(FLUSH2)
+);
+endmodule
+
+module DPRAM_18K_BLK (   
+    CLK1_i,
+    WEN1_i,
+    REN1_i,
+    WR1_ADDR_i,
+    RD1_ADDR_i,
+    WDATA1_i,
+    RDATA1_o,
+    
+    CLK2_i,
+    WEN2_i,
+    REN2_i,
+    WR2_ADDR_i,
+    RD2_ADDR_i,
+    WDATA2_i,
+    RDATA2_o
+);
+
+parameter ADDR_WIDTH = 10;
+parameter DATA_WIDTH = 18;
+parameter BE1_WIDTH = 2;
+parameter BE2_WIDTH = 2;
+
+input wire CLK1_i;
+input wire WEN1_i;
+input wire REN1_i;
+input wire [ADDR_WIDTH-1 :0] WR1_ADDR_i;
+input wire [ADDR_WIDTH-1 :0] RD1_ADDR_i;
+input wire [DATA_WIDTH-1 :0] WDATA1_i;
+output wire [DATA_WIDTH-1 :0] RDATA1_o;
+
+input wire CLK2_i;
+input wire WEN2_i;
+input wire REN2_i;
+input wire [ADDR_WIDTH-1 :0] WR2_ADDR_i;
+input wire [ADDR_WIDTH-1 :0] RD2_ADDR_i;
+input wire [DATA_WIDTH-1 :0] WDATA2_i;
+output wire [DATA_WIDTH-1 :0] RDATA2_o;
+
+(* is_inferred = 1 *)
+BRAM2x18_DP #(
+	.CFG_ABITS(ADDR_WIDTH),
+	.CFG_DBITS(DATA_WIDTH),
+	.CFG_ENABLE_B(BE1_WIDTH),
+	.CFG_ENABLE_D(BE2_WIDTH)
+) bram2x18_inst (
+	.A1ADDR(RD1_ADDR_i),
+	.A1DATA(RDATA1_o),
+	.A1EN(REN1_i),
+	.B1ADDR(WR1_ADDR_i),
+	.B1DATA(WDATA1_i),
+	.B1EN({WEN1_i,WEN1_i}),
+	.CLK1(CLK1_i),
+
+	.C1ADDR(RD2_ADDR_i),
+	.C1DATA(RDATA2_o),
+	.C1EN(REN2_i),
+	.D1ADDR(WR2_ADDR_i),
+	.D1DATA(WDATA2_i),
+	.D1EN({WEN2_i,WEN2_i}),
+	.CLK2(CLK2_i),
+
+	.E1ADDR(),
+	.E1DATA(),
+	.E1EN(),
+	.F1ADDR(),
+	.F1DATA(),
+	.F1EN(),
+	.CLK3(),
+
+	.G1ADDR(),
+	.G1DATA(),
+	.G1EN(),
+	.H1ADDR(),
+	.H1DATA(),
+	.H1EN(),
+	.CLK4()
+);
+endmodule
+
diff --git a/ql-qlf-plugin/qlf_k6n10f/brams_sim.v b/ql-qlf-plugin/qlf_k6n10f/brams_sim.v
new file mode 100644
index 0000000..c4ad3a7
--- /dev/null
+++ b/ql-qlf-plugin/qlf_k6n10f/brams_sim.v
@@ -0,0 +1,20075 @@
+// Copyright 2020-2022 F4PGA Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+`timescale 1ns /10ps
+
+`default_nettype none
+
+module TDP_BRAM18 (
+    (* clkbuf_sink *)
+    input wire CLOCKA,
+    (* clkbuf_sink *)
+    input wire CLOCKB,
+    input wire READENABLEA,
+    input wire READENABLEB,
+    input wire [13:0] ADDRA,
+    input wire [13:0] ADDRB,
+    input wire [15:0] WRITEDATAA,
+    input wire [15:0] WRITEDATAB,
+    input wire [1:0] WRITEDATAAP,
+    input wire [1:0] WRITEDATABP,
+    input wire WRITEENABLEA,
+    input wire WRITEENABLEB,
+    input wire [1:0] BYTEENABLEA,
+    input wire [1:0] BYTEENABLEB,
+    //input wire [2:0] WRITEDATAWIDTHA,
+    //input wire [2:0] WRITEDATAWIDTHB,
+    //input wire [2:0] READDATAWIDTHA,
+    //input wire [2:0] READDATAWIDTHB,
+    output wire [15:0] READDATAA,
+    output wire [15:0] READDATAB,
+    output wire [1:0] READDATAAP,
+    output wire [1:0] READDATABP
+);
+    parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter integer READ_WIDTH_A = 0;
+    parameter integer READ_WIDTH_B = 0;
+    parameter integer WRITE_WIDTH_A = 0;
+    parameter integer WRITE_WIDTH_B = 0;
+
+endmodule
+
+module TDP36K (
+    RESET_ni,
+    WEN_A1_i,
+    WEN_B1_i,
+    REN_A1_i,
+    REN_B1_i,
+    CLK_A1_i,
+    CLK_B1_i,
+    BE_A1_i,
+    BE_B1_i,
+    ADDR_A1_i,
+    ADDR_B1_i,
+    WDATA_A1_i,
+    WDATA_B1_i,
+    RDATA_A1_o,
+    RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,
+    WEN_B2_i,
+    REN_A2_i,
+    REN_B2_i,
+    CLK_A2_i,
+    CLK_B2_i,
+    BE_A2_i,
+    BE_B2_i,
+    ADDR_A2_i,
+    ADDR_B2_i,
+    WDATA_A2_i,
+    WDATA_B2_i,
+    RDATA_A2_o,
+    RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    // First 18K RAMFIFO (41 bits)
+    localparam [ 0:0] SYNC_FIFO1_i  = MODE_BITS[0];
+    localparam [ 2:0] RMODE_A1_i    = MODE_BITS[3 : 1];
+    localparam [ 2:0] RMODE_B1_i    = MODE_BITS[6 : 4];
+    localparam [ 2:0] WMODE_A1_i    = MODE_BITS[9 : 7];
+    localparam [ 2:0] WMODE_B1_i    = MODE_BITS[12:10];
+    localparam [ 0:0] FMODE1_i      = MODE_BITS[13];
+    localparam [ 0:0] POWERDN1_i    = MODE_BITS[14];
+    localparam [ 0:0] SLEEP1_i      = MODE_BITS[15];
+    localparam [ 0:0] PROTECT1_i    = MODE_BITS[16];
+    localparam [11:0] UPAE1_i       = MODE_BITS[28:17];
+    localparam [11:0] UPAF1_i       = MODE_BITS[40:29];
+
+    // Second 18K RAMFIFO (39 bits)
+    localparam [ 0:0] SYNC_FIFO2_i  = MODE_BITS[41];
+    localparam [ 2:0] RMODE_A2_i    = MODE_BITS[44:42];
+    localparam [ 2:0] RMODE_B2_i    = MODE_BITS[47:45];
+    localparam [ 2:0] WMODE_A2_i    = MODE_BITS[50:48];
+    localparam [ 2:0] WMODE_B2_i    = MODE_BITS[53:51];
+    localparam [ 0:0] FMODE2_i      = MODE_BITS[54];
+    localparam [ 0:0] POWERDN2_i    = MODE_BITS[55];
+    localparam [ 0:0] SLEEP2_i      = MODE_BITS[56];
+    localparam [ 0:0] PROTECT2_i    = MODE_BITS[57];
+    localparam [10:0] UPAE2_i       = MODE_BITS[68:58];
+    localparam [10:0] UPAF2_i       = MODE_BITS[79:69];
+
+    // Split (1 bit)
+    localparam [ 0:0] SPLIT_i       = MODE_BITS[80];
+
+    parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+
+    input wire RESET_ni;
+    input wire WEN_A1_i;
+    input wire WEN_B1_i;
+    input wire REN_A1_i;
+    input wire REN_B1_i;
+    (* clkbuf_sink *)
+    input wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input wire CLK_B1_i;
+    input wire [1:0] BE_A1_i;
+    input wire [1:0] BE_B1_i;
+    input wire [14:0] ADDR_A1_i;
+    input wire [14:0] ADDR_B1_i;
+    input wire [17:0] WDATA_A1_i;
+    input wire [17:0] WDATA_B1_i;
+    output reg [17:0] RDATA_A1_o;
+    output reg [17:0] RDATA_B1_o;
+    input wire FLUSH1_i;
+    input wire WEN_A2_i;
+    input wire WEN_B2_i;
+    input wire REN_A2_i;
+    input wire REN_B2_i;
+    (* clkbuf_sink *)
+    input wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input wire CLK_B2_i;
+    input wire [1:0] BE_A2_i;
+    input wire [1:0] BE_B2_i;
+    input wire [13:0] ADDR_A2_i;
+    input wire [13:0] ADDR_B2_i;
+    input wire [17:0] WDATA_A2_i;
+    input wire [17:0] WDATA_B2_i;
+    output reg [17:0] RDATA_A2_o;
+    output reg [17:0] RDATA_B2_o;
+    input wire FLUSH2_i;
+    wire EMPTY2;
+    wire EPO2;
+    wire EWM2;
+    wire FULL2;
+    wire FMO2;
+    wire FWM2;
+    wire EMPTY1;
+    wire EPO1;
+    wire EWM1;
+    wire FULL1;
+    wire FMO1;
+    wire FWM1;
+    wire UNDERRUN1;
+    wire OVERRUN1;
+    wire UNDERRUN2;
+    wire OVERRUN2;
+    wire UNDERRUN3;
+    wire OVERRUN3;
+    wire EMPTY3;
+    wire EPO3;
+    wire EWM3;
+    wire FULL3;
+    wire FMO3;
+    wire FWM3;
+    wire ram_fmode1;
+    wire ram_fmode2;
+    wire [17:0] ram_rdata_a1;
+    wire [17:0] ram_rdata_b1;
+    wire [17:0] ram_rdata_a2;
+    wire [17:0] ram_rdata_b2;
+    reg [17:0] ram_wdata_a1;
+    reg [17:0] ram_wdata_b1;
+    reg [17:0] ram_wdata_a2;
+    reg [17:0] ram_wdata_b2;
+    reg [14:0] laddr_a1;
+    reg [14:0] laddr_b1;
+    wire [13:0] ram_addr_a1;
+    wire [13:0] ram_addr_b1;
+    wire [13:0] ram_addr_a2;
+    wire [13:0] ram_addr_b2;
+    wire smux_clk_a1;
+    wire smux_clk_b1;
+    wire smux_clk_a2;
+    wire smux_clk_b2;
+    reg [1:0] ram_be_a1;
+    reg [1:0] ram_be_a2;
+    reg [1:0] ram_be_b1;
+    reg [1:0] ram_be_b2;
+    wire [2:0] ram_rmode_a1;
+    wire [2:0] ram_wmode_a1;
+    wire [2:0] ram_rmode_b1;
+    wire [2:0] ram_wmode_b1;
+    wire [2:0] ram_rmode_a2;
+    wire [2:0] ram_wmode_a2;
+    wire [2:0] ram_rmode_b2;
+    wire [2:0] ram_wmode_b2;
+    wire ram_ren_a1;
+    wire ram_ren_b1;
+    wire ram_ren_a2;
+    wire ram_ren_b2;
+    wire ram_wen_a1;
+    wire ram_wen_b1;
+    wire ram_wen_a2;
+    wire ram_wen_b2;
+    wire ren_o;
+    wire [11:0] ff_raddr;
+    wire [11:0] ff_waddr;
+    reg [35:0] fifo_rdata;
+    wire [1:0] fifo_rmode;
+    wire [1:0] fifo_wmode;
+    wire [1:0] bwl;
+    wire [17:0] pl_dout0;
+    wire [17:0] pl_dout1;
+    wire sclk_a1;
+    wire sclk_b1;
+    wire sclk_a2;
+    wire sclk_b2;
+    wire sreset;
+    wire flush1;
+    wire flush2;
+    assign sreset = RESET_ni;
+    assign flush1 = ~FLUSH1_i;
+    assign flush2 = ~FLUSH2_i;
+    assign ram_fmode1 = FMODE1_i & SPLIT_i;
+    assign ram_fmode2 = FMODE2_i & SPLIT_i;
+    assign smux_clk_a1 = CLK_A1_i;
+    assign smux_clk_b1 = (FMODE1_i ? (SYNC_FIFO1_i ? CLK_A1_i : CLK_B1_i) : CLK_B1_i);
+    assign smux_clk_a2 = (SPLIT_i ? CLK_A2_i : CLK_A1_i);
+    assign smux_clk_b2 = (SPLIT_i ? (FMODE2_i ? (SYNC_FIFO2_i ? CLK_A2_i : CLK_B2_i) : CLK_B2_i) : (FMODE1_i ? (SYNC_FIFO1_i ? CLK_A1_i : CLK_B1_i) : CLK_B1_i));
+    assign sclk_a1 = smux_clk_a1;
+    assign sclk_a2 = smux_clk_a2;
+    assign sclk_b1 = smux_clk_b1;
+    assign sclk_b2 = smux_clk_b2;
+    assign ram_ren_a1 = (SPLIT_i ? REN_A1_i : (FMODE1_i ? 0 : REN_A1_i));
+    assign ram_ren_a2 = (SPLIT_i ? REN_A2_i : (FMODE1_i ? 0 : REN_A1_i));
+    assign ram_ren_b1 = (SPLIT_i ? REN_B1_i : (FMODE1_i ? ren_o : REN_B1_i));
+    assign ram_ren_b2 = (SPLIT_i ? REN_B2_i : (FMODE1_i ? ren_o : REN_B1_i));
+    localparam MODE_36 = 3'b011;
+    assign ram_wen_a1 = (SPLIT_i ? WEN_A1_i : (FMODE1_i ? ~FULL3 & WEN_A1_i : (WMODE_A1_i == MODE_36 ? WEN_A1_i : WEN_A1_i & ~ADDR_A1_i[4])));
+    assign ram_wen_a2 = (SPLIT_i ? WEN_A2_i : (FMODE1_i ? ~FULL3 & WEN_A1_i : (WMODE_A1_i == MODE_36 ? WEN_A1_i : WEN_A1_i & ADDR_A1_i[4])));
+    assign ram_wen_b1 = (SPLIT_i ? WEN_B1_i : (WMODE_B1_i == MODE_36 ? WEN_B1_i : WEN_B1_i & ~ADDR_B1_i[4]));
+    assign ram_wen_b2 = (SPLIT_i ? WEN_B2_i : (WMODE_B1_i == MODE_36 ? WEN_B1_i : WEN_B1_i & ADDR_B1_i[4]));
+    assign ram_addr_a1 = (SPLIT_i ? ADDR_A1_i[13:0] : (FMODE1_i ? {ff_waddr[11:2], ff_waddr[0], 3'b000} : {ADDR_A1_i[14:5], ADDR_A1_i[3:0]}));
+    assign ram_addr_b1 = (SPLIT_i ? ADDR_B1_i[13:0] : (FMODE1_i ? {ff_raddr[11:2], ff_raddr[0], 3'b000} : {ADDR_B1_i[14:5], ADDR_B1_i[3:0]}));
+    assign ram_addr_a2 = (SPLIT_i ? ADDR_A2_i[13:0] : (FMODE1_i ? {ff_waddr[11:2], ff_waddr[0], 3'b000} : {ADDR_A1_i[14:5], ADDR_A1_i[3:0]}));
+    assign ram_addr_b2 = (SPLIT_i ? ADDR_B2_i[13:0] : (FMODE1_i ? {ff_raddr[11:2], ff_raddr[0], 3'b000} : {ADDR_B1_i[14:5], ADDR_B1_i[3:0]}));
+    assign bwl = (SPLIT_i ? ADDR_A1_i[4:3] : (FMODE1_i ? ff_waddr[1:0] : ADDR_A1_i[4:3]));
+    localparam MODE_18 = 3'b010;
+    localparam MODE_9 = 3'b001;
+    always @(*) begin : WDATA_SEL
+        case (SPLIT_i)
+            1: begin
+                ram_wdata_a1 = WDATA_A1_i;
+                ram_wdata_a2 = WDATA_A2_i;
+                ram_wdata_b1 = WDATA_B1_i;
+                ram_wdata_b2 = WDATA_B2_i;
+                ram_be_a2 = BE_A2_i;
+                ram_be_b2 = BE_B2_i;
+                ram_be_a1 = BE_A1_i;
+                ram_be_b1 = BE_B1_i;
+            end
+            0: begin
+                case (WMODE_A1_i)
+                    MODE_36: begin
+                        ram_wdata_a1 = WDATA_A1_i;
+                        ram_wdata_a2 = WDATA_A2_i;
+                        ram_be_a2 = (FMODE1_i ? 2'b11 : BE_A2_i);
+                        ram_be_a1 = (FMODE1_i ? 2'b11 : BE_A1_i);
+                    end
+                    MODE_18: begin
+                        ram_wdata_a1 = WDATA_A1_i;
+                        ram_wdata_a2 = WDATA_A1_i;
+                        ram_be_a1 = (FMODE1_i ? (ff_waddr[1] ? 2'b00 : 2'b11) : BE_A1_i);
+                        ram_be_a2 = (FMODE1_i ? (ff_waddr[1] ? 2'b11 : 2'b00) : BE_A1_i);
+                    end
+                    MODE_9: begin
+                        ram_wdata_a1[7:0] = WDATA_A1_i[7:0];
+                        ram_wdata_a1[16] = WDATA_A1_i[16];
+                        ram_wdata_a1[15:8] = WDATA_A1_i[7:0];
+                        ram_wdata_a1[17] = WDATA_A1_i[16];
+                        ram_wdata_a2[7:0] = WDATA_A1_i[7:0];
+                        ram_wdata_a2[16] = WDATA_A1_i[16];
+                        ram_wdata_a2[15:8] = WDATA_A1_i[7:0];
+                        ram_wdata_a2[17] = WDATA_A1_i[16];
+                        case (bwl)
+                            0: {ram_be_a2, ram_be_a1} = 4'b0001;
+                            1: {ram_be_a2, ram_be_a1} = 4'b0010;
+                            2: {ram_be_a2, ram_be_a1} = 4'b0100;
+                            3: {ram_be_a2, ram_be_a1} = 4'b1000;
+                        endcase
+                    end
+                    default: begin
+                        ram_wdata_a1 = WDATA_A1_i;
+                        ram_wdata_a2 = WDATA_A1_i;
+                        ram_be_a2 = (FMODE1_i ? 2'b11 : BE_A1_i);
+                        ram_be_a1 = (FMODE1_i ? 2'b11 : BE_A1_i);
+                    end
+                endcase
+                case (WMODE_B1_i)
+                    MODE_36: begin
+                        ram_wdata_b1 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i);
+                        ram_wdata_b2 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B2_i);
+                        ram_be_b2 = BE_B2_i;
+                        ram_be_b1 = BE_B1_i;
+                    end
+                    MODE_18: begin
+                        ram_wdata_b1 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i);
+                        ram_wdata_b2 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i);
+                        ram_be_b1 = BE_B1_i;
+                        ram_be_b2 = BE_B1_i;
+                    end
+                    MODE_9: begin
+                        ram_wdata_b1[7:0] = WDATA_B1_i[7:0];
+                        ram_wdata_b1[16] = WDATA_B1_i[16];
+                        ram_wdata_b1[15:8] = WDATA_B1_i[7:0];
+                        ram_wdata_b1[17] = WDATA_B1_i[16];
+                        ram_wdata_b2[7:0] = WDATA_B1_i[7:0];
+                        ram_wdata_b2[16] = WDATA_B1_i[16];
+                        ram_wdata_b2[15:8] = WDATA_B1_i[7:0];
+                        ram_wdata_b2[17] = WDATA_B1_i[16];
+                        case (ADDR_B1_i[4:3])
+                            0: {ram_be_b2, ram_be_b1} = 4'b0001;
+                            1: {ram_be_b2, ram_be_b1} = 4'b0010;
+                            2: {ram_be_b2, ram_be_b1} = 4'b0100;
+                            3: {ram_be_b2, ram_be_b1} = 4'b1000;
+                        endcase
+                    end
+                    default: begin
+                        ram_wdata_b1 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i);
+                        ram_wdata_b2 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i);
+                        ram_be_b2 = BE_B1_i;
+                        ram_be_b1 = BE_B1_i;
+                    end
+                endcase
+            end
+        endcase
+    end
+    assign ram_rmode_a1 = (SPLIT_i ? (RMODE_A1_i == MODE_36 ? MODE_18 : RMODE_A1_i) : (RMODE_A1_i == MODE_36 ? MODE_18 : RMODE_A1_i));
+    assign ram_rmode_a2 = (SPLIT_i ? (RMODE_A2_i == MODE_36 ? MODE_18 : RMODE_A2_i) : (RMODE_A1_i == MODE_36 ? MODE_18 : RMODE_A1_i));
+    assign ram_wmode_a1 = (SPLIT_i ? (WMODE_A1_i == MODE_36 ? MODE_18 : WMODE_A1_i) : (WMODE_A1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : WMODE_A1_i)));
+    assign ram_wmode_a2 = (SPLIT_i ? (WMODE_A2_i == MODE_36 ? MODE_18 : WMODE_A2_i) : (WMODE_A1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : WMODE_A1_i)));
+    assign ram_rmode_b1 = (SPLIT_i ? (RMODE_B1_i == MODE_36 ? MODE_18 : RMODE_B1_i) : (RMODE_B1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : RMODE_B1_i)));
+    assign ram_rmode_b2 = (SPLIT_i ? (RMODE_B2_i == MODE_36 ? MODE_18 : RMODE_B2_i) : (RMODE_B1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : RMODE_B1_i)));
+    assign ram_wmode_b1 = (SPLIT_i ? (WMODE_B1_i == MODE_36 ? MODE_18 : WMODE_B1_i) : (WMODE_B1_i == MODE_36 ? MODE_18 : WMODE_B1_i));
+    assign ram_wmode_b2 = (SPLIT_i ? (WMODE_B2_i == MODE_36 ? MODE_18 : WMODE_B2_i) : (WMODE_B1_i == MODE_36 ? MODE_18 : WMODE_B1_i));
+    always @(*) begin : FIFO_READ_SEL
+        case (RMODE_B1_i)
+            MODE_36: fifo_rdata = {ram_rdata_b2[17:16], ram_rdata_b1[17:16], ram_rdata_b2[15:0], ram_rdata_b1[15:0]};
+            MODE_18: fifo_rdata = (ff_raddr[1] ? {18'b000000000000000000, ram_rdata_b2} : {18'b000000000000000000, ram_rdata_b1});
+            MODE_9:
+                case (ff_raddr[1:0])
+                    0: fifo_rdata = {19'b0000000000000000000, ram_rdata_b1[16], 8'b00000000, ram_rdata_b1[7:0]};
+                    1: fifo_rdata = {19'b0000000000000000000, ram_rdata_b1[17], 8'b00000000, ram_rdata_b1[15:8]};
+                    2: fifo_rdata = {19'b0000000000000000000, ram_rdata_b2[16], 8'b00000000, ram_rdata_b2[7:0]};
+                    3: fifo_rdata = {19'b0000000000000000000, ram_rdata_b2[17], 8'b00000000, ram_rdata_b2[15:8]};
+                endcase
+            default: fifo_rdata = {ram_rdata_b2, ram_rdata_b1};
+        endcase
+    end
+    localparam MODE_1 = 3'b101;
+    localparam MODE_2 = 3'b110;
+    localparam MODE_4 = 3'b100;
+    always @(*) begin : RDATA_SEL
+        case (SPLIT_i)
+            1: begin
+                RDATA_A1_o = (FMODE1_i ? {10'b0000000000, EMPTY1, EPO1, EWM1, UNDERRUN1, FULL1, FMO1, FWM1, OVERRUN1} : ram_rdata_a1);
+                RDATA_B1_o = ram_rdata_b1;
+                RDATA_A2_o = (FMODE2_i ? {10'b0000000000, EMPTY2, EPO2, EWM2, UNDERRUN2, FULL2, FMO2, FWM2, OVERRUN2} : ram_rdata_a2);
+                RDATA_B2_o = ram_rdata_b2;
+            end
+            0: begin
+                if (FMODE1_i) begin
+                    RDATA_A1_o = {10'b0000000000, EMPTY3, EPO3, EWM3, UNDERRUN3, FULL3, FMO3, FWM3, OVERRUN3};
+                    RDATA_A2_o = 18'b000000000000000000;
+                end
+                else
+                    case (RMODE_A1_i)
+                        MODE_36: begin
+                            RDATA_A1_o = {ram_rdata_a1[17:0]};
+                            RDATA_A2_o = {ram_rdata_a2[17:0]};
+                        end
+                        MODE_18: begin
+                            RDATA_A1_o = (laddr_a1[4] ? ram_rdata_a2 : ram_rdata_a1);
+                            RDATA_A2_o = 18'b000000000000000000;
+                        end
+                        MODE_9: begin
+                            RDATA_A1_o = (laddr_a1[4] ? {{2 {ram_rdata_a2[16]}}, {2 {ram_rdata_a2[7:0]}}} : {{2 {ram_rdata_a1[16]}}, {2 {ram_rdata_a1[7:0]}}});
+                            RDATA_A2_o = 18'b000000000000000000;
+                        end
+                        MODE_4: begin
+                            RDATA_A2_o = 18'b000000000000000000;
+                            RDATA_A1_o[17:4] = 14'b00000000000000;
+                            RDATA_A1_o[3:0] = (laddr_a1[4] ? ram_rdata_a2[3:0] : ram_rdata_a1[3:0]);
+                        end
+                        MODE_2: begin
+                            RDATA_A2_o = 18'b000000000000000000;
+                            RDATA_A1_o[17:2] = 16'b0000000000000000;
+                            RDATA_A1_o[1:0] = (laddr_a1[4] ? ram_rdata_a2[1:0] : ram_rdata_a1[1:0]);
+                        end
+                        MODE_1: begin
+                            RDATA_A2_o = 18'b000000000000000000;
+                            RDATA_A1_o[17:1] = 17'b00000000000000000;
+                            RDATA_A1_o[0] = (laddr_a1[4] ? ram_rdata_a2[0] : ram_rdata_a1[0]);
+                        end
+                        default: begin
+                            RDATA_A1_o = {ram_rdata_a2[1:0], ram_rdata_a1[15:0]};
+                            RDATA_A2_o = {ram_rdata_a2[17:16], ram_rdata_a1[17:16], ram_rdata_a2[15:2]};
+                        end
+                    endcase
+                case (RMODE_B1_i)
+                    MODE_36: begin
+                        RDATA_B1_o = {ram_rdata_b1};
+                        RDATA_B2_o = {ram_rdata_b2};
+                    end
+                    MODE_18: begin
+                        RDATA_B1_o = (FMODE1_i ? fifo_rdata[17:0] : (laddr_b1[4] ? ram_rdata_b2 : ram_rdata_b1));
+                        RDATA_B2_o = 18'b000000000000000000;
+                    end
+                    MODE_9: begin
+                        RDATA_B1_o = (FMODE1_i ? {fifo_rdata[17:0]} : (laddr_b1[4] ? {1'b0, ram_rdata_b2[16], 8'b00000000, ram_rdata_b2[7:0]} : {1'b0, ram_rdata_b1[16], 8'b00000000, ram_rdata_b1[7:0]}));
+                        RDATA_B2_o = 18'b000000000000000000;
+                    end
+                    MODE_4: begin
+                        RDATA_B2_o = 18'b000000000000000000;
+                        RDATA_B1_o[17:4] = 14'b00000000000000;
+                        RDATA_B1_o[3:0] = (laddr_b1[4] ? ram_rdata_b2[3:0] : ram_rdata_b1[3:0]);
+                    end
+                    MODE_2: begin
+                        RDATA_B2_o = 18'b000000000000000000;
+                        RDATA_B1_o[17:2] = 16'b0000000000000000;
+                        RDATA_B1_o[1:0] = (laddr_b1[4] ? ram_rdata_b2[1:0] : ram_rdata_b1[1:0]);
+                    end
+                    MODE_1: begin
+                        RDATA_B2_o = 18'b000000000000000000;
+                        RDATA_B1_o[17:1] = 17'b00000000000000000;
+                        RDATA_B1_o[0] = (laddr_b1[4] ? ram_rdata_b2[0] : ram_rdata_b1[0]);
+                    end
+                    default: begin
+                        RDATA_B1_o = ram_rdata_b1;
+                        RDATA_B2_o = ram_rdata_b2;
+                    end
+                endcase
+            end
+        endcase
+    end
+    always @(posedge sclk_a1 or negedge sreset)
+        if (sreset == 0)
+            laddr_a1 <= 1'sb0;
+        else
+            laddr_a1 <= ADDR_A1_i;
+    always @(posedge sclk_b1 or negedge sreset)
+        if (sreset == 0)
+            laddr_b1 <= 1'sb0;
+        else
+            laddr_b1 <= ADDR_B1_i;
+    assign fifo_wmode = ((WMODE_A1_i == MODE_36) ? 2'b00 : ((WMODE_A1_i == MODE_18) ? 2'b01 : ((WMODE_A1_i == MODE_9) ? 2'b10 : 2'b00)));
+    assign fifo_rmode = ((RMODE_B1_i == MODE_36) ? 2'b00 : ((RMODE_B1_i == MODE_18) ? 2'b01 : ((RMODE_B1_i == MODE_9) ? 2'b10 : 2'b00)));
+    fifo_ctl #(
+        .ADDR_WIDTH(12),
+        .FIFO_WIDTH(3'd4),
+        .DEPTH(7)
+    ) fifo36_ctl(
+        .rclk(sclk_b1),
+        .rst_R_n(flush1),
+        .wclk(sclk_a1),
+        .rst_W_n(flush1),
+        .ren(REN_B1_i),
+        .wen(ram_wen_a1),
+        .sync(SYNC_FIFO1_i),
+        .rmode(fifo_rmode),
+        .wmode(fifo_wmode),
+        .ren_o(ren_o),
+        .fflags({FULL3, FMO3, FWM3, OVERRUN3, EMPTY3, EPO3, EWM3, UNDERRUN3}),
+        .raddr(ff_raddr),
+        .waddr(ff_waddr),
+        .upaf(UPAF1_i),
+        .upae(UPAE1_i)
+    );
+    TDP18K_FIFO #(
+        .UPAF_i(UPAF1_i[10:0]),
+        .UPAE_i(UPAE1_i[10:0]),
+        .SYNC_FIFO_i(SYNC_FIFO1_i),
+        .POWERDN_i(POWERDN1_i),
+        .SLEEP_i(SLEEP1_i),
+        .PROTECT_i(PROTECT1_i)
+    )u1(
+        .RMODE_A_i(ram_rmode_a1),
+        .RMODE_B_i(ram_rmode_b1),
+        .WMODE_A_i(ram_wmode_a1),
+        .WMODE_B_i(ram_wmode_b1),
+        .WEN_A_i(ram_wen_a1),
+        .WEN_B_i(ram_wen_b1),
+        .REN_A_i(ram_ren_a1),
+        .REN_B_i(ram_ren_b1),
+        .CLK_A_i(sclk_a1),
+        .CLK_B_i(sclk_b1),
+        .BE_A_i(ram_be_a1),
+        .BE_B_i(ram_be_b1),
+        .ADDR_A_i(ram_addr_a1),
+        .ADDR_B_i(ram_addr_b1),
+        .WDATA_A_i(ram_wdata_a1),
+        .WDATA_B_i(ram_wdata_b1),
+        .RDATA_A_o(ram_rdata_a1),
+        .RDATA_B_o(ram_rdata_b1),
+        .EMPTY_o(EMPTY1),
+        .EPO_o(EPO1),
+        .EWM_o(EWM1),
+        .UNDERRUN_o(UNDERRUN1),
+        .FULL_o(FULL1),
+        .FMO_o(FMO1),
+        .FWM_o(FWM1),
+        .OVERRUN_o(OVERRUN1),
+        .FLUSH_ni(flush1),
+        .FMODE_i(ram_fmode1)
+    );
+    TDP18K_FIFO #(
+        .UPAF_i(UPAF2_i),
+        .UPAE_i(UPAE2_i),
+        .SYNC_FIFO_i(SYNC_FIFO2_i),
+        .POWERDN_i(POWERDN2_i),
+        .SLEEP_i(SLEEP2_i),
+        .PROTECT_i(PROTECT2_i)
+    )u2(
+        .RMODE_A_i(ram_rmode_a2),
+        .RMODE_B_i(ram_rmode_b2),
+        .WMODE_A_i(ram_wmode_a2),
+        .WMODE_B_i(ram_wmode_b2),
+        .WEN_A_i(ram_wen_a2),
+        .WEN_B_i(ram_wen_b2),
+        .REN_A_i(ram_ren_a2),
+        .REN_B_i(ram_ren_b2),
+        .CLK_A_i(sclk_a2),
+        .CLK_B_i(sclk_b2),
+        .BE_A_i(ram_be_a2),
+        .BE_B_i(ram_be_b2),
+        .ADDR_A_i(ram_addr_a2),
+        .ADDR_B_i(ram_addr_b2),
+        .WDATA_A_i(ram_wdata_a2),
+        .WDATA_B_i(ram_wdata_b2),
+        .RDATA_A_o(ram_rdata_a2),
+        .RDATA_B_o(ram_rdata_b2),
+        .EMPTY_o(EMPTY2),
+        .EPO_o(EPO2),
+        .EWM_o(EWM2),
+        .UNDERRUN_o(UNDERRUN2),
+        .FULL_o(FULL2),
+        .FMO_o(FMO2),
+        .FWM_o(FWM2),
+        .OVERRUN_o(OVERRUN2),
+        .FLUSH_ni(flush2),
+        .FMODE_i(ram_fmode2)
+    );
+endmodule
+
+module BRAM2x18_TDP (A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN, C1ADDR, C1DATA, C1EN, CLK1, CLK2, CLK3, CLK4, D1ADDR, D1DATA, D1EN, E1ADDR, E1DATA, E1EN, F1ADDR, F1DATA, F1EN, G1ADDR, G1DATA, G1EN, H1ADDR, H1DATA, H1EN);
+    parameter CFG_ABITS = 11;
+    parameter CFG_DBITS = 18;
+    parameter CFG_ENABLE_B = 4;
+    parameter CFG_ENABLE_D = 4;
+    parameter CFG_ENABLE_F = 4;
+    parameter CFG_ENABLE_H = 4;
+
+    parameter CLKPOL2 = 1;
+    parameter CLKPOL3 = 1;
+    parameter [18431:0] INIT0 = 18432'bx;
+    parameter [18431:0] INIT1 = 18432'bx;
+
+    localparam MODE_36 = 3'b011; // 36- or 32-bit
+    localparam MODE_18 = 3'b010; // 18- or 16-bit
+    localparam MODE_9 = 3'b001; // 9- or 8-bit
+    localparam MODE_4 = 3'b100; // 4-bit
+    localparam MODE_2 = 3'b110; // 2-bit
+    localparam MODE_1 = 3'b101; // 1-bit
+
+    input wire CLK1;
+    input wire CLK2;
+    input wire CLK3;
+    input wire CLK4;
+
+    input  wire [CFG_ABITS-1:0] A1ADDR;
+    output wire [CFG_DBITS-1:0] A1DATA;
+    input  wire A1EN;
+
+    input  wire [CFG_ABITS-1:0] B1ADDR;
+    input  wire [CFG_DBITS-1:0] B1DATA;
+    input  wire [CFG_ENABLE_B-1:0] B1EN;
+
+    input  wire [CFG_ABITS-1:0] C1ADDR;
+    output wire [CFG_DBITS-1:0] C1DATA;
+    input  wire C1EN;
+
+    input  wire [CFG_ABITS-1:0] D1ADDR;
+    input  wire [CFG_DBITS-1:0] D1DATA;
+    input  wire [CFG_ENABLE_D-1:0] D1EN;
+
+    input  wire [CFG_ABITS-1:0] E1ADDR;
+    output wire [CFG_DBITS-1:0] E1DATA;
+    input  wire E1EN;
+
+    input  wire [CFG_ABITS-1:0] F1ADDR;
+    input  wire [CFG_DBITS-1:0] F1DATA;
+    input  wire [CFG_ENABLE_F-1:0] F1EN;
+
+    input  wire [CFG_ABITS-1:0] G1ADDR;
+    output wire [CFG_DBITS-1:0] G1DATA;
+    input  wire G1EN;
+
+    input  wire [CFG_ABITS-1:0] H1ADDR;
+    input  wire [CFG_DBITS-1:0] H1DATA;
+    input  wire [CFG_ENABLE_H-1:0] H1EN;
+
+    wire FLUSH1;
+    wire FLUSH2;
+    wire SPLIT;
+
+    wire [13:CFG_ABITS] A1ADDR_CMPL = {14-CFG_ABITS{1'b0}};
+    wire [13:CFG_ABITS] B1ADDR_CMPL = {14-CFG_ABITS{1'b0}};
+    wire [13:CFG_ABITS] C1ADDR_CMPL = {14-CFG_ABITS{1'b0}};
+    wire [13:CFG_ABITS] D1ADDR_CMPL = {14-CFG_ABITS{1'b0}};
+    wire [13:CFG_ABITS] E1ADDR_CMPL = {14-CFG_ABITS{1'b0}};
+    wire [13:CFG_ABITS] F1ADDR_CMPL = {14-CFG_ABITS{1'b0}};
+    wire [13:CFG_ABITS] G1ADDR_CMPL = {14-CFG_ABITS{1'b0}};
+    wire [13:CFG_ABITS] H1ADDR_CMPL = {14-CFG_ABITS{1'b0}};
+
+    wire [13:0] A1ADDR_TOTAL = {A1ADDR_CMPL, A1ADDR};
+    wire [13:0] B1ADDR_TOTAL = {B1ADDR_CMPL, B1ADDR};
+    wire [13:0] C1ADDR_TOTAL = {C1ADDR_CMPL, C1ADDR};
+    wire [13:0] D1ADDR_TOTAL = {D1ADDR_CMPL, D1ADDR};
+    wire [13:0] E1ADDR_TOTAL = {E1ADDR_CMPL, E1ADDR};
+    wire [13:0] F1ADDR_TOTAL = {F1ADDR_CMPL, F1ADDR};
+    wire [13:0] G1ADDR_TOTAL = {G1ADDR_CMPL, G1ADDR};
+    wire [13:0] H1ADDR_TOTAL = {H1ADDR_CMPL, H1ADDR};
+
+    wire [17:CFG_DBITS] A1_RDATA_CMPL;
+    wire [17:CFG_DBITS] C1_RDATA_CMPL;
+    wire [17:CFG_DBITS] E1_RDATA_CMPL;
+    wire [17:CFG_DBITS] G1_RDATA_CMPL;
+
+    wire [17:CFG_DBITS] B1_WDATA_CMPL;
+    wire [17:CFG_DBITS] D1_WDATA_CMPL;
+    wire [17:CFG_DBITS] F1_WDATA_CMPL;
+    wire [17:CFG_DBITS] H1_WDATA_CMPL;
+
+    wire [13:0] PORT_A1_ADDR;
+    wire [13:0] PORT_A2_ADDR;
+    wire [13:0] PORT_B1_ADDR;
+    wire [13:0] PORT_B2_ADDR;
+
+    case (CFG_DBITS)
+        1: begin
+            assign PORT_A1_ADDR = A1EN ? A1ADDR_TOTAL : (B1EN ? B1ADDR_TOTAL : 14'd0);
+            assign PORT_B1_ADDR = C1EN ? C1ADDR_TOTAL : (D1EN ? D1ADDR_TOTAL : 14'd0);
+            assign PORT_A2_ADDR = E1EN ? E1ADDR_TOTAL : (F1EN ? F1ADDR_TOTAL : 14'd0);
+            assign PORT_B2_ADDR = G1EN ? G1ADDR_TOTAL : (H1EN ? H1ADDR_TOTAL : 14'd0);
+            defparam bram_2x18k.MODE_BITS = { 1'b1,
+                11'd10, 11'd10, 4'd0, MODE_1, MODE_1, MODE_1, MODE_1, 1'd0,
+                12'd10, 12'd10, 4'd0, MODE_1, MODE_1, MODE_1, MODE_1, 1'd0
+            };
+        end
+
+        2: begin
+            assign PORT_A1_ADDR = A1EN ? (A1ADDR_TOTAL << 1) : (B1EN ? (B1ADDR_TOTAL << 1) : 14'd0);
+            assign PORT_B1_ADDR = C1EN ? (C1ADDR_TOTAL << 1) : (D1EN ? (D1ADDR_TOTAL << 1) : 14'd0);
+            assign PORT_A2_ADDR = E1EN ? (E1ADDR_TOTAL << 1) : (F1EN ? (F1ADDR_TOTAL << 1) : 14'd0);
+            assign PORT_B2_ADDR = G1EN ? (G1ADDR_TOTAL << 1) : (H1EN ? (H1ADDR_TOTAL << 1) : 14'd0);
+            defparam bram_2x18k.MODE_BITS = { 1'b1,
+                11'd10, 11'd10, 4'd0, MODE_2, MODE_2, MODE_2, MODE_2, 1'd0,
+                12'd10, 12'd10, 4'd0, MODE_2, MODE_2, MODE_2, MODE_2, 1'd0
+            };
+        end
+
+        4: begin
+            assign PORT_A1_ADDR = A1EN ? (A1ADDR_TOTAL << 2) : (B1EN ? (B1ADDR_TOTAL << 2) : 14'd0);
+            assign PORT_B1_ADDR = C1EN ? (C1ADDR_TOTAL << 2) : (D1EN ? (D1ADDR_TOTAL << 2) : 14'd0);
+            assign PORT_A2_ADDR = E1EN ? (E1ADDR_TOTAL << 2) : (F1EN ? (F1ADDR_TOTAL << 2) : 14'd0);
+            assign PORT_B2_ADDR = G1EN ? (G1ADDR_TOTAL << 2) : (H1EN ? (H1ADDR_TOTAL << 2) : 14'd0);
+            defparam bram_2x18k.MODE_BITS = { 1'b1,
+                11'd10, 11'd10, 4'd0, MODE_4, MODE_4, MODE_4, MODE_4, 1'd0,
+                12'd10, 12'd10, 4'd0, MODE_4, MODE_4, MODE_4, MODE_4, 1'd0
+            };
+        end
+
+        8, 9: begin
+            assign PORT_A1_ADDR = A1EN ? (A1ADDR_TOTAL << 3) : (B1EN ? (B1ADDR_TOTAL << 3) : 14'd0);
+            assign PORT_B1_ADDR = C1EN ? (C1ADDR_TOTAL << 3) : (D1EN ? (D1ADDR_TOTAL << 3) : 14'd0);
+            assign PORT_A2_ADDR = E1EN ? (E1ADDR_TOTAL << 3) : (F1EN ? (F1ADDR_TOTAL << 3) : 14'd0);
+            assign PORT_B2_ADDR = G1EN ? (G1ADDR_TOTAL << 3) : (H1EN ? (H1ADDR_TOTAL << 3) : 14'd0);
+            defparam bram_2x18k.MODE_BITS = { 1'b1,
+                11'd10, 11'd10, 4'd0, MODE_9, MODE_9, MODE_9, MODE_9, 1'd0,
+                12'd10, 12'd10, 4'd0, MODE_9, MODE_9, MODE_9, MODE_9, 1'd0
+            };
+        end
+
+        16, 18: begin
+            assign PORT_A1_ADDR = A1EN ? (A1ADDR_TOTAL << 4) : (B1EN ? (B1ADDR_TOTAL << 4) : 14'd0);
+            assign PORT_B1_ADDR = C1EN ? (C1ADDR_TOTAL << 4) : (D1EN ? (D1ADDR_TOTAL << 4) : 14'd0);
+            assign PORT_A2_ADDR = E1EN ? (E1ADDR_TOTAL << 4) : (F1EN ? (F1ADDR_TOTAL << 4) : 14'd0);
+            assign PORT_B2_ADDR = G1EN ? (G1ADDR_TOTAL << 4) : (H1EN ? (H1ADDR_TOTAL << 4) : 14'd0);
+            defparam bram_2x18k.MODE_BITS = { 1'b1,
+                11'd10, 11'd10, 4'd0, MODE_18, MODE_18, MODE_18, MODE_18, 1'd0,
+                12'd10, 12'd10, 4'd0, MODE_18, MODE_18, MODE_18, MODE_18, 1'd0
+            };
+        end
+
+        default: begin
+            assign PORT_A1_ADDR = A1EN ? A1ADDR_TOTAL : (B1EN ? B1ADDR_TOTAL : 14'd0);
+            assign PORT_B1_ADDR = C1EN ? C1ADDR_TOTAL : (D1EN ? D1ADDR_TOTAL : 14'd0);
+            assign PORT_A2_ADDR = E1EN ? E1ADDR_TOTAL : (F1EN ? F1ADDR_TOTAL : 14'd0);
+            assign PORT_B2_ADDR = G1EN ? G1ADDR_TOTAL : (H1EN ? H1ADDR_TOTAL : 14'd0);
+            defparam bram_2x18k.MODE_BITS = { 1'b1,
+                11'd10, 11'd10, 4'd0, MODE_36, MODE_36, MODE_36, MODE_36, 1'd0,
+                12'd10, 12'd10, 4'd0, MODE_36, MODE_36, MODE_36, MODE_36, 1'd0
+            };
+        end
+    endcase
+
+    assign FLUSH1 = 1'b0;
+    assign FLUSH2 = 1'b0;
+
+    wire [17:0] PORT_A1_RDATA = {A1_RDATA_CMPL, A1DATA};
+    wire [17:0] PORT_B1_RDATA = {C1_RDATA_CMPL, C1DATA};
+    wire [17:0] PORT_A2_RDATA = {E1_RDATA_CMPL, E1DATA};
+    wire [17:0] PORT_B2_RDATA = {G1_RDATA_CMPL, G1DATA};
+
+    wire [17:0] PORT_A1_WDATA = {B1_WDATA_CMPL, B1DATA};
+    wire [17:0] PORT_B1_WDATA = {D1_WDATA_CMPL, D1DATA};
+    wire [17:0] PORT_A2_WDATA = {F1_WDATA_CMPL, F1DATA};
+    wire [17:0] PORT_B2_WDATA = {H1_WDATA_CMPL, H1DATA};
+
+    wire PORT_A1_CLK = CLK1;
+    wire PORT_A2_CLK = CLK3;
+    wire PORT_B1_CLK = CLK2;
+    wire PORT_B2_CLK = CLK4;
+
+    wire PORT_A1_REN = A1EN;
+    wire PORT_A1_WEN = B1EN[0];
+    wire [CFG_ENABLE_B-1:0] PORT_A1_BE = {B1EN[1],B1EN[0]};
+
+    wire PORT_A2_REN = E1EN;
+    wire PORT_A2_WEN = F1EN[0];
+    wire [CFG_ENABLE_F-1:0] PORT_A2_BE = {F1EN[1],F1EN[0]};
+
+    wire PORT_B1_REN = C1EN;
+    wire PORT_B1_WEN = D1EN[0];
+    wire [CFG_ENABLE_D-1:0] PORT_B1_BE = {D1EN[1],D1EN[0]};
+
+    wire PORT_B2_REN = G1EN;
+    wire PORT_B2_WEN = H1EN[0];
+    wire [CFG_ENABLE_H-1:0] PORT_B2_BE = {H1EN[1],H1EN[0]};
+
+    TDP36K bram_2x18k (
+        .WDATA_A1_i(PORT_A1_WDATA),
+        .RDATA_A1_o(PORT_A1_RDATA),
+        .ADDR_A1_i(PORT_A1_ADDR),
+        .CLK_A1_i(PORT_A1_CLK),
+        .REN_A1_i(PORT_A1_REN),
+        .WEN_A1_i(PORT_A1_WEN),
+        .BE_A1_i(PORT_A1_BE),
+
+        .WDATA_A2_i(PORT_A2_WDATA),
+        .RDATA_A2_o(PORT_A2_RDATA),
+        .ADDR_A2_i(PORT_A2_ADDR),
+        .CLK_A2_i(PORT_A2_CLK),
+        .REN_A2_i(PORT_A2_REN),
+        .WEN_A2_i(PORT_A2_WEN),
+        .BE_A2_i(PORT_A2_BE),
+
+        .WDATA_B1_i(PORT_B1_WDATA),
+        .RDATA_B1_o(PORT_B1_RDATA),
+        .ADDR_B1_i(PORT_B1_ADDR),
+        .CLK_B1_i(PORT_B1_CLK),
+        .REN_B1_i(PORT_B1_REN),
+        .WEN_B1_i(PORT_B1_WEN),
+        .BE_B1_i(PORT_B1_BE),
+
+        .WDATA_B2_i(PORT_B2_WDATA),
+        .RDATA_B2_o(PORT_B2_RDATA),
+        .ADDR_B2_i(PORT_B2_ADDR),
+        .CLK_B2_i(PORT_B2_CLK),
+        .REN_B2_i(PORT_B2_REN),
+        .WEN_B2_i(PORT_B2_WEN),
+        .BE_B2_i(PORT_B2_BE),
+
+        .FLUSH1_i(FLUSH1),
+        .FLUSH2_i(FLUSH2)
+    );
+endmodule
+
+module BRAM2x18_SDP (A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN, C1ADDR, C1DATA, C1EN, CLK1, CLK2, D1ADDR, D1DATA, D1EN);
+    parameter CFG_ABITS = 11;
+    parameter CFG_DBITS = 18;
+    parameter CFG_ENABLE_B = 4;
+    parameter CFG_ENABLE_D = 4;
+
+    parameter CLKPOL2 = 1;
+    parameter CLKPOL3 = 1;
+    parameter [18431:0] INIT0 = 18432'bx;
+    parameter [18431:0] INIT1 = 18432'bx;
+
+    localparam MODE_36 = 3'b011; // 36- or 32-bit
+    localparam MODE_18 = 3'b010; // 18- or 16-bit
+    localparam MODE_9 = 3'b001; // 9- or 8-bit
+    localparam MODE_4 = 3'b100; // 4-bit
+    localparam MODE_2 = 3'b110; // 2-bit
+    localparam MODE_1 = 3'b101; // 1-bit
+
+    input  wire CLK1;
+    input  wire CLK2;
+
+    input  wire [CFG_ABITS-1:0] A1ADDR;
+    output wire [CFG_DBITS-1:0] A1DATA;
+    input  wire A1EN;
+
+    input  wire [CFG_ABITS-1:0] B1ADDR;
+    input  wire [CFG_DBITS-1:0] B1DATA;
+    input  wire [CFG_ENABLE_B-1:0] B1EN;
+
+    input  wire [CFG_ABITS-1:0] C1ADDR;
+    output wire [CFG_DBITS-1:0] C1DATA;
+    input  wire C1EN;
+
+    input  wire [CFG_ABITS-1:0] D1ADDR;
+    input  wire [CFG_DBITS-1:0] D1DATA;
+    input  wire [CFG_ENABLE_D-1:0] D1EN;
+
+    wire FLUSH1;
+    wire FLUSH2;
+
+    wire [13:CFG_ABITS] A1ADDR_CMPL = {14-CFG_ABITS{1'b0}};
+    wire [13:CFG_ABITS] B1ADDR_CMPL = {14-CFG_ABITS{1'b0}};
+    wire [13:CFG_ABITS] C1ADDR_CMPL = {14-CFG_ABITS{1'b0}};
+    wire [13:CFG_ABITS] D1ADDR_CMPL = {14-CFG_ABITS{1'b0}};
+
+    wire [13:0] A1ADDR_TOTAL = {A1ADDR_CMPL, A1ADDR};
+    wire [13:0] B1ADDR_TOTAL = {B1ADDR_CMPL, B1ADDR};
+    wire [13:0] C1ADDR_TOTAL = {C1ADDR_CMPL, C1ADDR};
+    wire [13:0] D1ADDR_TOTAL = {D1ADDR_CMPL, D1ADDR};
+
+    wire [17:CFG_DBITS] A1_RDATA_CMPL;
+    wire [17:CFG_DBITS] C1_RDATA_CMPL;
+
+    wire [17:CFG_DBITS] B1_WDATA_CMPL;
+    wire [17:CFG_DBITS] D1_WDATA_CMPL;
+
+    wire [13:0] PORT_A1_ADDR;
+    wire [13:0] PORT_A2_ADDR;
+    wire [13:0] PORT_B1_ADDR;
+    wire [13:0] PORT_B2_ADDR;
+
+    case (CFG_DBITS)
+        1: begin
+            assign PORT_A1_ADDR = A1ADDR_TOTAL;
+            assign PORT_B1_ADDR = B1ADDR_TOTAL;
+            assign PORT_A2_ADDR = C1ADDR_TOTAL;
+            assign PORT_B2_ADDR = D1ADDR_TOTAL;
+            defparam bram_2x18k.MODE_BITS = { 1'b1,
+                11'd10, 11'd10, 4'd0, MODE_1, MODE_1, MODE_1, MODE_1, 1'd0,
+                12'd10, 12'd10, 4'd0, MODE_1, MODE_1, MODE_1, MODE_1, 1'd0
+            };
+        end
+
+        2: begin
+            assign PORT_A1_ADDR = A1ADDR_TOTAL << 1;
+            assign PORT_B1_ADDR = B1ADDR_TOTAL << 1;
+            assign PORT_A2_ADDR = C1ADDR_TOTAL << 1;
+            assign PORT_B2_ADDR = D1ADDR_TOTAL << 1;
+            defparam bram_2x18k.MODE_BITS = { 1'b1,
+                11'd10, 11'd10, 4'd0, MODE_2, MODE_2, MODE_2, MODE_2, 1'd0,
+                12'd10, 12'd10, 4'd0, MODE_2, MODE_2, MODE_2, MODE_2, 1'd0
+            };
+        end
+
+        4: begin
+            assign PORT_A1_ADDR = A1ADDR_TOTAL << 2;
+            assign PORT_B1_ADDR = B1ADDR_TOTAL << 2;
+            assign PORT_A2_ADDR = C1ADDR_TOTAL << 2;
+            assign PORT_B2_ADDR = D1ADDR_TOTAL << 2;
+            defparam bram_2x18k.MODE_BITS = { 1'b1,
+                11'd10, 11'd10, 4'd0, MODE_4, MODE_4, MODE_4, MODE_4, 1'd0,
+                12'd10, 12'd10, 4'd0, MODE_4, MODE_4, MODE_4, MODE_4, 1'd0
+            };
+        end
+
+        8, 9: begin
+            assign PORT_A1_ADDR = A1ADDR_TOTAL << 3;
+            assign PORT_B1_ADDR = B1ADDR_TOTAL << 3;
+            assign PORT_A2_ADDR = C1ADDR_TOTAL << 3;
+            assign PORT_B2_ADDR = D1ADDR_TOTAL << 3;
+            defparam bram_2x18k.MODE_BITS = { 1'b1,
+                11'd10, 11'd10, 4'd0, MODE_9, MODE_9, MODE_9, MODE_9, 1'd0,
+                12'd10, 12'd10, 4'd0, MODE_9, MODE_9, MODE_9, MODE_9, 1'd0
+            };
+        end
+
+        16, 18: begin
+            assign PORT_A1_ADDR = A1ADDR_TOTAL << 4;
+            assign PORT_B1_ADDR = B1ADDR_TOTAL << 4;
+            assign PORT_A2_ADDR = C1ADDR_TOTAL << 4;
+            assign PORT_B2_ADDR = D1ADDR_TOTAL << 4;
+            defparam bram_2x18k.MODE_BITS = { 1'b1,
+                11'd10, 11'd10, 4'd0, MODE_18, MODE_18, MODE_18, MODE_18, 1'd0,
+                12'd10, 12'd10, 4'd0, MODE_18, MODE_18, MODE_18, MODE_18, 1'd0
+            };
+        end
+
+        default: begin
+            assign PORT_A1_ADDR = A1ADDR_TOTAL;
+            assign PORT_B1_ADDR = B1ADDR_TOTAL;
+            assign PORT_A2_ADDR = D1ADDR_TOTAL;
+            assign PORT_B2_ADDR = C1ADDR_TOTAL;
+            defparam bram_2x18k.MODE_BITS = { 1'b1,
+                11'd10, 11'd10, 4'd0, MODE_36, MODE_36, MODE_36, MODE_36, 1'd0,
+                12'd10, 12'd10, 4'd0, MODE_36, MODE_36, MODE_36, MODE_36, 1'd0
+            };
+        end
+    endcase
+
+    assign FLUSH1 = 1'b0;
+    assign FLUSH2 = 1'b0;
+
+    wire [17:0] PORT_A1_RDATA;
+    wire [17:0] PORT_B1_RDATA;
+    wire [17:0] PORT_A2_RDATA;
+    wire [17:0] PORT_B2_RDATA;
+
+    wire [17:0] PORT_A1_WDATA;
+    wire [17:0] PORT_B1_WDATA;
+    wire [17:0] PORT_A2_WDATA;
+    wire [17:0] PORT_B2_WDATA;
+
+    // Assign read/write data - handle special case for 9bit mode
+    // parity bit for 9bit mode is placed in R/W port on bit #16
+    case (CFG_DBITS)
+        9: begin
+            assign A1DATA = {PORT_A1_RDATA[16], PORT_A1_RDATA[7:0]};
+            assign C1DATA = {PORT_A2_RDATA[16], PORT_A2_RDATA[7:0]};
+            assign PORT_A1_WDATA = {18{1'b0}};
+            assign PORT_B1_WDATA = {B1_WDATA_CMPL[17], B1DATA[8], B1_WDATA_CMPL[16:9], B1DATA[7:0]};
+            assign PORT_A2_WDATA = {18{1'b0}};
+            assign PORT_B2_WDATA = {D1_WDATA_CMPL[17], D1DATA[8], D1_WDATA_CMPL[16:9], D1DATA[7:0]};
+        end
+        default: begin
+            assign A1DATA = PORT_A1_RDATA[CFG_DBITS-1:0];
+            assign C1DATA = PORT_A2_RDATA[CFG_DBITS-1:0];
+            assign PORT_A1_WDATA = {18{1'b1}};
+            assign PORT_B1_WDATA = {B1_WDATA_CMPL, B1DATA};
+            assign PORT_A2_WDATA = {18{1'b1}};
+            assign PORT_B2_WDATA = {D1_WDATA_CMPL, D1DATA};
+
+        end
+    endcase
+
+    wire PORT_A1_CLK = CLK1;
+    wire PORT_A2_CLK = CLK2;
+    wire PORT_B1_CLK = CLK1;
+    wire PORT_B2_CLK = CLK2;
+
+    wire PORT_A1_REN = A1EN;
+    wire PORT_A1_WEN = 1'b0;
+    wire [CFG_ENABLE_B-1:0] PORT_A1_BE = {PORT_A1_WEN,PORT_A1_WEN};
+
+    wire PORT_A2_REN = C1EN;
+    wire PORT_A2_WEN = 1'b0;
+    wire [CFG_ENABLE_D-1:0] PORT_A2_BE = {PORT_A2_WEN,PORT_A2_WEN};
+
+    wire PORT_B1_REN = 1'b0;
+    wire PORT_B1_WEN = B1EN[0];
+    wire [CFG_ENABLE_B-1:0] PORT_B1_BE = {B1EN[1],B1EN[0]};
+
+    wire PORT_B2_REN = 1'b0;
+    wire PORT_B2_WEN = D1EN[0];
+    wire [CFG_ENABLE_D-1:0] PORT_B2_BE = {D1EN[1],D1EN[0]};
+
+    TDP36K  bram_2x18k (
+        .WDATA_A1_i(PORT_A1_WDATA),
+        .RDATA_A1_o(PORT_A1_RDATA),
+        .ADDR_A1_i(PORT_A1_ADDR),
+        .CLK_A1_i(PORT_A1_CLK),
+        .REN_A1_i(PORT_A1_REN),
+        .WEN_A1_i(PORT_A1_WEN),
+        .BE_A1_i(PORT_A1_BE),
+
+        .WDATA_A2_i(PORT_A2_WDATA),
+        .RDATA_A2_o(PORT_A2_RDATA),
+        .ADDR_A2_i(PORT_A2_ADDR),
+        .CLK_A2_i(PORT_A2_CLK),
+        .REN_A2_i(PORT_A2_REN),
+        .WEN_A2_i(PORT_A2_WEN),
+        .BE_A2_i(PORT_A2_BE),
+
+        .WDATA_B1_i(PORT_B1_WDATA),
+        .RDATA_B1_o(PORT_B1_RDATA),
+        .ADDR_B1_i(PORT_B1_ADDR),
+        .CLK_B1_i(PORT_B1_CLK),
+        .REN_B1_i(PORT_B1_REN),
+        .WEN_B1_i(PORT_B1_WEN),
+        .BE_B1_i(PORT_B1_BE),
+
+        .WDATA_B2_i(PORT_B2_WDATA),
+        .RDATA_B2_o(PORT_B2_RDATA),
+        .ADDR_B2_i(PORT_B2_ADDR),
+        .CLK_B2_i(PORT_B2_CLK),
+        .REN_B2_i(PORT_B2_REN),
+        .WEN_B2_i(PORT_B2_WEN),
+        .BE_B2_i(PORT_B2_BE),
+
+        .FLUSH1_i(FLUSH1),
+        .FLUSH2_i(FLUSH2)
+    );
+endmodule
+
+module \_$_mem_v2_asymmetric (RD_ADDR, RD_ARST, RD_CLK, RD_DATA, RD_EN, RD_SRST, WR_ADDR, WR_CLK, WR_DATA, WR_EN);
+    localparam CFG_ABITS = 10;
+    localparam CFG_DBITS = 36;
+    localparam CFG_ENABLE_B = 4;
+
+    localparam CLKPOL2 = 1;
+    localparam CLKPOL3 = 1;
+
+    parameter READ_ADDR_WIDTH = 11;
+    parameter READ_DATA_WIDTH = 16;
+    parameter WRITE_ADDR_WIDTH = 10;
+    parameter WRITE_DATA_WIDTH = 32;
+    parameter ABITS = 0;
+    parameter MEMID = 0;
+    parameter [36863:0] INIT = 36864'bx;
+    parameter OFFSET = 0;
+    parameter RD_ARST_VALUE = 0;
+    parameter RD_CE_OVER_SRST = 0;
+    parameter RD_CLK_ENABLE = 0;
+    parameter RD_CLK_POLARITY = 0;
+    parameter RD_COLLISION_X_MASK = 0;
+    parameter RD_INIT_VALUE = 0;
+    parameter RD_PORTS = 0;
+    parameter RD_SRST_VALUE = 0;
+    parameter RD_TRANSPARENCY_MASK = 0;
+    parameter RD_WIDE_CONTINUATION = 0;
+    parameter SIZE = 0;
+    parameter WIDTH = 0;
+    parameter WR_CLK_ENABLE = 0;
+    parameter WR_CLK_POLARITY = 0;
+    parameter WR_PORTS = 0;
+    parameter WR_PRIORITY_MASK = 0;
+    parameter WR_WIDE_CONTINUATION = 0;
+
+    localparam MODE_36 = 3'b011; // 36- or 32-bit
+    localparam MODE_18 = 3'b010; // 18- or 16-bit
+    localparam MODE_9 = 3'b001; // 9- or 8-bit
+    localparam MODE_4 = 3'b100; // 4-bit
+    localparam MODE_2 = 3'b110; // 2-bit
+    localparam MODE_1 = 3'b101; // 1-bit
+
+    input  wire RD_CLK;
+    input  wire WR_CLK;
+    input  wire RD_ARST;
+    input  wire RD_SRST;
+
+    input  wire [CFG_ABITS-1:0] RD_ADDR;
+    output wire [CFG_DBITS-1:0] RD_DATA;
+    input  wire RD_EN;
+
+    input  wire [CFG_ABITS-1:0] WR_ADDR;
+    input  wire [CFG_DBITS-1:0] WR_DATA;
+    input  wire [CFG_ENABLE_B-1:0] WR_EN;
+
+    wire [14:0] RD_ADDR_15;
+    wire [14:0] WR_ADDR_15;
+
+    wire [35:0] DOBDO;
+
+    wire [14:CFG_ABITS] RD_ADDR_CMPL;
+    wire [14:CFG_ABITS] WR_ADDR_CMPL;
+    wire [35:CFG_DBITS] RD_DATA_CMPL;
+    wire [35:CFG_DBITS] WR_DATA_CMPL;
+
+    wire [14:0] RD_ADDR_TOTAL;
+    wire [14:0] WR_ADDR_TOTAL;
+    wire [35:0] RD_DATA_TOTAL;
+    wire [35:0] WR_DATA_TOTAL;
+
+    wire FLUSH1;
+    wire FLUSH2;
+
+    assign RD_ADDR_CMPL = {15-CFG_ABITS{1'b0}};
+    assign WR_ADDR_CMPL = {15-CFG_ABITS{1'b0}};
+
+    assign RD_ADDR_TOTAL = {RD_ADDR_CMPL, RD_ADDR};
+    assign WR_ADDR_TOTAL = {WR_ADDR_CMPL, WR_ADDR};
+
+    assign RD_DATA_TOTAL = {RD_DATA_CMPL, RD_DATA};
+    assign WR_DATA_TOTAL = {WR_DATA_CMPL, WR_DATA};
+
+    case (CFG_DBITS)
+        1: begin
+            assign RD_ADDR_15 = RD_ADDR_TOTAL;
+            assign WR_ADDR_15 = WR_ADDR_TOTAL;
+            defparam bram_asymmetric.MODE_BITS = { 1'b0,
+                11'd10, 11'd10, 4'd0, MODE_1, MODE_1, MODE_1, MODE_1, 1'd0,
+                12'd10, 12'd10, 4'd0, MODE_1, MODE_1, MODE_1, MODE_1, 1'd0
+            };
+        end
+
+        2: begin
+            assign RD_ADDR_15 = RD_ADDR_TOTAL << 1;
+            assign WR_ADDR_15 = WR_ADDR_TOTAL << 1;
+            defparam bram_asymmetric.MODE_BITS = { 1'b0,
+                11'd10, 11'd10, 4'd0, MODE_2, MODE_2, MODE_2, MODE_2, 1'd0,
+                12'd10, 12'd10, 4'd0, MODE_2, MODE_2, MODE_2, MODE_2, 1'd0
+            };
+        end
+
+        4: begin
+            assign RD_ADDR_15 = RD_ADDR_TOTAL << 2;
+            assign WR_ADDR_15 = WR_ADDR_TOTAL << 2;
+            defparam bram_asymmetric.MODE_BITS = { 1'b0,
+                11'd10, 11'd10, 4'd0, MODE_4, MODE_4, MODE_4, MODE_4, 1'd0,
+                12'd10, 12'd10, 4'd0, MODE_4, MODE_4, MODE_4, MODE_4, 1'd0
+            };
+        end
+        8, 9: begin
+            assign RD_ADDR_15 = RD_ADDR_TOTAL << 3;
+            assign WR_ADDR_15 = WR_ADDR_TOTAL << 3;
+            defparam bram_asymmetric.MODE_BITS = { 1'b0,
+                11'd10, 11'd10, 4'd0, MODE_9, MODE_9, MODE_9, MODE_9, 1'd0,
+                12'd10, 12'd10, 4'd0, MODE_9, MODE_9, MODE_9, MODE_9, 1'd0
+            };
+        end
+
+        16, 18: begin
+            assign RD_ADDR_15 = RD_ADDR_TOTAL << 4;
+            assign WR_ADDR_15 = WR_ADDR_TOTAL << 4;
+            defparam bram_asymmetric.MODE_BITS = { 1'b0,
+                11'd10, 11'd10, 4'd0, MODE_18, MODE_18, MODE_18, MODE_18, 1'd0,
+                12'd10, 12'd10, 4'd0, MODE_18, MODE_18, MODE_18, MODE_18, 1'd0
+            };
+        end
+        32, 36: begin
+            assign RD_ADDR_15 = RD_ADDR_TOTAL << 5;
+            assign WR_ADDR_15 = WR_ADDR_TOTAL << 5;
+            defparam bram_asymmetric.MODE_BITS = { 1'b0,
+                11'd10, 11'd10, 4'd0, MODE_36, MODE_36, MODE_36, MODE_36, 1'd0,
+                12'd10, 12'd10, 4'd0, MODE_36, MODE_36, MODE_36, MODE_36, 1'd0
+            };
+        end
+        default: begin
+            assign RD_ADDR_15 = RD_ADDR_TOTAL;
+            assign WR_ADDR_15 = WR_ADDR_TOTAL;
+            defparam bram_asymmetric.MODE_BITS = { 1'b0,
+                11'd10, 11'd10, 4'd0, MODE_36, MODE_36, MODE_36, MODE_36, 1'd0,
+                12'd10, 12'd10, 4'd0, MODE_36, MODE_36, MODE_36, MODE_36, 1'd0
+            };
+        end
+    endcase
+
+    assign FLUSH1 = 1'b0;
+    assign FLUSH2 = 1'b0;
+
+    TDP36K bram_asymmetric (
+        .RESET_ni(1'b1),
+        .WDATA_A1_i(18'h3FFFF),
+        .WDATA_A2_i(18'h3FFFF),
+        .RDATA_A1_o(RD_DATA_TOTAL[17:0]),
+        .RDATA_A2_o(RD_DATA_TOTAL[35:18]),
+        .ADDR_A1_i(RD_ADDR_15),
+        .ADDR_A2_i(RD_ADDR_15),
+        .CLK_A1_i(RD_CLK),
+        .CLK_A2_i(RD_CLK),
+        .REN_A1_i(RD_EN),
+        .REN_A2_i(RD_EN),
+        .WEN_A1_i(1'b0),
+        .WEN_A2_i(1'b0),
+        .BE_A1_i({RD_EN, RD_EN}),
+        .BE_A2_i({RD_EN, RD_EN}),
+
+        .WDATA_B1_i(WR_DATA[17:0]),
+        .WDATA_B2_i(WR_DATA[35:18]),
+        .RDATA_B1_o(DOBDO[17:0]),
+        .RDATA_B2_o(DOBDO[35:18]),
+        .ADDR_B1_i(WR_ADDR_15),
+        .ADDR_B2_i(WR_ADDR_15),
+        .CLK_B1_i(WR_CLK),
+        .CLK_B2_i(WR_CLK),
+        .REN_B1_i(1'b0),
+        .REN_B2_i(1'b0),
+        .WEN_B1_i(WR_EN[0]),
+        .WEN_B2_i(WR_EN[0]),
+        .BE_B1_i(WR_EN[1:0]),
+        .BE_B2_i(WR_EN[3:2]),
+
+        .FLUSH1_i(FLUSH1),
+        .FLUSH2_i(FLUSH2)
+    );
+endmodule
+
+module BRAM2x18_SP (
+    RESET_ni,
+    
+    WEN1_i,
+    REN1_i,
+    WR1_CLK_i,
+    RD1_CLK_i,
+    WR1_BE_i,
+    WR1_ADDR_i,
+    RD1_ADDR_i,
+    WDATA1_i,
+    RDATA1_o,
+    
+    WEN2_i,
+    REN2_i,
+    WR2_CLK_i,
+    RD2_CLK_i,
+    WR2_BE_i,
+    WR2_ADDR_i,
+    RD2_ADDR_i,
+    WDATA2_i,
+    RDATA2_o
+);
+
+parameter WR_ADDR_WIDTH = 10;
+parameter RD_ADDR_WIDTH = 10;
+parameter WR_DATA_WIDTH = 18;
+parameter RD_DATA_WIDTH = 18;
+parameter BE1_WIDTH = 2;
+parameter BE2_WIDTH = 2;
+
+localparam MODE_36 = 3'b011; // 36- or 32-bit
+localparam MODE_18 = 3'b010; // 18- or 16-bit
+localparam MODE_9 = 3'b001; // 9- or 8-bit
+localparam MODE_4 = 3'b100; // 4-bit
+localparam MODE_2 = 3'b110; // 2-bit
+localparam MODE_1 = 3'b101; // 1-bit
+
+input wire RESET_ni;
+
+input wire WEN1_i;
+input wire REN1_i;
+input wire WR1_CLK_i;
+input wire RD1_CLK_i;
+input wire [BE1_WIDTH-1:0] WR1_BE_i;
+input wire [WR_ADDR_WIDTH-1 :0] WR1_ADDR_i;
+input wire [RD_ADDR_WIDTH-1 :0] RD1_ADDR_i;
+input wire [WR_DATA_WIDTH-1 :0] WDATA1_i;
+output wire [RD_DATA_WIDTH-1 :0] RDATA1_o;
+
+input wire WEN2_i;
+input wire REN2_i;
+input wire WR2_CLK_i;
+input wire RD2_CLK_i;
+input wire [BE2_WIDTH-1:0] WR2_BE_i;
+input wire [WR_ADDR_WIDTH-1 :0] WR2_ADDR_i;
+input wire [RD_ADDR_WIDTH-1 :0] RD2_ADDR_i;
+input wire [WR_DATA_WIDTH-1 :0] WDATA2_i;
+output wire [RD_DATA_WIDTH-1 :0] RDATA2_o;
+
+//localparam READ_DATA_BITS_TO_SKIP = 18 - RD_DATA_WIDTH;
+
+wire [14:RD_ADDR_WIDTH] RD1_ADDR_CMPL;
+wire [14:WR_ADDR_WIDTH] WR1_ADDR_CMPL;
+wire [17:RD_DATA_WIDTH] RD1_DATA_CMPL;
+wire [17:WR_DATA_WIDTH] WR1_DATA_CMPL;
+           
+wire [14:RD_ADDR_WIDTH] RD2_ADDR_CMPL;
+wire [14:WR_ADDR_WIDTH] WR2_ADDR_CMPL;
+wire [17:RD_DATA_WIDTH] RD2_DATA_CMPL;
+wire [17:WR_DATA_WIDTH] WR2_DATA_CMPL;
+
+wire [14:0] RD1_ADDR_TOTAL;
+wire [14:0] WR1_ADDR_TOTAL;
+
+wire [14:0] RD2_ADDR_TOTAL;
+wire [14:0] WR2_ADDR_TOTAL;
+
+wire [14:0] RD1_ADDR_SHIFTED;
+wire [14:0] WR1_ADDR_SHIFTED;
+
+wire [14:0] RD2_ADDR_SHIFTED;
+wire [14:0] WR2_ADDR_SHIFTED;
+
+wire [1:0] WR1_BE;
+wire [1:0] WR2_BE;
+
+wire FLUSH1;
+wire FLUSH2;
+
+generate
+  if (WR_ADDR_WIDTH == 15) begin
+    assign WR1_ADDR_TOTAL = WR1_ADDR_i;
+    assign WR2_ADDR_TOTAL = WR2_ADDR_i;
+  end else begin
+    assign WR1_ADDR_TOTAL[14:WR_ADDR_WIDTH] = 0;
+    assign WR1_ADDR_TOTAL[WR_ADDR_WIDTH-1:0] = WR1_ADDR_i;
+    assign WR2_ADDR_TOTAL[14:WR_ADDR_WIDTH] = 0;
+    assign WR2_ADDR_TOTAL[WR_ADDR_WIDTH-1:0] = WR2_ADDR_i;
+  end
+endgenerate
+
+generate
+  if (RD_ADDR_WIDTH == 15) begin
+    assign RD1_ADDR_TOTAL = RD1_ADDR_i;
+    assign RD2_ADDR_TOTAL = RD2_ADDR_i;
+  end else begin
+    assign RD1_ADDR_TOTAL[14:RD_ADDR_WIDTH] = 0;
+    assign RD1_ADDR_TOTAL[RD_ADDR_WIDTH-1:0] = RD1_ADDR_i;
+    assign RD2_ADDR_TOTAL[14:RD_ADDR_WIDTH] = 0;
+    assign RD2_ADDR_TOTAL[RD_ADDR_WIDTH-1:0] = RD2_ADDR_i;
+  end
+endgenerate
+
+// Apply shift
+case (RD_DATA_WIDTH)
+	1: begin
+		assign RD1_ADDR_SHIFTED = RD1_ADDR_TOTAL;
+	end
+	2: begin
+		assign RD1_ADDR_SHIFTED = RD1_ADDR_TOTAL << 1;
+	end
+	4: begin
+		assign RD1_ADDR_SHIFTED = RD1_ADDR_TOTAL << 2;
+	end
+	8, 9: begin
+		assign RD1_ADDR_SHIFTED = RD1_ADDR_TOTAL << 3;
+	end
+	16, 18: begin
+		assign RD1_ADDR_SHIFTED = RD1_ADDR_TOTAL << 4;
+	end
+	default: begin
+		assign RD1_ADDR_SHIFTED = RD1_ADDR_TOTAL;
+	end
+endcase
+
+case (WR_DATA_WIDTH)
+	1: begin
+		assign WR1_ADDR_SHIFTED = WR1_ADDR_TOTAL;
+	end
+	2: begin
+		assign WR1_ADDR_SHIFTED = WR1_ADDR_TOTAL << 1;
+	end
+	4: begin
+		assign WR1_ADDR_SHIFTED = WR1_ADDR_TOTAL << 2;
+	end
+	8, 9: begin
+		assign WR1_ADDR_SHIFTED = WR1_ADDR_TOTAL << 3;
+	end
+	16, 18: begin
+		assign WR1_ADDR_SHIFTED = WR1_ADDR_TOTAL << 4;
+	end
+	default: begin
+		assign WR1_ADDR_SHIFTED = WR1_ADDR_TOTAL;
+	end
+endcase
+
+case (RD_DATA_WIDTH)
+	1: begin
+		assign RD2_ADDR_SHIFTED = RD2_ADDR_TOTAL;
+	end
+	2: begin
+		assign RD2_ADDR_SHIFTED = RD2_ADDR_TOTAL << 1;
+	end
+	4: begin
+		assign RD2_ADDR_SHIFTED = RD2_ADDR_TOTAL << 2;
+	end
+	8, 9: begin
+		assign RD2_ADDR_SHIFTED = RD2_ADDR_TOTAL << 3;
+	end
+	16, 18: begin
+		assign RD2_ADDR_SHIFTED = RD2_ADDR_TOTAL << 4;
+	end
+	default: begin
+		assign RD2_ADDR_SHIFTED = RD2_ADDR_TOTAL;
+	end
+endcase
+
+case (WR_DATA_WIDTH)
+	1: begin
+		assign WR2_ADDR_SHIFTED = WR2_ADDR_TOTAL;
+	end
+	2: begin
+		assign WR2_ADDR_SHIFTED = WR2_ADDR_TOTAL << 1;
+	end
+	4: begin
+		assign WR2_ADDR_SHIFTED = WR2_ADDR_TOTAL << 2;
+	end
+	8, 9: begin
+		assign WR2_ADDR_SHIFTED = WR2_ADDR_TOTAL << 3;
+	end
+	16, 18: begin
+		assign WR2_ADDR_SHIFTED = WR2_ADDR_TOTAL << 4;
+	end
+	default: begin
+		assign WR2_ADDR_SHIFTED = WR2_ADDR_TOTAL;
+	end
+endcase
+
+case (BE1_WIDTH)
+	2: begin
+		assign WR1_BE = WR1_BE_i[BE1_WIDTH-1 :0];
+	end
+	default: begin
+		assign WR1_BE[1:BE1_WIDTH] = 0;
+    assign WR1_BE[BE1_WIDTH-1 :0] = WR1_BE_i[BE1_WIDTH-1 :0];
+	end
+endcase
+
+case (BE2_WIDTH)
+	2: begin
+		assign WR2_BE = WR2_BE_i[BE2_WIDTH-1 :0];
+	end
+	default: begin
+		assign WR2_BE[1:BE2_WIDTH] = 0;
+    assign WR2_BE[BE2_WIDTH-1 :0] = WR2_BE_i[BE2_WIDTH-1 :0];
+	end
+endcase
+
+assign FLUSH1 = 1'b0;
+assign FLUSH2 = 1'b0;
+
+// TODO configure per width
+wire [17:0] PORT_B1_RDATA;
+wire [17:0] PORT_B2_RDATA;
+wire [17:0] PORT_A1_WDATA;
+wire [17:0] PORT_A2_WDATA;
+
+generate
+  if (WR_DATA_WIDTH == 18) begin
+    assign PORT_A1_WDATA[WR_DATA_WIDTH-1:0] = WDATA1_i[WR_DATA_WIDTH-1:0];
+    assign PORT_A2_WDATA[WR_DATA_WIDTH-1:0] = WDATA2_i[WR_DATA_WIDTH-1:0];
+  end else if (WR_DATA_WIDTH == 9) begin
+    assign PORT_A1_WDATA = {19'h0, WDATA1_i[8], 8'h0, WDATA1_i[7:0]};
+    assign PORT_A2_WDATA = {19'h0, WDATA2_i[8], 8'h0, WDATA2_i[7:0]};
+  end else begin
+    assign PORT_A1_WDATA[17:WR_DATA_WIDTH] = 0;
+    assign PORT_A1_WDATA[WR_DATA_WIDTH-1:0] = WDATA1_i[WR_DATA_WIDTH-1:0];
+    assign PORT_A2_WDATA[17:WR_DATA_WIDTH] = 0;
+    assign PORT_A2_WDATA[WR_DATA_WIDTH-1:0] = WDATA2_i[WR_DATA_WIDTH-1:0];
+  end
+endgenerate
+
+case (RD_DATA_WIDTH)
+	9: begin
+		assign RDATA1_o = {PORT_B1_RDATA[16], PORT_B1_RDATA[7:0]};
+    assign RDATA2_o = {PORT_B2_RDATA[16], PORT_B2_RDATA[7:0]};
+	end
+	default: begin
+		assign RDATA1_o = PORT_B1_RDATA[RD_DATA_WIDTH-1:0];
+    assign RDATA2_o = PORT_B2_RDATA[RD_DATA_WIDTH-1:0];
+	end
+endcase
+
+// Assign parameters
+case (RD_DATA_WIDTH)
+	1: begin
+		case (WR_DATA_WIDTH)
+			1: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, MODE_1, MODE_1, MODE_1, MODE_1, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_1, MODE_1, MODE_1, MODE_1, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* is_split = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(RESET_ni),
+        
+          .WDATA_A1_i(PORT_A1_WDATA),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR1_ADDR_SHIFTED),
+          .CLK_A1_i(WR1_CLK_i),
+          .REN_A1_i(),
+          .WEN_A1_i(WEN1_i),
+          .BE_A1_i(WR1_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA),
+          .ADDR_B1_i(RD1_ADDR_SHIFTED),
+          .CLK_B1_i(RD1_CLK_i),
+          .REN_B1_i(REN1_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN1_i,REN1_i}),
+        
+          .WDATA_A2_i(PORT_A2_WDATA),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR2_ADDR_SHIFTED),
+          .CLK_A2_i(WR2_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN2_i),
+          .BE_A2_i(WR2_BE[1:0]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA),
+          .ADDR_B2_i(RD2_ADDR_SHIFTED),
+          .CLK_B2_i(RD2_CLK_i),
+          .REN_B2_i(REN2_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN2_i,REN2_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			2: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, MODE_1, MODE_2, MODE_1, MODE_2, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_1, MODE_2, MODE_1, MODE_2, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* is_split = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(RESET_ni),
+        
+          .WDATA_A1_i(PORT_A1_WDATA),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR1_ADDR_SHIFTED),
+          .CLK_A1_i(WR1_CLK_i),
+          .REN_A1_i(),
+          .WEN_A1_i(WEN1_i),
+          .BE_A1_i(WR1_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA),
+          .ADDR_B1_i(RD1_ADDR_SHIFTED),
+          .CLK_B1_i(RD1_CLK_i),
+          .REN_B1_i(REN1_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN1_i,REN1_i}),
+        
+          .WDATA_A2_i(PORT_A2_WDATA),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR2_ADDR_SHIFTED),
+          .CLK_A2_i(WR2_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN2_i),
+          .BE_A2_i(WR2_BE[1:0]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA),
+          .ADDR_B2_i(RD2_ADDR_SHIFTED),
+          .CLK_B2_i(RD2_CLK_i),
+          .REN_B2_i(REN2_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN2_i,REN2_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			4: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, MODE_1, MODE_4, MODE_1, MODE_4, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_1, MODE_4, MODE_1, MODE_4, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* is_split = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(RESET_ni),
+        
+          .WDATA_A1_i(PORT_A1_WDATA),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR1_ADDR_SHIFTED),
+          .CLK_A1_i(WR1_CLK_i),
+          .REN_A1_i(),
+          .WEN_A1_i(WEN1_i),
+          .BE_A1_i(WR1_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA),
+          .ADDR_B1_i(RD1_ADDR_SHIFTED),
+          .CLK_B1_i(RD1_CLK_i),
+          .REN_B1_i(REN1_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN1_i,REN1_i}),
+        
+          .WDATA_A2_i(PORT_A2_WDATA),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR2_ADDR_SHIFTED),
+          .CLK_A2_i(WR2_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN2_i),
+          .BE_A2_i(WR2_BE[1:0]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA),
+          .ADDR_B2_i(RD2_ADDR_SHIFTED),
+          .CLK_B2_i(RD2_CLK_i),
+          .REN_B2_i(REN2_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN2_i,REN2_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			8, 9: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, MODE_1, MODE_9, MODE_1, MODE_9, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_1, MODE_9, MODE_1, MODE_9, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* is_split = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(RESET_ni),
+        
+          .WDATA_A1_i(PORT_A1_WDATA),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR1_ADDR_SHIFTED),
+          .CLK_A1_i(WR1_CLK_i),
+          .REN_A1_i(),
+          .WEN_A1_i(WEN1_i),
+          .BE_A1_i(WR1_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA),
+          .ADDR_B1_i(RD1_ADDR_SHIFTED),
+          .CLK_B1_i(RD1_CLK_i),
+          .REN_B1_i(REN1_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN1_i,REN1_i}),
+        
+          .WDATA_A2_i(PORT_A2_WDATA),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR2_ADDR_SHIFTED),
+          .CLK_A2_i(WR2_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN2_i),
+          .BE_A2_i(WR2_BE[1:0]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA),
+          .ADDR_B2_i(RD2_ADDR_SHIFTED),
+          .CLK_B2_i(RD2_CLK_i),
+          .REN_B2_i(REN2_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN2_i,REN2_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			16, 18: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, MODE_1, MODE_18, MODE_1, MODE_18, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_1, MODE_18, MODE_1, MODE_18, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* is_split = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(RESET_ni),
+        
+          .WDATA_A1_i(PORT_A1_WDATA),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR1_ADDR_SHIFTED),
+          .CLK_A1_i(WR1_CLK_i),
+          .REN_A1_i(),
+          .WEN_A1_i(WEN1_i),
+          .BE_A1_i(WR1_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA),
+          .ADDR_B1_i(RD1_ADDR_SHIFTED),
+          .CLK_B1_i(RD1_CLK_i),
+          .REN_B1_i(REN1_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN1_i,REN1_i}),
+        
+          .WDATA_A2_i(PORT_A2_WDATA),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR2_ADDR_SHIFTED),
+          .CLK_A2_i(WR2_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN2_i),
+          .BE_A2_i(WR2_BE[1:0]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA),
+          .ADDR_B2_i(RD2_ADDR_SHIFTED),
+          .CLK_B2_i(RD2_CLK_i),
+          .REN_B2_i(REN2_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN2_i,REN2_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			default: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, MODE_1, MODE_1, MODE_1, MODE_1, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_1, MODE_1, MODE_1, MODE_1, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* is_split = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(RESET_ni),
+        
+          .WDATA_A1_i(PORT_A1_WDATA),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR1_ADDR_SHIFTED),
+          .CLK_A1_i(WR1_CLK_i),
+          .REN_A1_i(),
+          .WEN_A1_i(WEN1_i),
+          .BE_A1_i(WR1_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA),
+          .ADDR_B1_i(RD1_ADDR_SHIFTED),
+          .CLK_B1_i(RD1_CLK_i),
+          .REN_B1_i(REN1_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN1_i,REN1_i}),
+        
+          .WDATA_A2_i(PORT_A2_WDATA),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR2_ADDR_SHIFTED),
+          .CLK_A2_i(WR2_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN2_i),
+          .BE_A2_i(WR2_BE[1:0]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA),
+          .ADDR_B2_i(RD2_ADDR_SHIFTED),
+          .CLK_B2_i(RD2_CLK_i),
+          .REN_B2_i(REN2_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN2_i,REN2_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+		endcase
+	end
+	2: begin
+		case (WR_DATA_WIDTH)
+			1: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, MODE_2, MODE_1, MODE_2, MODE_1, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_2, MODE_1, MODE_2, MODE_1, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* is_split = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(RESET_ni),
+        
+          .WDATA_A1_i(PORT_A1_WDATA),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR1_ADDR_SHIFTED),
+          .CLK_A1_i(WR1_CLK_i),
+          .REN_A1_i(),
+          .WEN_A1_i(WEN1_i),
+          .BE_A1_i(WR1_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA),
+          .ADDR_B1_i(RD1_ADDR_SHIFTED),
+          .CLK_B1_i(RD1_CLK_i),
+          .REN_B1_i(REN1_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN1_i,REN1_i}),
+        
+          .WDATA_A2_i(PORT_A2_WDATA),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR2_ADDR_SHIFTED),
+          .CLK_A2_i(WR2_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN2_i),
+          .BE_A2_i(WR2_BE[1:0]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA),
+          .ADDR_B2_i(RD2_ADDR_SHIFTED),
+          .CLK_B2_i(RD2_CLK_i),
+          .REN_B2_i(REN2_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN2_i,REN2_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			2: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, MODE_2, MODE_2, MODE_2, MODE_2, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_2, MODE_2, MODE_2, MODE_2, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* is_split = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(RESET_ni),
+        
+          .WDATA_A1_i(PORT_A1_WDATA),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR1_ADDR_SHIFTED),
+          .CLK_A1_i(WR1_CLK_i),
+          .REN_A1_i(),
+          .WEN_A1_i(WEN1_i),
+          .BE_A1_i(WR1_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA),
+          .ADDR_B1_i(RD1_ADDR_SHIFTED),
+          .CLK_B1_i(RD1_CLK_i),
+          .REN_B1_i(REN1_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN1_i,REN1_i}),
+        
+          .WDATA_A2_i(PORT_A2_WDATA),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR2_ADDR_SHIFTED),
+          .CLK_A2_i(WR2_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN2_i),
+          .BE_A2_i(WR2_BE[1:0]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA),
+          .ADDR_B2_i(RD2_ADDR_SHIFTED),
+          .CLK_B2_i(RD2_CLK_i),
+          .REN_B2_i(REN2_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN2_i,REN2_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			4: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, MODE_2, MODE_4, MODE_2, MODE_4, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_2, MODE_4, MODE_2, MODE_4, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* is_split = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(RESET_ni),
+        
+          .WDATA_A1_i(PORT_A1_WDATA),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR1_ADDR_SHIFTED),
+          .CLK_A1_i(WR1_CLK_i),
+          .REN_A1_i(),
+          .WEN_A1_i(WEN1_i),
+          .BE_A1_i(WR1_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA),
+          .ADDR_B1_i(RD1_ADDR_SHIFTED),
+          .CLK_B1_i(RD1_CLK_i),
+          .REN_B1_i(REN1_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN1_i,REN1_i}),
+        
+          .WDATA_A2_i(PORT_A2_WDATA),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR2_ADDR_SHIFTED),
+          .CLK_A2_i(WR2_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN2_i),
+          .BE_A2_i(WR2_BE[1:0]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA),
+          .ADDR_B2_i(RD2_ADDR_SHIFTED),
+          .CLK_B2_i(RD2_CLK_i),
+          .REN_B2_i(REN2_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN2_i,REN2_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			8, 9: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, MODE_2, MODE_9, MODE_2, MODE_9, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_2, MODE_9, MODE_2, MODE_9, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* is_split = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(RESET_ni),
+        
+          .WDATA_A1_i(PORT_A1_WDATA),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR1_ADDR_SHIFTED),
+          .CLK_A1_i(WR1_CLK_i),
+          .REN_A1_i(),
+          .WEN_A1_i(WEN1_i),
+          .BE_A1_i(WR1_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA),
+          .ADDR_B1_i(RD1_ADDR_SHIFTED),
+          .CLK_B1_i(RD1_CLK_i),
+          .REN_B1_i(REN1_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN1_i,REN1_i}),
+        
+          .WDATA_A2_i(PORT_A2_WDATA),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR2_ADDR_SHIFTED),
+          .CLK_A2_i(WR2_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN2_i),
+          .BE_A2_i(WR2_BE[1:0]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA),
+          .ADDR_B2_i(RD2_ADDR_SHIFTED),
+          .CLK_B2_i(RD2_CLK_i),
+          .REN_B2_i(REN2_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN2_i,REN2_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			16, 18: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, MODE_2, MODE_18, MODE_2, MODE_18, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_2, MODE_18, MODE_2, MODE_18, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* is_split = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(RESET_ni),
+        
+          .WDATA_A1_i(PORT_A1_WDATA),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR1_ADDR_SHIFTED),
+          .CLK_A1_i(WR1_CLK_i),
+          .REN_A1_i(),
+          .WEN_A1_i(WEN1_i),
+          .BE_A1_i(WR1_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA),
+          .ADDR_B1_i(RD1_ADDR_SHIFTED),
+          .CLK_B1_i(RD1_CLK_i),
+          .REN_B1_i(REN1_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN1_i,REN1_i}),
+        
+          .WDATA_A2_i(PORT_A2_WDATA),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR2_ADDR_SHIFTED),
+          .CLK_A2_i(WR2_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN2_i),
+          .BE_A2_i(WR2_BE[1:0]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA),
+          .ADDR_B2_i(RD2_ADDR_SHIFTED),
+          .CLK_B2_i(RD2_CLK_i),
+          .REN_B2_i(REN2_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN2_i,REN2_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			default: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, MODE_2, MODE_1, MODE_2, MODE_1, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_2, MODE_1, MODE_2, MODE_1, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* is_split = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(RESET_ni),
+        
+          .WDATA_A1_i(PORT_A1_WDATA),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR1_ADDR_SHIFTED),
+          .CLK_A1_i(WR1_CLK_i),
+          .REN_A1_i(),
+          .WEN_A1_i(WEN1_i),
+          .BE_A1_i(WR1_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA),
+          .ADDR_B1_i(RD1_ADDR_SHIFTED),
+          .CLK_B1_i(RD1_CLK_i),
+          .REN_B1_i(REN1_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN1_i,REN1_i}),
+        
+          .WDATA_A2_i(PORT_A2_WDATA),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR2_ADDR_SHIFTED),
+          .CLK_A2_i(WR2_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN2_i),
+          .BE_A2_i(WR2_BE[1:0]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA),
+          .ADDR_B2_i(RD2_ADDR_SHIFTED),
+          .CLK_B2_i(RD2_CLK_i),
+          .REN_B2_i(REN2_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN2_i,REN2_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+		endcase
+	end
+	4: begin
+		case (WR_DATA_WIDTH)
+			1: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, MODE_4, MODE_1, MODE_4, MODE_1, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_4, MODE_1, MODE_4, MODE_1, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* is_split = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(RESET_ni),
+        
+          .WDATA_A1_i(PORT_A1_WDATA),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR1_ADDR_SHIFTED),
+          .CLK_A1_i(WR1_CLK_i),
+          .REN_A1_i(),
+          .WEN_A1_i(WEN1_i),
+          .BE_A1_i(WR1_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA),
+          .ADDR_B1_i(RD1_ADDR_SHIFTED),
+          .CLK_B1_i(RD1_CLK_i),
+          .REN_B1_i(REN1_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN1_i,REN1_i}),
+        
+          .WDATA_A2_i(PORT_A2_WDATA),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR2_ADDR_SHIFTED),
+          .CLK_A2_i(WR2_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN2_i),
+          .BE_A2_i(WR2_BE[1:0]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA),
+          .ADDR_B2_i(RD2_ADDR_SHIFTED),
+          .CLK_B2_i(RD2_CLK_i),
+          .REN_B2_i(REN2_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN2_i,REN2_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			2: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, MODE_4, MODE_2, MODE_4, MODE_2, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_4, MODE_2, MODE_4, MODE_2, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* is_split = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(RESET_ni),
+        
+          .WDATA_A1_i(PORT_A1_WDATA),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR1_ADDR_SHIFTED),
+          .CLK_A1_i(WR1_CLK_i),
+          .REN_A1_i(),
+          .WEN_A1_i(WEN1_i),
+          .BE_A1_i(WR1_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA),
+          .ADDR_B1_i(RD1_ADDR_SHIFTED),
+          .CLK_B1_i(RD1_CLK_i),
+          .REN_B1_i(REN1_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN1_i,REN1_i}),
+        
+          .WDATA_A2_i(PORT_A2_WDATA),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR2_ADDR_SHIFTED),
+          .CLK_A2_i(WR2_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN2_i),
+          .BE_A2_i(WR2_BE[1:0]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA),
+          .ADDR_B2_i(RD2_ADDR_SHIFTED),
+          .CLK_B2_i(RD2_CLK_i),
+          .REN_B2_i(REN2_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN2_i,REN2_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			4: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, MODE_4, MODE_4, MODE_4, MODE_4, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_4, MODE_4, MODE_4, MODE_4, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* is_split = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(RESET_ni),
+        
+          .WDATA_A1_i(PORT_A1_WDATA),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR1_ADDR_SHIFTED),
+          .CLK_A1_i(WR1_CLK_i),
+          .REN_A1_i(),
+          .WEN_A1_i(WEN1_i),
+          .BE_A1_i(WR1_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA),
+          .ADDR_B1_i(RD1_ADDR_SHIFTED),
+          .CLK_B1_i(RD1_CLK_i),
+          .REN_B1_i(REN1_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN1_i,REN1_i}),
+        
+          .WDATA_A2_i(PORT_A2_WDATA),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR2_ADDR_SHIFTED),
+          .CLK_A2_i(WR2_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN2_i),
+          .BE_A2_i(WR2_BE[1:0]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA),
+          .ADDR_B2_i(RD2_ADDR_SHIFTED),
+          .CLK_B2_i(RD2_CLK_i),
+          .REN_B2_i(REN2_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN2_i,REN2_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			8, 9: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, MODE_4, MODE_9, MODE_4, MODE_9, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_4, MODE_9, MODE_4, MODE_9, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* is_split = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(RESET_ni),
+        
+          .WDATA_A1_i(PORT_A1_WDATA),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR1_ADDR_SHIFTED),
+          .CLK_A1_i(WR1_CLK_i),
+          .REN_A1_i(),
+          .WEN_A1_i(WEN1_i),
+          .BE_A1_i(WR1_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA),
+          .ADDR_B1_i(RD1_ADDR_SHIFTED),
+          .CLK_B1_i(RD1_CLK_i),
+          .REN_B1_i(REN1_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN1_i,REN1_i}),
+        
+          .WDATA_A2_i(PORT_A2_WDATA),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR2_ADDR_SHIFTED),
+          .CLK_A2_i(WR2_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN2_i),
+          .BE_A2_i(WR2_BE[1:0]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA),
+          .ADDR_B2_i(RD2_ADDR_SHIFTED),
+          .CLK_B2_i(RD2_CLK_i),
+          .REN_B2_i(REN2_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN2_i,REN2_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );       
+			end
+			16, 18: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, MODE_4, MODE_18, MODE_4, MODE_18, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_4, MODE_18, MODE_4, MODE_18, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* is_split = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(RESET_ni),
+        
+          .WDATA_A1_i(PORT_A1_WDATA),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR1_ADDR_SHIFTED),
+          .CLK_A1_i(WR1_CLK_i),
+          .REN_A1_i(),
+          .WEN_A1_i(WEN1_i),
+          .BE_A1_i(WR1_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA),
+          .ADDR_B1_i(RD1_ADDR_SHIFTED),
+          .CLK_B1_i(RD1_CLK_i),
+          .REN_B1_i(REN1_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN1_i,REN1_i}),
+        
+          .WDATA_A2_i(PORT_A2_WDATA),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR2_ADDR_SHIFTED),
+          .CLK_A2_i(WR2_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN2_i),
+          .BE_A2_i(WR2_BE[1:0]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA),
+          .ADDR_B2_i(RD2_ADDR_SHIFTED),
+          .CLK_B2_i(RD2_CLK_i),
+          .REN_B2_i(REN2_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN2_i,REN2_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			default: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, MODE_4, MODE_1, MODE_4, MODE_1, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_4, MODE_1, MODE_4, MODE_1, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* is_split = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(RESET_ni),
+        
+          .WDATA_A1_i(PORT_A1_WDATA),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR1_ADDR_SHIFTED),
+          .CLK_A1_i(WR1_CLK_i),
+          .REN_A1_i(),
+          .WEN_A1_i(WEN1_i),
+          .BE_A1_i(WR1_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA),
+          .ADDR_B1_i(RD1_ADDR_SHIFTED),
+          .CLK_B1_i(RD1_CLK_i),
+          .REN_B1_i(REN1_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN1_i,REN1_i}),
+        
+          .WDATA_A2_i(PORT_A2_WDATA),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR2_ADDR_SHIFTED),
+          .CLK_A2_i(WR2_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN2_i),
+          .BE_A2_i(WR2_BE[1:0]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA),
+          .ADDR_B2_i(RD2_ADDR_SHIFTED),
+          .CLK_B2_i(RD2_CLK_i),
+          .REN_B2_i(REN2_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN2_i,REN2_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+		endcase
+	end
+	8, 9: begin
+		case (WR_DATA_WIDTH)
+			1: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, MODE_9, MODE_1, MODE_9, MODE_1, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_9, MODE_1, MODE_9, MODE_1, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* is_split = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(RESET_ni),
+        
+          .WDATA_A1_i(PORT_A1_WDATA),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR1_ADDR_SHIFTED),
+          .CLK_A1_i(WR1_CLK_i),
+          .REN_A1_i(),
+          .WEN_A1_i(WEN1_i),
+          .BE_A1_i(WR1_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA),
+          .ADDR_B1_i(RD1_ADDR_SHIFTED),
+          .CLK_B1_i(RD1_CLK_i),
+          .REN_B1_i(REN1_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN1_i,REN1_i}),
+        
+          .WDATA_A2_i(PORT_A2_WDATA),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR2_ADDR_SHIFTED),
+          .CLK_A2_i(WR2_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN2_i),
+          .BE_A2_i(WR2_BE[1:0]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA),
+          .ADDR_B2_i(RD2_ADDR_SHIFTED),
+          .CLK_B2_i(RD2_CLK_i),
+          .REN_B2_i(REN2_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN2_i,REN2_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			2: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, MODE_9, MODE_2, MODE_9, MODE_2, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_9, MODE_2, MODE_9, MODE_2, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* is_split = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(RESET_ni),
+        
+          .WDATA_A1_i(PORT_A1_WDATA),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR1_ADDR_SHIFTED),
+          .CLK_A1_i(WR1_CLK_i),
+          .REN_A1_i(),
+          .WEN_A1_i(WEN1_i),
+          .BE_A1_i(WR1_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA),
+          .ADDR_B1_i(RD1_ADDR_SHIFTED),
+          .CLK_B1_i(RD1_CLK_i),
+          .REN_B1_i(REN1_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN1_i,REN1_i}),
+        
+          .WDATA_A2_i(PORT_A2_WDATA),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR2_ADDR_SHIFTED),
+          .CLK_A2_i(WR2_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN2_i),
+          .BE_A2_i(WR2_BE[1:0]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA),
+          .ADDR_B2_i(RD2_ADDR_SHIFTED),
+          .CLK_B2_i(RD2_CLK_i),
+          .REN_B2_i(REN2_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN2_i,REN2_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			4: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, MODE_9, MODE_4, MODE_9, MODE_4, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_9, MODE_4, MODE_9, MODE_4, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* is_split = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(RESET_ni),
+        
+          .WDATA_A1_i(PORT_A1_WDATA),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR1_ADDR_SHIFTED),
+          .CLK_A1_i(WR1_CLK_i),
+          .REN_A1_i(),
+          .WEN_A1_i(WEN1_i),
+          .BE_A1_i(WR1_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA),
+          .ADDR_B1_i(RD1_ADDR_SHIFTED),
+          .CLK_B1_i(RD1_CLK_i),
+          .REN_B1_i(REN1_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN1_i,REN1_i}),
+        
+          .WDATA_A2_i(PORT_A2_WDATA),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR2_ADDR_SHIFTED),
+          .CLK_A2_i(WR2_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN2_i),
+          .BE_A2_i(WR2_BE[1:0]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA),
+          .ADDR_B2_i(RD2_ADDR_SHIFTED),
+          .CLK_B2_i(RD2_CLK_i),
+          .REN_B2_i(REN2_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN2_i,REN2_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			8, 9: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, MODE_9, MODE_9, MODE_9, MODE_9, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_9, MODE_9, MODE_9, MODE_9, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* is_split = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(RESET_ni),
+        
+          .WDATA_A1_i(PORT_A1_WDATA),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR1_ADDR_SHIFTED),
+          .CLK_A1_i(WR1_CLK_i),
+          .REN_A1_i(),
+          .WEN_A1_i(WEN1_i),
+          .BE_A1_i(WR1_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA),
+          .ADDR_B1_i(RD1_ADDR_SHIFTED),
+          .CLK_B1_i(RD1_CLK_i),
+          .REN_B1_i(REN1_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN1_i,REN1_i}),
+        
+          .WDATA_A2_i(PORT_A2_WDATA),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR2_ADDR_SHIFTED),
+          .CLK_A2_i(WR2_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN2_i),
+          .BE_A2_i(WR2_BE[1:0]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA),
+          .ADDR_B2_i(RD2_ADDR_SHIFTED),
+          .CLK_B2_i(RD2_CLK_i),
+          .REN_B2_i(REN2_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN2_i,REN2_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			16, 18: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, MODE_9, MODE_18, MODE_9, MODE_18, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_9, MODE_18, MODE_9, MODE_18, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* is_split = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(RESET_ni),
+        
+          .WDATA_A1_i(PORT_A1_WDATA),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR1_ADDR_SHIFTED),
+          .CLK_A1_i(WR1_CLK_i),
+          .REN_A1_i(),
+          .WEN_A1_i(WEN1_i),
+          .BE_A1_i(WR1_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA),
+          .ADDR_B1_i(RD1_ADDR_SHIFTED),
+          .CLK_B1_i(RD1_CLK_i),
+          .REN_B1_i(REN1_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN1_i,REN1_i}),
+        
+          .WDATA_A2_i(PORT_A2_WDATA),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR2_ADDR_SHIFTED),
+          .CLK_A2_i(WR2_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN2_i),
+          .BE_A2_i(WR2_BE[1:0]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA),
+          .ADDR_B2_i(RD2_ADDR_SHIFTED),
+          .CLK_B2_i(RD2_CLK_i),
+          .REN_B2_i(REN2_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN2_i,REN2_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			default: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, MODE_9, MODE_1, MODE_9, MODE_1, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_9, MODE_1, MODE_9, MODE_1, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* is_split = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(RESET_ni),
+        
+          .WDATA_A1_i(PORT_A1_WDATA),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR1_ADDR_SHIFTED),
+          .CLK_A1_i(WR1_CLK_i),
+          .REN_A1_i(),
+          .WEN_A1_i(WEN1_i),
+          .BE_A1_i(WR1_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA),
+          .ADDR_B1_i(RD1_ADDR_SHIFTED),
+          .CLK_B1_i(RD1_CLK_i),
+          .REN_B1_i(REN1_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN1_i,REN1_i}),
+        
+          .WDATA_A2_i(PORT_A2_WDATA),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR2_ADDR_SHIFTED),
+          .CLK_A2_i(WR2_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN2_i),
+          .BE_A2_i(WR2_BE[1:0]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA),
+          .ADDR_B2_i(RD2_ADDR_SHIFTED),
+          .CLK_B2_i(RD2_CLK_i),
+          .REN_B2_i(REN2_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN2_i,REN2_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+		endcase
+	end
+	16, 18: begin
+		case (WR_DATA_WIDTH)
+			1: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, MODE_18, MODE_1, MODE_18, MODE_1, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_18, MODE_1, MODE_18, MODE_1, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* is_split = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(RESET_ni),
+        
+          .WDATA_A1_i(PORT_A1_WDATA),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR1_ADDR_SHIFTED),
+          .CLK_A1_i(WR1_CLK_i),
+          .REN_A1_i(),
+          .WEN_A1_i(WEN1_i),
+          .BE_A1_i(WR1_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA),
+          .ADDR_B1_i(RD1_ADDR_SHIFTED),
+          .CLK_B1_i(RD1_CLK_i),
+          .REN_B1_i(REN1_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN1_i,REN1_i}),
+        
+          .WDATA_A2_i(PORT_A2_WDATA),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR2_ADDR_SHIFTED),
+          .CLK_A2_i(WR2_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN2_i),
+          .BE_A2_i(WR2_BE[1:0]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA),
+          .ADDR_B2_i(RD2_ADDR_SHIFTED),
+          .CLK_B2_i(RD2_CLK_i),
+          .REN_B2_i(REN2_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN2_i,REN2_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			2: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, MODE_18, MODE_2, MODE_18, MODE_2, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_18, MODE_2, MODE_18, MODE_2, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* is_split = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(RESET_ni),
+        
+          .WDATA_A1_i(PORT_A1_WDATA),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR1_ADDR_SHIFTED),
+          .CLK_A1_i(WR1_CLK_i),
+          .REN_A1_i(),
+          .WEN_A1_i(WEN1_i),
+          .BE_A1_i(WR1_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA),
+          .ADDR_B1_i(RD1_ADDR_SHIFTED),
+          .CLK_B1_i(RD1_CLK_i),
+          .REN_B1_i(REN1_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN1_i,REN1_i}),
+        
+          .WDATA_A2_i(PORT_A2_WDATA),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR2_ADDR_SHIFTED),
+          .CLK_A2_i(WR2_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN2_i),
+          .BE_A2_i(WR2_BE[1:0]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA),
+          .ADDR_B2_i(RD2_ADDR_SHIFTED),
+          .CLK_B2_i(RD2_CLK_i),
+          .REN_B2_i(REN2_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN2_i,REN2_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			4: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, MODE_18, MODE_4, MODE_18, MODE_4, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_18, MODE_4, MODE_18, MODE_4, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* is_split = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(RESET_ni),
+        
+          .WDATA_A1_i(PORT_A1_WDATA),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR1_ADDR_SHIFTED),
+          .CLK_A1_i(WR1_CLK_i),
+          .REN_A1_i(),
+          .WEN_A1_i(WEN1_i),
+          .BE_A1_i(WR1_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA),
+          .ADDR_B1_i(RD1_ADDR_SHIFTED),
+          .CLK_B1_i(RD1_CLK_i),
+          .REN_B1_i(REN1_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN1_i,REN1_i}),
+        
+          .WDATA_A2_i(PORT_A2_WDATA),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR2_ADDR_SHIFTED),
+          .CLK_A2_i(WR2_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN2_i),
+          .BE_A2_i(WR2_BE[1:0]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA),
+          .ADDR_B2_i(RD2_ADDR_SHIFTED),
+          .CLK_B2_i(RD2_CLK_i),
+          .REN_B2_i(REN2_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN2_i,REN2_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			8, 9: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, MODE_18, MODE_9, MODE_18, MODE_9, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_18, MODE_9, MODE_18, MODE_9, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* is_split = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(RESET_ni),
+        
+          .WDATA_A1_i(PORT_A1_WDATA),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR1_ADDR_SHIFTED),
+          .CLK_A1_i(WR1_CLK_i),
+          .REN_A1_i(),
+          .WEN_A1_i(WEN1_i),
+          .BE_A1_i(WR1_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA),
+          .ADDR_B1_i(RD1_ADDR_SHIFTED),
+          .CLK_B1_i(RD1_CLK_i),
+          .REN_B1_i(REN1_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN1_i,REN1_i}),
+        
+          .WDATA_A2_i(PORT_A2_WDATA),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR2_ADDR_SHIFTED),
+          .CLK_A2_i(WR2_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN2_i),
+          .BE_A2_i(WR2_BE[1:0]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA),
+          .ADDR_B2_i(RD2_ADDR_SHIFTED),
+          .CLK_B2_i(RD2_CLK_i),
+          .REN_B2_i(REN2_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN2_i,REN2_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			16, 18: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, MODE_18, MODE_18, MODE_18, MODE_18, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_18, MODE_18, MODE_18, MODE_18, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* is_split = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(RESET_ni),
+        
+          .WDATA_A1_i(PORT_A1_WDATA),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR1_ADDR_SHIFTED),
+          .CLK_A1_i(WR1_CLK_i),
+          .REN_A1_i(),
+          .WEN_A1_i(WEN1_i),
+          .BE_A1_i(WR1_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA),
+          .ADDR_B1_i(RD1_ADDR_SHIFTED),
+          .CLK_B1_i(RD1_CLK_i),
+          .REN_B1_i(REN1_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN1_i,REN1_i}),
+        
+          .WDATA_A2_i(PORT_A2_WDATA),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR2_ADDR_SHIFTED),
+          .CLK_A2_i(WR2_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN2_i),
+          .BE_A2_i(WR2_BE[1:0]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA),
+          .ADDR_B2_i(RD2_ADDR_SHIFTED),
+          .CLK_B2_i(RD2_CLK_i),
+          .REN_B2_i(REN2_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN2_i,REN2_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			default: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, MODE_18, MODE_1, MODE_18, MODE_1, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_18, MODE_1, MODE_18, MODE_1, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* is_split = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(RESET_ni),
+        
+          .WDATA_A1_i(PORT_A1_WDATA),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR1_ADDR_SHIFTED),
+          .CLK_A1_i(WR1_CLK_i),
+          .REN_A1_i(),
+          .WEN_A1_i(WEN1_i),
+          .BE_A1_i(WR1_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA),
+          .ADDR_B1_i(RD1_ADDR_SHIFTED),
+          .CLK_B1_i(RD1_CLK_i),
+          .REN_B1_i(REN1_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN1_i,REN1_i}),
+        
+          .WDATA_A2_i(PORT_A2_WDATA),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR2_ADDR_SHIFTED),
+          .CLK_A2_i(WR2_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN2_i),
+          .BE_A2_i(WR2_BE[1:0]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA),
+          .ADDR_B2_i(RD2_ADDR_SHIFTED),
+          .CLK_B2_i(RD2_CLK_i),
+          .REN_B2_i(REN2_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN2_i,REN2_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+		endcase
+	end
+	default: begin
+		case (WR_DATA_WIDTH)
+			1: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, MODE_1, MODE_1, MODE_1, MODE_1, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_1, MODE_1, MODE_1, MODE_1, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* is_split = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(RESET_ni),
+        
+          .WDATA_A1_i(PORT_A1_WDATA),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR1_ADDR_SHIFTED),
+          .CLK_A1_i(WR1_CLK_i),
+          .REN_A1_i(),
+          .WEN_A1_i(WEN1_i),
+          .BE_A1_i(WR1_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA),
+          .ADDR_B1_i(RD1_ADDR_SHIFTED),
+          .CLK_B1_i(RD1_CLK_i),
+          .REN_B1_i(REN1_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN1_i,REN1_i}),
+        
+          .WDATA_A2_i(PORT_A2_WDATA),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR2_ADDR_SHIFTED),
+          .CLK_A2_i(WR2_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN2_i),
+          .BE_A2_i(WR2_BE[1:0]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA),
+          .ADDR_B2_i(RD2_ADDR_SHIFTED),
+          .CLK_B2_i(RD2_CLK_i),
+          .REN_B2_i(REN2_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN2_i,REN2_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			2: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, MODE_1, MODE_2, MODE_1, MODE_2, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_1, MODE_2, MODE_1, MODE_2, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* is_split = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(RESET_ni),
+        
+          .WDATA_A1_i(PORT_A1_WDATA),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR1_ADDR_SHIFTED),
+          .CLK_A1_i(WR1_CLK_i),
+          .REN_A1_i(),
+          .WEN_A1_i(WEN1_i),
+          .BE_A1_i(WR1_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA),
+          .ADDR_B1_i(RD1_ADDR_SHIFTED),
+          .CLK_B1_i(RD1_CLK_i),
+          .REN_B1_i(REN1_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN1_i,REN1_i}),
+        
+          .WDATA_A2_i(PORT_A2_WDATA),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR2_ADDR_SHIFTED),
+          .CLK_A2_i(WR2_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN2_i),
+          .BE_A2_i(WR2_BE[1:0]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA),
+          .ADDR_B2_i(RD2_ADDR_SHIFTED),
+          .CLK_B2_i(RD2_CLK_i),
+          .REN_B2_i(REN2_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN2_i,REN2_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			4: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, MODE_1, MODE_4, MODE_1, MODE_4, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_1, MODE_4, MODE_1, MODE_4, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* is_split = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(RESET_ni),
+        
+          .WDATA_A1_i(PORT_A1_WDATA),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR1_ADDR_SHIFTED),
+          .CLK_A1_i(WR1_CLK_i),
+          .REN_A1_i(),
+          .WEN_A1_i(WEN1_i),
+          .BE_A1_i(WR1_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA),
+          .ADDR_B1_i(RD1_ADDR_SHIFTED),
+          .CLK_B1_i(RD1_CLK_i),
+          .REN_B1_i(REN1_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN1_i,REN1_i}),
+        
+          .WDATA_A2_i(PORT_A2_WDATA),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR2_ADDR_SHIFTED),
+          .CLK_A2_i(WR2_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN2_i),
+          .BE_A2_i(WR2_BE[1:0]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA),
+          .ADDR_B2_i(RD2_ADDR_SHIFTED),
+          .CLK_B2_i(RD2_CLK_i),
+          .REN_B2_i(REN2_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN2_i,REN2_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			8, 9: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, MODE_1, MODE_9, MODE_1, MODE_9, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_1, MODE_9, MODE_1, MODE_9, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* is_split = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(RESET_ni),
+        
+          .WDATA_A1_i(PORT_A1_WDATA),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR1_ADDR_SHIFTED),
+          .CLK_A1_i(WR1_CLK_i),
+          .REN_A1_i(),
+          .WEN_A1_i(WEN1_i),
+          .BE_A1_i(WR1_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA),
+          .ADDR_B1_i(RD1_ADDR_SHIFTED),
+          .CLK_B1_i(RD1_CLK_i),
+          .REN_B1_i(REN1_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN1_i,REN1_i}),
+        
+          .WDATA_A2_i(PORT_A2_WDATA),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR2_ADDR_SHIFTED),
+          .CLK_A2_i(WR2_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN2_i),
+          .BE_A2_i(WR2_BE[1:0]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA),
+          .ADDR_B2_i(RD2_ADDR_SHIFTED),
+          .CLK_B2_i(RD2_CLK_i),
+          .REN_B2_i(REN2_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN2_i,REN2_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			16, 18: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, MODE_1, MODE_18, MODE_1, MODE_18, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_1, MODE_18, MODE_1, MODE_18, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* is_split = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(RESET_ni),
+        
+          .WDATA_A1_i(PORT_A1_WDATA),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR1_ADDR_SHIFTED),
+          .CLK_A1_i(WR1_CLK_i),
+          .REN_A1_i(),
+          .WEN_A1_i(WEN1_i),
+          .BE_A1_i(WR1_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA),
+          .ADDR_B1_i(RD1_ADDR_SHIFTED),
+          .CLK_B1_i(RD1_CLK_i),
+          .REN_B1_i(REN1_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN1_i,REN1_i}),
+        
+          .WDATA_A2_i(PORT_A2_WDATA),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR2_ADDR_SHIFTED),
+          .CLK_A2_i(WR2_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN2_i),
+          .BE_A2_i(WR2_BE[1:0]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA),
+          .ADDR_B2_i(RD2_ADDR_SHIFTED),
+          .CLK_B2_i(RD2_CLK_i),
+          .REN_B2_i(REN2_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN2_i,REN2_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			default: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b1,
+					11'd10, 11'd10, 4'd0, MODE_1, MODE_1, MODE_1, MODE_1, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_1, MODE_1, MODE_1, MODE_1, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* is_split = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(RESET_ni),
+        
+          .WDATA_A1_i(PORT_A1_WDATA),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR1_ADDR_SHIFTED),
+          .CLK_A1_i(WR1_CLK_i),
+          .REN_A1_i(),
+          .WEN_A1_i(WEN1_i),
+          .BE_A1_i(WR1_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA),
+          .ADDR_B1_i(RD1_ADDR_SHIFTED),
+          .CLK_B1_i(RD1_CLK_i),
+          .REN_B1_i(REN1_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN1_i,REN1_i}),
+        
+          .WDATA_A2_i(PORT_A2_WDATA),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR2_ADDR_SHIFTED),
+          .CLK_A2_i(WR2_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN2_i),
+          .BE_A2_i(WR2_BE[1:0]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA),
+          .ADDR_B2_i(RD2_ADDR_SHIFTED),
+          .CLK_B2_i(RD2_CLK_i),
+          .REN_B2_i(REN2_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN2_i,REN2_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+		endcase
+	end
+endcase
+
+endmodule
+
+module RAM_18K_BLK (
+    WEN_i,
+    REN_i,
+    WR_CLK_i,
+    RD_CLK_i,
+    WR_BE_i,
+    WR_ADDR_i,
+    RD_ADDR_i,
+    WDATA_i,
+    RDATA_o
+);
+
+parameter WR_ADDR_WIDTH = 10;
+parameter RD_ADDR_WIDTH = 10;
+parameter WR_DATA_WIDTH = 18;
+parameter RD_DATA_WIDTH = 18;
+parameter BE_WIDTH = 2;
+
+input wire WEN_i;
+input wire REN_i;
+input wire WR_CLK_i;
+input wire RD_CLK_i;
+input wire [BE_WIDTH-1:0] WR_BE_i;
+input wire [WR_ADDR_WIDTH-1 :0] WR_ADDR_i;
+input wire [RD_ADDR_WIDTH-1 :0] RD_ADDR_i;
+input wire [WR_DATA_WIDTH-1 :0] WDATA_i;
+output wire [RD_DATA_WIDTH-1 :0] RDATA_o;
+
+  BRAM2x18_SP  #(
+      .WR_ADDR_WIDTH(WR_ADDR_WIDTH), 
+      .RD_ADDR_WIDTH(RD_ADDR_WIDTH),
+      .WR_DATA_WIDTH(WR_DATA_WIDTH), 
+      .RD_DATA_WIDTH(RD_DATA_WIDTH),
+      .BE1_WIDTH(BE_WIDTH),
+      .BE2_WIDTH()      
+       ) U1
+      (
+      .RESET_ni(1'b1),
+      
+      .WEN1_i(WEN_i),
+      .REN1_i(REN_i),
+      .WR1_CLK_i(WR_CLK_i),
+      .RD1_CLK_i(RD_CLK_i),
+      .WR1_BE_i(WR_BE_i),
+      .WR1_ADDR_i(WR_ADDR_i),
+      .RD1_ADDR_i(RD_ADDR_i),
+      .WDATA1_i(WDATA_i),
+      .RDATA1_o(RDATA_o),
+      
+      .WEN2_i(),
+      .REN2_i(),
+      .WR2_CLK_i(),
+      .RD2_CLK_i(),
+      .WR2_BE_i(),
+      .WR2_ADDR_i(),
+      .RD2_ADDR_i(),
+      .WDATA2_i(),
+      .RDATA2_o()
+      );
+    
+endmodule
+
+module RAM_36K_BLK (
+    WEN_i,
+    REN_i,
+    WR_CLK_i,
+    RD_CLK_i,
+    WR_BE_i,
+    WR_ADDR_i,
+    RD_ADDR_i,
+    WDATA_i,
+    RDATA_o
+);
+
+parameter WR_ADDR_WIDTH = 10;
+parameter RD_ADDR_WIDTH = 10;
+parameter WR_DATA_WIDTH = 36;
+parameter RD_DATA_WIDTH = 36;
+parameter BE_WIDTH = 4;
+
+localparam MODE_36 = 3'b011; // 36- or 32-bit
+localparam MODE_18 = 3'b010; // 18- or 16-bit
+localparam MODE_9 = 3'b001; // 9- or 8-bit
+localparam MODE_4 = 3'b100; // 4-bit
+localparam MODE_2 = 3'b110; // 2-bit
+localparam MODE_1 = 3'b101; // 1-bit
+
+input wire WEN_i;
+input wire REN_i;
+input wire WR_CLK_i;
+input wire RD_CLK_i;
+input wire [BE_WIDTH-1:0] WR_BE_i;
+input wire [WR_ADDR_WIDTH-1 :0] WR_ADDR_i;
+input wire [RD_ADDR_WIDTH-1 :0] RD_ADDR_i;
+input wire [WR_DATA_WIDTH-1 :0] WDATA_i;
+output wire [RD_DATA_WIDTH-1 :0] RDATA_o;
+
+wire [14:RD_ADDR_WIDTH] RD_ADDR_CMPL;
+wire [14:WR_ADDR_WIDTH] WR_ADDR_CMPL;
+wire [35:0] RD_DATA_CMPL;
+wire [35:WR_DATA_WIDTH] WR_DATA_CMPL;
+
+wire [14:0] RD_ADDR_TOTAL;
+wire [14:0] WR_ADDR_TOTAL;
+
+wire [14:0] RD_ADDR_SHIFTED;
+wire [14:0] WR_ADDR_SHIFTED;
+
+wire [3:0] WR_BE;
+
+wire FLUSH1;
+wire FLUSH2;
+
+generate
+  if (WR_ADDR_WIDTH == 15) begin
+    assign WR_ADDR_TOTAL = WR_ADDR_i;
+  end else begin
+    assign WR_ADDR_TOTAL[14:WR_ADDR_WIDTH] = 0;
+    assign WR_ADDR_TOTAL[WR_ADDR_WIDTH-1:0] = WR_ADDR_i;
+  end
+endgenerate
+
+generate
+  if (RD_ADDR_WIDTH == 15) begin
+    assign RD_ADDR_TOTAL = RD_ADDR_i;
+  end else begin
+    assign RD_ADDR_TOTAL[14:RD_ADDR_WIDTH] = 0;
+    assign RD_ADDR_TOTAL[RD_ADDR_WIDTH-1:0] = RD_ADDR_i;
+  end
+endgenerate
+
+// Apply shift
+case (RD_DATA_WIDTH)
+	1: begin
+		assign RD_ADDR_SHIFTED = RD_ADDR_TOTAL;
+	end
+	2: begin
+		assign RD_ADDR_SHIFTED = RD_ADDR_TOTAL << 1;
+	end
+	4: begin
+		assign RD_ADDR_SHIFTED = RD_ADDR_TOTAL << 2;
+	end
+	8, 9: begin
+		assign RD_ADDR_SHIFTED = RD_ADDR_TOTAL << 3;
+	end
+	16, 18: begin
+		assign RD_ADDR_SHIFTED = RD_ADDR_TOTAL << 4;
+	end
+	32, 36: begin
+		assign RD_ADDR_SHIFTED = RD_ADDR_TOTAL << 5;
+	end
+	default: begin
+		assign RD_ADDR_SHIFTED = RD_ADDR_TOTAL;
+	end
+endcase
+
+case (WR_DATA_WIDTH)
+	1: begin
+		assign WR_ADDR_SHIFTED = WR_ADDR_TOTAL;
+	end
+	2: begin
+		assign WR_ADDR_SHIFTED = WR_ADDR_TOTAL << 1;
+	end
+	4: begin
+		assign WR_ADDR_SHIFTED = WR_ADDR_TOTAL << 2;
+	end
+	8, 9: begin
+		assign WR_ADDR_SHIFTED = WR_ADDR_TOTAL << 3;
+	end
+	16, 18: begin
+		assign WR_ADDR_SHIFTED = WR_ADDR_TOTAL << 4;
+	end
+	32, 36: begin
+		assign WR_ADDR_SHIFTED = WR_ADDR_TOTAL << 5;
+	end
+	default: begin
+		assign WR_ADDR_SHIFTED = WR_ADDR_TOTAL;
+	end
+endcase
+
+case (BE_WIDTH)
+	4: begin
+		assign WR_BE = WR_BE_i[BE_WIDTH-1 :0];
+	end
+	default: begin
+		assign WR_BE[3:BE_WIDTH] = 0;
+    assign WR_BE[BE_WIDTH-1 :0] = WR_BE_i[BE_WIDTH-1 :0];
+	end
+endcase
+
+assign FLUSH1 = 1'b0;
+assign FLUSH2 = 1'b0;
+
+// TODO configure per width
+wire [17:0] PORT_B1_RDATA;
+wire [17:0] PORT_B2_RDATA;
+wire [35:0] PORT_A_WDATA;
+
+generate
+  if (WR_DATA_WIDTH == 36) begin
+    assign PORT_A_WDATA[WR_DATA_WIDTH-1:0] = WDATA_i[WR_DATA_WIDTH-1:0];
+  end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin
+    assign PORT_A_WDATA[WR_DATA_WIDTH+1:18]  = WDATA_i[WR_DATA_WIDTH-1:16];
+    assign PORT_A_WDATA[17:0] = {2'b00,WDATA_i[15:0]};
+  end else if (WR_DATA_WIDTH == 9) begin
+    assign PORT_A_WDATA = {19'h0, WDATA_i[8], 8'h0, WDATA_i[7:0]};
+  end else begin
+    assign PORT_A_WDATA[35:WR_DATA_WIDTH] = 0;
+    assign PORT_A_WDATA[WR_DATA_WIDTH-1:0] = WDATA_i[WR_DATA_WIDTH-1:0];
+  end
+endgenerate
+
+generate
+  if (RD_DATA_WIDTH == 36) begin
+    assign RD_DATA_CMPL = {PORT_B2_RDATA, PORT_B1_RDATA};
+  end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin
+    assign RD_DATA_CMPL  = {2'b00,PORT_B2_RDATA[17:0],PORT_B1_RDATA[15:0]};
+  end else if (RD_DATA_WIDTH == 9) begin
+    assign RD_DATA_CMPL = { 27'h0, PORT_B1_RDATA[16], PORT_B1_RDATA[7:0]};
+  end else begin
+    assign RD_DATA_CMPL = {18'h0, PORT_B1_RDATA};
+  end
+endgenerate
+
+assign RDATA_o = RD_DATA_CMPL[RD_DATA_WIDTH-1:0];
+
+// Assign parameters
+case (RD_DATA_WIDTH)
+	1: begin
+		case (WR_DATA_WIDTH)
+			1: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_1, MODE_1, MODE_1, MODE_1, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_1, MODE_1, MODE_1, MODE_1, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(1'b1),
+        
+          .WDATA_A1_i(PORT_A_WDATA[17:0]),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR_ADDR_SHIFTED),
+          .CLK_A1_i(WR_CLK_i),
+          .REN_A1_i(1'b0),
+          .WEN_A1_i(WEN_i),
+          .BE_A1_i(WR_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA[17:0]),
+          .ADDR_B1_i(RD_ADDR_SHIFTED),
+          .CLK_B1_i(RD_CLK_i),
+          .REN_B1_i(REN_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN_i,REN_i}),
+        
+          .WDATA_A2_i(PORT_A_WDATA[35:18]),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR_ADDR_SHIFTED),
+          .CLK_A2_i(WR_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN_i),
+          .BE_A2_i(WR_BE[3:2]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA[17:0]),
+          .ADDR_B2_i(RD_ADDR_SHIFTED),
+          .CLK_B2_i(RD_CLK_i),
+          .REN_B2_i(REN_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN_i,REN_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			2: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_1, MODE_2, MODE_1, MODE_2, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_1, MODE_2, MODE_1, MODE_2, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(1'b1),
+        
+          .WDATA_A1_i(PORT_A_WDATA[17:0]),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR_ADDR_SHIFTED),
+          .CLK_A1_i(WR_CLK_i),
+          .REN_A1_i(1'b0),
+          .WEN_A1_i(WEN_i),
+          .BE_A1_i(WR_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA[17:0]),
+          .ADDR_B1_i(RD_ADDR_SHIFTED),
+          .CLK_B1_i(RD_CLK_i),
+          .REN_B1_i(REN_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN_i,REN_i}),
+        
+          .WDATA_A2_i(PORT_A_WDATA[35:18]),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR_ADDR_SHIFTED),
+          .CLK_A2_i(WR_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN_i),
+          .BE_A2_i(WR_BE[3:2]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA[17:0]),
+          .ADDR_B2_i(RD_ADDR_SHIFTED),
+          .CLK_B2_i(RD_CLK_i),
+          .REN_B2_i(REN_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN_i,REN_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );       
+			end
+			4: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_1, MODE_4, MODE_1, MODE_4, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_1, MODE_4, MODE_1, MODE_4, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(1'b1),
+        
+          .WDATA_A1_i(PORT_A_WDATA[17:0]),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR_ADDR_SHIFTED),
+          .CLK_A1_i(WR_CLK_i),
+          .REN_A1_i(1'b0),
+          .WEN_A1_i(WEN_i),
+          .BE_A1_i(WR_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA[17:0]),
+          .ADDR_B1_i(RD_ADDR_SHIFTED),
+          .CLK_B1_i(RD_CLK_i),
+          .REN_B1_i(REN_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN_i,REN_i}),
+        
+          .WDATA_A2_i(PORT_A_WDATA[35:18]),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR_ADDR_SHIFTED),
+          .CLK_A2_i(WR_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN_i),
+          .BE_A2_i(WR_BE[3:2]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA[17:0]),
+          .ADDR_B2_i(RD_ADDR_SHIFTED),
+          .CLK_B2_i(RD_CLK_i),
+          .REN_B2_i(REN_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN_i,REN_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			8, 9: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_1, MODE_9, MODE_1, MODE_9, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_1, MODE_9, MODE_1, MODE_9, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(1'b1),
+        
+          .WDATA_A1_i(PORT_A_WDATA[17:0]),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR_ADDR_SHIFTED),
+          .CLK_A1_i(WR_CLK_i),
+          .REN_A1_i(1'b0),
+          .WEN_A1_i(WEN_i),
+          .BE_A1_i(WR_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA[17:0]),
+          .ADDR_B1_i(RD_ADDR_SHIFTED),
+          .CLK_B1_i(RD_CLK_i),
+          .REN_B1_i(REN_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN_i,REN_i}),
+        
+          .WDATA_A2_i(PORT_A_WDATA[35:18]),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR_ADDR_SHIFTED),
+          .CLK_A2_i(WR_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN_i),
+          .BE_A2_i(WR_BE[3:2]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA[17:0]),
+          .ADDR_B2_i(RD_ADDR_SHIFTED),
+          .CLK_B2_i(RD_CLK_i),
+          .REN_B2_i(REN_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN_i,REN_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			16, 18: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_1, MODE_18, MODE_1, MODE_18, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_1, MODE_18, MODE_1, MODE_18, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(1'b1),
+        
+          .WDATA_A1_i(PORT_A_WDATA[17:0]),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR_ADDR_SHIFTED),
+          .CLK_A1_i(WR_CLK_i),
+          .REN_A1_i(1'b0),
+          .WEN_A1_i(WEN_i),
+          .BE_A1_i(WR_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA[17:0]),
+          .ADDR_B1_i(RD_ADDR_SHIFTED),
+          .CLK_B1_i(RD_CLK_i),
+          .REN_B1_i(REN_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN_i,REN_i}),
+        
+          .WDATA_A2_i(PORT_A_WDATA[35:18]),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR_ADDR_SHIFTED),
+          .CLK_A2_i(WR_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN_i),
+          .BE_A2_i(WR_BE[3:2]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA[17:0]),
+          .ADDR_B2_i(RD_ADDR_SHIFTED),
+          .CLK_B2_i(RD_CLK_i),
+          .REN_B2_i(REN_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN_i,REN_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			32, 36: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_1, MODE_36, MODE_1, MODE_36, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_1, MODE_36, MODE_1, MODE_36, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(1'b1),
+        
+          .WDATA_A1_i(PORT_A_WDATA[17:0]),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR_ADDR_SHIFTED),
+          .CLK_A1_i(WR_CLK_i),
+          .REN_A1_i(1'b0),
+          .WEN_A1_i(WEN_i),
+          .BE_A1_i(WR_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA[17:0]),
+          .ADDR_B1_i(RD_ADDR_SHIFTED),
+          .CLK_B1_i(RD_CLK_i),
+          .REN_B1_i(REN_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN_i,REN_i}),
+        
+          .WDATA_A2_i(PORT_A_WDATA[35:18]),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR_ADDR_SHIFTED),
+          .CLK_A2_i(WR_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN_i),
+          .BE_A2_i(WR_BE[3:2]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA[17:0]),
+          .ADDR_B2_i(RD_ADDR_SHIFTED),
+          .CLK_B2_i(RD_CLK_i),
+          .REN_B2_i(REN_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN_i,REN_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			default: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_1, MODE_1, MODE_1, MODE_1, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_1, MODE_1, MODE_1, MODE_1, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(1'b1),
+        
+          .WDATA_A1_i(PORT_A_WDATA[17:0]),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR_ADDR_SHIFTED),
+          .CLK_A1_i(WR_CLK_i),
+          .REN_A1_i(1'b0),
+          .WEN_A1_i(WEN_i),
+          .BE_A1_i(WR_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA[17:0]),
+          .ADDR_B1_i(RD_ADDR_SHIFTED),
+          .CLK_B1_i(RD_CLK_i),
+          .REN_B1_i(REN_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN_i,REN_i}),
+        
+          .WDATA_A2_i(PORT_A_WDATA[35:18]),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR_ADDR_SHIFTED),
+          .CLK_A2_i(WR_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN_i),
+          .BE_A2_i(WR_BE[3:2]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA[17:0]),
+          .ADDR_B2_i(RD_ADDR_SHIFTED),
+          .CLK_B2_i(RD_CLK_i),
+          .REN_B2_i(REN_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN_i,REN_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );       
+			end
+		endcase
+	end
+	2: begin
+		case (WR_DATA_WIDTH)
+			1: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_2, MODE_1, MODE_2, MODE_1, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_2, MODE_1, MODE_2, MODE_1, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(1'b1),
+        
+          .WDATA_A1_i(PORT_A_WDATA[17:0]),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR_ADDR_SHIFTED),
+          .CLK_A1_i(WR_CLK_i),
+          .REN_A1_i(1'b0),
+          .WEN_A1_i(WEN_i),
+          .BE_A1_i(WR_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA[17:0]),
+          .ADDR_B1_i(RD_ADDR_SHIFTED),
+          .CLK_B1_i(RD_CLK_i),
+          .REN_B1_i(REN_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN_i,REN_i}),
+        
+          .WDATA_A2_i(PORT_A_WDATA[35:18]),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR_ADDR_SHIFTED),
+          .CLK_A2_i(WR_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN_i),
+          .BE_A2_i(WR_BE[3:2]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA[17:0]),
+          .ADDR_B2_i(RD_ADDR_SHIFTED),
+          .CLK_B2_i(RD_CLK_i),
+          .REN_B2_i(REN_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN_i,REN_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			2: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_2, MODE_2, MODE_2, MODE_2, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_2, MODE_2, MODE_2, MODE_2, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(1'b1),
+        
+          .WDATA_A1_i(PORT_A_WDATA[17:0]),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR_ADDR_SHIFTED),
+          .CLK_A1_i(WR_CLK_i),
+          .REN_A1_i(1'b0),
+          .WEN_A1_i(WEN_i),
+          .BE_A1_i(WR_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA[17:0]),
+          .ADDR_B1_i(RD_ADDR_SHIFTED),
+          .CLK_B1_i(RD_CLK_i),
+          .REN_B1_i(REN_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN_i,REN_i}),
+        
+          .WDATA_A2_i(PORT_A_WDATA[35:18]),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR_ADDR_SHIFTED),
+          .CLK_A2_i(WR_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN_i),
+          .BE_A2_i(WR_BE[3:2]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA[17:0]),
+          .ADDR_B2_i(RD_ADDR_SHIFTED),
+          .CLK_B2_i(RD_CLK_i),
+          .REN_B2_i(REN_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN_i,REN_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			4: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_2, MODE_4, MODE_2, MODE_4, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_2, MODE_4, MODE_2, MODE_4, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(1'b1),
+        
+          .WDATA_A1_i(PORT_A_WDATA[17:0]),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR_ADDR_SHIFTED),
+          .CLK_A1_i(WR_CLK_i),
+          .REN_A1_i(1'b0),
+          .WEN_A1_i(WEN_i),
+          .BE_A1_i(WR_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA[17:0]),
+          .ADDR_B1_i(RD_ADDR_SHIFTED),
+          .CLK_B1_i(RD_CLK_i),
+          .REN_B1_i(REN_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN_i,REN_i}),
+        
+          .WDATA_A2_i(PORT_A_WDATA[35:18]),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR_ADDR_SHIFTED),
+          .CLK_A2_i(WR_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN_i),
+          .BE_A2_i(WR_BE[3:2]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA[17:0]),
+          .ADDR_B2_i(RD_ADDR_SHIFTED),
+          .CLK_B2_i(RD_CLK_i),
+          .REN_B2_i(REN_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN_i,REN_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			8, 9: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_2, MODE_9, MODE_2, MODE_9, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_2, MODE_9, MODE_2, MODE_9, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(1'b1),
+        
+          .WDATA_A1_i(PORT_A_WDATA[17:0]),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR_ADDR_SHIFTED),
+          .CLK_A1_i(WR_CLK_i),
+          .REN_A1_i(1'b0),
+          .WEN_A1_i(WEN_i),
+          .BE_A1_i(WR_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA[17:0]),
+          .ADDR_B1_i(RD_ADDR_SHIFTED),
+          .CLK_B1_i(RD_CLK_i),
+          .REN_B1_i(REN_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN_i,REN_i}),
+        
+          .WDATA_A2_i(PORT_A_WDATA[35:18]),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR_ADDR_SHIFTED),
+          .CLK_A2_i(WR_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN_i),
+          .BE_A2_i(WR_BE[3:2]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA[17:0]),
+          .ADDR_B2_i(RD_ADDR_SHIFTED),
+          .CLK_B2_i(RD_CLK_i),
+          .REN_B2_i(REN_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN_i,REN_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			16, 18: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_2, MODE_18, MODE_2, MODE_18, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_2, MODE_18, MODE_2, MODE_18, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(1'b1),
+        
+          .WDATA_A1_i(PORT_A_WDATA[17:0]),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR_ADDR_SHIFTED),
+          .CLK_A1_i(WR_CLK_i),
+          .REN_A1_i(1'b0),
+          .WEN_A1_i(WEN_i),
+          .BE_A1_i(WR_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA[17:0]),
+          .ADDR_B1_i(RD_ADDR_SHIFTED),
+          .CLK_B1_i(RD_CLK_i),
+          .REN_B1_i(REN_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN_i,REN_i}),
+        
+          .WDATA_A2_i(PORT_A_WDATA[35:18]),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR_ADDR_SHIFTED),
+          .CLK_A2_i(WR_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN_i),
+          .BE_A2_i(WR_BE[3:2]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA[17:0]),
+          .ADDR_B2_i(RD_ADDR_SHIFTED),
+          .CLK_B2_i(RD_CLK_i),
+          .REN_B2_i(REN_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN_i,REN_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			32, 36: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_2, MODE_36, MODE_2, MODE_36, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_2, MODE_36, MODE_2, MODE_36, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(1'b1),
+        
+          .WDATA_A1_i(PORT_A_WDATA[17:0]),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR_ADDR_SHIFTED),
+          .CLK_A1_i(WR_CLK_i),
+          .REN_A1_i(1'b0),
+          .WEN_A1_i(WEN_i),
+          .BE_A1_i(WR_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA[17:0]),
+          .ADDR_B1_i(RD_ADDR_SHIFTED),
+          .CLK_B1_i(RD_CLK_i),
+          .REN_B1_i(REN_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN_i,REN_i}),
+        
+          .WDATA_A2_i(PORT_A_WDATA[35:18]),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR_ADDR_SHIFTED),
+          .CLK_A2_i(WR_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN_i),
+          .BE_A2_i(WR_BE[3:2]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA[17:0]),
+          .ADDR_B2_i(RD_ADDR_SHIFTED),
+          .CLK_B2_i(RD_CLK_i),
+          .REN_B2_i(REN_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN_i,REN_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			default: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_2, MODE_1, MODE_2, MODE_1, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_2, MODE_1, MODE_2, MODE_1, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(1'b1),
+        
+          .WDATA_A1_i(PORT_A_WDATA[17:0]),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR_ADDR_SHIFTED),
+          .CLK_A1_i(WR_CLK_i),
+          .REN_A1_i(1'b0),
+          .WEN_A1_i(WEN_i),
+          .BE_A1_i(WR_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA[17:0]),
+          .ADDR_B1_i(RD_ADDR_SHIFTED),
+          .CLK_B1_i(RD_CLK_i),
+          .REN_B1_i(REN_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN_i,REN_i}),
+        
+          .WDATA_A2_i(PORT_A_WDATA[35:18]),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR_ADDR_SHIFTED),
+          .CLK_A2_i(WR_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN_i),
+          .BE_A2_i(WR_BE[3:2]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA[17:0]),
+          .ADDR_B2_i(RD_ADDR_SHIFTED),
+          .CLK_B2_i(RD_CLK_i),
+          .REN_B2_i(REN_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN_i,REN_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+		endcase
+	end
+	4: begin
+		case (WR_DATA_WIDTH)
+			1: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_4, MODE_1, MODE_4, MODE_1, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_4, MODE_1, MODE_4, MODE_1, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(1'b1),
+        
+          .WDATA_A1_i(PORT_A_WDATA[17:0]),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR_ADDR_SHIFTED),
+          .CLK_A1_i(WR_CLK_i),
+          .REN_A1_i(1'b0),
+          .WEN_A1_i(WEN_i),
+          .BE_A1_i(WR_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA[17:0]),
+          .ADDR_B1_i(RD_ADDR_SHIFTED),
+          .CLK_B1_i(RD_CLK_i),
+          .REN_B1_i(REN_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN_i,REN_i}),
+        
+          .WDATA_A2_i(PORT_A_WDATA[35:18]),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR_ADDR_SHIFTED),
+          .CLK_A2_i(WR_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN_i),
+          .BE_A2_i(WR_BE[3:2]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA[17:0]),
+          .ADDR_B2_i(RD_ADDR_SHIFTED),
+          .CLK_B2_i(RD_CLK_i),
+          .REN_B2_i(REN_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN_i,REN_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );
+			end
+			2: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_4, MODE_2, MODE_4, MODE_2, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_4, MODE_2, MODE_4, MODE_2, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(1'b1),
+        
+          .WDATA_A1_i(PORT_A_WDATA[17:0]),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR_ADDR_SHIFTED),
+          .CLK_A1_i(WR_CLK_i),
+          .REN_A1_i(1'b0),
+          .WEN_A1_i(WEN_i),
+          .BE_A1_i(WR_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA[17:0]),
+          .ADDR_B1_i(RD_ADDR_SHIFTED),
+          .CLK_B1_i(RD_CLK_i),
+          .REN_B1_i(REN_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN_i,REN_i}),
+        
+          .WDATA_A2_i(PORT_A_WDATA[35:18]),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR_ADDR_SHIFTED),
+          .CLK_A2_i(WR_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN_i),
+          .BE_A2_i(WR_BE[3:2]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA[17:0]),
+          .ADDR_B2_i(RD_ADDR_SHIFTED),
+          .CLK_B2_i(RD_CLK_i),
+          .REN_B2_i(REN_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN_i,REN_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			4: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_4, MODE_4, MODE_4, MODE_4, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_4, MODE_4, MODE_4, MODE_4, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(1'b1),
+        
+          .WDATA_A1_i(PORT_A_WDATA[17:0]),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR_ADDR_SHIFTED),
+          .CLK_A1_i(WR_CLK_i),
+          .REN_A1_i(1'b0),
+          .WEN_A1_i(WEN_i),
+          .BE_A1_i(WR_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA[17:0]),
+          .ADDR_B1_i(RD_ADDR_SHIFTED),
+          .CLK_B1_i(RD_CLK_i),
+          .REN_B1_i(REN_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN_i,REN_i}),
+        
+          .WDATA_A2_i(PORT_A_WDATA[35:18]),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR_ADDR_SHIFTED),
+          .CLK_A2_i(WR_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN_i),
+          .BE_A2_i(WR_BE[3:2]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA[17:0]),
+          .ADDR_B2_i(RD_ADDR_SHIFTED),
+          .CLK_B2_i(RD_CLK_i),
+          .REN_B2_i(REN_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN_i,REN_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			8, 9: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_4, MODE_9, MODE_4, MODE_9, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_4, MODE_9, MODE_4, MODE_9, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(1'b1),
+        
+          .WDATA_A1_i(PORT_A_WDATA[17:0]),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR_ADDR_SHIFTED),
+          .CLK_A1_i(WR_CLK_i),
+          .REN_A1_i(1'b0),
+          .WEN_A1_i(WEN_i),
+          .BE_A1_i(WR_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA[17:0]),
+          .ADDR_B1_i(RD_ADDR_SHIFTED),
+          .CLK_B1_i(RD_CLK_i),
+          .REN_B1_i(REN_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN_i,REN_i}),
+        
+          .WDATA_A2_i(PORT_A_WDATA[35:18]),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR_ADDR_SHIFTED),
+          .CLK_A2_i(WR_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN_i),
+          .BE_A2_i(WR_BE[3:2]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA[17:0]),
+          .ADDR_B2_i(RD_ADDR_SHIFTED),
+          .CLK_B2_i(RD_CLK_i),
+          .REN_B2_i(REN_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN_i,REN_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			16, 18: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_4, MODE_18, MODE_4, MODE_18, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_4, MODE_18, MODE_4, MODE_18, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(1'b1),
+        
+          .WDATA_A1_i(PORT_A_WDATA[17:0]),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR_ADDR_SHIFTED),
+          .CLK_A1_i(WR_CLK_i),
+          .REN_A1_i(1'b0),
+          .WEN_A1_i(WEN_i),
+          .BE_A1_i(WR_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA[17:0]),
+          .ADDR_B1_i(RD_ADDR_SHIFTED),
+          .CLK_B1_i(RD_CLK_i),
+          .REN_B1_i(REN_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN_i,REN_i}),
+        
+          .WDATA_A2_i(PORT_A_WDATA[35:18]),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR_ADDR_SHIFTED),
+          .CLK_A2_i(WR_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN_i),
+          .BE_A2_i(WR_BE[3:2]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA[17:0]),
+          .ADDR_B2_i(RD_ADDR_SHIFTED),
+          .CLK_B2_i(RD_CLK_i),
+          .REN_B2_i(REN_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN_i,REN_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			32, 36: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_4, MODE_36, MODE_4, MODE_36, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_4, MODE_36, MODE_4, MODE_36, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(1'b1),
+        
+          .WDATA_A1_i(PORT_A_WDATA[17:0]),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR_ADDR_SHIFTED),
+          .CLK_A1_i(WR_CLK_i),
+          .REN_A1_i(1'b0),
+          .WEN_A1_i(WEN_i),
+          .BE_A1_i(WR_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA[17:0]),
+          .ADDR_B1_i(RD_ADDR_SHIFTED),
+          .CLK_B1_i(RD_CLK_i),
+          .REN_B1_i(REN_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN_i,REN_i}),
+        
+          .WDATA_A2_i(PORT_A_WDATA[35:18]),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR_ADDR_SHIFTED),
+          .CLK_A2_i(WR_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN_i),
+          .BE_A2_i(WR_BE[3:2]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA[17:0]),
+          .ADDR_B2_i(RD_ADDR_SHIFTED),
+          .CLK_B2_i(RD_CLK_i),
+          .REN_B2_i(REN_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN_i,REN_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			default: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_4, MODE_1, MODE_4, MODE_1, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_4, MODE_1, MODE_4, MODE_1, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(1'b1),
+        
+          .WDATA_A1_i(PORT_A_WDATA[17:0]),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR_ADDR_SHIFTED),
+          .CLK_A1_i(WR_CLK_i),
+          .REN_A1_i(1'b0),
+          .WEN_A1_i(WEN_i),
+          .BE_A1_i(WR_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA[17:0]),
+          .ADDR_B1_i(RD_ADDR_SHIFTED),
+          .CLK_B1_i(RD_CLK_i),
+          .REN_B1_i(REN_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN_i,REN_i}),
+        
+          .WDATA_A2_i(PORT_A_WDATA[35:18]),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR_ADDR_SHIFTED),
+          .CLK_A2_i(WR_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN_i),
+          .BE_A2_i(WR_BE[3:2]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA[17:0]),
+          .ADDR_B2_i(RD_ADDR_SHIFTED),
+          .CLK_B2_i(RD_CLK_i),
+          .REN_B2_i(REN_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN_i,REN_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+		endcase
+	end
+	8, 9: begin
+		case (WR_DATA_WIDTH)
+			1: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_9, MODE_1, MODE_9, MODE_1, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_9, MODE_1, MODE_9, MODE_1, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(1'b1),
+        
+          .WDATA_A1_i(PORT_A_WDATA[17:0]),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR_ADDR_SHIFTED),
+          .CLK_A1_i(WR_CLK_i),
+          .REN_A1_i(1'b0),
+          .WEN_A1_i(WEN_i),
+          .BE_A1_i(WR_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA[17:0]),
+          .ADDR_B1_i(RD_ADDR_SHIFTED),
+          .CLK_B1_i(RD_CLK_i),
+          .REN_B1_i(REN_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN_i,REN_i}),
+        
+          .WDATA_A2_i(PORT_A_WDATA[35:18]),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR_ADDR_SHIFTED),
+          .CLK_A2_i(WR_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN_i),
+          .BE_A2_i(WR_BE[3:2]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA[17:0]),
+          .ADDR_B2_i(RD_ADDR_SHIFTED),
+          .CLK_B2_i(RD_CLK_i),
+          .REN_B2_i(REN_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN_i,REN_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			2: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_9, MODE_2, MODE_9, MODE_2, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_9, MODE_2, MODE_9, MODE_2, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(1'b1),
+        
+          .WDATA_A1_i(PORT_A_WDATA[17:0]),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR_ADDR_SHIFTED),
+          .CLK_A1_i(WR_CLK_i),
+          .REN_A1_i(1'b0),
+          .WEN_A1_i(WEN_i),
+          .BE_A1_i(WR_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA[17:0]),
+          .ADDR_B1_i(RD_ADDR_SHIFTED),
+          .CLK_B1_i(RD_CLK_i),
+          .REN_B1_i(REN_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN_i,REN_i}),
+        
+          .WDATA_A2_i(PORT_A_WDATA[35:18]),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR_ADDR_SHIFTED),
+          .CLK_A2_i(WR_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN_i),
+          .BE_A2_i(WR_BE[3:2]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA[17:0]),
+          .ADDR_B2_i(RD_ADDR_SHIFTED),
+          .CLK_B2_i(RD_CLK_i),
+          .REN_B2_i(REN_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN_i,REN_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			4: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_9, MODE_4, MODE_9, MODE_4, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_9, MODE_4, MODE_9, MODE_4, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(1'b1),
+        
+          .WDATA_A1_i(PORT_A_WDATA[17:0]),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR_ADDR_SHIFTED),
+          .CLK_A1_i(WR_CLK_i),
+          .REN_A1_i(1'b0),
+          .WEN_A1_i(WEN_i),
+          .BE_A1_i(WR_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA[17:0]),
+          .ADDR_B1_i(RD_ADDR_SHIFTED),
+          .CLK_B1_i(RD_CLK_i),
+          .REN_B1_i(REN_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN_i,REN_i}),
+        
+          .WDATA_A2_i(PORT_A_WDATA[35:18]),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR_ADDR_SHIFTED),
+          .CLK_A2_i(WR_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN_i),
+          .BE_A2_i(WR_BE[3:2]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA[17:0]),
+          .ADDR_B2_i(RD_ADDR_SHIFTED),
+          .CLK_B2_i(RD_CLK_i),
+          .REN_B2_i(REN_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN_i,REN_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			8, 9: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_9, MODE_9, MODE_9, MODE_9, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_9, MODE_9, MODE_9, MODE_9, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(1'b1),
+        
+          .WDATA_A1_i(PORT_A_WDATA[17:0]),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR_ADDR_SHIFTED),
+          .CLK_A1_i(WR_CLK_i),
+          .REN_A1_i(1'b0),
+          .WEN_A1_i(WEN_i),
+          .BE_A1_i(WR_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA[17:0]),
+          .ADDR_B1_i(RD_ADDR_SHIFTED),
+          .CLK_B1_i(RD_CLK_i),
+          .REN_B1_i(REN_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN_i,REN_i}),
+        
+          .WDATA_A2_i(PORT_A_WDATA[35:18]),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR_ADDR_SHIFTED),
+          .CLK_A2_i(WR_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN_i),
+          .BE_A2_i(WR_BE[3:2]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA[17:0]),
+          .ADDR_B2_i(RD_ADDR_SHIFTED),
+          .CLK_B2_i(RD_CLK_i),
+          .REN_B2_i(REN_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN_i,REN_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			16, 18: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_9, MODE_18, MODE_9, MODE_18, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_9, MODE_18, MODE_9, MODE_18, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(1'b1),
+        
+          .WDATA_A1_i(PORT_A_WDATA[17:0]),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR_ADDR_SHIFTED),
+          .CLK_A1_i(WR_CLK_i),
+          .REN_A1_i(1'b0),
+          .WEN_A1_i(WEN_i),
+          .BE_A1_i(WR_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA[17:0]),
+          .ADDR_B1_i(RD_ADDR_SHIFTED),
+          .CLK_B1_i(RD_CLK_i),
+          .REN_B1_i(REN_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN_i,REN_i}),
+        
+          .WDATA_A2_i(PORT_A_WDATA[35:18]),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR_ADDR_SHIFTED),
+          .CLK_A2_i(WR_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN_i),
+          .BE_A2_i(WR_BE[3:2]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA[17:0]),
+          .ADDR_B2_i(RD_ADDR_SHIFTED),
+          .CLK_B2_i(RD_CLK_i),
+          .REN_B2_i(REN_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN_i,REN_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			32, 36: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_9, MODE_36, MODE_9, MODE_36, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_9, MODE_36, MODE_9, MODE_36, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(1'b1),
+        
+          .WDATA_A1_i(PORT_A_WDATA[17:0]),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR_ADDR_SHIFTED),
+          .CLK_A1_i(WR_CLK_i),
+          .REN_A1_i(1'b0),
+          .WEN_A1_i(WEN_i),
+          .BE_A1_i(WR_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA[17:0]),
+          .ADDR_B1_i(RD_ADDR_SHIFTED),
+          .CLK_B1_i(RD_CLK_i),
+          .REN_B1_i(REN_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN_i,REN_i}),
+        
+          .WDATA_A2_i(PORT_A_WDATA[35:18]),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR_ADDR_SHIFTED),
+          .CLK_A2_i(WR_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN_i),
+          .BE_A2_i(WR_BE[3:2]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA[17:0]),
+          .ADDR_B2_i(RD_ADDR_SHIFTED),
+          .CLK_B2_i(RD_CLK_i),
+          .REN_B2_i(REN_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN_i,REN_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			default: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_9, MODE_1, MODE_9, MODE_1, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_9, MODE_1, MODE_9, MODE_1, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(1'b1),
+        
+          .WDATA_A1_i(PORT_A_WDATA[17:0]),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR_ADDR_SHIFTED),
+          .CLK_A1_i(WR_CLK_i),
+          .REN_A1_i(1'b0),
+          .WEN_A1_i(WEN_i),
+          .BE_A1_i(WR_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA[17:0]),
+          .ADDR_B1_i(RD_ADDR_SHIFTED),
+          .CLK_B1_i(RD_CLK_i),
+          .REN_B1_i(REN_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN_i,REN_i}),
+        
+          .WDATA_A2_i(PORT_A_WDATA[35:18]),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR_ADDR_SHIFTED),
+          .CLK_A2_i(WR_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN_i),
+          .BE_A2_i(WR_BE[3:2]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA[17:0]),
+          .ADDR_B2_i(RD_ADDR_SHIFTED),
+          .CLK_B2_i(RD_CLK_i),
+          .REN_B2_i(REN_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN_i,REN_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+		endcase
+	end
+	16, 18: begin
+		case (WR_DATA_WIDTH)
+			1: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_18, MODE_1, MODE_18, MODE_1, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_18, MODE_1, MODE_18, MODE_1, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(1'b1),
+        
+          .WDATA_A1_i(PORT_A_WDATA[17:0]),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR_ADDR_SHIFTED),
+          .CLK_A1_i(WR_CLK_i),
+          .REN_A1_i(1'b0),
+          .WEN_A1_i(WEN_i),
+          .BE_A1_i(WR_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA[17:0]),
+          .ADDR_B1_i(RD_ADDR_SHIFTED),
+          .CLK_B1_i(RD_CLK_i),
+          .REN_B1_i(REN_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN_i,REN_i}),
+        
+          .WDATA_A2_i(PORT_A_WDATA[35:18]),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR_ADDR_SHIFTED),
+          .CLK_A2_i(WR_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN_i),
+          .BE_A2_i(WR_BE[3:2]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA[17:0]),
+          .ADDR_B2_i(RD_ADDR_SHIFTED),
+          .CLK_B2_i(RD_CLK_i),
+          .REN_B2_i(REN_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN_i,REN_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			2: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_18, MODE_2, MODE_18, MODE_2, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_18, MODE_2, MODE_18, MODE_2, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(1'b1),
+        
+          .WDATA_A1_i(PORT_A_WDATA[17:0]),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR_ADDR_SHIFTED),
+          .CLK_A1_i(WR_CLK_i),
+          .REN_A1_i(1'b0),
+          .WEN_A1_i(WEN_i),
+          .BE_A1_i(WR_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA[17:0]),
+          .ADDR_B1_i(RD_ADDR_SHIFTED),
+          .CLK_B1_i(RD_CLK_i),
+          .REN_B1_i(REN_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN_i,REN_i}),
+        
+          .WDATA_A2_i(PORT_A_WDATA[35:18]),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR_ADDR_SHIFTED),
+          .CLK_A2_i(WR_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN_i),
+          .BE_A2_i(WR_BE[3:2]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA[17:0]),
+          .ADDR_B2_i(RD_ADDR_SHIFTED),
+          .CLK_B2_i(RD_CLK_i),
+          .REN_B2_i(REN_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN_i,REN_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			4: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_18, MODE_4, MODE_18, MODE_4, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_18, MODE_4, MODE_18, MODE_4, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(1'b1),
+        
+          .WDATA_A1_i(PORT_A_WDATA[17:0]),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR_ADDR_SHIFTED),
+          .CLK_A1_i(WR_CLK_i),
+          .REN_A1_i(1'b0),
+          .WEN_A1_i(WEN_i),
+          .BE_A1_i(WR_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA[17:0]),
+          .ADDR_B1_i(RD_ADDR_SHIFTED),
+          .CLK_B1_i(RD_CLK_i),
+          .REN_B1_i(REN_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN_i,REN_i}),
+        
+          .WDATA_A2_i(PORT_A_WDATA[35:18]),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR_ADDR_SHIFTED),
+          .CLK_A2_i(WR_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN_i),
+          .BE_A2_i(WR_BE[3:2]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA[17:0]),
+          .ADDR_B2_i(RD_ADDR_SHIFTED),
+          .CLK_B2_i(RD_CLK_i),
+          .REN_B2_i(REN_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN_i,REN_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			8, 9: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_18, MODE_9, MODE_18, MODE_9, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_18, MODE_9, MODE_18, MODE_9, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(1'b1),
+        
+          .WDATA_A1_i(PORT_A_WDATA[17:0]),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR_ADDR_SHIFTED),
+          .CLK_A1_i(WR_CLK_i),
+          .REN_A1_i(1'b0),
+          .WEN_A1_i(WEN_i),
+          .BE_A1_i(WR_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA[17:0]),
+          .ADDR_B1_i(RD_ADDR_SHIFTED),
+          .CLK_B1_i(RD_CLK_i),
+          .REN_B1_i(REN_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN_i,REN_i}),
+        
+          .WDATA_A2_i(PORT_A_WDATA[35:18]),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR_ADDR_SHIFTED),
+          .CLK_A2_i(WR_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN_i),
+          .BE_A2_i(WR_BE[3:2]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA[17:0]),
+          .ADDR_B2_i(RD_ADDR_SHIFTED),
+          .CLK_B2_i(RD_CLK_i),
+          .REN_B2_i(REN_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN_i,REN_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			16, 18: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_18, MODE_18, MODE_18, MODE_18, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_18, MODE_18, MODE_18, MODE_18, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(1'b1),
+        
+          .WDATA_A1_i(PORT_A_WDATA[17:0]),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR_ADDR_SHIFTED),
+          .CLK_A1_i(WR_CLK_i),
+          .REN_A1_i(1'b0),
+          .WEN_A1_i(WEN_i),
+          .BE_A1_i(WR_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA[17:0]),
+          .ADDR_B1_i(RD_ADDR_SHIFTED),
+          .CLK_B1_i(RD_CLK_i),
+          .REN_B1_i(REN_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN_i,REN_i}),
+        
+          .WDATA_A2_i(PORT_A_WDATA[35:18]),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR_ADDR_SHIFTED),
+          .CLK_A2_i(WR_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN_i),
+          .BE_A2_i(WR_BE[3:2]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA[17:0]),
+          .ADDR_B2_i(RD_ADDR_SHIFTED),
+          .CLK_B2_i(RD_CLK_i),
+          .REN_B2_i(REN_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN_i,REN_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			32, 36: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_18, MODE_36, MODE_18, MODE_36, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_18, MODE_36, MODE_18, MODE_36, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(1'b1),
+        
+          .WDATA_A1_i(PORT_A_WDATA[17:0]),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR_ADDR_SHIFTED),
+          .CLK_A1_i(WR_CLK_i),
+          .REN_A1_i(1'b0),
+          .WEN_A1_i(WEN_i),
+          .BE_A1_i(WR_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA[17:0]),
+          .ADDR_B1_i(RD_ADDR_SHIFTED),
+          .CLK_B1_i(RD_CLK_i),
+          .REN_B1_i(REN_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN_i,REN_i}),
+        
+          .WDATA_A2_i(PORT_A_WDATA[35:18]),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR_ADDR_SHIFTED),
+          .CLK_A2_i(WR_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN_i),
+          .BE_A2_i(WR_BE[3:2]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA[17:0]),
+          .ADDR_B2_i(RD_ADDR_SHIFTED),
+          .CLK_B2_i(RD_CLK_i),
+          .REN_B2_i(REN_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN_i,REN_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			default: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_18, MODE_1, MODE_18, MODE_1, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_18, MODE_1, MODE_18, MODE_1, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(1'b1),
+        
+          .WDATA_A1_i(PORT_A_WDATA[17:0]),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR_ADDR_SHIFTED),
+          .CLK_A1_i(WR_CLK_i),
+          .REN_A1_i(1'b0),
+          .WEN_A1_i(WEN_i),
+          .BE_A1_i(WR_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA[17:0]),
+          .ADDR_B1_i(RD_ADDR_SHIFTED),
+          .CLK_B1_i(RD_CLK_i),
+          .REN_B1_i(REN_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN_i,REN_i}),
+        
+          .WDATA_A2_i(PORT_A_WDATA[35:18]),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR_ADDR_SHIFTED),
+          .CLK_A2_i(WR_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN_i),
+          .BE_A2_i(WR_BE[3:2]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA[17:0]),
+          .ADDR_B2_i(RD_ADDR_SHIFTED),
+          .CLK_B2_i(RD_CLK_i),
+          .REN_B2_i(REN_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN_i,REN_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+		endcase
+	end
+	32, 36: begin
+		case (WR_DATA_WIDTH)
+			1: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_36, MODE_1, MODE_36, MODE_1, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_36, MODE_1, MODE_36, MODE_1, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(1'b1),
+        
+          .WDATA_A1_i(PORT_A_WDATA[17:0]),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR_ADDR_SHIFTED),
+          .CLK_A1_i(WR_CLK_i),
+          .REN_A1_i(1'b0),
+          .WEN_A1_i(WEN_i),
+          .BE_A1_i(WR_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA[17:0]),
+          .ADDR_B1_i(RD_ADDR_SHIFTED),
+          .CLK_B1_i(RD_CLK_i),
+          .REN_B1_i(REN_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN_i,REN_i}),
+        
+          .WDATA_A2_i(PORT_A_WDATA[35:18]),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR_ADDR_SHIFTED),
+          .CLK_A2_i(WR_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN_i),
+          .BE_A2_i(WR_BE[3:2]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA[17:0]),
+          .ADDR_B2_i(RD_ADDR_SHIFTED),
+          .CLK_B2_i(RD_CLK_i),
+          .REN_B2_i(REN_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN_i,REN_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			2: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_36, MODE_2, MODE_36, MODE_2, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_36, MODE_2, MODE_36, MODE_2, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(1'b1),
+        
+          .WDATA_A1_i(PORT_A_WDATA[17:0]),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR_ADDR_SHIFTED),
+          .CLK_A1_i(WR_CLK_i),
+          .REN_A1_i(1'b0),
+          .WEN_A1_i(WEN_i),
+          .BE_A1_i(WR_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA[17:0]),
+          .ADDR_B1_i(RD_ADDR_SHIFTED),
+          .CLK_B1_i(RD_CLK_i),
+          .REN_B1_i(REN_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN_i,REN_i}),
+        
+          .WDATA_A2_i(PORT_A_WDATA[35:18]),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR_ADDR_SHIFTED),
+          .CLK_A2_i(WR_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN_i),
+          .BE_A2_i(WR_BE[3:2]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA[17:0]),
+          .ADDR_B2_i(RD_ADDR_SHIFTED),
+          .CLK_B2_i(RD_CLK_i),
+          .REN_B2_i(REN_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN_i,REN_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			4: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_36, MODE_4, MODE_36, MODE_4, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_36, MODE_4, MODE_36, MODE_4, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(1'b1),
+        
+          .WDATA_A1_i(PORT_A_WDATA[17:0]),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR_ADDR_SHIFTED),
+          .CLK_A1_i(WR_CLK_i),
+          .REN_A1_i(1'b0),
+          .WEN_A1_i(WEN_i),
+          .BE_A1_i(WR_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA[17:0]),
+          .ADDR_B1_i(RD_ADDR_SHIFTED),
+          .CLK_B1_i(RD_CLK_i),
+          .REN_B1_i(REN_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN_i,REN_i}),
+        
+          .WDATA_A2_i(PORT_A_WDATA[35:18]),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR_ADDR_SHIFTED),
+          .CLK_A2_i(WR_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN_i),
+          .BE_A2_i(WR_BE[3:2]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA[17:0]),
+          .ADDR_B2_i(RD_ADDR_SHIFTED),
+          .CLK_B2_i(RD_CLK_i),
+          .REN_B2_i(REN_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN_i,REN_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			8, 9: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_36, MODE_9, MODE_36, MODE_9, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_36, MODE_9, MODE_36, MODE_9, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(1'b1),
+        
+          .WDATA_A1_i(PORT_A_WDATA[17:0]),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR_ADDR_SHIFTED),
+          .CLK_A1_i(WR_CLK_i),
+          .REN_A1_i(1'b0),
+          .WEN_A1_i(WEN_i),
+          .BE_A1_i(WR_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA[17:0]),
+          .ADDR_B1_i(RD_ADDR_SHIFTED),
+          .CLK_B1_i(RD_CLK_i),
+          .REN_B1_i(REN_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN_i,REN_i}),
+        
+          .WDATA_A2_i(PORT_A_WDATA[35:18]),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR_ADDR_SHIFTED),
+          .CLK_A2_i(WR_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN_i),
+          .BE_A2_i(WR_BE[3:2]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA[17:0]),
+          .ADDR_B2_i(RD_ADDR_SHIFTED),
+          .CLK_B2_i(RD_CLK_i),
+          .REN_B2_i(REN_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN_i,REN_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			16, 18: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_36, MODE_18, MODE_36, MODE_18, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_36, MODE_18, MODE_36, MODE_18, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(1'b1),
+        
+          .WDATA_A1_i(PORT_A_WDATA[17:0]),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR_ADDR_SHIFTED),
+          .CLK_A1_i(WR_CLK_i),
+          .REN_A1_i(1'b0),
+          .WEN_A1_i(WEN_i),
+          .BE_A1_i(WR_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA[17:0]),
+          .ADDR_B1_i(RD_ADDR_SHIFTED),
+          .CLK_B1_i(RD_CLK_i),
+          .REN_B1_i(REN_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN_i,REN_i}),
+        
+          .WDATA_A2_i(PORT_A_WDATA[35:18]),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR_ADDR_SHIFTED),
+          .CLK_A2_i(WR_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN_i),
+          .BE_A2_i(WR_BE[3:2]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA[17:0]),
+          .ADDR_B2_i(RD_ADDR_SHIFTED),
+          .CLK_B2_i(RD_CLK_i),
+          .REN_B2_i(REN_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN_i,REN_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			32, 36: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_36, MODE_36, MODE_36, MODE_36, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_36, MODE_36, MODE_36, MODE_36, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(1'b1),
+        
+          .WDATA_A1_i(PORT_A_WDATA[17:0]),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR_ADDR_SHIFTED),
+          .CLK_A1_i(WR_CLK_i),
+          .REN_A1_i(1'b0),
+          .WEN_A1_i(WEN_i),
+          .BE_A1_i(WR_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA[17:0]),
+          .ADDR_B1_i(RD_ADDR_SHIFTED),
+          .CLK_B1_i(RD_CLK_i),
+          .REN_B1_i(REN_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN_i,REN_i}),
+        
+          .WDATA_A2_i(PORT_A_WDATA[35:18]),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR_ADDR_SHIFTED),
+          .CLK_A2_i(WR_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN_i),
+          .BE_A2_i(WR_BE[3:2]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA[17:0]),
+          .ADDR_B2_i(RD_ADDR_SHIFTED),
+          .CLK_B2_i(RD_CLK_i),
+          .REN_B2_i(REN_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN_i,REN_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			default: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_36, MODE_1, MODE_36, MODE_1, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_36, MODE_1, MODE_36, MODE_1, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(1'b1),
+        
+          .WDATA_A1_i(PORT_A_WDATA[17:0]),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR_ADDR_SHIFTED),
+          .CLK_A1_i(WR_CLK_i),
+          .REN_A1_i(1'b0),
+          .WEN_A1_i(WEN_i),
+          .BE_A1_i(WR_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA[17:0]),
+          .ADDR_B1_i(RD_ADDR_SHIFTED),
+          .CLK_B1_i(RD_CLK_i),
+          .REN_B1_i(REN_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN_i,REN_i}),
+        
+          .WDATA_A2_i(PORT_A_WDATA[35:18]),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR_ADDR_SHIFTED),
+          .CLK_A2_i(WR_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN_i),
+          .BE_A2_i(WR_BE[3:2]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA[17:0]),
+          .ADDR_B2_i(RD_ADDR_SHIFTED),
+          .CLK_B2_i(RD_CLK_i),
+          .REN_B2_i(REN_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN_i,REN_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+		endcase
+	end
+	default: begin
+		case (WR_DATA_WIDTH)
+			1: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_1, MODE_1, MODE_1, MODE_1, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_1, MODE_1, MODE_1, MODE_1, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(1'b1),
+        
+          .WDATA_A1_i(PORT_A_WDATA[17:0]),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR_ADDR_SHIFTED),
+          .CLK_A1_i(WR_CLK_i),
+          .REN_A1_i(1'b0),
+          .WEN_A1_i(WEN_i),
+          .BE_A1_i(WR_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA[17:0]),
+          .ADDR_B1_i(RD_ADDR_SHIFTED),
+          .CLK_B1_i(RD_CLK_i),
+          .REN_B1_i(REN_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN_i,REN_i}),
+        
+          .WDATA_A2_i(PORT_A_WDATA[35:18]),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR_ADDR_SHIFTED),
+          .CLK_A2_i(WR_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN_i),
+          .BE_A2_i(WR_BE[3:2]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA[17:0]),
+          .ADDR_B2_i(RD_ADDR_SHIFTED),
+          .CLK_B2_i(RD_CLK_i),
+          .REN_B2_i(REN_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN_i,REN_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			2: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_1, MODE_2, MODE_1, MODE_2, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_1, MODE_2, MODE_1, MODE_2, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(1'b1),
+        
+          .WDATA_A1_i(PORT_A_WDATA[17:0]),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR_ADDR_SHIFTED),
+          .CLK_A1_i(WR_CLK_i),
+          .REN_A1_i(1'b0),
+          .WEN_A1_i(WEN_i),
+          .BE_A1_i(WR_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA[17:0]),
+          .ADDR_B1_i(RD_ADDR_SHIFTED),
+          .CLK_B1_i(RD_CLK_i),
+          .REN_B1_i(REN_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN_i,REN_i}),
+        
+          .WDATA_A2_i(PORT_A_WDATA[35:18]),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR_ADDR_SHIFTED),
+          .CLK_A2_i(WR_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN_i),
+          .BE_A2_i(WR_BE[3:2]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA[17:0]),
+          .ADDR_B2_i(RD_ADDR_SHIFTED),
+          .CLK_B2_i(RD_CLK_i),
+          .REN_B2_i(REN_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN_i,REN_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			4: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_1, MODE_4, MODE_1, MODE_4, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_1, MODE_4, MODE_1, MODE_4, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(1'b1),
+        
+          .WDATA_A1_i(PORT_A_WDATA[17:0]),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR_ADDR_SHIFTED),
+          .CLK_A1_i(WR_CLK_i),
+          .REN_A1_i(1'b0),
+          .WEN_A1_i(WEN_i),
+          .BE_A1_i(WR_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA[17:0]),
+          .ADDR_B1_i(RD_ADDR_SHIFTED),
+          .CLK_B1_i(RD_CLK_i),
+          .REN_B1_i(REN_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN_i,REN_i}),
+        
+          .WDATA_A2_i(PORT_A_WDATA[35:18]),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR_ADDR_SHIFTED),
+          .CLK_A2_i(WR_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN_i),
+          .BE_A2_i(WR_BE[3:2]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA[17:0]),
+          .ADDR_B2_i(RD_ADDR_SHIFTED),
+          .CLK_B2_i(RD_CLK_i),
+          .REN_B2_i(REN_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN_i,REN_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			8, 9: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_1, MODE_9, MODE_1, MODE_9, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_1, MODE_9, MODE_1, MODE_9, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(1'b1),
+        
+          .WDATA_A1_i(PORT_A_WDATA[17:0]),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR_ADDR_SHIFTED),
+          .CLK_A1_i(WR_CLK_i),
+          .REN_A1_i(1'b0),
+          .WEN_A1_i(WEN_i),
+          .BE_A1_i(WR_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA[17:0]),
+          .ADDR_B1_i(RD_ADDR_SHIFTED),
+          .CLK_B1_i(RD_CLK_i),
+          .REN_B1_i(REN_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN_i,REN_i}),
+        
+          .WDATA_A2_i(PORT_A_WDATA[35:18]),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR_ADDR_SHIFTED),
+          .CLK_A2_i(WR_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN_i),
+          .BE_A2_i(WR_BE[3:2]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA[17:0]),
+          .ADDR_B2_i(RD_ADDR_SHIFTED),
+          .CLK_B2_i(RD_CLK_i),
+          .REN_B2_i(REN_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN_i,REN_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );       
+			end
+			16, 18: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_1, MODE_18, MODE_1, MODE_18, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_1, MODE_18, MODE_1, MODE_18, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(1'b1),
+        
+          .WDATA_A1_i(PORT_A_WDATA[17:0]),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR_ADDR_SHIFTED),
+          .CLK_A1_i(WR_CLK_i),
+          .REN_A1_i(1'b0),
+          .WEN_A1_i(WEN_i),
+          .BE_A1_i(WR_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA[17:0]),
+          .ADDR_B1_i(RD_ADDR_SHIFTED),
+          .CLK_B1_i(RD_CLK_i),
+          .REN_B1_i(REN_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN_i,REN_i}),
+        
+          .WDATA_A2_i(PORT_A_WDATA[35:18]),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR_ADDR_SHIFTED),
+          .CLK_A2_i(WR_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN_i),
+          .BE_A2_i(WR_BE[3:2]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA[17:0]),
+          .ADDR_B2_i(RD_ADDR_SHIFTED),
+          .CLK_B2_i(RD_CLK_i),
+          .REN_B2_i(REN_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN_i,REN_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );       
+			end
+			32, 36: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_1, MODE_36, MODE_1, MODE_36, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_1, MODE_36, MODE_1, MODE_36, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(1'b1),
+        
+          .WDATA_A1_i(PORT_A_WDATA[17:0]),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR_ADDR_SHIFTED),
+          .CLK_A1_i(WR_CLK_i),
+          .REN_A1_i(1'b0),
+          .WEN_A1_i(WEN_i),
+          .BE_A1_i(WR_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA[17:0]),
+          .ADDR_B1_i(RD_ADDR_SHIFTED),
+          .CLK_B1_i(RD_CLK_i),
+          .REN_B1_i(REN_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN_i,REN_i}),
+        
+          .WDATA_A2_i(PORT_A_WDATA[35:18]),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR_ADDR_SHIFTED),
+          .CLK_A2_i(WR_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN_i),
+          .BE_A2_i(WR_BE[3:2]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA[17:0]),
+          .ADDR_B2_i(RD_ADDR_SHIFTED),
+          .CLK_B2_i(RD_CLK_i),
+          .REN_B2_i(REN_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN_i,REN_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+			default: begin
+				defparam BRAM_BLK.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_1, MODE_1, MODE_1, MODE_1, 1'd0,
+					12'd10, 12'd10, 4'd0, MODE_1, MODE_1, MODE_1, MODE_1, 1'd0
+				};
+        (* is_inferred = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K BRAM_BLK (
+          .RESET_ni(1'b1),
+        
+          .WDATA_A1_i(PORT_A_WDATA[17:0]),
+          .RDATA_A1_o(),
+          .ADDR_A1_i(WR_ADDR_SHIFTED),
+          .CLK_A1_i(WR_CLK_i),
+          .REN_A1_i(1'b0),
+          .WEN_A1_i(WEN_i),
+          .BE_A1_i(WR_BE[1:0]),
+        
+          .WDATA_B1_i(18'h0),
+          .RDATA_B1_o(PORT_B1_RDATA[17:0]),
+          .ADDR_B1_i(RD_ADDR_SHIFTED),
+          .CLK_B1_i(RD_CLK_i),
+          .REN_B1_i(REN_i),
+          .WEN_B1_i(1'b0),
+          .BE_B1_i({REN_i,REN_i}),
+        
+          .WDATA_A2_i(PORT_A_WDATA[35:18]),
+          .RDATA_A2_o(),
+          .ADDR_A2_i(WR_ADDR_SHIFTED),
+          .CLK_A2_i(WR_CLK_i),
+          .REN_A2_i(1'b0),
+          .WEN_A2_i(WEN_i),
+          .BE_A2_i(WR_BE[3:2]),
+        
+          .WDATA_B2_i(18'h0),
+          .RDATA_B2_o(PORT_B2_RDATA[17:0]),
+          .ADDR_B2_i(RD_ADDR_SHIFTED),
+          .CLK_B2_i(RD_CLK_i),
+          .REN_B2_i(REN_i),
+          .WEN_B2_i(1'b0),
+          .BE_B2_i({REN_i,REN_i}),
+        
+          .FLUSH1_i(FLUSH1),
+          .FLUSH2_i(FLUSH2)
+        );        
+			end
+		endcase
+	end
+endcase
+
+endmodule
+
+module BRAM2x18_DP (A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN, C1ADDR, C1DATA, C1EN, CLK1, CLK2, CLK3, CLK4, D1ADDR, D1DATA, D1EN, E1ADDR, E1DATA, E1EN, F1ADDR, F1DATA, F1EN, G1ADDR, G1DATA, G1EN, H1ADDR, H1DATA, H1EN);
+	parameter CFG_ABITS = 11;
+	parameter CFG_DBITS = 18;
+	parameter CFG_ENABLE_B = 4;
+	parameter CFG_ENABLE_D = 4;
+	parameter CFG_ENABLE_F = 4;
+	parameter CFG_ENABLE_H = 4;
+
+	parameter CLKPOL2 = 1;
+	parameter CLKPOL3 = 1;
+	parameter [18431:0] INIT0 = 18432'bx;
+	parameter [18431:0] INIT1 = 18432'bx;
+  
+  localparam MODE_36 = 3'b011; // 36- or 32-bit
+  localparam MODE_18 = 3'b010; // 18- or 16-bit
+  localparam MODE_9 = 3'b001; // 9- or 8-bit
+  localparam MODE_4 = 3'b100; // 4-bit
+  localparam MODE_2 = 3'b110; // 2-bit
+  localparam MODE_1 = 3'b101; // 1-bit
+
+  input wire CLK1;
+  input wire CLK2;
+  input wire CLK3;
+  input wire CLK4;
+
+  input  wire [CFG_ABITS-1:0] A1ADDR;
+  output wire [CFG_DBITS-1:0] A1DATA;
+  input  wire A1EN;
+
+  input  wire [CFG_ABITS-1:0] B1ADDR;
+  input  wire [CFG_DBITS-1:0] B1DATA;
+  input  wire [CFG_ENABLE_B-1:0] B1EN;
+
+  input  wire [CFG_ABITS-1:0] C1ADDR;
+  output wire [CFG_DBITS-1:0] C1DATA;
+  input  wire C1EN;
+
+  input  wire [CFG_ABITS-1:0] D1ADDR;
+  input  wire [CFG_DBITS-1:0] D1DATA;
+  input  wire [CFG_ENABLE_D-1:0] D1EN;
+
+  input  wire [CFG_ABITS-1:0] E1ADDR;
+  output wire [CFG_DBITS-1:0] E1DATA;
+  input  wire E1EN;
+
+  input  wire [CFG_ABITS-1:0] F1ADDR;
+  input  wire [CFG_DBITS-1:0] F1DATA;
+  input  wire [CFG_ENABLE_F-1:0] F1EN;
+
+  input  wire [CFG_ABITS-1:0] G1ADDR;
+  output wire [CFG_DBITS-1:0] G1DATA;
+  input  wire G1EN;
+
+  input  wire [CFG_ABITS-1:0] H1ADDR;
+  input  wire [CFG_DBITS-1:0] H1DATA;
+  input  wire [CFG_ENABLE_H-1:0] H1EN;
+
+	wire FLUSH1;
+	wire FLUSH2;
+
+	wire [14:0] A1ADDR_TOTAL;
+	wire [14:0] B1ADDR_TOTAL;
+	wire [14:0] C1ADDR_TOTAL;
+	wire [14:0] D1ADDR_TOTAL;
+	wire [14:0] E1ADDR_TOTAL;
+	wire [14:0] F1ADDR_TOTAL;
+	wire [14:0] G1ADDR_TOTAL;
+	wire [14:0] H1ADDR_TOTAL;
+  
+  generate
+    if (CFG_ABITS == 15) begin
+      assign A1ADDR_TOTAL = A1ADDR;
+      assign B1ADDR_TOTAL = B1ADDR;
+      assign C1ADDR_TOTAL = C1ADDR;
+      assign D1ADDR_TOTAL = D1ADDR;
+      assign E1ADDR_TOTAL = E1ADDR;
+      assign F1ADDR_TOTAL = F1ADDR;
+      assign G1ADDR_TOTAL = G1ADDR;
+      assign H1ADDR_TOTAL = H1ADDR;
+    end else begin
+      assign A1ADDR_TOTAL[14:CFG_ABITS] = 0;
+      assign A1ADDR_TOTAL[CFG_ABITS-1:0] = A1ADDR;
+      assign B1ADDR_TOTAL[14:CFG_ABITS] = 0;
+      assign B1ADDR_TOTAL[CFG_ABITS-1:0] = B1ADDR;
+      assign C1ADDR_TOTAL[14:CFG_ABITS] = 0;
+      assign C1ADDR_TOTAL[CFG_ABITS-1:0] = C1ADDR;
+      assign D1ADDR_TOTAL[14:CFG_ABITS] = 0;
+      assign D1ADDR_TOTAL[CFG_ABITS-1:0] = D1ADDR;
+      assign E1ADDR_TOTAL[14:CFG_ABITS] = 0;
+      assign E1ADDR_TOTAL[CFG_ABITS-1:0] = E1ADDR;
+      assign F1ADDR_TOTAL[14:CFG_ABITS] = 0;
+      assign F1ADDR_TOTAL[CFG_ABITS-1:0] = F1ADDR;
+      assign G1ADDR_TOTAL[14:CFG_ABITS] = 0;
+      assign G1ADDR_TOTAL[CFG_ABITS-1:0] = G1ADDR;
+      assign H1ADDR_TOTAL[14:CFG_ABITS] = 0;
+      assign H1ADDR_TOTAL[CFG_ABITS-1:0] = H1ADDR;
+    end
+  endgenerate
+
+	wire [17:CFG_DBITS] A1_RDATA_CMPL;
+	wire [17:CFG_DBITS] C1_RDATA_CMPL;
+	wire [17:CFG_DBITS] E1_RDATA_CMPL;
+	wire [17:CFG_DBITS] G1_RDATA_CMPL;
+
+	wire [17:CFG_DBITS] B1_WDATA_CMPL;
+	wire [17:CFG_DBITS] D1_WDATA_CMPL;
+	wire [17:CFG_DBITS] F1_WDATA_CMPL;
+	wire [17:CFG_DBITS] H1_WDATA_CMPL;
+
+	wire [14:0] PORT_A1_ADDR;
+	wire [14:0] PORT_A2_ADDR;
+	wire [14:0] PORT_B1_ADDR;
+	wire [14:0] PORT_B2_ADDR;
+
+	assign FLUSH1 = 1'b0;
+	assign FLUSH2 = 1'b0;
+
+	wire [17:0] PORT_A1_RDATA;
+	wire [17:0] PORT_B1_RDATA;
+	wire [17:0] PORT_A2_RDATA;
+	wire [17:0] PORT_B2_RDATA;
+
+	wire [17:0] PORT_A1_WDATA;
+	wire [17:0] PORT_B1_WDATA;
+	wire [17:0] PORT_A2_WDATA;
+	wire [17:0] PORT_B2_WDATA;
+
+	// Assign read/write data - handle special case for 9bit mode
+	// parity bit for 9bit mode is placed in R/W port on bit #16
+	case (CFG_DBITS)
+		9: begin
+			assign A1DATA = {PORT_A1_RDATA[16], PORT_A1_RDATA[7:0]};
+			assign C1DATA = {PORT_B1_RDATA[16], PORT_B1_RDATA[7:0]};
+			assign E1DATA = {PORT_A2_RDATA[16], PORT_A2_RDATA[7:0]};
+			assign G1DATA = {PORT_B2_RDATA[16], PORT_B2_RDATA[7:0]};
+			assign PORT_A1_WDATA = {B1_WDATA_CMPL[17], B1DATA[8], B1_WDATA_CMPL[16:9], B1DATA[7:0]};
+			assign PORT_B1_WDATA = {D1_WDATA_CMPL[17], D1DATA[8], D1_WDATA_CMPL[16:9], D1DATA[7:0]};
+			assign PORT_A2_WDATA = {F1_WDATA_CMPL[17], F1DATA[8], F1_WDATA_CMPL[16:9], F1DATA[7:0]};
+			assign PORT_B2_WDATA = {H1_WDATA_CMPL[17], H1DATA[8], H1_WDATA_CMPL[16:9], H1DATA[7:0]};
+		end
+		default: begin
+			assign A1DATA = PORT_A1_RDATA[CFG_DBITS-1:0];
+			assign C1DATA = PORT_B1_RDATA[CFG_DBITS-1:0];
+			assign E1DATA = PORT_A2_RDATA[CFG_DBITS-1:0];
+			assign G1DATA = PORT_B2_RDATA[CFG_DBITS-1:0];
+			assign PORT_A1_WDATA = {B1_WDATA_CMPL, B1DATA};
+			assign PORT_B1_WDATA = {D1_WDATA_CMPL, D1DATA};
+			assign PORT_A2_WDATA = {F1_WDATA_CMPL, F1DATA};
+			assign PORT_B2_WDATA = {H1_WDATA_CMPL, H1DATA};
+
+		end
+	endcase
+
+	wire PORT_A1_CLK = CLK1;
+	wire PORT_A2_CLK = CLK3;
+	wire PORT_B1_CLK = CLK2;
+	wire PORT_B2_CLK = CLK4;
+
+	wire PORT_A1_REN = A1EN;
+	wire PORT_A1_WEN = B1EN[0];
+	wire [CFG_ENABLE_B-1:0] PORT_A1_BE = {B1EN[1],B1EN[0]};
+
+	wire PORT_A2_REN = E1EN;
+	wire PORT_A2_WEN = F1EN[0];
+	wire [CFG_ENABLE_F-1:0] PORT_A2_BE = {F1EN[1],F1EN[0]};
+
+	wire PORT_B1_REN = C1EN;
+	wire PORT_B1_WEN = D1EN[0];
+	wire [CFG_ENABLE_D-1:0] PORT_B1_BE = {D1EN[1],D1EN[0]};
+
+	wire PORT_B2_REN = G1EN;
+	wire PORT_B2_WEN = H1EN[0];
+	wire [CFG_ENABLE_H-1:0] PORT_B2_BE = {H1EN[1],H1EN[0]};
+  
+  	case (CFG_DBITS)
+		1: begin
+			assign PORT_A1_ADDR = A1EN ? A1ADDR_TOTAL : (B1EN ? B1ADDR_TOTAL : 14'd0);
+			assign PORT_B1_ADDR = C1EN ? C1ADDR_TOTAL : (D1EN ? D1ADDR_TOTAL : 14'd0);
+			assign PORT_A2_ADDR = E1EN ? E1ADDR_TOTAL : (F1EN ? F1ADDR_TOTAL : 14'd0);
+			assign PORT_B2_ADDR = G1EN ? G1ADDR_TOTAL : (H1EN ? H1ADDR_TOTAL : 14'd0);
+			defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1,
+				11'd10, 11'd10, 4'd0, MODE_1, MODE_1, MODE_1, MODE_1, 1'd0,
+				12'd10, 12'd10, 4'd0, MODE_1, MODE_1, MODE_1, MODE_1, 1'd0
+			};
+      (* is_split = 1 *)
+      (* rd_data_width = CFG_DBITS *)
+      (* wr_data_width = CFG_DBITS *)
+      TDP36K  _TECHMAP_REPLACE_ (
+        .WDATA_A1_i(PORT_A1_WDATA),
+        .RDATA_A1_o(PORT_A1_RDATA),
+        .ADDR_A1_i(PORT_A1_ADDR),
+        .CLK_A1_i(PORT_A1_CLK),
+        .REN_A1_i(PORT_A1_REN),
+        .WEN_A1_i(PORT_A1_WEN),
+        .BE_A1_i(PORT_A1_BE),
+    
+        .WDATA_A2_i(PORT_A2_WDATA),
+        .RDATA_A2_o(PORT_A2_RDATA),
+        .ADDR_A2_i(PORT_A2_ADDR),
+        .CLK_A2_i(PORT_A2_CLK),
+        .REN_A2_i(PORT_A2_REN),
+        .WEN_A2_i(PORT_A2_WEN),
+        .BE_A2_i(PORT_A2_BE),
+    
+        .WDATA_B1_i(PORT_B1_WDATA),
+        .RDATA_B1_o(PORT_B1_RDATA),
+        .ADDR_B1_i(PORT_B1_ADDR),
+        .CLK_B1_i(PORT_B1_CLK),
+        .REN_B1_i(PORT_B1_REN),
+        .WEN_B1_i(PORT_B1_WEN),
+        .BE_B1_i(PORT_B1_BE),
+    
+        .WDATA_B2_i(PORT_B2_WDATA),
+        .RDATA_B2_o(PORT_B2_RDATA),
+        .ADDR_B2_i(PORT_B2_ADDR),
+        .CLK_B2_i(PORT_B2_CLK),
+        .REN_B2_i(PORT_B2_REN),
+        .WEN_B2_i(PORT_B2_WEN),
+        .BE_B2_i(PORT_B2_BE),
+    
+        .FLUSH1_i(FLUSH1),
+        .FLUSH2_i(FLUSH2)
+      );
+		end
+
+		2: begin
+			assign PORT_A1_ADDR = A1EN ? (A1ADDR_TOTAL << 1) : (B1EN ? (B1ADDR_TOTAL << 1) : 14'd0);
+			assign PORT_B1_ADDR = C1EN ? (C1ADDR_TOTAL << 1) : (D1EN ? (D1ADDR_TOTAL << 1) : 14'd0);
+			assign PORT_A2_ADDR = E1EN ? (E1ADDR_TOTAL << 1) : (F1EN ? (F1ADDR_TOTAL << 1) : 14'd0);
+			assign PORT_B2_ADDR = G1EN ? (G1ADDR_TOTAL << 1) : (H1EN ? (H1ADDR_TOTAL << 1) : 14'd0);
+			defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1,
+				11'd10, 11'd10, 4'd0, MODE_2, MODE_2, MODE_2, MODE_2, 1'd0,
+				12'd10, 12'd10, 4'd0, MODE_2, MODE_2, MODE_2, MODE_2, 1'd0
+			};
+      (* is_split = 1 *)
+      (* rd_data_width = CFG_DBITS *)
+      (* wr_data_width = CFG_DBITS *)
+      TDP36K  _TECHMAP_REPLACE_ (
+        .WDATA_A1_i(PORT_A1_WDATA),
+        .RDATA_A1_o(PORT_A1_RDATA),
+        .ADDR_A1_i(PORT_A1_ADDR),
+        .CLK_A1_i(PORT_A1_CLK),
+        .REN_A1_i(PORT_A1_REN),
+        .WEN_A1_i(PORT_A1_WEN),
+        .BE_A1_i(PORT_A1_BE),
+    
+        .WDATA_A2_i(PORT_A2_WDATA),
+        .RDATA_A2_o(PORT_A2_RDATA),
+        .ADDR_A2_i(PORT_A2_ADDR),
+        .CLK_A2_i(PORT_A2_CLK),
+        .REN_A2_i(PORT_A2_REN),
+        .WEN_A2_i(PORT_A2_WEN),
+        .BE_A2_i(PORT_A2_BE),
+    
+        .WDATA_B1_i(PORT_B1_WDATA),
+        .RDATA_B1_o(PORT_B1_RDATA),
+        .ADDR_B1_i(PORT_B1_ADDR),
+        .CLK_B1_i(PORT_B1_CLK),
+        .REN_B1_i(PORT_B1_REN),
+        .WEN_B1_i(PORT_B1_WEN),
+        .BE_B1_i(PORT_B1_BE),
+    
+        .WDATA_B2_i(PORT_B2_WDATA),
+        .RDATA_B2_o(PORT_B2_RDATA),
+        .ADDR_B2_i(PORT_B2_ADDR),
+        .CLK_B2_i(PORT_B2_CLK),
+        .REN_B2_i(PORT_B2_REN),
+        .WEN_B2_i(PORT_B2_WEN),
+        .BE_B2_i(PORT_B2_BE),
+    
+        .FLUSH1_i(FLUSH1),
+        .FLUSH2_i(FLUSH2)
+      );
+		end
+
+		4: begin
+			assign PORT_A1_ADDR = A1EN ? (A1ADDR_TOTAL << 2) : (B1EN ? (B1ADDR_TOTAL << 2) : 14'd0);
+			assign PORT_B1_ADDR = C1EN ? (C1ADDR_TOTAL << 2) : (D1EN ? (D1ADDR_TOTAL << 2) : 14'd0);
+			assign PORT_A2_ADDR = E1EN ? (E1ADDR_TOTAL << 2) : (F1EN ? (F1ADDR_TOTAL << 2) : 14'd0);
+			assign PORT_B2_ADDR = G1EN ? (G1ADDR_TOTAL << 2) : (H1EN ? (H1ADDR_TOTAL << 2) : 14'd0);
+			defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1,
+				11'd10, 11'd10, 4'd0, MODE_4, MODE_4, MODE_4, MODE_4, 1'd0,
+				12'd10, 12'd10, 4'd0, MODE_4, MODE_4, MODE_4, MODE_4, 1'd0
+			};
+      (* is_split = 1 *)
+      (* rd_data_width = CFG_DBITS *)
+      (* wr_data_width = CFG_DBITS *)
+      TDP36K  _TECHMAP_REPLACE_ (
+        .WDATA_A1_i(PORT_A1_WDATA),
+        .RDATA_A1_o(PORT_A1_RDATA),
+        .ADDR_A1_i(PORT_A1_ADDR),
+        .CLK_A1_i(PORT_A1_CLK),
+        .REN_A1_i(PORT_A1_REN),
+        .WEN_A1_i(PORT_A1_WEN),
+        .BE_A1_i(PORT_A1_BE),
+    
+        .WDATA_A2_i(PORT_A2_WDATA),
+        .RDATA_A2_o(PORT_A2_RDATA),
+        .ADDR_A2_i(PORT_A2_ADDR),
+        .CLK_A2_i(PORT_A2_CLK),
+        .REN_A2_i(PORT_A2_REN),
+        .WEN_A2_i(PORT_A2_WEN),
+        .BE_A2_i(PORT_A2_BE),
+    
+        .WDATA_B1_i(PORT_B1_WDATA),
+        .RDATA_B1_o(PORT_B1_RDATA),
+        .ADDR_B1_i(PORT_B1_ADDR),
+        .CLK_B1_i(PORT_B1_CLK),
+        .REN_B1_i(PORT_B1_REN),
+        .WEN_B1_i(PORT_B1_WEN),
+        .BE_B1_i(PORT_B1_BE),
+    
+        .WDATA_B2_i(PORT_B2_WDATA),
+        .RDATA_B2_o(PORT_B2_RDATA),
+        .ADDR_B2_i(PORT_B2_ADDR),
+        .CLK_B2_i(PORT_B2_CLK),
+        .REN_B2_i(PORT_B2_REN),
+        .WEN_B2_i(PORT_B2_WEN),
+        .BE_B2_i(PORT_B2_BE),
+    
+        .FLUSH1_i(FLUSH1),
+        .FLUSH2_i(FLUSH2)
+      );
+		end
+
+		8, 9: begin
+			assign PORT_A1_ADDR = A1EN ? (A1ADDR_TOTAL << 3) : (B1EN ? (B1ADDR_TOTAL << 3) : 14'd0);
+			assign PORT_B1_ADDR = C1EN ? (C1ADDR_TOTAL << 3) : (D1EN ? (D1ADDR_TOTAL << 3) : 14'd0);
+			assign PORT_A2_ADDR = E1EN ? (E1ADDR_TOTAL << 3) : (F1EN ? (F1ADDR_TOTAL << 3) : 14'd0);
+			assign PORT_B2_ADDR = G1EN ? (G1ADDR_TOTAL << 3) : (H1EN ? (H1ADDR_TOTAL << 3) : 14'd0);
+			defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1,
+				11'd10, 11'd10, 4'd0, MODE_9, MODE_9, MODE_9, MODE_9, 1'd0,
+				12'd10, 12'd10, 4'd0, MODE_9, MODE_9, MODE_9, MODE_9, 1'd0
+			};
+      (* is_split = 1 *)
+      (* rd_data_width = CFG_DBITS *)
+      (* wr_data_width = CFG_DBITS *)
+      TDP36K  _TECHMAP_REPLACE_ (
+        .WDATA_A1_i(PORT_A1_WDATA),
+        .RDATA_A1_o(PORT_A1_RDATA),
+        .ADDR_A1_i(PORT_A1_ADDR),
+        .CLK_A1_i(PORT_A1_CLK),
+        .REN_A1_i(PORT_A1_REN),
+        .WEN_A1_i(PORT_A1_WEN),
+        .BE_A1_i(PORT_A1_BE),
+    
+        .WDATA_A2_i(PORT_A2_WDATA),
+        .RDATA_A2_o(PORT_A2_RDATA),
+        .ADDR_A2_i(PORT_A2_ADDR),
+        .CLK_A2_i(PORT_A2_CLK),
+        .REN_A2_i(PORT_A2_REN),
+        .WEN_A2_i(PORT_A2_WEN),
+        .BE_A2_i(PORT_A2_BE),
+    
+        .WDATA_B1_i(PORT_B1_WDATA),
+        .RDATA_B1_o(PORT_B1_RDATA),
+        .ADDR_B1_i(PORT_B1_ADDR),
+        .CLK_B1_i(PORT_B1_CLK),
+        .REN_B1_i(PORT_B1_REN),
+        .WEN_B1_i(PORT_B1_WEN),
+        .BE_B1_i(PORT_B1_BE),
+    
+        .WDATA_B2_i(PORT_B2_WDATA),
+        .RDATA_B2_o(PORT_B2_RDATA),
+        .ADDR_B2_i(PORT_B2_ADDR),
+        .CLK_B2_i(PORT_B2_CLK),
+        .REN_B2_i(PORT_B2_REN),
+        .WEN_B2_i(PORT_B2_WEN),
+        .BE_B2_i(PORT_B2_BE),
+    
+        .FLUSH1_i(FLUSH1),
+        .FLUSH2_i(FLUSH2)
+      );
+		end
+
+		16, 18: begin
+			assign PORT_A1_ADDR = A1EN ? (A1ADDR_TOTAL << 4) : (B1EN ? (B1ADDR_TOTAL << 4) : 14'd0);
+			assign PORT_B1_ADDR = C1EN ? (C1ADDR_TOTAL << 4) : (D1EN ? (D1ADDR_TOTAL << 4) : 14'd0);
+			assign PORT_A2_ADDR = E1EN ? (E1ADDR_TOTAL << 4) : (F1EN ? (F1ADDR_TOTAL << 4) : 14'd0);
+			assign PORT_B2_ADDR = G1EN ? (G1ADDR_TOTAL << 4) : (H1EN ? (H1ADDR_TOTAL << 4) : 14'd0);
+			defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1,
+				11'd10, 11'd10, 4'd0, MODE_18, MODE_18, MODE_18, MODE_18, 1'd0,
+				12'd10, 12'd10, 4'd0, MODE_18, MODE_18, MODE_18, MODE_18, 1'd0
+			};
+      (* is_split = 1 *)
+      (* rd_data_width = CFG_DBITS *)
+      (* wr_data_width = CFG_DBITS *)
+      TDP36K  _TECHMAP_REPLACE_ (
+        .WDATA_A1_i(PORT_A1_WDATA),
+        .RDATA_A1_o(PORT_A1_RDATA),
+        .ADDR_A1_i(PORT_A1_ADDR),
+        .CLK_A1_i(PORT_A1_CLK),
+        .REN_A1_i(PORT_A1_REN),
+        .WEN_A1_i(PORT_A1_WEN),
+        .BE_A1_i(PORT_A1_BE),
+    
+        .WDATA_A2_i(PORT_A2_WDATA),
+        .RDATA_A2_o(PORT_A2_RDATA),
+        .ADDR_A2_i(PORT_A2_ADDR),
+        .CLK_A2_i(PORT_A2_CLK),
+        .REN_A2_i(PORT_A2_REN),
+        .WEN_A2_i(PORT_A2_WEN),
+        .BE_A2_i(PORT_A2_BE),
+    
+        .WDATA_B1_i(PORT_B1_WDATA),
+        .RDATA_B1_o(PORT_B1_RDATA),
+        .ADDR_B1_i(PORT_B1_ADDR),
+        .CLK_B1_i(PORT_B1_CLK),
+        .REN_B1_i(PORT_B1_REN),
+        .WEN_B1_i(PORT_B1_WEN),
+        .BE_B1_i(PORT_B1_BE),
+    
+        .WDATA_B2_i(PORT_B2_WDATA),
+        .RDATA_B2_o(PORT_B2_RDATA),
+        .ADDR_B2_i(PORT_B2_ADDR),
+        .CLK_B2_i(PORT_B2_CLK),
+        .REN_B2_i(PORT_B2_REN),
+        .WEN_B2_i(PORT_B2_WEN),
+        .BE_B2_i(PORT_B2_BE),
+    
+        .FLUSH1_i(FLUSH1),
+        .FLUSH2_i(FLUSH2)
+      );
+		end
+
+		default: begin
+			assign PORT_A1_ADDR = A1EN ? A1ADDR_TOTAL : (B1EN ? B1ADDR_TOTAL : 14'd0);
+			assign PORT_B1_ADDR = C1EN ? C1ADDR_TOTAL : (D1EN ? D1ADDR_TOTAL : 14'd0);
+			assign PORT_A2_ADDR = E1EN ? E1ADDR_TOTAL : (F1EN ? F1ADDR_TOTAL : 14'd0);
+			assign PORT_B2_ADDR = G1EN ? G1ADDR_TOTAL : (H1EN ? H1ADDR_TOTAL : 14'd0);
+			defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1,
+				11'd10, 11'd10, 4'd0, MODE_36, MODE_36, MODE_36, MODE_36, 1'd0,
+				12'd10, 12'd10, 4'd0, MODE_36, MODE_36, MODE_36, MODE_36, 1'd0
+			};
+      (* is_split = 1 *)
+      (* rd_data_width = CFG_DBITS *)
+      (* wr_data_width = CFG_DBITS *)
+      TDP36K  _TECHMAP_REPLACE_ (
+        .WDATA_A1_i(PORT_A1_WDATA),
+        .RDATA_A1_o(PORT_A1_RDATA),
+        .ADDR_A1_i(PORT_A1_ADDR),
+        .CLK_A1_i(PORT_A1_CLK),
+        .REN_A1_i(PORT_A1_REN),
+        .WEN_A1_i(PORT_A1_WEN),
+        .BE_A1_i(PORT_A1_BE),
+    
+        .WDATA_A2_i(PORT_A2_WDATA),
+        .RDATA_A2_o(PORT_A2_RDATA),
+        .ADDR_A2_i(PORT_A2_ADDR),
+        .CLK_A2_i(PORT_A2_CLK),
+        .REN_A2_i(PORT_A2_REN),
+        .WEN_A2_i(PORT_A2_WEN),
+        .BE_A2_i(PORT_A2_BE),
+    
+        .WDATA_B1_i(PORT_B1_WDATA),
+        .RDATA_B1_o(PORT_B1_RDATA),
+        .ADDR_B1_i(PORT_B1_ADDR),
+        .CLK_B1_i(PORT_B1_CLK),
+        .REN_B1_i(PORT_B1_REN),
+        .WEN_B1_i(PORT_B1_WEN),
+        .BE_B1_i(PORT_B1_BE),
+    
+        .WDATA_B2_i(PORT_B2_WDATA),
+        .RDATA_B2_o(PORT_B2_RDATA),
+        .ADDR_B2_i(PORT_B2_ADDR),
+        .CLK_B2_i(PORT_B2_CLK),
+        .REN_B2_i(PORT_B2_REN),
+        .WEN_B2_i(PORT_B2_WEN),
+        .BE_B2_i(PORT_B2_BE),
+    
+        .FLUSH1_i(FLUSH1),
+        .FLUSH2_i(FLUSH2)
+      );
+		end
+	endcase
+
+endmodule
+
+module DPRAM_18K_BLK (   
+    CLK1_i,
+    WEN1_i,
+    REN1_i,
+    WR1_ADDR_i,
+    RD1_ADDR_i,
+    WDATA1_i,
+    RDATA1_o,
+    
+    CLK2_i,
+    WEN2_i,
+    REN2_i,
+    WR2_ADDR_i,
+    RD2_ADDR_i,
+    WDATA2_i,
+    RDATA2_o
+);
+
+parameter ADDR_WIDTH = 10;
+parameter DATA_WIDTH = 18;
+parameter BE1_WIDTH = 2;
+parameter BE2_WIDTH = 2;
+
+input wire CLK1_i;
+input wire WEN1_i;
+input wire REN1_i;
+input wire [ADDR_WIDTH-1 :0] WR1_ADDR_i;
+input wire [ADDR_WIDTH-1 :0] RD1_ADDR_i;
+input wire [DATA_WIDTH-1 :0] WDATA1_i;
+output wire [DATA_WIDTH-1 :0] RDATA1_o;
+
+input wire CLK2_i;
+input wire WEN2_i;
+input wire REN2_i;
+input wire [ADDR_WIDTH-1 :0] WR2_ADDR_i;
+input wire [ADDR_WIDTH-1 :0] RD2_ADDR_i;
+input wire [DATA_WIDTH-1 :0] WDATA2_i;
+output wire [DATA_WIDTH-1 :0] RDATA2_o;
+
+(* is_inferred = 1 *)
+BRAM2x18_DP #(
+	.CFG_ABITS(ADDR_WIDTH),
+	.CFG_DBITS(DATA_WIDTH),
+	.CFG_ENABLE_B(BE1_WIDTH),
+	.CFG_ENABLE_D(BE2_WIDTH)
+) bram2x18_inst (
+	.A1ADDR(RD1_ADDR_i),
+	.A1DATA(RDATA1_o),
+	.A1EN(REN1_i),
+	.B1ADDR(WR1_ADDR_i),
+	.B1DATA(WDATA1_i),
+	.B1EN({WEN1_i,WEN1_i}),
+	.CLK1(CLK1_i),
+
+	.C1ADDR(RD2_ADDR_i),
+	.C1DATA(RDATA2_o),
+	.C1EN(REN2_i),
+	.D1ADDR(WR2_ADDR_i),
+	.D1DATA(WDATA2_i),
+	.D1EN({WEN2_i,WEN2_i}),
+	.CLK2(CLK2_i),
+
+	.E1ADDR(),
+	.E1DATA(),
+	.E1EN(),
+	.F1ADDR(),
+	.F1DATA(),
+	.F1EN(),
+	.CLK3(),
+
+	.G1ADDR(),
+	.G1DATA(),
+	.G1EN(),
+	.H1ADDR(),
+	.H1DATA(),
+	.H1EN(),
+	.CLK4()
+);
+endmodule
+
+module DPRAM_36K_BLK (   
+    CLK1_i,
+    WEN1_i,
+    WR1_BE_i,
+    REN1_i,
+    WR1_ADDR_i,
+    RD1_ADDR_i,
+    WDATA1_i,
+    RDATA1_o,
+    
+    CLK2_i,
+    WEN2_i,
+    WR2_BE_i,
+    REN2_i,
+    WR2_ADDR_i,
+    RD2_ADDR_i,
+    WDATA2_i,
+    RDATA2_o
+);
+
+parameter ADDR_WIDTH = 10;
+parameter DATA_WIDTH = 36;
+parameter BE1_WIDTH = 4;
+parameter BE2_WIDTH = 4;
+
+localparam MODE_36 = 3'b011; // 36- or 32-bit
+localparam MODE_18 = 3'b010; // 18- or 16-bit
+localparam MODE_9 = 3'b001; // 9- or 8-bit
+localparam MODE_4 = 3'b100; // 4-bit
+localparam MODE_2 = 3'b110; // 2-bit
+localparam MODE_1 = 3'b101; // 1-bit
+
+input wire CLK1_i;
+input wire WEN1_i;
+input wire [BE1_WIDTH-1 :0] WR1_BE_i;
+input wire REN1_i;
+input wire [ADDR_WIDTH-1 :0] WR1_ADDR_i;
+input wire [ADDR_WIDTH-1 :0] RD1_ADDR_i;
+input wire [DATA_WIDTH-1 :0] WDATA1_i;
+output wire [DATA_WIDTH-1 :0] RDATA1_o;
+
+input wire CLK2_i;
+input wire WEN2_i;
+input wire [BE2_WIDTH-1 :0] WR2_BE_i;
+input wire REN2_i;
+input wire [ADDR_WIDTH-1 :0] WR2_ADDR_i;
+input wire [ADDR_WIDTH-1 :0] RD2_ADDR_i;
+input wire [DATA_WIDTH-1 :0] WDATA2_i;
+output wire [DATA_WIDTH-1 :0] RDATA2_o;
+
+wire FLUSH1;
+wire FLUSH2;
+
+wire [14:0] A1ADDR_TOTAL;
+wire [14:0] B1ADDR_TOTAL;
+wire [14:0] C1ADDR_TOTAL;
+wire [14:0] D1ADDR_TOTAL;
+
+generate
+  if (ADDR_WIDTH == 15) begin
+    assign A1ADDR_TOTAL = RD1_ADDR_i;
+    assign B1ADDR_TOTAL = WR1_ADDR_i;
+    assign C1ADDR_TOTAL = RD2_ADDR_i;
+    assign D1ADDR_TOTAL = WR2_ADDR_i;
+  end else begin
+    assign A1ADDR_TOTAL[14:ADDR_WIDTH] = 0;
+    assign A1ADDR_TOTAL[ADDR_WIDTH-1:0] = RD1_ADDR_i;
+    assign B1ADDR_TOTAL[14:ADDR_WIDTH] = 0;
+    assign B1ADDR_TOTAL[ADDR_WIDTH-1:0] = WR1_ADDR_i;
+    assign C1ADDR_TOTAL[14:ADDR_WIDTH] = 0;
+    assign C1ADDR_TOTAL[ADDR_WIDTH-1:0] = RD2_ADDR_i;
+    assign D1ADDR_TOTAL[14:ADDR_WIDTH] = 0;
+    assign D1ADDR_TOTAL[ADDR_WIDTH-1:0] = WR2_ADDR_i;
+  end
+endgenerate
+
+wire [35:DATA_WIDTH] A1DATA_CMPL;
+wire [35:DATA_WIDTH] B1DATA_CMPL;
+wire [35:DATA_WIDTH] C1DATA_CMPL;
+wire [35:DATA_WIDTH] D1DATA_CMPL;
+
+wire [35:0] A1DATA_TOTAL;
+wire [35:0] B1DATA_TOTAL;
+wire [35:0] C1DATA_TOTAL;
+wire [35:0] D1DATA_TOTAL;
+
+wire [14:0] PORT_A_ADDR;
+wire [14:0] PORT_B_ADDR;
+
+wire [3:0] WR1_BE;
+wire [3:0] WR2_BE;
+
+generate
+  if (BE1_WIDTH == 4) begin
+    assign WR1_BE = WR1_BE_i;
+  end else begin
+    assign WR1_BE[3:BE1_WIDTH] = 0;
+    assign WR1_BE[BE1_WIDTH-1:0] = WR1_BE_i[BE1_WIDTH-1:0];
+  end
+endgenerate
+
+generate
+  if (BE2_WIDTH == 4) begin
+    assign WR2_BE = WR2_BE_i;
+  end else begin
+    assign WR2_BE[3:BE2_WIDTH] = 0;
+    assign WR2_BE[BE2_WIDTH-1:0] = WR2_BE_i[BE2_WIDTH-1:0];
+  end
+endgenerate
+
+// Assign read/write data - handle special case for 9bit mode
+// parity bit for 9bit mode is placed in R/W port on bit #16
+case (DATA_WIDTH)
+	9: begin
+		assign RDATA1_o = {A1DATA_TOTAL[16], A1DATA_TOTAL[7:0]};
+		assign RDATA2_o = {C1DATA_TOTAL[16], C1DATA_TOTAL[7:0]};
+		assign B1DATA_TOTAL = {B1DATA_CMPL[35:17], WDATA1_i[8], B1DATA_CMPL[16:9], WDATA1_i[7:0]};
+		assign D1DATA_TOTAL = {D1DATA_CMPL[35:17], WDATA2_i[8], D1DATA_CMPL[16:9], WDATA2_i[7:0]};
+	end
+	default: begin
+		assign RDATA1_o = A1DATA_TOTAL[DATA_WIDTH-1:0];
+		assign RDATA2_o = C1DATA_TOTAL[DATA_WIDTH-1:0];
+		assign B1DATA_TOTAL = {B1DATA_CMPL, WDATA1_i};
+		assign D1DATA_TOTAL = {D1DATA_CMPL, WDATA2_i};
+	end
+endcase
+
+assign FLUSH1 = 1'b0;
+assign FLUSH2 = 1'b0;
+
+case (DATA_WIDTH)
+	1: begin
+		assign PORT_A_ADDR = REN1_i ? A1ADDR_TOTAL : (WEN1_i ? B1ADDR_TOTAL : 15'd0);
+		assign PORT_B_ADDR = REN2_i ? C1ADDR_TOTAL : (WEN2_i ? D1ADDR_TOTAL : 15'd0);
+          defparam U1.MODE_BITS = { 1'b0,
+              11'd10, 11'd10, 4'd0, MODE_1, MODE_1, MODE_1, MODE_1, 1'd0,
+              12'd10, 12'd10, 4'd0, MODE_1, MODE_1, MODE_1, MODE_1, 1'd0
+          };
+          (* is_inferred = 1 *)
+          (* rd_data_width = DATA_WIDTH *)
+          (* wr_data_width = DATA_WIDTH *)
+          TDP36K U1 (
+            .RESET_ni(1'b1),
+            .WDATA_A1_i(B1DATA_TOTAL[17:0]),
+            .WDATA_A2_i(B1DATA_TOTAL[35:18]),
+            .RDATA_A1_o(A1DATA_TOTAL[17:0]),
+            .RDATA_A2_o(A1DATA_TOTAL[35:18]),
+            .ADDR_A1_i(PORT_A_ADDR),
+            .ADDR_A2_i(PORT_A_ADDR),
+            .CLK_A1_i(CLK1_i),
+            .CLK_A2_i(CLK1_i),
+            .REN_A1_i(REN1_i),
+            .REN_A2_i(REN1_i),
+            .WEN_A1_i(WEN1_i),
+            .WEN_A2_i(WEN1_i),
+            .BE_A1_i(WR1_BE[1:0]),
+            .BE_A2_i(WR1_BE[3:0]),
+          
+            .WDATA_B1_i(D1DATA_TOTAL[17:0]),
+            .WDATA_B2_i(D1DATA_TOTAL[35:18]),
+            .RDATA_B1_o(C1DATA_TOTAL[17:0]),
+            .RDATA_B2_o(C1DATA_TOTAL[35:18]),
+            .ADDR_B1_i(PORT_B_ADDR),
+            .ADDR_B2_i(PORT_B_ADDR),
+            .CLK_B1_i(CLK2_i),
+            .CLK_B2_i(CLK2_i),
+            .REN_B1_i(REN2_i),
+            .REN_B2_i(REN2_i),
+            .WEN_B1_i(WEN2_i),
+            .WEN_B2_i(WEN2_i),
+            .BE_B1_i(WR2_BE[1:0]),
+            .BE_B2_i(WR2_BE[3:0]),
+          
+            .FLUSH1_i(FLUSH1),
+            .FLUSH2_i(FLUSH2)
+          );          
+	end
+
+	2: begin
+		assign PORT_A_ADDR = REN1_i ? (A1ADDR_TOTAL << 1) : (WEN1_i ? (B1ADDR_TOTAL << 1) : 15'd0);
+		assign PORT_B_ADDR = REN2_i ? (C1ADDR_TOTAL << 1) : (WEN2_i ? (D1ADDR_TOTAL << 1) : 15'd0);
+          defparam U1.MODE_BITS = { 1'b0,
+              11'd10, 11'd10, 4'd0, MODE_2, MODE_2, MODE_2, MODE_2, 1'd0,
+              12'd10, 12'd10, 4'd0, MODE_2, MODE_2, MODE_2, MODE_2, 1'd0
+          };
+          (* is_inferred = 1 *)
+          (* rd_data_width = DATA_WIDTH *)
+          (* wr_data_width = DATA_WIDTH *)
+          TDP36K U1 (
+            .RESET_ni(1'b1),
+            .WDATA_A1_i(B1DATA_TOTAL[17:0]),
+            .WDATA_A2_i(B1DATA_TOTAL[35:18]),
+            .RDATA_A1_o(A1DATA_TOTAL[17:0]),
+            .RDATA_A2_o(A1DATA_TOTAL[35:18]),
+            .ADDR_A1_i(PORT_A_ADDR),
+            .ADDR_A2_i(PORT_A_ADDR),
+            .CLK_A1_i(CLK1_i),
+            .CLK_A2_i(CLK1_i),
+            .REN_A1_i(REN1_i),
+            .REN_A2_i(REN1_i),
+            .WEN_A1_i(WEN1_i),
+            .WEN_A2_i(WEN1_i),
+            .BE_A1_i(WR1_BE[1:0]),
+            .BE_A2_i(WR1_BE[3:0]),
+          
+            .WDATA_B1_i(D1DATA_TOTAL[17:0]),
+            .WDATA_B2_i(D1DATA_TOTAL[35:18]),
+            .RDATA_B1_o(C1DATA_TOTAL[17:0]),
+            .RDATA_B2_o(C1DATA_TOTAL[35:18]),
+            .ADDR_B1_i(PORT_B_ADDR),
+            .ADDR_B2_i(PORT_B_ADDR),
+            .CLK_B1_i(CLK2_i),
+            .CLK_B2_i(CLK2_i),
+            .REN_B1_i(REN2_i),
+            .REN_B2_i(REN2_i),
+            .WEN_B1_i(WEN2_i),
+            .WEN_B2_i(WEN2_i),
+            .BE_B1_i(WR2_BE[1:0]),
+            .BE_B2_i(WR2_BE[3:0]),
+          
+            .FLUSH1_i(FLUSH1),
+            .FLUSH2_i(FLUSH2)
+          );          
+	end
+
+	4: begin
+		assign PORT_A_ADDR = REN1_i ? (A1ADDR_TOTAL << 2) : (WEN1_i ? (B1ADDR_TOTAL << 2) : 15'd0);
+		assign PORT_B_ADDR = REN2_i ? (C1ADDR_TOTAL << 2) : (WEN2_i ? (D1ADDR_TOTAL << 2) : 15'd0);
+          defparam U1.MODE_BITS = { 1'b0,
+              11'd10, 11'd10, 4'd0, MODE_4, MODE_4, MODE_4, MODE_4, 1'd0,
+              12'd10, 12'd10, 4'd0, MODE_4, MODE_4, MODE_4, MODE_4, 1'd0
+          };
+          (* is_inferred = 1 *)
+          (* rd_data_width = DATA_WIDTH *)
+          (* wr_data_width = DATA_WIDTH *)
+          TDP36K U1 (
+            .RESET_ni(1'b1),
+            .WDATA_A1_i(B1DATA_TOTAL[17:0]),
+            .WDATA_A2_i(B1DATA_TOTAL[35:18]),
+            .RDATA_A1_o(A1DATA_TOTAL[17:0]),
+            .RDATA_A2_o(A1DATA_TOTAL[35:18]),
+            .ADDR_A1_i(PORT_A_ADDR),
+            .ADDR_A2_i(PORT_A_ADDR),
+            .CLK_A1_i(CLK1_i),
+            .CLK_A2_i(CLK1_i),
+            .REN_A1_i(REN1_i),
+            .REN_A2_i(REN1_i),
+            .WEN_A1_i(WEN1_i),
+            .WEN_A2_i(WEN1_i),
+            .BE_A1_i(WR1_BE[1:0]),
+            .BE_A2_i(WR1_BE[3:0]),
+          
+            .WDATA_B1_i(D1DATA_TOTAL[17:0]),
+            .WDATA_B2_i(D1DATA_TOTAL[35:18]),
+            .RDATA_B1_o(C1DATA_TOTAL[17:0]),
+            .RDATA_B2_o(C1DATA_TOTAL[35:18]),
+            .ADDR_B1_i(PORT_B_ADDR),
+            .ADDR_B2_i(PORT_B_ADDR),
+            .CLK_B1_i(CLK2_i),
+            .CLK_B2_i(CLK2_i),
+            .REN_B1_i(REN2_i),
+            .REN_B2_i(REN2_i),
+            .WEN_B1_i(WEN2_i),
+            .WEN_B2_i(WEN2_i),
+            .BE_B1_i(WR2_BE[1:0]),
+            .BE_B2_i(WR2_BE[3:0]),
+          
+            .FLUSH1_i(FLUSH1),
+            .FLUSH2_i(FLUSH2)
+          );          
+	end
+
+	8, 9: begin
+		assign PORT_A_ADDR = REN1_i ? (A1ADDR_TOTAL << 3) : (WEN1_i ? (B1ADDR_TOTAL << 3) : 15'd0);
+		assign PORT_B_ADDR = REN2_i ? (C1ADDR_TOTAL << 3) : (WEN2_i ? (D1ADDR_TOTAL << 3) : 15'd0);
+          defparam U1.MODE_BITS = { 1'b0,
+              11'd10, 11'd10, 4'd0, MODE_9, MODE_9, MODE_9, MODE_9, 1'd0,
+              12'd10, 12'd10, 4'd0, MODE_9, MODE_9, MODE_9, MODE_9, 1'd0
+          };
+          (* is_inferred = 1 *)
+          (* rd_data_width = DATA_WIDTH *)
+          (* wr_data_width = DATA_WIDTH *)
+          TDP36K U1 (
+            .RESET_ni(1'b1),
+            .WDATA_A1_i(B1DATA_TOTAL[17:0]),
+            .WDATA_A2_i(B1DATA_TOTAL[35:18]),
+            .RDATA_A1_o(A1DATA_TOTAL[17:0]),
+            .RDATA_A2_o(A1DATA_TOTAL[35:18]),
+            .ADDR_A1_i(PORT_A_ADDR),
+            .ADDR_A2_i(PORT_A_ADDR),
+            .CLK_A1_i(CLK1_i),
+            .CLK_A2_i(CLK1_i),
+            .REN_A1_i(REN1_i),
+            .REN_A2_i(REN1_i),
+            .WEN_A1_i(WEN1_i),
+            .WEN_A2_i(WEN1_i),
+            .BE_A1_i(WR1_BE[1:0]),
+            .BE_A2_i(WR1_BE[3:0]),
+          
+            .WDATA_B1_i(D1DATA_TOTAL[17:0]),
+            .WDATA_B2_i(D1DATA_TOTAL[35:18]),
+            .RDATA_B1_o(C1DATA_TOTAL[17:0]),
+            .RDATA_B2_o(C1DATA_TOTAL[35:18]),
+            .ADDR_B1_i(PORT_B_ADDR),
+            .ADDR_B2_i(PORT_B_ADDR),
+            .CLK_B1_i(CLK2_i),
+            .CLK_B2_i(CLK2_i),
+            .REN_B1_i(REN2_i),
+            .REN_B2_i(REN2_i),
+            .WEN_B1_i(WEN2_i),
+            .WEN_B2_i(WEN2_i),
+            .BE_B1_i(WR2_BE[1:0]),
+            .BE_B2_i(WR2_BE[3:0]),
+          
+            .FLUSH1_i(FLUSH1),
+            .FLUSH2_i(FLUSH2)
+          );          
+	end
+
+	16, 18: begin
+		assign PORT_A_ADDR = REN1_i ? (A1ADDR_TOTAL << 4) : (WEN1_i ? (B1ADDR_TOTAL << 4) : 15'd0);
+		assign PORT_B_ADDR = REN2_i ? (C1ADDR_TOTAL << 4) : (WEN2_i ? (D1ADDR_TOTAL << 4) : 15'd0);
+          defparam U1.MODE_BITS = { 1'b0,
+              11'd10, 11'd10, 4'd0, MODE_18, MODE_18, MODE_18, MODE_18, 1'd0,
+              12'd10, 12'd10, 4'd0, MODE_18, MODE_18, MODE_18, MODE_18, 1'd0
+          };
+          (* is_inferred = 1 *)
+          (* rd_data_width = DATA_WIDTH *)
+          (* wr_data_width = DATA_WIDTH *)
+          TDP36K U1 (
+            .RESET_ni(1'b1),
+            .WDATA_A1_i(B1DATA_TOTAL[17:0]),
+            .WDATA_A2_i(B1DATA_TOTAL[35:18]),
+            .RDATA_A1_o(A1DATA_TOTAL[17:0]),
+            .RDATA_A2_o(A1DATA_TOTAL[35:18]),
+            .ADDR_A1_i(PORT_A_ADDR),
+            .ADDR_A2_i(PORT_A_ADDR),
+            .CLK_A1_i(CLK1_i),
+            .CLK_A2_i(CLK1_i),
+            .REN_A1_i(REN1_i),
+            .REN_A2_i(REN1_i),
+            .WEN_A1_i(WEN1_i),
+            .WEN_A2_i(WEN1_i),
+            .BE_A1_i(WR1_BE[1:0]),
+            .BE_A2_i(WR1_BE[3:0]),
+          
+            .WDATA_B1_i(D1DATA_TOTAL[17:0]),
+            .WDATA_B2_i(D1DATA_TOTAL[35:18]),
+            .RDATA_B1_o(C1DATA_TOTAL[17:0]),
+            .RDATA_B2_o(C1DATA_TOTAL[35:18]),
+            .ADDR_B1_i(PORT_B_ADDR),
+            .ADDR_B2_i(PORT_B_ADDR),
+            .CLK_B1_i(CLK2_i),
+            .CLK_B2_i(CLK2_i),
+            .REN_B1_i(REN2_i),
+            .REN_B2_i(REN2_i),
+            .WEN_B1_i(WEN2_i),
+            .WEN_B2_i(WEN2_i),
+            .BE_B1_i(WR2_BE[1:0]),
+            .BE_B2_i(WR2_BE[3:0]),
+          
+            .FLUSH1_i(FLUSH1),
+            .FLUSH2_i(FLUSH2)
+          );          
+	end
+
+	32, 36: begin
+		assign PORT_A_ADDR = REN1_i ? (A1ADDR_TOTAL << 5) : (WEN1_i ? (B1ADDR_TOTAL << 5) : 15'd0);
+		assign PORT_B_ADDR = REN2_i ? (C1ADDR_TOTAL << 5) : (WEN2_i ? (D1ADDR_TOTAL << 5) : 15'd0);
+          defparam U1.MODE_BITS = { 1'b0,
+              11'd10, 11'd10, 4'd0, MODE_36, MODE_36, MODE_36, MODE_36, 1'd0,
+              12'd10, 12'd10, 4'd0, MODE_36, MODE_36, MODE_36, MODE_36, 1'd0
+          };
+          (* is_inferred = 1 *)
+          (* rd_data_width = DATA_WIDTH *)
+          (* wr_data_width = DATA_WIDTH *)
+          TDP36K U1 (
+            .RESET_ni(1'b1),
+            .WDATA_A1_i(B1DATA_TOTAL[17:0]),
+            .WDATA_A2_i(B1DATA_TOTAL[35:18]),
+            .RDATA_A1_o(A1DATA_TOTAL[17:0]),
+            .RDATA_A2_o(A1DATA_TOTAL[35:18]),
+            .ADDR_A1_i(PORT_A_ADDR),
+            .ADDR_A2_i(PORT_A_ADDR),
+            .CLK_A1_i(CLK1_i),
+            .CLK_A2_i(CLK1_i),
+            .REN_A1_i(REN1_i),
+            .REN_A2_i(REN1_i),
+            .WEN_A1_i(WEN1_i),
+            .WEN_A2_i(WEN1_i),
+            .BE_A1_i(WR1_BE[1:0]),
+            .BE_A2_i(WR1_BE[3:0]),
+          
+            .WDATA_B1_i(D1DATA_TOTAL[17:0]),
+            .WDATA_B2_i(D1DATA_TOTAL[35:18]),
+            .RDATA_B1_o(C1DATA_TOTAL[17:0]),
+            .RDATA_B2_o(C1DATA_TOTAL[35:18]),
+            .ADDR_B1_i(PORT_B_ADDR),
+            .ADDR_B2_i(PORT_B_ADDR),
+            .CLK_B1_i(CLK2_i),
+            .CLK_B2_i(CLK2_i),
+            .REN_B1_i(REN2_i),
+            .REN_B2_i(REN2_i),
+            .WEN_B1_i(WEN2_i),
+            .WEN_B2_i(WEN2_i),
+            .BE_B1_i(WR2_BE[1:0]),
+            .BE_B2_i(WR2_BE[3:0]),
+          
+            .FLUSH1_i(FLUSH1),
+            .FLUSH2_i(FLUSH2)
+          );          
+	end
+	default: begin
+		assign PORT_A_ADDR = REN1_i ? (A1ADDR_TOTAL << 5) : (WEN1_i ? (B1ADDR_TOTAL << 5) : 15'd0);
+		assign PORT_B_ADDR = REN2_i ? (C1ADDR_TOTAL << 5) : (WEN2_i ? (D1ADDR_TOTAL << 5) : 15'd0);
+          defparam U1.MODE_BITS = { 1'b0,
+              11'd10, 11'd10, 4'd0, MODE_36, MODE_36, MODE_36, MODE_36, 1'd0,
+              12'd10, 12'd10, 4'd0, MODE_36, MODE_36, MODE_36, MODE_36, 1'd0
+          };
+          (* is_inferred = 1 *)
+          (* rd_data_width = DATA_WIDTH *)
+          (* wr_data_width = DATA_WIDTH *)
+          TDP36K U1 (
+            .RESET_ni(1'b1),
+            .WDATA_A1_i(B1DATA_TOTAL[17:0]),
+            .WDATA_A2_i(B1DATA_TOTAL[35:18]),
+            .RDATA_A1_o(A1DATA_TOTAL[17:0]),
+            .RDATA_A2_o(A1DATA_TOTAL[35:18]),
+            .ADDR_A1_i(PORT_A_ADDR),
+            .ADDR_A2_i(PORT_A_ADDR),
+            .CLK_A1_i(CLK1_i),
+            .CLK_A2_i(CLK1_i),
+            .REN_A1_i(REN1_i),
+            .REN_A2_i(REN1_i),
+            .WEN_A1_i(WEN1_i),
+            .WEN_A2_i(WEN1_i),
+            .BE_A1_i(WR1_BE[1:0]),
+            .BE_A2_i(WR1_BE[3:0]),
+          
+            .WDATA_B1_i(D1DATA_TOTAL[17:0]),
+            .WDATA_B2_i(D1DATA_TOTAL[35:18]),
+            .RDATA_B1_o(C1DATA_TOTAL[17:0]),
+            .RDATA_B2_o(C1DATA_TOTAL[35:18]),
+            .ADDR_B1_i(PORT_B_ADDR),
+            .ADDR_B2_i(PORT_B_ADDR),
+            .CLK_B1_i(CLK2_i),
+            .CLK_B2_i(CLK2_i),
+            .REN_B1_i(REN2_i),
+            .REN_B2_i(REN2_i),
+            .WEN_B1_i(WEN2_i),
+            .WEN_B2_i(WEN2_i),
+            .BE_B1_i(WR2_BE[1:0]),
+            .BE_B2_i(WR2_BE[3:0]),
+          
+            .FLUSH1_i(FLUSH1),
+            .FLUSH2_i(FLUSH2)
+          );          
+	end
+endcase
+
+endmodule
+
+// ============================================================================
+// TDP36K write width 1 functional modes
+
+module TDP36K_BRAM_WR_X1_RD_X1_nonsplit (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input wire RESET_ni;
+    input wire WEN_A1_i, WEN_B1_i;
+    input wire REN_A1_i, REN_B1_i;
+    input wire WEN_A2_i, WEN_B2_i;
+    input wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_BRAM_WR_X1_RD_X2_nonsplit (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_BRAM_WR_X1_RD_X4_nonsplit (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_BRAM_WR_X1_RD_X9_nonsplit (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_BRAM_WR_X1_RD_X18_nonsplit (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_BRAM_WR_X1_RD_X36_nonsplit (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+// ============================================================================
+// TDP36K write width 2 functional modes
+
+module TDP36K_BRAM_WR_X2_RD_X1_nonsplit (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_BRAM_WR_X2_RD_X2_nonsplit (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_BRAM_WR_X2_RD_X4_nonsplit (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_BRAM_WR_X2_RD_X9_nonsplit (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_BRAM_WR_X2_RD_X18_nonsplit (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify  
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_BRAM_WR_X2_RD_X36_nonsplit (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+// ============================================================================
+// TDP36K write width 4 functional modes
+
+module TDP36K_BRAM_WR_X4_RD_X1_nonsplit (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_BRAM_WR_X4_RD_X2_nonsplit (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_BRAM_WR_X4_RD_X4_nonsplit (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_BRAM_WR_X4_RD_X9_nonsplit (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_BRAM_WR_X4_RD_X18_nonsplit (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_BRAM_WR_X4_RD_X36_nonsplit (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+// ============================================================================
+// TDP36K write width 9 functional modes
+
+module TDP36K_BRAM_WR_X9_RD_X1_nonsplit (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_BRAM_WR_X9_RD_X2_nonsplit (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_BRAM_WR_X9_RD_X4_nonsplit (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_BRAM_WR_X9_RD_X9_nonsplit (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_BRAM_WR_X9_RD_X18_nonsplit (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_BRAM_WR_X9_RD_X36_nonsplit (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+// ============================================================================
+// TDP36K write width 18 functional modes
+
+module TDP36K_BRAM_WR_X18_RD_X1_nonsplit (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_BRAM_WR_X18_RD_X2_nonsplit (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_BRAM_WR_X18_RD_X4_nonsplit (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_BRAM_WR_X18_RD_X9_nonsplit (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_BRAM_WR_X18_RD_X18_nonsplit (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_BRAM_WR_X18_RD_X36_nonsplit (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+// ============================================================================
+// TDP36K write width 36 functional modes
+
+module TDP36K_BRAM_WR_X36_RD_X1_nonsplit (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_BRAM_WR_X36_RD_X2_nonsplit (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_BRAM_WR_X36_RD_X4_nonsplit (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_BRAM_WR_X36_RD_X9_nonsplit (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+	
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_BRAM_WR_X36_RD_X18_nonsplit (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_BRAM_WR_X36_RD_X36_nonsplit (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+// ============================================================================
+// TDP36K (split mode) write width 1 functional modes
+
+module TDP36K_BRAM_WR_X1_RD_X1_split (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_BRAM_WR_X1_RD_X2_split (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_BRAM_WR_X1_RD_X4_split (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_BRAM_WR_X1_RD_X9_split (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_BRAM_WR_X1_RD_X18_split (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+// ============================================================================
+// TDP36K (split mode) write width 2 functional modes
+
+module TDP36K_BRAM_WR_X2_RD_X1_split (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_BRAM_WR_X2_RD_X2_split (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_BRAM_WR_X2_RD_X4_split (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_BRAM_WR_X2_RD_X9_split (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_BRAM_WR_X2_RD_X18_split (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+// ============================================================================
+// TDP36K (split mode) write width 4 functional modes
+
+module TDP36K_BRAM_WR_X4_RD_X1_split (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_BRAM_WR_X4_RD_X2_split (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_BRAM_WR_X4_RD_X4_split (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_BRAM_WR_X4_RD_X9_split (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_BRAM_WR_X4_RD_X18_split (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+// ============================================================================
+// TDP36K (split mode) write width 9 functional modes
+
+module TDP36K_BRAM_WR_X9_RD_X1_split (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_BRAM_WR_X9_RD_X2_split (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_BRAM_WR_X9_RD_X4_split (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_BRAM_WR_X9_RD_X9_split (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_BRAM_WR_X9_RD_X18_split (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+// ============================================================================
+// TDP36K (split mode) write width 18 functional modes
+
+module TDP36K_BRAM_WR_X18_RD_X1_split (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_BRAM_WR_X18_RD_X2_split (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_BRAM_WR_X18_RD_X4_split (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_BRAM_WR_X18_RD_X9_split (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_BRAM_WR_X18_RD_X18_split (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input  wire RESET_ni;
+    input  wire WEN_A1_i, WEN_B1_i;
+    input  wire REN_A1_i, REN_B1_i;
+    input  wire WEN_A2_i, WEN_B2_i;
+    input  wire REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input  wire CLK_A1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B1_i;
+    (* clkbuf_sink *)
+    input  wire CLK_A2_i;
+    (* clkbuf_sink *)
+    input  wire CLK_B2_i;
+
+    input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+    input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input  wire FLUSH1_i;
+
+    input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+    input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input  wire FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+//=================================================================================
+
+module SFIFO_18K_BLK (
+    DIN,
+    PUSH,
+    POP,
+    CLK,
+    Async_Flush,
+    Overrun_Error,
+    Full_Watermark,
+    Almost_Full,
+    Full,
+    Underrun_Error,
+    Empty_Watermark,
+    Almost_Empty,
+    Empty,
+    DOUT
+);
+  
+  parameter WR_DATA_WIDTH = 18;
+  parameter RD_DATA_WIDTH = 18;
+  parameter UPAE_DBITS = 11'd10;
+  parameter UPAF_DBITS = 11'd10;
+
+  input wire CLK;
+  input wire PUSH, POP;
+  input wire [WR_DATA_WIDTH-1:0] DIN;
+  input wire Async_Flush;
+  output wire [RD_DATA_WIDTH-1:0] DOUT;
+  output wire Almost_Full, Almost_Empty;
+  output wire Full, Empty;
+  output wire Full_Watermark, Empty_Watermark;
+  output wire Overrun_Error, Underrun_Error;
+ 
+ 	BRAM2x18_SFIFO  #(
+      .WR_DATA_WIDTH(WR_DATA_WIDTH), 
+      .RD_DATA_WIDTH(RD_DATA_WIDTH),
+      .UPAE_DBITS1(UPAE_DBITS),
+      .UPAF_DBITS1(UPAF_DBITS),
+      .UPAE_DBITS2(),
+      .UPAF_DBITS2()     
+       ) U1
+      (
+      .DIN1(DIN),
+      .PUSH1(PUSH),
+      .POP1(POP),
+      .CLK1(CLK),
+      .Async_Flush1(Async_Flush),
+      .Overrun_Error1(Overrun_Error),
+      .Full_Watermark1(Full_Watermark),
+      .Almost_Full1(Almost_Full),
+      .Full1(Full),
+      .Underrun_Error1(Underrun_Error),
+      .Empty_Watermark1(Empty_Watermark),
+      .Almost_Empty1(Almost_Empty),
+      .Empty1(Empty),
+      .DOUT1(DOUT),
+      
+      .DIN2(),
+      .PUSH2(),
+      .POP2(),
+      .CLK2(),
+      .Async_Flush2(),
+      .Overrun_Error2(),
+      .Full_Watermark2(),
+      .Almost_Full2(),
+      .Full2(),
+      .Underrun_Error2(),
+      .Empty_Watermark2(),
+      .Almost_Empty2(),
+      .Empty2(),
+      .DOUT2()
+	);
+
+endmodule
+
+module AFIFO_18K_BLK (
+    DIN,
+    PUSH,
+    POP,
+    Push_Clk,
+    Pop_Clk,
+    Async_Flush,
+    Overrun_Error,
+    Full_Watermark,
+    Almost_Full,
+    Full,
+    Underrun_Error,
+    Empty_Watermark,
+    Almost_Empty,
+    Empty,
+    DOUT
+);
+  
+  parameter WR_DATA_WIDTH = 18;
+  parameter RD_DATA_WIDTH = 18;
+  parameter UPAE_DBITS = 11'd10;
+  parameter UPAF_DBITS = 11'd10;
+
+  input wire Push_Clk, Pop_Clk;
+  input wire PUSH, POP;
+  input wire [WR_DATA_WIDTH-1:0] DIN;
+  input wire Async_Flush;
+  output wire [RD_DATA_WIDTH-1:0] DOUT;
+  output wire Almost_Full, Almost_Empty;
+  output wire Full, Empty;
+  output wire Full_Watermark, Empty_Watermark;
+  output wire Overrun_Error, Underrun_Error;
+ 
+ 	BRAM2x18_AFIFO  #(
+      .WR_DATA_WIDTH(WR_DATA_WIDTH), 
+      .RD_DATA_WIDTH(RD_DATA_WIDTH),
+      .UPAE_DBITS1(UPAE_DBITS),
+      .UPAF_DBITS1(UPAF_DBITS),
+      .UPAE_DBITS2(),
+      .UPAF_DBITS2()       
+       ) U1
+      (
+      .DIN1(DIN),
+      .PUSH1(PUSH),
+      .POP1(POP),
+      .Push_Clk1(Push_Clk),
+      .Pop_Clk1(Pop_Clk),
+      .Async_Flush1(Async_Flush),
+      .Overrun_Error1(Overrun_Error),
+      .Full_Watermark1(Full_Watermark),
+      .Almost_Full1(Almost_Full),
+      .Full1(Full),
+      .Underrun_Error1(Underrun_Error),
+      .Empty_Watermark1(Empty_Watermark),
+      .Almost_Empty1(Almost_Empty),
+      .Empty1(Empty),
+      .DOUT1(DOUT),
+      
+      .DIN2(),
+      .PUSH2(),
+      .POP2(),
+      .Push_Clk2(),
+      .Pop_Clk2(),
+      .Async_Flush2(),
+      .Overrun_Error2(),
+      .Full_Watermark2(),
+      .Almost_Full2(),
+      .Full2(),
+      .Underrun_Error2(),
+      .Empty_Watermark2(),
+      .Almost_Empty2(),
+      .Empty2(),
+      .DOUT2()
+	);
+
+endmodule
+
+module BRAM2x18_SFIFO (
+    DIN1,
+    PUSH1,
+    POP1,
+    CLK1,
+    Async_Flush1,
+    Overrun_Error1,
+    Full_Watermark1,
+    Almost_Full1,
+    Full1,
+    Underrun_Error1,
+    Empty_Watermark1,
+    Almost_Empty1,
+    Empty1,
+    DOUT1,
+    
+    DIN2,
+    PUSH2,
+    POP2,
+    CLK2,
+    Async_Flush2,
+    Overrun_Error2,
+    Full_Watermark2,
+    Almost_Full2,
+    Full2,
+    Underrun_Error2,
+    Empty_Watermark2,
+    Almost_Empty2,
+    Empty2,
+    DOUT2
+);
+
+  parameter WR_DATA_WIDTH = 18;
+  parameter RD_DATA_WIDTH = 18;
+
+  
+  parameter UPAE_DBITS1 = 11'd10;
+  parameter UPAF_DBITS1 = 11'd10;
+  
+  parameter UPAE_DBITS2 = 11'd10;
+  parameter UPAF_DBITS2 = 11'd10;
+  
+  localparam MODE_36 = 3'b011; // 36- or 32-bit
+  localparam MODE_18 = 3'b010; // 18- or 16-bit
+  localparam MODE_9 = 3'b001; // 9- or 8-bit
+  localparam MODE_4 = 3'b100; // 4-bit
+  localparam MODE_2 = 3'b110; // 2-bit
+  localparam MODE_1 = 3'b101; // 1-bit
+
+  input wire CLK1;
+  input wire PUSH1, POP1;
+  input wire [WR_DATA_WIDTH-1:0] DIN1;
+  input wire Async_Flush1;
+  output wire [RD_DATA_WIDTH-1:0] DOUT1;
+  output wire Almost_Full1, Almost_Empty1;
+  output wire Full1, Empty1;
+  output wire Full_Watermark1, Empty_Watermark1;
+  output wire Overrun_Error1, Underrun_Error1;
+  
+  input wire CLK2;
+  input wire PUSH2, POP2;
+  input wire [WR_DATA_WIDTH-1:0] DIN2;
+  input wire Async_Flush2;
+  output wire [RD_DATA_WIDTH-1:0] DOUT2;
+  output wire Almost_Full2, Almost_Empty2;
+  output wire Full2, Empty2;
+  output wire Full_Watermark2, Empty_Watermark2;
+  output wire Overrun_Error2, Underrun_Error2;
+  
+  wire [17:0] in_reg1;
+  wire [17:0] out_reg1;
+  wire [17:0] fifo1_flags;
+  
+  wire [17:0] in_reg2;
+  wire [17:0] out_reg2;
+  wire [17:0] fifo2_flags;
+  
+  wire Push_Clk1, Pop_Clk1;
+  wire Push_Clk2, Pop_Clk2;
+  assign Push_Clk1 = CLK1;
+  assign Pop_Clk1 = CLK1;
+  assign Push_Clk2 = CLK2;
+  assign Pop_Clk2 = CLK2;
+  
+  assign Overrun_Error1 = fifo1_flags[0];
+  assign Full_Watermark1 = fifo1_flags[1];
+  assign Almost_Full1 = fifo1_flags[2];
+  assign Full1 = fifo1_flags[3];
+  assign Underrun_Error1 = fifo1_flags[4];
+  assign Empty_Watermark1 = fifo1_flags[5];
+  assign Almost_Empty1 = fifo1_flags[6];
+  assign Empty1 = fifo1_flags[7];
+  
+  assign Overrun_Error2 = fifo2_flags[0];
+  assign Full_Watermark2 = fifo2_flags[1];
+  assign Almost_Full2 = fifo2_flags[2];
+  assign Full2 = fifo2_flags[3];
+  assign Underrun_Error2 = fifo2_flags[4];
+  assign Empty_Watermark2 = fifo2_flags[5];
+  assign Almost_Empty2 = fifo2_flags[6];
+  assign Empty2 = fifo2_flags[7];
+  
+  generate
+    if (WR_DATA_WIDTH == 18) begin
+      assign in_reg1[17:0] = DIN1[17:0];
+      assign in_reg2[17:0] = DIN2[17:0];
+    end else if (WR_DATA_WIDTH == 9) begin
+      assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]};
+      assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]};
+    end else begin
+      assign in_reg1[17:WR_DATA_WIDTH]  = 0;
+      assign in_reg1[WR_DATA_WIDTH-1:0] = DIN1[WR_DATA_WIDTH-1:0];
+      assign in_reg2[17:WR_DATA_WIDTH]  = 0;
+      assign in_reg2[WR_DATA_WIDTH-1:0] = DIN2[WR_DATA_WIDTH-1:0];
+    end
+  endgenerate     
+  
+ case (RD_DATA_WIDTH)
+	8, 9: begin
+		case (WR_DATA_WIDTH)
+			8, 9: begin
+				defparam U1.MODE_BITS = { 1'b1,
+					UPAF_DBITS2, UPAE_DBITS2, 4'h1, MODE_9, MODE_9, MODE_9, MODE_9, 1'b1,
+					1'b0, UPAF_DBITS1, 1'b0, UPAE_DBITS1, 4'h1, MODE_9, MODE_9, MODE_9, MODE_9, 1'b1
+				};
+        (* is_fifo = 1 *) 
+        (* sync_fifo = 1 *) 
+        (* is_split = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *) 
+        TDP36K U1 (
+          .RESET_ni(1'b1),
+          .WDATA_A1_i(in_reg1[17:0]),
+          .WDATA_A2_i(in_reg2[17:0]),
+          .RDATA_A1_o(fifo1_flags),
+          .RDATA_A2_o(fifo2_flags),
+          .ADDR_A1_i(14'h0),
+          .ADDR_A2_i(14'h0),
+          .CLK_A1_i(Push_Clk1),
+          .CLK_A2_i(Push_Clk2),
+          .REN_A1_i(1'b1),
+          .REN_A2_i(1'b1),
+          .WEN_A1_i(PUSH1),
+          .WEN_A2_i(PUSH2),
+          .BE_A1_i(2'b11),
+          .BE_A2_i(2'b11),
+      
+          .WDATA_B1_i(18'h0),
+          .WDATA_B2_i(18'h0),
+          .RDATA_B1_o(out_reg1[17:0]),
+          .RDATA_B2_o(out_reg2[17:0]),
+          .ADDR_B1_i(14'h0),
+          .ADDR_B2_i(14'h0),
+          .CLK_B1_i(Pop_Clk1),
+          .CLK_B2_i(Pop_Clk2),
+          .REN_B1_i(POP1),
+          .REN_B2_i(POP2),
+          .WEN_B1_i(1'b0),
+          .WEN_B2_i(1'b0),
+          .BE_B1_i(2'b11),
+          .BE_B2_i(2'b11),
+      
+          .FLUSH1_i(Async_Flush1),
+          .FLUSH2_i(Async_Flush2)
+        );        
+			end
+			16, 18: begin
+				defparam U1.MODE_BITS = { 1'b1,
+					UPAF_DBITS2, UPAE_DBITS2, 4'h1, MODE_9, MODE_18, MODE_9, MODE_18, 1'b1,
+					1'b0, UPAF_DBITS1, 1'b0, UPAE_DBITS1, 4'h1, MODE_9, MODE_18, MODE_9, MODE_18, 1'b1
+				};
+        (* is_fifo = 1 *) 
+        (* sync_fifo = 1 *) 
+        (* is_split = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *) 
+        TDP36K U1 (
+          .RESET_ni(1'b1),
+          .WDATA_A1_i(in_reg1[17:0]),
+          .WDATA_A2_i(in_reg2[17:0]),
+          .RDATA_A1_o(fifo1_flags),
+          .RDATA_A2_o(fifo2_flags),
+          .ADDR_A1_i(14'h0),
+          .ADDR_A2_i(14'h0),
+          .CLK_A1_i(Push_Clk1),
+          .CLK_A2_i(Push_Clk2),
+          .REN_A1_i(1'b1),
+          .REN_A2_i(1'b1),
+          .WEN_A1_i(PUSH1),
+          .WEN_A2_i(PUSH2),
+          .BE_A1_i(2'b11),
+          .BE_A2_i(2'b11),
+      
+          .WDATA_B1_i(18'h0),
+          .WDATA_B2_i(18'h0),
+          .RDATA_B1_o(out_reg1[17:0]),
+          .RDATA_B2_o(out_reg2[17:0]),
+          .ADDR_B1_i(14'h0),
+          .ADDR_B2_i(14'h0),
+          .CLK_B1_i(Pop_Clk1),
+          .CLK_B2_i(Pop_Clk2),
+          .REN_B1_i(POP1),
+          .REN_B2_i(POP2),
+          .WEN_B1_i(1'b0),
+          .WEN_B2_i(1'b0),
+          .BE_B1_i(2'b11),
+          .BE_B2_i(2'b11),
+      
+          .FLUSH1_i(Async_Flush1),
+          .FLUSH2_i(Async_Flush2)
+        );        
+			end
+			default: begin
+				defparam U1.MODE_BITS = { 1'b1,
+					UPAF_DBITS2, UPAE_DBITS2, 4'h1, MODE_9, MODE_9, MODE_9, MODE_9, 1'b1,
+					1'b0, UPAF_DBITS1, 1'b0, UPAE_DBITS1, 4'h1, MODE_9, MODE_9, MODE_9, MODE_9, 1'b1
+				};
+        (* is_fifo = 1 *) 
+        (* sync_fifo = 1 *) 
+        (* is_split = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *) 
+        TDP36K U1 (
+          .RESET_ni(1'b1),
+          .WDATA_A1_i(in_reg1[17:0]),
+          .WDATA_A2_i(in_reg2[17:0]),
+          .RDATA_A1_o(fifo1_flags),
+          .RDATA_A2_o(fifo2_flags),
+          .ADDR_A1_i(14'h0),
+          .ADDR_A2_i(14'h0),
+          .CLK_A1_i(Push_Clk1),
+          .CLK_A2_i(Push_Clk2),
+          .REN_A1_i(1'b1),
+          .REN_A2_i(1'b1),
+          .WEN_A1_i(PUSH1),
+          .WEN_A2_i(PUSH2),
+          .BE_A1_i(2'b11),
+          .BE_A2_i(2'b11),
+      
+          .WDATA_B1_i(18'h0),
+          .WDATA_B2_i(18'h0),
+          .RDATA_B1_o(out_reg1[17:0]),
+          .RDATA_B2_o(out_reg2[17:0]),
+          .ADDR_B1_i(14'h0),
+          .ADDR_B2_i(14'h0),
+          .CLK_B1_i(Pop_Clk1),
+          .CLK_B2_i(Pop_Clk2),
+          .REN_B1_i(POP1),
+          .REN_B2_i(POP2),
+          .WEN_B1_i(1'b0),
+          .WEN_B2_i(1'b0),
+          .BE_B1_i(2'b11),
+          .BE_B2_i(2'b11),
+      
+          .FLUSH1_i(Async_Flush1),
+          .FLUSH2_i(Async_Flush2)
+        );        
+			end
+		endcase
+	end
+	16, 18: begin
+		case (WR_DATA_WIDTH)
+			8, 9: begin
+				defparam U1.MODE_BITS = { 1'b1,
+					UPAF_DBITS2, UPAE_DBITS2, 4'h1, MODE_18, MODE_9, MODE_18, MODE_9, 1'b1,
+					1'b0, UPAF_DBITS1, 1'b0, UPAE_DBITS1, 4'h1, MODE_18, MODE_9, MODE_18, MODE_9, 1'b1
+				};
+        (* is_fifo = 1 *) 
+        (* sync_fifo = 1 *) 
+        (* is_split = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *) 
+        TDP36K U1 (
+          .RESET_ni(1'b1),
+          .WDATA_A1_i(in_reg1[17:0]),
+          .WDATA_A2_i(in_reg2[17:0]),
+          .RDATA_A1_o(fifo1_flags),
+          .RDATA_A2_o(fifo2_flags),
+          .ADDR_A1_i(14'h0),
+          .ADDR_A2_i(14'h0),
+          .CLK_A1_i(Push_Clk1),
+          .CLK_A2_i(Push_Clk2),
+          .REN_A1_i(1'b1),
+          .REN_A2_i(1'b1),
+          .WEN_A1_i(PUSH1),
+          .WEN_A2_i(PUSH2),
+          .BE_A1_i(2'b11),
+          .BE_A2_i(2'b11),
+      
+          .WDATA_B1_i(18'h0),
+          .WDATA_B2_i(18'h0),
+          .RDATA_B1_o(out_reg1[17:0]),
+          .RDATA_B2_o(out_reg2[17:0]),
+          .ADDR_B1_i(14'h0),
+          .ADDR_B2_i(14'h0),
+          .CLK_B1_i(Pop_Clk1),
+          .CLK_B2_i(Pop_Clk2),
+          .REN_B1_i(POP1),
+          .REN_B2_i(POP2),
+          .WEN_B1_i(1'b0),
+          .WEN_B2_i(1'b0),
+          .BE_B1_i(2'b11),
+          .BE_B2_i(2'b11),
+      
+          .FLUSH1_i(Async_Flush1),
+          .FLUSH2_i(Async_Flush2)
+        );        
+			end
+			16, 18: begin
+				defparam U1.MODE_BITS = { 1'b1,
+					UPAF_DBITS2, UPAE_DBITS2, 4'h1, MODE_18, MODE_18, MODE_18, MODE_18, 1'b1,
+					1'b0, UPAF_DBITS1, 1'b0, UPAE_DBITS1, 4'h1, MODE_18, MODE_18, MODE_18, MODE_18, 1'b1
+				};
+        (* is_fifo = 1 *) 
+        (* sync_fifo = 1 *) 
+        (* is_split = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *) 
+        TDP36K U1 (
+          .RESET_ni(1'b1),
+          .WDATA_A1_i(in_reg1[17:0]),
+          .WDATA_A2_i(in_reg2[17:0]),
+          .RDATA_A1_o(fifo1_flags),
+          .RDATA_A2_o(fifo2_flags),
+          .ADDR_A1_i(14'h0),
+          .ADDR_A2_i(14'h0),
+          .CLK_A1_i(Push_Clk1),
+          .CLK_A2_i(Push_Clk2),
+          .REN_A1_i(1'b1),
+          .REN_A2_i(1'b1),
+          .WEN_A1_i(PUSH1),
+          .WEN_A2_i(PUSH2),
+          .BE_A1_i(2'b11),
+          .BE_A2_i(2'b11),
+      
+          .WDATA_B1_i(18'h0),
+          .WDATA_B2_i(18'h0),
+          .RDATA_B1_o(out_reg1[17:0]),
+          .RDATA_B2_o(out_reg2[17:0]),
+          .ADDR_B1_i(14'h0),
+          .ADDR_B2_i(14'h0),
+          .CLK_B1_i(Pop_Clk1),
+          .CLK_B2_i(Pop_Clk2),
+          .REN_B1_i(POP1),
+          .REN_B2_i(POP2),
+          .WEN_B1_i(1'b0),
+          .WEN_B2_i(1'b0),
+          .BE_B1_i(2'b11),
+          .BE_B2_i(2'b11),
+      
+          .FLUSH1_i(Async_Flush1),
+          .FLUSH2_i(Async_Flush2)
+        );        
+			end
+			default: begin
+				defparam U1.MODE_BITS = { 1'b1,
+					UPAF_DBITS2, UPAE_DBITS2, 4'h1, MODE_18, MODE_18, MODE_18, MODE_18, 1'b1,
+					1'b0, UPAF_DBITS1, 1'b0, UPAE_DBITS1, 4'h1, MODE_18, MODE_18, MODE_18, MODE_18, 1'b1
+				};
+        (* is_fifo = 1 *) 
+        (* sync_fifo = 1 *) 
+        (* is_split = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *) 
+        TDP36K U1 (
+          .RESET_ni(1'b1),
+          .WDATA_A1_i(in_reg1[17:0]),
+          .WDATA_A2_i(in_reg2[17:0]),
+          .RDATA_A1_o(fifo1_flags),
+          .RDATA_A2_o(fifo2_flags),
+          .ADDR_A1_i(14'h0),
+          .ADDR_A2_i(14'h0),
+          .CLK_A1_i(Push_Clk1),
+          .CLK_A2_i(Push_Clk2),
+          .REN_A1_i(1'b1),
+          .REN_A2_i(1'b1),
+          .WEN_A1_i(PUSH1),
+          .WEN_A2_i(PUSH2),
+          .BE_A1_i(2'b11),
+          .BE_A2_i(2'b11),
+      
+          .WDATA_B1_i(18'h0),
+          .WDATA_B2_i(18'h0),
+          .RDATA_B1_o(out_reg1[17:0]),
+          .RDATA_B2_o(out_reg2[17:0]),
+          .ADDR_B1_i(14'h0),
+          .ADDR_B2_i(14'h0),
+          .CLK_B1_i(Pop_Clk1),
+          .CLK_B2_i(Pop_Clk2),
+          .REN_B1_i(POP1),
+          .REN_B2_i(POP2),
+          .WEN_B1_i(1'b0),
+          .WEN_B2_i(1'b0),
+          .BE_B1_i(2'b11),
+          .BE_B2_i(2'b11),
+      
+          .FLUSH1_i(Async_Flush1),
+          .FLUSH2_i(Async_Flush2)
+        );        
+			end
+		endcase
+	end
+	default: begin
+		case (WR_DATA_WIDTH)
+			8, 9: begin
+				defparam U1.MODE_BITS = { 1'b1,
+					UPAF_DBITS2, UPAE_DBITS2, 4'h1, MODE_9, MODE_9, MODE_9, MODE_9, 1'b1,
+					1'b0, UPAF_DBITS1, 1'b0, UPAE_DBITS1, 4'h1, MODE_9, MODE_9, MODE_9, MODE_9, 1'b1
+				};
+        (* is_fifo = 1 *) 
+        (* sync_fifo = 1 *) 
+        (* is_split = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *) 
+        TDP36K U1 (
+          .RESET_ni(1'b1),
+          .WDATA_A1_i(in_reg1[17:0]),
+          .WDATA_A2_i(in_reg2[17:0]),
+          .RDATA_A1_o(fifo1_flags),
+          .RDATA_A2_o(fifo2_flags),
+          .ADDR_A1_i(14'h0),
+          .ADDR_A2_i(14'h0),
+          .CLK_A1_i(Push_Clk1),
+          .CLK_A2_i(Push_Clk2),
+          .REN_A1_i(1'b1),
+          .REN_A2_i(1'b1),
+          .WEN_A1_i(PUSH1),
+          .WEN_A2_i(PUSH2),
+          .BE_A1_i(2'b11),
+          .BE_A2_i(2'b11),
+      
+          .WDATA_B1_i(18'h0),
+          .WDATA_B2_i(18'h0),
+          .RDATA_B1_o(out_reg1[17:0]),
+          .RDATA_B2_o(out_reg2[17:0]),
+          .ADDR_B1_i(14'h0),
+          .ADDR_B2_i(14'h0),
+          .CLK_B1_i(Pop_Clk1),
+          .CLK_B2_i(Pop_Clk2),
+          .REN_B1_i(POP1),
+          .REN_B2_i(POP2),
+          .WEN_B1_i(1'b0),
+          .WEN_B2_i(1'b0),
+          .BE_B1_i(2'b11),
+          .BE_B2_i(2'b11),
+      
+          .FLUSH1_i(Async_Flush1),
+          .FLUSH2_i(Async_Flush2)
+        );        
+			end
+			16, 18: begin
+				defparam U1.MODE_BITS = { 1'b1,
+					UPAF_DBITS2, UPAE_DBITS2, 4'h1, MODE_18, MODE_18, MODE_18, MODE_18, 1'b1,
+					1'b0, UPAF_DBITS1, 1'b0, UPAE_DBITS1, 4'h1, MODE_18, MODE_18, MODE_18, MODE_18, 1'b1
+				};
+        (* is_fifo = 1 *) 
+        (* sync_fifo = 1 *) 
+        (* is_split = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *) 
+        TDP36K U1 (
+          .RESET_ni(1'b1),
+          .WDATA_A1_i(in_reg1[17:0]),
+          .WDATA_A2_i(in_reg2[17:0]),
+          .RDATA_A1_o(fifo1_flags),
+          .RDATA_A2_o(fifo2_flags),
+          .ADDR_A1_i(14'h0),
+          .ADDR_A2_i(14'h0),
+          .CLK_A1_i(Push_Clk1),
+          .CLK_A2_i(Push_Clk2),
+          .REN_A1_i(1'b1),
+          .REN_A2_i(1'b1),
+          .WEN_A1_i(PUSH1),
+          .WEN_A2_i(PUSH2),
+          .BE_A1_i(2'b11),
+          .BE_A2_i(2'b11),
+      
+          .WDATA_B1_i(18'h0),
+          .WDATA_B2_i(18'h0),
+          .RDATA_B1_o(out_reg1[17:0]),
+          .RDATA_B2_o(out_reg2[17:0]),
+          .ADDR_B1_i(14'h0),
+          .ADDR_B2_i(14'h0),
+          .CLK_B1_i(Pop_Clk1),
+          .CLK_B2_i(Pop_Clk2),
+          .REN_B1_i(POP1),
+          .REN_B2_i(POP2),
+          .WEN_B1_i(1'b0),
+          .WEN_B2_i(1'b0),
+          .BE_B1_i(2'b11),
+          .BE_B2_i(2'b11),
+      
+          .FLUSH1_i(Async_Flush1),
+          .FLUSH2_i(Async_Flush2)
+        );        
+			end
+			default: begin
+				defparam U1.MODE_BITS = { 1'b1,
+					UPAF_DBITS2, UPAE_DBITS2, 4'h1, MODE_18, MODE_18, MODE_18, MODE_18, 1'b1,
+					1'b0, UPAF_DBITS1, 1'b0, UPAE_DBITS1, 4'h1, MODE_18, MODE_18, MODE_18, MODE_18, 1'b1
+				};
+        (* is_fifo = 1 *) 
+        (* sync_fifo = 1 *) 
+        (* is_split = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *) 
+        TDP36K U1 (
+          .RESET_ni(1'b1),
+          .WDATA_A1_i(in_reg1[17:0]),
+          .WDATA_A2_i(in_reg2[17:0]),
+          .RDATA_A1_o(fifo1_flags),
+          .RDATA_A2_o(fifo2_flags),
+          .ADDR_A1_i(14'h0),
+          .ADDR_A2_i(14'h0),
+          .CLK_A1_i(Push_Clk1),
+          .CLK_A2_i(Push_Clk2),
+          .REN_A1_i(1'b1),
+          .REN_A2_i(1'b1),
+          .WEN_A1_i(PUSH1),
+          .WEN_A2_i(PUSH2),
+          .BE_A1_i(2'b11),
+          .BE_A2_i(2'b11),
+      
+          .WDATA_B1_i(18'h0),
+          .WDATA_B2_i(18'h0),
+          .RDATA_B1_o(out_reg1[17:0]),
+          .RDATA_B2_o(out_reg2[17:0]),
+          .ADDR_B1_i(14'h0),
+          .ADDR_B2_i(14'h0),
+          .CLK_B1_i(Pop_Clk1),
+          .CLK_B2_i(Pop_Clk2),
+          .REN_B1_i(POP1),
+          .REN_B2_i(POP2),
+          .WEN_B1_i(1'b0),
+          .WEN_B2_i(1'b0),
+          .BE_B1_i(2'b11),
+          .BE_B2_i(2'b11),
+      
+          .FLUSH1_i(Async_Flush1),
+          .FLUSH2_i(Async_Flush2)
+        );
+			end
+		endcase
+	end
+  endcase
+
+  generate
+    if (RD_DATA_WIDTH == 9) begin
+      assign DOUT1[RD_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]};
+      assign DOUT2[RD_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]};
+    end else begin
+      assign DOUT1[RD_DATA_WIDTH-1:0] = out_reg1[RD_DATA_WIDTH-1:0];
+      assign DOUT2[RD_DATA_WIDTH-1:0] = out_reg2[RD_DATA_WIDTH-1:0];
+    end
+  endgenerate 
+
+endmodule
+
+module BRAM2x18_AFIFO (
+    DIN1,
+    PUSH1,
+    POP1,
+    Push_Clk1,
+    Pop_Clk1,
+    Async_Flush1,
+    Overrun_Error1,
+    Full_Watermark1,
+    Almost_Full1,
+    Full1,
+    Underrun_Error1,
+    Empty_Watermark1,
+    Almost_Empty1,
+    Empty1,
+    DOUT1,
+    
+    DIN2,
+    PUSH2,
+    POP2,
+    Push_Clk2,
+    Pop_Clk2,
+    Async_Flush2,
+    Overrun_Error2,
+    Full_Watermark2,
+    Almost_Full2,
+    Full2,
+    Underrun_Error2,
+    Empty_Watermark2,
+    Almost_Empty2,
+    Empty2,
+    DOUT2
+);
+
+  parameter WR_DATA_WIDTH = 18;
+  parameter RD_DATA_WIDTH = 18;
+
+  
+  parameter UPAE_DBITS1 = 11'd10;
+  parameter UPAF_DBITS1 = 11'd10;
+  
+  parameter UPAE_DBITS2 = 11'd10;
+  parameter UPAF_DBITS2 = 11'd10;
+  
+  localparam MODE_36 = 3'b011; // 36- or 32-bit
+  localparam MODE_18 = 3'b010; // 18- or 16-bit
+  localparam MODE_9 = 3'b001; // 9- or 8-bit
+  localparam MODE_4 = 3'b100; // 4-bit
+  localparam MODE_2 = 3'b110; // 2-bit
+  localparam MODE_1 = 3'b101; // 1-bit
+
+  input wire Push_Clk1, Pop_Clk1;
+  input wire PUSH1, POP1;
+  input wire [WR_DATA_WIDTH-1:0] DIN1;
+  input wire Async_Flush1;
+  output wire [RD_DATA_WIDTH-1:0] DOUT1;
+  output wire Almost_Full1, Almost_Empty1;
+  output wire Full1, Empty1;
+  output wire Full_Watermark1, Empty_Watermark1;
+  output wire Overrun_Error1, Underrun_Error1;
+  
+  input wire Push_Clk2, Pop_Clk2;
+  input wire PUSH2, POP2;
+  input wire [WR_DATA_WIDTH-1:0] DIN2;
+  input wire Async_Flush2;
+  output wire [RD_DATA_WIDTH-1:0] DOUT2;
+  output wire Almost_Full2, Almost_Empty2;
+  output wire Full2, Empty2;
+  output wire Full_Watermark2, Empty_Watermark2;
+  output wire Overrun_Error2, Underrun_Error2;
+  
+  wire [17:0] in_reg1;
+  wire [17:0] out_reg1;
+  wire [17:0] fifo1_flags;
+  
+  wire [17:0] in_reg2;
+  wire [17:0] out_reg2;
+  wire [17:0] fifo2_flags;
+  
+  assign Overrun_Error1 = fifo1_flags[0];
+  assign Full_Watermark1 = fifo1_flags[1];
+  assign Almost_Full1 = fifo1_flags[2];
+  assign Full1 = fifo1_flags[3];
+  assign Underrun_Error1 = fifo1_flags[4];
+  assign Empty_Watermark1 = fifo1_flags[5];
+  assign Almost_Empty1 = fifo1_flags[6];
+  assign Empty1 = fifo1_flags[7];
+  
+  assign Overrun_Error2 = fifo2_flags[0];
+  assign Full_Watermark2 = fifo2_flags[1];
+  assign Almost_Full2 = fifo2_flags[2];
+  assign Full2 = fifo2_flags[3];
+  assign Underrun_Error2 = fifo2_flags[4];
+  assign Empty_Watermark2 = fifo2_flags[5];
+  assign Almost_Empty2 = fifo2_flags[6];
+  assign Empty2 = fifo2_flags[7];
+  
+  generate
+    if (WR_DATA_WIDTH == 18) begin
+      assign in_reg1[17:0] = DIN1[17:0];
+      assign in_reg2[17:0] = DIN2[17:0];
+    end else if (WR_DATA_WIDTH == 9) begin
+      assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]};
+      assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]};
+    end else begin
+      assign in_reg1[17:WR_DATA_WIDTH]  = 0;
+      assign in_reg1[WR_DATA_WIDTH-1:0] = DIN1[WR_DATA_WIDTH-1:0];
+      assign in_reg2[17:WR_DATA_WIDTH]  = 0;
+      assign in_reg2[WR_DATA_WIDTH-1:0] = DIN2[WR_DATA_WIDTH-1:0];
+    end
+  endgenerate   
+  
+ case (RD_DATA_WIDTH)
+	8, 9: begin
+		case (WR_DATA_WIDTH)
+			8, 9: begin
+				defparam U1.MODE_BITS = { 1'b1,
+					UPAF_DBITS2, UPAE_DBITS2, 4'h1, MODE_9, MODE_9, MODE_9, MODE_9, 1'b0,
+					1'b0, UPAF_DBITS1, 1'b0, UPAE_DBITS1, 4'h1, MODE_9, MODE_9, MODE_9, MODE_9, 1'b0
+				};
+        (* is_fifo = 1 *) 
+        (* sync_fifo = 0 *) 
+        (* is_split = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *) 
+        TDP36K U1 (
+          .RESET_ni(1'b1),
+          .WDATA_A1_i(in_reg1[17:0]),
+          .WDATA_A2_i(in_reg2[17:0]),
+          .RDATA_A1_o(fifo1_flags),
+          .RDATA_A2_o(fifo2_flags),
+          .ADDR_A1_i(14'h0),
+          .ADDR_A2_i(14'h0),
+          .CLK_A1_i(Push_Clk1),
+          .CLK_A2_i(Push_Clk2),
+          .REN_A1_i(1'b1),
+          .REN_A2_i(1'b1),
+          .WEN_A1_i(PUSH1),
+          .WEN_A2_i(PUSH2),
+          .BE_A1_i(2'b11),
+          .BE_A2_i(2'b11),
+      
+          .WDATA_B1_i(18'h0),
+          .WDATA_B2_i(18'h0),
+          .RDATA_B1_o(out_reg1[17:0]),
+          .RDATA_B2_o(out_reg2[17:0]),
+          .ADDR_B1_i(14'h0),
+          .ADDR_B2_i(14'h0),
+          .CLK_B1_i(Pop_Clk1),
+          .CLK_B2_i(Pop_Clk2),
+          .REN_B1_i(POP1),
+          .REN_B2_i(POP2),
+          .WEN_B1_i(1'b0),
+          .WEN_B2_i(1'b0),
+          .BE_B1_i(2'b11),
+          .BE_B2_i(2'b11),
+      
+          .FLUSH1_i(Async_Flush1),
+          .FLUSH2_i(Async_Flush2)
+        );        
+			end
+			16, 18: begin
+				defparam U1.MODE_BITS = { 1'b1,
+					UPAF_DBITS2, UPAE_DBITS2, 4'h1, MODE_9, MODE_18, MODE_9, MODE_18, 1'b0,
+					1'b0, UPAF_DBITS1, 1'b0, UPAE_DBITS1, 4'h1, MODE_9, MODE_18, MODE_9, MODE_18, 1'b0
+				};
+        (* is_fifo = 1 *) 
+        (* sync_fifo = 0 *) 
+        (* is_split = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *) 
+        TDP36K U1 (
+          .RESET_ni(1'b1),
+          .WDATA_A1_i(in_reg1[17:0]),
+          .WDATA_A2_i(in_reg2[17:0]),
+          .RDATA_A1_o(fifo1_flags),
+          .RDATA_A2_o(fifo2_flags),
+          .ADDR_A1_i(14'h0),
+          .ADDR_A2_i(14'h0),
+          .CLK_A1_i(Push_Clk1),
+          .CLK_A2_i(Push_Clk2),
+          .REN_A1_i(1'b1),
+          .REN_A2_i(1'b1),
+          .WEN_A1_i(PUSH1),
+          .WEN_A2_i(PUSH2),
+          .BE_A1_i(2'b11),
+          .BE_A2_i(2'b11),
+      
+          .WDATA_B1_i(18'h0),
+          .WDATA_B2_i(18'h0),
+          .RDATA_B1_o(out_reg1[17:0]),
+          .RDATA_B2_o(out_reg2[17:0]),
+          .ADDR_B1_i(14'h0),
+          .ADDR_B2_i(14'h0),
+          .CLK_B1_i(Pop_Clk1),
+          .CLK_B2_i(Pop_Clk2),
+          .REN_B1_i(POP1),
+          .REN_B2_i(POP2),
+          .WEN_B1_i(1'b0),
+          .WEN_B2_i(1'b0),
+          .BE_B1_i(2'b11),
+          .BE_B2_i(2'b11),
+      
+          .FLUSH1_i(Async_Flush1),
+          .FLUSH2_i(Async_Flush2)
+        );        
+			end
+			default: begin
+				defparam U1.MODE_BITS = { 1'b1,
+					UPAF_DBITS2, UPAE_DBITS2, 4'h1, MODE_9, MODE_9, MODE_9, MODE_9, 1'b0,
+					1'b0, UPAF_DBITS1, 1'b0, UPAE_DBITS1, 4'h1, MODE_9, MODE_9, MODE_9, MODE_9, 1'b0
+				};
+        (* is_fifo = 1 *) 
+        (* sync_fifo = 0 *) 
+        (* is_split = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *) 
+        TDP36K U1 (
+          .RESET_ni(1'b1),
+          .WDATA_A1_i(in_reg1[17:0]),
+          .WDATA_A2_i(in_reg2[17:0]),
+          .RDATA_A1_o(fifo1_flags),
+          .RDATA_A2_o(fifo2_flags),
+          .ADDR_A1_i(14'h0),
+          .ADDR_A2_i(14'h0),
+          .CLK_A1_i(Push_Clk1),
+          .CLK_A2_i(Push_Clk2),
+          .REN_A1_i(1'b1),
+          .REN_A2_i(1'b1),
+          .WEN_A1_i(PUSH1),
+          .WEN_A2_i(PUSH2),
+          .BE_A1_i(2'b11),
+          .BE_A2_i(2'b11),
+      
+          .WDATA_B1_i(18'h0),
+          .WDATA_B2_i(18'h0),
+          .RDATA_B1_o(out_reg1[17:0]),
+          .RDATA_B2_o(out_reg2[17:0]),
+          .ADDR_B1_i(14'h0),
+          .ADDR_B2_i(14'h0),
+          .CLK_B1_i(Pop_Clk1),
+          .CLK_B2_i(Pop_Clk2),
+          .REN_B1_i(POP1),
+          .REN_B2_i(POP2),
+          .WEN_B1_i(1'b0),
+          .WEN_B2_i(1'b0),
+          .BE_B1_i(2'b11),
+          .BE_B2_i(2'b11),
+      
+          .FLUSH1_i(Async_Flush1),
+          .FLUSH2_i(Async_Flush2)
+        );        
+			end
+		endcase
+	end
+	16, 18: begin
+		case (WR_DATA_WIDTH)
+			8, 9: begin
+				defparam U1.MODE_BITS = { 1'b1,
+					UPAF_DBITS2, UPAE_DBITS2, 4'h1, MODE_18, MODE_9, MODE_18, MODE_9, 1'b0,
+					1'b0, UPAF_DBITS1, 1'b0, UPAE_DBITS1, 4'h1, MODE_18, MODE_9, MODE_18, MODE_9, 1'b0
+				};
+        (* is_fifo = 1 *) 
+        (* sync_fifo = 0 *) 
+        (* is_split = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *) 
+        TDP36K U1 (
+          .RESET_ni(1'b1),
+          .WDATA_A1_i(in_reg1[17:0]),
+          .WDATA_A2_i(in_reg2[17:0]),
+          .RDATA_A1_o(fifo1_flags),
+          .RDATA_A2_o(fifo2_flags),
+          .ADDR_A1_i(14'h0),
+          .ADDR_A2_i(14'h0),
+          .CLK_A1_i(Push_Clk1),
+          .CLK_A2_i(Push_Clk2),
+          .REN_A1_i(1'b1),
+          .REN_A2_i(1'b1),
+          .WEN_A1_i(PUSH1),
+          .WEN_A2_i(PUSH2),
+          .BE_A1_i(2'b11),
+          .BE_A2_i(2'b11),
+      
+          .WDATA_B1_i(18'h0),
+          .WDATA_B2_i(18'h0),
+          .RDATA_B1_o(out_reg1[17:0]),
+          .RDATA_B2_o(out_reg2[17:0]),
+          .ADDR_B1_i(14'h0),
+          .ADDR_B2_i(14'h0),
+          .CLK_B1_i(Pop_Clk1),
+          .CLK_B2_i(Pop_Clk2),
+          .REN_B1_i(POP1),
+          .REN_B2_i(POP2),
+          .WEN_B1_i(1'b0),
+          .WEN_B2_i(1'b0),
+          .BE_B1_i(2'b11),
+          .BE_B2_i(2'b11),
+      
+          .FLUSH1_i(Async_Flush1),
+          .FLUSH2_i(Async_Flush2)
+        );        
+			end
+			16, 18: begin
+				defparam U1.MODE_BITS = { 1'b1,
+					UPAF_DBITS2, UPAE_DBITS2, 4'h1, MODE_18, MODE_18, MODE_18, MODE_18, 1'b0,
+					1'b0, UPAF_DBITS1, 1'b0, UPAE_DBITS1, 4'h1, MODE_18, MODE_18, MODE_18, MODE_18, 1'b0
+				};
+        (* is_fifo = 1 *) 
+        (* sync_fifo = 0 *) 
+        (* is_split = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *) 
+        TDP36K U1 (
+          .RESET_ni(1'b1),
+          .WDATA_A1_i(in_reg1[17:0]),
+          .WDATA_A2_i(in_reg2[17:0]),
+          .RDATA_A1_o(fifo1_flags),
+          .RDATA_A2_o(fifo2_flags),
+          .ADDR_A1_i(14'h0),
+          .ADDR_A2_i(14'h0),
+          .CLK_A1_i(Push_Clk1),
+          .CLK_A2_i(Push_Clk2),
+          .REN_A1_i(1'b1),
+          .REN_A2_i(1'b1),
+          .WEN_A1_i(PUSH1),
+          .WEN_A2_i(PUSH2),
+          .BE_A1_i(2'b11),
+          .BE_A2_i(2'b11),
+      
+          .WDATA_B1_i(18'h0),
+          .WDATA_B2_i(18'h0),
+          .RDATA_B1_o(out_reg1[17:0]),
+          .RDATA_B2_o(out_reg2[17:0]),
+          .ADDR_B1_i(14'h0),
+          .ADDR_B2_i(14'h0),
+          .CLK_B1_i(Pop_Clk1),
+          .CLK_B2_i(Pop_Clk2),
+          .REN_B1_i(POP1),
+          .REN_B2_i(POP2),
+          .WEN_B1_i(1'b0),
+          .WEN_B2_i(1'b0),
+          .BE_B1_i(2'b11),
+          .BE_B2_i(2'b11),
+      
+          .FLUSH1_i(Async_Flush1),
+          .FLUSH2_i(Async_Flush2)
+        );        
+			end
+			default: begin
+				defparam U1.MODE_BITS = { 1'b1,
+					UPAF_DBITS2, UPAE_DBITS2, 4'h1, MODE_18, MODE_18, MODE_18, MODE_18, 1'b0,
+					1'b0, UPAF_DBITS1, 1'b0, UPAE_DBITS1, 4'h1, MODE_18, MODE_18, MODE_18, MODE_18, 1'b0
+				};
+        (* is_fifo = 1 *) 
+        (* sync_fifo = 0 *) 
+        (* is_split = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *) 
+        TDP36K U1 (
+          .RESET_ni(1'b1),
+          .WDATA_A1_i(in_reg1[17:0]),
+          .WDATA_A2_i(in_reg2[17:0]),
+          .RDATA_A1_o(fifo1_flags),
+          .RDATA_A2_o(fifo2_flags),
+          .ADDR_A1_i(14'h0),
+          .ADDR_A2_i(14'h0),
+          .CLK_A1_i(Push_Clk1),
+          .CLK_A2_i(Push_Clk2),
+          .REN_A1_i(1'b1),
+          .REN_A2_i(1'b1),
+          .WEN_A1_i(PUSH1),
+          .WEN_A2_i(PUSH2),
+          .BE_A1_i(2'b11),
+          .BE_A2_i(2'b11),
+      
+          .WDATA_B1_i(18'h0),
+          .WDATA_B2_i(18'h0),
+          .RDATA_B1_o(out_reg1[17:0]),
+          .RDATA_B2_o(out_reg2[17:0]),
+          .ADDR_B1_i(14'h0),
+          .ADDR_B2_i(14'h0),
+          .CLK_B1_i(Pop_Clk1),
+          .CLK_B2_i(Pop_Clk2),
+          .REN_B1_i(POP1),
+          .REN_B2_i(POP2),
+          .WEN_B1_i(1'b0),
+          .WEN_B2_i(1'b0),
+          .BE_B1_i(2'b11),
+          .BE_B2_i(2'b11),
+      
+          .FLUSH1_i(Async_Flush1),
+          .FLUSH2_i(Async_Flush2)
+        );        
+			end
+		endcase
+	end
+	default: begin
+		case (WR_DATA_WIDTH)
+			8, 9: begin
+				defparam U1.MODE_BITS = { 1'b1,
+					UPAF_DBITS2, UPAE_DBITS2, 4'h1, MODE_9, MODE_9, MODE_9, MODE_9, 1'b0,
+					1'b0, UPAF_DBITS1, 1'b0, UPAE_DBITS1, 4'h1, MODE_9, MODE_9, MODE_9, MODE_9, 1'b0
+				};
+        (* is_fifo = 1 *) 
+        (* sync_fifo = 0 *) 
+        (* is_split = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *) 
+        TDP36K U1 (
+          .RESET_ni(1'b1),
+          .WDATA_A1_i(in_reg1[17:0]),
+          .WDATA_A2_i(in_reg2[17:0]),
+          .RDATA_A1_o(fifo1_flags),
+          .RDATA_A2_o(fifo2_flags),
+          .ADDR_A1_i(14'h0),
+          .ADDR_A2_i(14'h0),
+          .CLK_A1_i(Push_Clk1),
+          .CLK_A2_i(Push_Clk2),
+          .REN_A1_i(1'b1),
+          .REN_A2_i(1'b1),
+          .WEN_A1_i(PUSH1),
+          .WEN_A2_i(PUSH2),
+          .BE_A1_i(2'b11),
+          .BE_A2_i(2'b11),
+      
+          .WDATA_B1_i(18'h0),
+          .WDATA_B2_i(18'h0),
+          .RDATA_B1_o(out_reg1[17:0]),
+          .RDATA_B2_o(out_reg2[17:0]),
+          .ADDR_B1_i(14'h0),
+          .ADDR_B2_i(14'h0),
+          .CLK_B1_i(Pop_Clk1),
+          .CLK_B2_i(Pop_Clk2),
+          .REN_B1_i(POP1),
+          .REN_B2_i(POP2),
+          .WEN_B1_i(1'b0),
+          .WEN_B2_i(1'b0),
+          .BE_B1_i(2'b11),
+          .BE_B2_i(2'b11),
+      
+          .FLUSH1_i(Async_Flush1),
+          .FLUSH2_i(Async_Flush2)
+        );        
+			end
+			16, 18: begin
+				defparam U1.MODE_BITS = { 1'b1,
+					UPAF_DBITS2, UPAE_DBITS2, 4'h1, MODE_18, MODE_18, MODE_18, MODE_18, 1'b0,
+					1'b0, UPAF_DBITS1, 1'b0, UPAE_DBITS1, 4'h1, MODE_18, MODE_18, MODE_18, MODE_18, 1'b0
+				};
+        (* is_fifo = 1 *) 
+        (* sync_fifo = 0 *) 
+        (* is_split = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *) 
+        TDP36K U1 (
+          .RESET_ni(1'b1),
+          .WDATA_A1_i(in_reg1[17:0]),
+          .WDATA_A2_i(in_reg2[17:0]),
+          .RDATA_A1_o(fifo1_flags),
+          .RDATA_A2_o(fifo2_flags),
+          .ADDR_A1_i(14'h0),
+          .ADDR_A2_i(14'h0),
+          .CLK_A1_i(Push_Clk1),
+          .CLK_A2_i(Push_Clk2),
+          .REN_A1_i(1'b1),
+          .REN_A2_i(1'b1),
+          .WEN_A1_i(PUSH1),
+          .WEN_A2_i(PUSH2),
+          .BE_A1_i(2'b11),
+          .BE_A2_i(2'b11),
+      
+          .WDATA_B1_i(18'h0),
+          .WDATA_B2_i(18'h0),
+          .RDATA_B1_o(out_reg1[17:0]),
+          .RDATA_B2_o(out_reg2[17:0]),
+          .ADDR_B1_i(14'h0),
+          .ADDR_B2_i(14'h0),
+          .CLK_B1_i(Pop_Clk1),
+          .CLK_B2_i(Pop_Clk2),
+          .REN_B1_i(POP1),
+          .REN_B2_i(POP2),
+          .WEN_B1_i(1'b0),
+          .WEN_B2_i(1'b0),
+          .BE_B1_i(2'b11),
+          .BE_B2_i(2'b11),
+      
+          .FLUSH1_i(Async_Flush1),
+          .FLUSH2_i(Async_Flush2)
+        );       
+			end
+			default: begin
+				defparam U1.MODE_BITS = { 1'b1,
+					UPAF_DBITS2, UPAE_DBITS2, 4'h1, MODE_18, MODE_18, MODE_18, MODE_18, 1'b0,
+					1'b0, UPAF_DBITS1, 1'b0, UPAE_DBITS1, 4'h1, MODE_18, MODE_18, MODE_18, MODE_18, 1'b0
+				};
+        (* is_fifo = 1 *) 
+        (* sync_fifo = 0 *) 
+        (* is_split = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *)
+        (* wr_data_width = WR_DATA_WIDTH *) 
+        TDP36K U1 (
+          .RESET_ni(1'b1),
+          .WDATA_A1_i(in_reg1[17:0]),
+          .WDATA_A2_i(in_reg2[17:0]),
+          .RDATA_A1_o(fifo1_flags),
+          .RDATA_A2_o(fifo2_flags),
+          .ADDR_A1_i(14'h0),
+          .ADDR_A2_i(14'h0),
+          .CLK_A1_i(Push_Clk1),
+          .CLK_A2_i(Push_Clk2),
+          .REN_A1_i(1'b1),
+          .REN_A2_i(1'b1),
+          .WEN_A1_i(PUSH1),
+          .WEN_A2_i(PUSH2),
+          .BE_A1_i(2'b11),
+          .BE_A2_i(2'b11),
+      
+          .WDATA_B1_i(18'h0),
+          .WDATA_B2_i(18'h0),
+          .RDATA_B1_o(out_reg1[17:0]),
+          .RDATA_B2_o(out_reg2[17:0]),
+          .ADDR_B1_i(14'h0),
+          .ADDR_B2_i(14'h0),
+          .CLK_B1_i(Pop_Clk1),
+          .CLK_B2_i(Pop_Clk2),
+          .REN_B1_i(POP1),
+          .REN_B2_i(POP2),
+          .WEN_B1_i(1'b0),
+          .WEN_B2_i(1'b0),
+          .BE_B1_i(2'b11),
+          .BE_B2_i(2'b11),
+      
+          .FLUSH1_i(Async_Flush1),
+          .FLUSH2_i(Async_Flush2)
+        );
+			end
+		endcase
+	end
+  endcase
+
+  generate
+    if (RD_DATA_WIDTH == 9) begin
+      assign DOUT1[RD_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]};
+      assign DOUT2[RD_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]};
+    end else begin
+      assign DOUT1[RD_DATA_WIDTH-1:0] = out_reg1[RD_DATA_WIDTH-1:0];
+      assign DOUT2[RD_DATA_WIDTH-1:0] = out_reg2[RD_DATA_WIDTH-1:0];
+    end
+  endgenerate  
+
+endmodule
+
+module SFIFO_36K_BLK (
+    DIN,
+    PUSH,
+    POP,
+    CLK,
+    Async_Flush,
+    Overrun_Error,
+    Full_Watermark,
+    Almost_Full,
+    Full,
+    Underrun_Error,
+    Empty_Watermark,
+    Almost_Empty,
+    Empty,
+    DOUT
+);
+
+  parameter WR_DATA_WIDTH = 36;
+  parameter RD_DATA_WIDTH = 36;
+  parameter UPAE_DBITS = 12'd10;
+  parameter UPAF_DBITS = 12'd10;
+  
+  localparam MODE_36 = 3'b011; // 36- or 32-bit
+  localparam MODE_18 = 3'b010; // 18- or 16-bit
+  localparam MODE_9 = 3'b001; // 9- or 8-bit
+  localparam MODE_4 = 3'b100; // 4-bit
+  localparam MODE_2 = 3'b110; // 2-bit
+  localparam MODE_1 = 3'b101; // 1-bit
+
+  input wire CLK;
+  input wire PUSH, POP;
+  input wire [WR_DATA_WIDTH-1:0] DIN;
+  input wire Async_Flush;
+  output wire [RD_DATA_WIDTH-1:0] DOUT;
+  output wire Almost_Full, Almost_Empty;
+  output wire Full, Empty;
+  output wire Full_Watermark, Empty_Watermark;
+  output wire Overrun_Error, Underrun_Error;
+  
+  wire [35:0] in_reg;
+  wire [35:0] out_reg;
+  wire [17:0] fifo_flags;
+  
+  wire [35:0] RD_DATA_CMPL;
+  wire [35:WR_DATA_WIDTH] WR_DATA_CMPL;
+  
+  wire Push_Clk, Pop_Clk;
+  
+  assign Push_Clk = CLK;
+  assign Pop_Clk = CLK;
+  
+  assign Overrun_Error = fifo_flags[0];
+  assign Full_Watermark = fifo_flags[1];
+  assign Almost_Full = fifo_flags[2];
+  assign Full = fifo_flags[3];
+  assign Underrun_Error = fifo_flags[4];
+  assign Empty_Watermark = fifo_flags[5];
+  assign Almost_Empty = fifo_flags[6];
+  assign Empty = fifo_flags[7];
+   
+  generate
+    if (WR_DATA_WIDTH == 36) begin
+      assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0];
+    end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin
+      assign in_reg[WR_DATA_WIDTH+1:18] = DIN[WR_DATA_WIDTH-1:16];
+      assign in_reg[17:0] = {2'b00,DIN[15:0]};
+    end else if (WR_DATA_WIDTH == 9) begin
+      assign in_reg[35:0] = {19'h0, DIN[8], 8'h0, DIN[7:0]};
+    end else begin
+      assign in_reg[35:WR_DATA_WIDTH]  = 0;
+      assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0];
+    end
+  endgenerate
+  
+  generate
+    if (RD_DATA_WIDTH == 36) begin
+      assign RD_DATA_CMPL = out_reg;
+    end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin
+      assign RD_DATA_CMPL  = {2'b00,out_reg[35:18],out_reg[15:0]};
+    end else if (RD_DATA_WIDTH == 9) begin
+      assign RD_DATA_CMPL = { 27'h0, out_reg[16], out_reg[7:0]};
+    end else begin
+      assign RD_DATA_CMPL = {18'h0, out_reg[17:0]};
+    end
+  endgenerate
+  
+  case (RD_DATA_WIDTH)
+	8, 9: begin
+		case (WR_DATA_WIDTH)
+			8, 9: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_9, MODE_9, MODE_9, MODE_9, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, MODE_9, MODE_9, MODE_9, MODE_9, 1'b1
+				};
+        (* is_fifo = 1 *)
+        (* sync_fifo = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *) 
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K U1 (
+          .RESET_ni(1'b1),
+          .WDATA_A1_i(in_reg[17:0]),
+          .WDATA_A2_i(in_reg[35:18]),
+          .RDATA_A1_o(fifo_flags),
+          .RDATA_A2_o(),
+          .ADDR_A1_i(14'h0),
+          .ADDR_A2_i(14'h0),
+          .CLK_A1_i(Push_Clk),
+          .CLK_A2_i(1'b0),
+          .REN_A1_i(1'b1),
+          .REN_A2_i(1'b0),
+          .WEN_A1_i(PUSH),
+          .WEN_A2_i(1'b0),
+          .BE_A1_i(2'b11),
+          .BE_A2_i(2'b11),
+      
+          .WDATA_B1_i(18'h0),
+          .WDATA_B2_i(18'h0),
+          .RDATA_B1_o(out_reg[17:0]),
+          .RDATA_B2_o(out_reg[35:18]),
+          .ADDR_B1_i(14'h0),
+          .ADDR_B2_i(14'h0),
+          .CLK_B1_i(Pop_Clk),
+          .CLK_B2_i(1'b0),
+          .REN_B1_i(POP),
+          .REN_B2_i(1'b0),
+          .WEN_B1_i(1'b0),
+          .WEN_B2_i(1'b0),
+          .BE_B1_i(2'b11),
+          .BE_B2_i(2'b11),
+      
+          .FLUSH1_i(Async_Flush),
+          .FLUSH2_i(1'b0)
+        );
+			end
+			16, 18: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_9, MODE_18, MODE_9, MODE_18, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, MODE_9, MODE_18, MODE_9, MODE_18, 1'b1
+				};
+        (* is_fifo = 1 *)
+        (* sync_fifo = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *) 
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K U1 (
+          .RESET_ni(1'b1),
+          .WDATA_A1_i(in_reg[17:0]),
+          .WDATA_A2_i(in_reg[35:18]),
+          .RDATA_A1_o(fifo_flags),
+          .RDATA_A2_o(),
+          .ADDR_A1_i(14'h0),
+          .ADDR_A2_i(14'h0),
+          .CLK_A1_i(Push_Clk),
+          .CLK_A2_i(1'b0),
+          .REN_A1_i(1'b1),
+          .REN_A2_i(1'b0),
+          .WEN_A1_i(PUSH),
+          .WEN_A2_i(1'b0),
+          .BE_A1_i(2'b11),
+          .BE_A2_i(2'b11),
+      
+          .WDATA_B1_i(18'h0),
+          .WDATA_B2_i(18'h0),
+          .RDATA_B1_o(out_reg[17:0]),
+          .RDATA_B2_o(out_reg[35:18]),
+          .ADDR_B1_i(14'h0),
+          .ADDR_B2_i(14'h0),
+          .CLK_B1_i(Pop_Clk),
+          .CLK_B2_i(1'b0),
+          .REN_B1_i(POP),
+          .REN_B2_i(1'b0),
+          .WEN_B1_i(1'b0),
+          .WEN_B2_i(1'b0),
+          .BE_B1_i(2'b11),
+          .BE_B2_i(2'b11),
+      
+          .FLUSH1_i(Async_Flush),
+          .FLUSH2_i(1'b0)
+        );        
+			end
+			32, 36: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_9, MODE_36, MODE_9, MODE_36, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, MODE_9, MODE_36, MODE_9, MODE_36, 1'b1
+				};
+        (* is_fifo = 1 *)
+        (* sync_fifo = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *) 
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K U1 (
+          .RESET_ni(1'b1),
+          .WDATA_A1_i(in_reg[17:0]),
+          .WDATA_A2_i(in_reg[35:18]),
+          .RDATA_A1_o(fifo_flags),
+          .RDATA_A2_o(),
+          .ADDR_A1_i(14'h0),
+          .ADDR_A2_i(14'h0),
+          .CLK_A1_i(Push_Clk),
+          .CLK_A2_i(1'b0),
+          .REN_A1_i(1'b1),
+          .REN_A2_i(1'b0),
+          .WEN_A1_i(PUSH),
+          .WEN_A2_i(1'b0),
+          .BE_A1_i(2'b11),
+          .BE_A2_i(2'b11),
+      
+          .WDATA_B1_i(18'h0),
+          .WDATA_B2_i(18'h0),
+          .RDATA_B1_o(out_reg[17:0]),
+          .RDATA_B2_o(out_reg[35:18]),
+          .ADDR_B1_i(14'h0),
+          .ADDR_B2_i(14'h0),
+          .CLK_B1_i(Pop_Clk),
+          .CLK_B2_i(1'b0),
+          .REN_B1_i(POP),
+          .REN_B2_i(1'b0),
+          .WEN_B1_i(1'b0),
+          .WEN_B2_i(1'b0),
+          .BE_B1_i(2'b11),
+          .BE_B2_i(2'b11),
+      
+          .FLUSH1_i(Async_Flush),
+          .FLUSH2_i(1'b0)
+        );        
+			end
+			default: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_9, MODE_9, MODE_9, MODE_9, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, MODE_9, MODE_9, MODE_9, MODE_9, 1'b1
+				};
+        (* is_fifo = 1 *)
+        (* sync_fifo = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *) 
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K U1 (
+          .RESET_ni(1'b1),
+          .WDATA_A1_i(in_reg[17:0]),
+          .WDATA_A2_i(in_reg[35:18]),
+          .RDATA_A1_o(fifo_flags),
+          .RDATA_A2_o(),
+          .ADDR_A1_i(14'h0),
+          .ADDR_A2_i(14'h0),
+          .CLK_A1_i(Push_Clk),
+          .CLK_A2_i(1'b0),
+          .REN_A1_i(1'b1),
+          .REN_A2_i(1'b0),
+          .WEN_A1_i(PUSH),
+          .WEN_A2_i(1'b0),
+          .BE_A1_i(2'b11),
+          .BE_A2_i(2'b11),
+      
+          .WDATA_B1_i(18'h0),
+          .WDATA_B2_i(18'h0),
+          .RDATA_B1_o(out_reg[17:0]),
+          .RDATA_B2_o(out_reg[35:18]),
+          .ADDR_B1_i(14'h0),
+          .ADDR_B2_i(14'h0),
+          .CLK_B1_i(Pop_Clk),
+          .CLK_B2_i(1'b0),
+          .REN_B1_i(POP),
+          .REN_B2_i(1'b0),
+          .WEN_B1_i(1'b0),
+          .WEN_B2_i(1'b0),
+          .BE_B1_i(2'b11),
+          .BE_B2_i(2'b11),
+      
+          .FLUSH1_i(Async_Flush),
+          .FLUSH2_i(1'b0)
+        );        
+			end
+		endcase
+	end
+	16, 18: begin
+		case (WR_DATA_WIDTH)
+			8, 9: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_18, MODE_9, MODE_18, MODE_9, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, MODE_18, MODE_9, MODE_18, MODE_9, 1'b1
+				};
+        (* is_fifo = 1 *)
+        (* sync_fifo = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *) 
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K U1 (
+          .RESET_ni(1'b1),
+          .WDATA_A1_i(in_reg[17:0]),
+          .WDATA_A2_i(in_reg[35:18]),
+          .RDATA_A1_o(fifo_flags),
+          .RDATA_A2_o(),
+          .ADDR_A1_i(14'h0),
+          .ADDR_A2_i(14'h0),
+          .CLK_A1_i(Push_Clk),
+          .CLK_A2_i(1'b0),
+          .REN_A1_i(1'b1),
+          .REN_A2_i(1'b0),
+          .WEN_A1_i(PUSH),
+          .WEN_A2_i(1'b0),
+          .BE_A1_i(2'b11),
+          .BE_A2_i(2'b11),
+      
+          .WDATA_B1_i(18'h0),
+          .WDATA_B2_i(18'h0),
+          .RDATA_B1_o(out_reg[17:0]),
+          .RDATA_B2_o(out_reg[35:18]),
+          .ADDR_B1_i(14'h0),
+          .ADDR_B2_i(14'h0),
+          .CLK_B1_i(Pop_Clk),
+          .CLK_B2_i(1'b0),
+          .REN_B1_i(POP),
+          .REN_B2_i(1'b0),
+          .WEN_B1_i(1'b0),
+          .WEN_B2_i(1'b0),
+          .BE_B1_i(2'b11),
+          .BE_B2_i(2'b11),
+      
+          .FLUSH1_i(Async_Flush),
+          .FLUSH2_i(1'b0)
+        );        
+			end
+			16, 18: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_18, MODE_18, MODE_18, MODE_18, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, MODE_18, MODE_18, MODE_18, MODE_18, 1'b1
+				};
+        (* is_fifo = 1 *)
+        (* sync_fifo = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *) 
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K U1 (
+          .RESET_ni(1'b1),
+          .WDATA_A1_i(in_reg[17:0]),
+          .WDATA_A2_i(in_reg[35:18]),
+          .RDATA_A1_o(fifo_flags),
+          .RDATA_A2_o(),
+          .ADDR_A1_i(14'h0),
+          .ADDR_A2_i(14'h0),
+          .CLK_A1_i(Push_Clk),
+          .CLK_A2_i(1'b0),
+          .REN_A1_i(1'b1),
+          .REN_A2_i(1'b0),
+          .WEN_A1_i(PUSH),
+          .WEN_A2_i(1'b0),
+          .BE_A1_i(2'b11),
+          .BE_A2_i(2'b11),
+      
+          .WDATA_B1_i(18'h0),
+          .WDATA_B2_i(18'h0),
+          .RDATA_B1_o(out_reg[17:0]),
+          .RDATA_B2_o(out_reg[35:18]),
+          .ADDR_B1_i(14'h0),
+          .ADDR_B2_i(14'h0),
+          .CLK_B1_i(Pop_Clk),
+          .CLK_B2_i(1'b0),
+          .REN_B1_i(POP),
+          .REN_B2_i(1'b0),
+          .WEN_B1_i(1'b0),
+          .WEN_B2_i(1'b0),
+          .BE_B1_i(2'b11),
+          .BE_B2_i(2'b11),
+      
+          .FLUSH1_i(Async_Flush),
+          .FLUSH2_i(1'b0)
+        );        
+			end
+			32, 36: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_18, MODE_36, MODE_18, MODE_36, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, MODE_18, MODE_36, MODE_18, MODE_36, 1'b1
+				};
+        (* is_fifo = 1 *)
+        (* sync_fifo = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *) 
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K U1 (
+          .RESET_ni(1'b1),
+          .WDATA_A1_i(in_reg[17:0]),
+          .WDATA_A2_i(in_reg[35:18]),
+          .RDATA_A1_o(fifo_flags),
+          .RDATA_A2_o(),
+          .ADDR_A1_i(14'h0),
+          .ADDR_A2_i(14'h0),
+          .CLK_A1_i(Push_Clk),
+          .CLK_A2_i(1'b0),
+          .REN_A1_i(1'b1),
+          .REN_A2_i(1'b0),
+          .WEN_A1_i(PUSH),
+          .WEN_A2_i(1'b0),
+          .BE_A1_i(2'b11),
+          .BE_A2_i(2'b11),
+      
+          .WDATA_B1_i(18'h0),
+          .WDATA_B2_i(18'h0),
+          .RDATA_B1_o(out_reg[17:0]),
+          .RDATA_B2_o(out_reg[35:18]),
+          .ADDR_B1_i(14'h0),
+          .ADDR_B2_i(14'h0),
+          .CLK_B1_i(Pop_Clk),
+          .CLK_B2_i(1'b0),
+          .REN_B1_i(POP),
+          .REN_B2_i(1'b0),
+          .WEN_B1_i(1'b0),
+          .WEN_B2_i(1'b0),
+          .BE_B1_i(2'b11),
+          .BE_B2_i(2'b11),
+      
+          .FLUSH1_i(Async_Flush),
+          .FLUSH2_i(1'b0)
+        );        
+			end
+			default: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_18, MODE_18, MODE_18, MODE_18, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, MODE_18, MODE_18, MODE_18, MODE_18, 1'b1
+				};
+        (* is_fifo = 1 *)
+        (* sync_fifo = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *) 
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K U1 (
+          .RESET_ni(1'b1),
+          .WDATA_A1_i(in_reg[17:0]),
+          .WDATA_A2_i(in_reg[35:18]),
+          .RDATA_A1_o(fifo_flags),
+          .RDATA_A2_o(),
+          .ADDR_A1_i(14'h0),
+          .ADDR_A2_i(14'h0),
+          .CLK_A1_i(Push_Clk),
+          .CLK_A2_i(1'b0),
+          .REN_A1_i(1'b1),
+          .REN_A2_i(1'b0),
+          .WEN_A1_i(PUSH),
+          .WEN_A2_i(1'b0),
+          .BE_A1_i(2'b11),
+          .BE_A2_i(2'b11),
+      
+          .WDATA_B1_i(18'h0),
+          .WDATA_B2_i(18'h0),
+          .RDATA_B1_o(out_reg[17:0]),
+          .RDATA_B2_o(out_reg[35:18]),
+          .ADDR_B1_i(14'h0),
+          .ADDR_B2_i(14'h0),
+          .CLK_B1_i(Pop_Clk),
+          .CLK_B2_i(1'b0),
+          .REN_B1_i(POP),
+          .REN_B2_i(1'b0),
+          .WEN_B1_i(1'b0),
+          .WEN_B2_i(1'b0),
+          .BE_B1_i(2'b11),
+          .BE_B2_i(2'b11),
+      
+          .FLUSH1_i(Async_Flush),
+          .FLUSH2_i(1'b0)
+        );        
+			end
+		endcase
+	end
+	32, 36: begin
+		case (WR_DATA_WIDTH)
+			8, 9: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_36, MODE_9, MODE_36, MODE_9, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, MODE_36, MODE_9, MODE_36, MODE_9, 1'b1
+				};
+        (* is_fifo = 1 *)
+        (* sync_fifo = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *) 
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K U1 (
+          .RESET_ni(1'b1),
+          .WDATA_A1_i(in_reg[17:0]),
+          .WDATA_A2_i(in_reg[35:18]),
+          .RDATA_A1_o(fifo_flags),
+          .RDATA_A2_o(),
+          .ADDR_A1_i(14'h0),
+          .ADDR_A2_i(14'h0),
+          .CLK_A1_i(Push_Clk),
+          .CLK_A2_i(1'b0),
+          .REN_A1_i(1'b1),
+          .REN_A2_i(1'b0),
+          .WEN_A1_i(PUSH),
+          .WEN_A2_i(1'b0),
+          .BE_A1_i(2'b11),
+          .BE_A2_i(2'b11),
+      
+          .WDATA_B1_i(18'h0),
+          .WDATA_B2_i(18'h0),
+          .RDATA_B1_o(out_reg[17:0]),
+          .RDATA_B2_o(out_reg[35:18]),
+          .ADDR_B1_i(14'h0),
+          .ADDR_B2_i(14'h0),
+          .CLK_B1_i(Pop_Clk),
+          .CLK_B2_i(1'b0),
+          .REN_B1_i(POP),
+          .REN_B2_i(1'b0),
+          .WEN_B1_i(1'b0),
+          .WEN_B2_i(1'b0),
+          .BE_B1_i(2'b11),
+          .BE_B2_i(2'b11),
+      
+          .FLUSH1_i(Async_Flush),
+          .FLUSH2_i(1'b0)
+        );        
+			end
+			16, 18: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_36, MODE_18, MODE_36, MODE_18, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, MODE_36, MODE_18, MODE_36, MODE_18, 1'b1
+				};
+        (* is_fifo = 1 *)
+        (* sync_fifo = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *) 
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K U1 (
+          .RESET_ni(1'b1),
+          .WDATA_A1_i(in_reg[17:0]),
+          .WDATA_A2_i(in_reg[35:18]),
+          .RDATA_A1_o(fifo_flags),
+          .RDATA_A2_o(),
+          .ADDR_A1_i(14'h0),
+          .ADDR_A2_i(14'h0),
+          .CLK_A1_i(Push_Clk),
+          .CLK_A2_i(1'b0),
+          .REN_A1_i(1'b1),
+          .REN_A2_i(1'b0),
+          .WEN_A1_i(PUSH),
+          .WEN_A2_i(1'b0),
+          .BE_A1_i(2'b11),
+          .BE_A2_i(2'b11),
+      
+          .WDATA_B1_i(18'h0),
+          .WDATA_B2_i(18'h0),
+          .RDATA_B1_o(out_reg[17:0]),
+          .RDATA_B2_o(out_reg[35:18]),
+          .ADDR_B1_i(14'h0),
+          .ADDR_B2_i(14'h0),
+          .CLK_B1_i(Pop_Clk),
+          .CLK_B2_i(1'b0),
+          .REN_B1_i(POP),
+          .REN_B2_i(1'b0),
+          .WEN_B1_i(1'b0),
+          .WEN_B2_i(1'b0),
+          .BE_B1_i(2'b11),
+          .BE_B2_i(2'b11),
+      
+          .FLUSH1_i(Async_Flush),
+          .FLUSH2_i(1'b0)
+        );        
+			end
+			32, 36: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_36, MODE_36, MODE_36, MODE_36, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, MODE_36, MODE_36, MODE_36, MODE_36, 1'b1
+				};
+        (* is_fifo = 1 *)
+        (* sync_fifo = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *) 
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K U1 (
+          .RESET_ni(1'b1),
+          .WDATA_A1_i(in_reg[17:0]),
+          .WDATA_A2_i(in_reg[35:18]),
+          .RDATA_A1_o(fifo_flags),
+          .RDATA_A2_o(),
+          .ADDR_A1_i(14'h0),
+          .ADDR_A2_i(14'h0),
+          .CLK_A1_i(Push_Clk),
+          .CLK_A2_i(1'b0),
+          .REN_A1_i(1'b1),
+          .REN_A2_i(1'b0),
+          .WEN_A1_i(PUSH),
+          .WEN_A2_i(1'b0),
+          .BE_A1_i(2'b11),
+          .BE_A2_i(2'b11),
+      
+          .WDATA_B1_i(18'h0),
+          .WDATA_B2_i(18'h0),
+          .RDATA_B1_o(out_reg[17:0]),
+          .RDATA_B2_o(out_reg[35:18]),
+          .ADDR_B1_i(14'h0),
+          .ADDR_B2_i(14'h0),
+          .CLK_B1_i(Pop_Clk),
+          .CLK_B2_i(1'b0),
+          .REN_B1_i(POP),
+          .REN_B2_i(1'b0),
+          .WEN_B1_i(1'b0),
+          .WEN_B2_i(1'b0),
+          .BE_B1_i(2'b11),
+          .BE_B2_i(2'b11),
+      
+          .FLUSH1_i(Async_Flush),
+          .FLUSH2_i(1'b0)
+        );        
+			end
+			default: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_36, MODE_36, MODE_36, MODE_36, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, MODE_36, MODE_36, MODE_36, MODE_36, 1'b1
+				};
+        (* is_fifo = 1 *)
+        (* sync_fifo = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *) 
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K U1 (
+          .RESET_ni(1'b1),
+          .WDATA_A1_i(in_reg[17:0]),
+          .WDATA_A2_i(in_reg[35:18]),
+          .RDATA_A1_o(fifo_flags),
+          .RDATA_A2_o(),
+          .ADDR_A1_i(14'h0),
+          .ADDR_A2_i(14'h0),
+          .CLK_A1_i(Push_Clk),
+          .CLK_A2_i(1'b0),
+          .REN_A1_i(1'b1),
+          .REN_A2_i(1'b0),
+          .WEN_A1_i(PUSH),
+          .WEN_A2_i(1'b0),
+          .BE_A1_i(2'b11),
+          .BE_A2_i(2'b11),
+      
+          .WDATA_B1_i(18'h0),
+          .WDATA_B2_i(18'h0),
+          .RDATA_B1_o(out_reg[17:0]),
+          .RDATA_B2_o(out_reg[35:18]),
+          .ADDR_B1_i(14'h0),
+          .ADDR_B2_i(14'h0),
+          .CLK_B1_i(Pop_Clk),
+          .CLK_B2_i(1'b0),
+          .REN_B1_i(POP),
+          .REN_B2_i(1'b0),
+          .WEN_B1_i(1'b0),
+          .WEN_B2_i(1'b0),
+          .BE_B1_i(2'b11),
+          .BE_B2_i(2'b11),
+      
+          .FLUSH1_i(Async_Flush),
+          .FLUSH2_i(1'b0)
+        );        
+			end
+		endcase
+	end
+	default: begin
+		case (WR_DATA_WIDTH)
+			8, 9: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_9, MODE_9, MODE_9, MODE_9, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, MODE_9, MODE_9, MODE_9, MODE_9, 1'b1
+				};
+        (* is_fifo = 1 *)
+        (* sync_fifo = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *) 
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K U1 (
+          .RESET_ni(1'b1),
+          .WDATA_A1_i(in_reg[17:0]),
+          .WDATA_A2_i(in_reg[35:18]),
+          .RDATA_A1_o(fifo_flags),
+          .RDATA_A2_o(),
+          .ADDR_A1_i(14'h0),
+          .ADDR_A2_i(14'h0),
+          .CLK_A1_i(Push_Clk),
+          .CLK_A2_i(1'b0),
+          .REN_A1_i(1'b1),
+          .REN_A2_i(1'b0),
+          .WEN_A1_i(PUSH),
+          .WEN_A2_i(1'b0),
+          .BE_A1_i(2'b11),
+          .BE_A2_i(2'b11),
+      
+          .WDATA_B1_i(18'h0),
+          .WDATA_B2_i(18'h0),
+          .RDATA_B1_o(out_reg[17:0]),
+          .RDATA_B2_o(out_reg[35:18]),
+          .ADDR_B1_i(14'h0),
+          .ADDR_B2_i(14'h0),
+          .CLK_B1_i(Pop_Clk),
+          .CLK_B2_i(1'b0),
+          .REN_B1_i(POP),
+          .REN_B2_i(1'b0),
+          .WEN_B1_i(1'b0),
+          .WEN_B2_i(1'b0),
+          .BE_B1_i(2'b11),
+          .BE_B2_i(2'b11),
+      
+          .FLUSH1_i(Async_Flush),
+          .FLUSH2_i(1'b0)
+        );        
+			end
+			16, 18: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_18, MODE_18, MODE_18, MODE_18, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, MODE_18, MODE_18, MODE_18, MODE_18, 1'b1
+				};
+        (* is_fifo = 1 *)
+        (* sync_fifo = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *) 
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K U1 (
+          .RESET_ni(1'b1),
+          .WDATA_A1_i(in_reg[17:0]),
+          .WDATA_A2_i(in_reg[35:18]),
+          .RDATA_A1_o(fifo_flags),
+          .RDATA_A2_o(),
+          .ADDR_A1_i(14'h0),
+          .ADDR_A2_i(14'h0),
+          .CLK_A1_i(Push_Clk),
+          .CLK_A2_i(1'b0),
+          .REN_A1_i(1'b1),
+          .REN_A2_i(1'b0),
+          .WEN_A1_i(PUSH),
+          .WEN_A2_i(1'b0),
+          .BE_A1_i(2'b11),
+          .BE_A2_i(2'b11),
+      
+          .WDATA_B1_i(18'h0),
+          .WDATA_B2_i(18'h0),
+          .RDATA_B1_o(out_reg[17:0]),
+          .RDATA_B2_o(out_reg[35:18]),
+          .ADDR_B1_i(14'h0),
+          .ADDR_B2_i(14'h0),
+          .CLK_B1_i(Pop_Clk),
+          .CLK_B2_i(1'b0),
+          .REN_B1_i(POP),
+          .REN_B2_i(1'b0),
+          .WEN_B1_i(1'b0),
+          .WEN_B2_i(1'b0),
+          .BE_B1_i(2'b11),
+          .BE_B2_i(2'b11),
+      
+          .FLUSH1_i(Async_Flush),
+          .FLUSH2_i(1'b0)
+        );        
+			end
+			32, 36: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_36, MODE_36, MODE_36, MODE_36, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, MODE_36, MODE_36, MODE_36, MODE_36, 1'b1
+				};
+        (* is_fifo = 1 *)
+        (* sync_fifo = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *) 
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K U1 (
+          .RESET_ni(1'b1),
+          .WDATA_A1_i(in_reg[17:0]),
+          .WDATA_A2_i(in_reg[35:18]),
+          .RDATA_A1_o(fifo_flags),
+          .RDATA_A2_o(),
+          .ADDR_A1_i(14'h0),
+          .ADDR_A2_i(14'h0),
+          .CLK_A1_i(Push_Clk),
+          .CLK_A2_i(1'b0),
+          .REN_A1_i(1'b1),
+          .REN_A2_i(1'b0),
+          .WEN_A1_i(PUSH),
+          .WEN_A2_i(1'b0),
+          .BE_A1_i(2'b11),
+          .BE_A2_i(2'b11),
+      
+          .WDATA_B1_i(18'h0),
+          .WDATA_B2_i(18'h0),
+          .RDATA_B1_o(out_reg[17:0]),
+          .RDATA_B2_o(out_reg[35:18]),
+          .ADDR_B1_i(14'h0),
+          .ADDR_B2_i(14'h0),
+          .CLK_B1_i(Pop_Clk),
+          .CLK_B2_i(1'b0),
+          .REN_B1_i(POP),
+          .REN_B2_i(1'b0),
+          .WEN_B1_i(1'b0),
+          .WEN_B2_i(1'b0),
+          .BE_B1_i(2'b11),
+          .BE_B2_i(2'b11),
+      
+          .FLUSH1_i(Async_Flush),
+          .FLUSH2_i(1'b0)
+        );
+			end
+			default: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_36, MODE_36, MODE_36, MODE_36, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, MODE_36, MODE_36, MODE_36, MODE_36, 1'b1
+				};
+        (* is_fifo = 1 *)
+        (* sync_fifo = 1 *)
+        (* rd_data_width = RD_DATA_WIDTH *) 
+        (* wr_data_width = WR_DATA_WIDTH *)
+        TDP36K U1 (
+          .RESET_ni(1'b1),
+          .WDATA_A1_i(in_reg[17:0]),
+          .WDATA_A2_i(in_reg[35:18]),
+          .RDATA_A1_o(fifo_flags),
+          .RDATA_A2_o(),
+          .ADDR_A1_i(14'h0),
+          .ADDR_A2_i(14'h0),
+          .CLK_A1_i(Push_Clk),
+          .CLK_A2_i(1'b0),
+          .REN_A1_i(1'b1),
+          .REN_A2_i(1'b0),
+          .WEN_A1_i(PUSH),
+          .WEN_A2_i(1'b0),
+          .BE_A1_i(2'b11),
+          .BE_A2_i(2'b11),
+      
+          .WDATA_B1_i(18'h0),
+          .WDATA_B2_i(18'h0),
+          .RDATA_B1_o(out_reg[17:0]),
+          .RDATA_B2_o(out_reg[35:18]),
+          .ADDR_B1_i(14'h0),
+          .ADDR_B2_i(14'h0),
+          .CLK_B1_i(Pop_Clk),
+          .CLK_B2_i(1'b0),
+          .REN_B1_i(POP),
+          .REN_B2_i(1'b0),
+          .WEN_B1_i(1'b0),
+          .WEN_B2_i(1'b0),
+          .BE_B1_i(2'b11),
+          .BE_B2_i(2'b11),
+      
+          .FLUSH1_i(Async_Flush),
+          .FLUSH2_i(1'b0)
+        );
+			end
+		endcase
+	end
+ endcase
+
+  assign DOUT[RD_DATA_WIDTH-1 : 0] = RD_DATA_CMPL[RD_DATA_WIDTH-1 : 0];
+
+endmodule
+
+module AFIFO_36K_BLK (
+    DIN,
+    PUSH,
+    POP,
+    Push_Clk,
+    Pop_Clk,
+    Async_Flush,
+    Overrun_Error,
+    Full_Watermark,
+    Almost_Full,
+    Full,
+    Underrun_Error,
+    Empty_Watermark,
+    Almost_Empty,
+    Empty,
+    DOUT
+);
+
+  parameter WR_DATA_WIDTH = 36;
+  parameter RD_DATA_WIDTH = 36;
+  parameter UPAE_DBITS = 12'd10;
+  parameter UPAF_DBITS = 12'd10;
+
+  localparam MODE_36 = 3'b011; // 36- or 32-bit
+  localparam MODE_18 = 3'b010; // 18- or 16-bit
+  localparam MODE_9 = 3'b001; // 9- or 8-bit
+  localparam MODE_4 = 3'b100; // 4-bit
+  localparam MODE_2 = 3'b110; // 2-bit
+  localparam MODE_1 = 3'b101; // 1-bit
+
+  input wire Push_Clk, Pop_Clk;
+  input wire PUSH, POP;
+  input wire [WR_DATA_WIDTH-1:0] DIN;
+  input wire Async_Flush;
+  output wire [RD_DATA_WIDTH-1:0] DOUT;
+  output wire Almost_Full, Almost_Empty;
+  output wire Full, Empty;
+  output wire Full_Watermark, Empty_Watermark;
+  output wire Overrun_Error, Underrun_Error;
+  
+  wire [35:0] in_reg;
+  wire [35:0] out_reg;
+  wire [17:0] fifo_flags;
+  
+  wire [35:0] RD_DATA_CMPL;
+  wire [35:WR_DATA_WIDTH] WR_DATA_CMPL;
+  
+  assign Overrun_Error = fifo_flags[0];
+  assign Full_Watermark = fifo_flags[1];
+  assign Almost_Full = fifo_flags[2];
+  assign Full = fifo_flags[3];
+  assign Underrun_Error = fifo_flags[4];
+  assign Empty_Watermark = fifo_flags[5];
+  assign Almost_Empty = fifo_flags[6];
+  assign Empty = fifo_flags[7];
+   
+  generate
+    if (WR_DATA_WIDTH == 36) begin
+      assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0];
+    end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin
+      assign in_reg[WR_DATA_WIDTH+1:18] = DIN[WR_DATA_WIDTH-1:16];
+      assign in_reg[17:0] = {2'b00,DIN[15:0]};
+    end else if (WR_DATA_WIDTH == 9) begin
+      assign in_reg[35:0] = {19'h0, DIN[8], 8'h0, DIN[7:0]};
+    end else begin
+      assign in_reg[35:WR_DATA_WIDTH]  = 0;
+      assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0];
+    end
+  endgenerate
+  
+  generate
+    if (RD_DATA_WIDTH == 36) begin
+      assign RD_DATA_CMPL = out_reg;
+    end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin
+      assign RD_DATA_CMPL  = {2'b00,out_reg[35:18],out_reg[15:0]};
+    end else if (RD_DATA_WIDTH == 9) begin
+      assign RD_DATA_CMPL = { 27'h0, out_reg[16], out_reg[7:0]};
+    end else begin
+      assign RD_DATA_CMPL = {18'h0, out_reg[17:0]};
+    end
+  endgenerate
+  
+  case (RD_DATA_WIDTH)
+	8, 9: begin
+		case (WR_DATA_WIDTH)
+			8, 9: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_9, MODE_9, MODE_9, MODE_9, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, MODE_9, MODE_9, MODE_9, MODE_9, 1'b0
+				};
+        
+            (* is_fifo = 1 *)
+            (* sync_fifo = 0 *)
+            (* rd_data_width = RD_DATA_WIDTH *) 
+            (* wr_data_width = WR_DATA_WIDTH *)
+            TDP36K U1 (
+              .RESET_ni(1'b1),
+              .WDATA_A1_i(in_reg[17:0]),
+              .WDATA_A2_i(in_reg[35:18]),
+              .RDATA_A1_o(fifo_flags),
+              .RDATA_A2_o(),
+              .ADDR_A1_i(14'h0),
+              .ADDR_A2_i(14'h0),
+              .CLK_A1_i(Push_Clk),
+              .CLK_A2_i(1'b0),
+              .REN_A1_i(1'b1),
+              .REN_A2_i(1'b0),
+              .WEN_A1_i(PUSH),
+              .WEN_A2_i(1'b0),
+              .BE_A1_i(2'b11),
+              .BE_A2_i(2'b11),
+          
+              .WDATA_B1_i(18'h0),
+              .WDATA_B2_i(18'h0),
+              .RDATA_B1_o(out_reg[17:0]),
+              .RDATA_B2_o(out_reg[35:18]),
+              .ADDR_B1_i(14'h0),
+              .ADDR_B2_i(14'h0),
+              .CLK_B1_i(Pop_Clk),
+              .CLK_B2_i(1'b0),
+              .REN_B1_i(POP),
+              .REN_B2_i(1'b0),
+              .WEN_B1_i(1'b0),
+              .WEN_B2_i(1'b0),
+              .BE_B1_i(2'b11),
+              .BE_B2_i(2'b11),
+          
+              .FLUSH1_i(Async_Flush),
+              .FLUSH2_i(1'b0)
+            );
+  
+			end
+			16, 18: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_9, MODE_18, MODE_9, MODE_18, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, MODE_9, MODE_18, MODE_9, MODE_18, 1'b0
+				};
+        
+            (* is_fifo = 1 *)
+            (* sync_fifo = 0 *)
+            (* rd_data_width = RD_DATA_WIDTH *) 
+            (* wr_data_width = WR_DATA_WIDTH *)
+            TDP36K U1 (
+              .RESET_ni(1'b1),
+              .WDATA_A1_i(in_reg[17:0]),
+              .WDATA_A2_i(in_reg[35:18]),
+              .RDATA_A1_o(fifo_flags),
+              .RDATA_A2_o(),
+              .ADDR_A1_i(14'h0),
+              .ADDR_A2_i(14'h0),
+              .CLK_A1_i(Push_Clk),
+              .CLK_A2_i(1'b0),
+              .REN_A1_i(1'b1),
+              .REN_A2_i(1'b0),
+              .WEN_A1_i(PUSH),
+              .WEN_A2_i(1'b0),
+              .BE_A1_i(2'b11),
+              .BE_A2_i(2'b11),
+          
+              .WDATA_B1_i(18'h0),
+              .WDATA_B2_i(18'h0),
+              .RDATA_B1_o(out_reg[17:0]),
+              .RDATA_B2_o(out_reg[35:18]),
+              .ADDR_B1_i(14'h0),
+              .ADDR_B2_i(14'h0),
+              .CLK_B1_i(Pop_Clk),
+              .CLK_B2_i(1'b0),
+              .REN_B1_i(POP),
+              .REN_B2_i(1'b0),
+              .WEN_B1_i(1'b0),
+              .WEN_B2_i(1'b0),
+              .BE_B1_i(2'b11),
+              .BE_B2_i(2'b11),
+          
+              .FLUSH1_i(Async_Flush),
+              .FLUSH2_i(1'b0)
+            );
+  
+			end
+			32, 36: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_9, MODE_36, MODE_9, MODE_36, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, MODE_9, MODE_36, MODE_9, MODE_36, 1'b0
+				};
+        
+            (* is_fifo = 1 *)
+            (* sync_fifo = 0 *)
+            (* rd_data_width = RD_DATA_WIDTH *) 
+            (* wr_data_width = WR_DATA_WIDTH *)
+            TDP36K U1 (
+              .RESET_ni(1'b1),
+              .WDATA_A1_i(in_reg[17:0]),
+              .WDATA_A2_i(in_reg[35:18]),
+              .RDATA_A1_o(fifo_flags),
+              .RDATA_A2_o(),
+              .ADDR_A1_i(14'h0),
+              .ADDR_A2_i(14'h0),
+              .CLK_A1_i(Push_Clk),
+              .CLK_A2_i(1'b0),
+              .REN_A1_i(1'b1),
+              .REN_A2_i(1'b0),
+              .WEN_A1_i(PUSH),
+              .WEN_A2_i(1'b0),
+              .BE_A1_i(2'b11),
+              .BE_A2_i(2'b11),
+          
+              .WDATA_B1_i(18'h0),
+              .WDATA_B2_i(18'h0),
+              .RDATA_B1_o(out_reg[17:0]),
+              .RDATA_B2_o(out_reg[35:18]),
+              .ADDR_B1_i(14'h0),
+              .ADDR_B2_i(14'h0),
+              .CLK_B1_i(Pop_Clk),
+              .CLK_B2_i(1'b0),
+              .REN_B1_i(POP),
+              .REN_B2_i(1'b0),
+              .WEN_B1_i(1'b0),
+              .WEN_B2_i(1'b0),
+              .BE_B1_i(2'b11),
+              .BE_B2_i(2'b11),
+          
+              .FLUSH1_i(Async_Flush),
+              .FLUSH2_i(1'b0)
+            );
+  
+			end
+			default: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_9, MODE_9, MODE_9, MODE_9, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, MODE_9, MODE_9, MODE_9, MODE_9, 1'b0
+				};
+        
+            (* is_fifo = 1 *)
+            (* sync_fifo = 0 *)
+            (* rd_data_width = RD_DATA_WIDTH *) 
+            (* wr_data_width = WR_DATA_WIDTH *)
+            TDP36K U1 (
+              .RESET_ni(1'b1),
+              .WDATA_A1_i(in_reg[17:0]),
+              .WDATA_A2_i(in_reg[35:18]),
+              .RDATA_A1_o(fifo_flags),
+              .RDATA_A2_o(),
+              .ADDR_A1_i(14'h0),
+              .ADDR_A2_i(14'h0),
+              .CLK_A1_i(Push_Clk),
+              .CLK_A2_i(1'b0),
+              .REN_A1_i(1'b1),
+              .REN_A2_i(1'b0),
+              .WEN_A1_i(PUSH),
+              .WEN_A2_i(1'b0),
+              .BE_A1_i(2'b11),
+              .BE_A2_i(2'b11),
+          
+              .WDATA_B1_i(18'h0),
+              .WDATA_B2_i(18'h0),
+              .RDATA_B1_o(out_reg[17:0]),
+              .RDATA_B2_o(out_reg[35:18]),
+              .ADDR_B1_i(14'h0),
+              .ADDR_B2_i(14'h0),
+              .CLK_B1_i(Pop_Clk),
+              .CLK_B2_i(1'b0),
+              .REN_B1_i(POP),
+              .REN_B2_i(1'b0),
+              .WEN_B1_i(1'b0),
+              .WEN_B2_i(1'b0),
+              .BE_B1_i(2'b11),
+              .BE_B2_i(2'b11),
+          
+              .FLUSH1_i(Async_Flush),
+              .FLUSH2_i(1'b0)
+            );
+  
+			end
+		endcase
+	end
+	16, 18: begin
+		case (WR_DATA_WIDTH)
+			8, 9: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_18, MODE_9, MODE_18, MODE_9, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, MODE_18, MODE_9, MODE_18, MODE_9, 1'b0
+				};
+        
+            (* is_fifo = 1 *)
+            (* sync_fifo = 0 *)
+            (* rd_data_width = RD_DATA_WIDTH *) 
+            (* wr_data_width = WR_DATA_WIDTH *)
+            TDP36K U1 (
+              .RESET_ni(1'b1),
+              .WDATA_A1_i(in_reg[17:0]),
+              .WDATA_A2_i(in_reg[35:18]),
+              .RDATA_A1_o(fifo_flags),
+              .RDATA_A2_o(),
+              .ADDR_A1_i(14'h0),
+              .ADDR_A2_i(14'h0),
+              .CLK_A1_i(Push_Clk),
+              .CLK_A2_i(1'b0),
+              .REN_A1_i(1'b1),
+              .REN_A2_i(1'b0),
+              .WEN_A1_i(PUSH),
+              .WEN_A2_i(1'b0),
+              .BE_A1_i(2'b11),
+              .BE_A2_i(2'b11),
+          
+              .WDATA_B1_i(18'h0),
+              .WDATA_B2_i(18'h0),
+              .RDATA_B1_o(out_reg[17:0]),
+              .RDATA_B2_o(out_reg[35:18]),
+              .ADDR_B1_i(14'h0),
+              .ADDR_B2_i(14'h0),
+              .CLK_B1_i(Pop_Clk),
+              .CLK_B2_i(1'b0),
+              .REN_B1_i(POP),
+              .REN_B2_i(1'b0),
+              .WEN_B1_i(1'b0),
+              .WEN_B2_i(1'b0),
+              .BE_B1_i(2'b11),
+              .BE_B2_i(2'b11),
+          
+              .FLUSH1_i(Async_Flush),
+              .FLUSH2_i(1'b0)
+            );
+  
+			end
+			16, 18: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_18, MODE_18, MODE_18, MODE_18, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, MODE_18, MODE_18, MODE_18, MODE_18, 1'b0
+				};
+        
+            (* is_fifo = 1 *)
+            (* sync_fifo = 0 *)
+            (* rd_data_width = RD_DATA_WIDTH *) 
+            (* wr_data_width = WR_DATA_WIDTH *)
+            TDP36K U1 (
+              .RESET_ni(1'b1),
+              .WDATA_A1_i(in_reg[17:0]),
+              .WDATA_A2_i(in_reg[35:18]),
+              .RDATA_A1_o(fifo_flags),
+              .RDATA_A2_o(),
+              .ADDR_A1_i(14'h0),
+              .ADDR_A2_i(14'h0),
+              .CLK_A1_i(Push_Clk),
+              .CLK_A2_i(1'b0),
+              .REN_A1_i(1'b1),
+              .REN_A2_i(1'b0),
+              .WEN_A1_i(PUSH),
+              .WEN_A2_i(1'b0),
+              .BE_A1_i(2'b11),
+              .BE_A2_i(2'b11),
+          
+              .WDATA_B1_i(18'h0),
+              .WDATA_B2_i(18'h0),
+              .RDATA_B1_o(out_reg[17:0]),
+              .RDATA_B2_o(out_reg[35:18]),
+              .ADDR_B1_i(14'h0),
+              .ADDR_B2_i(14'h0),
+              .CLK_B1_i(Pop_Clk),
+              .CLK_B2_i(1'b0),
+              .REN_B1_i(POP),
+              .REN_B2_i(1'b0),
+              .WEN_B1_i(1'b0),
+              .WEN_B2_i(1'b0),
+              .BE_B1_i(2'b11),
+              .BE_B2_i(2'b11),
+          
+              .FLUSH1_i(Async_Flush),
+              .FLUSH2_i(1'b0)
+            );
+  
+			end
+			32, 36: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_18, MODE_36, MODE_18, MODE_36, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, MODE_18, MODE_36, MODE_18, MODE_36, 1'b0
+				};
+        
+            (* is_fifo = 1 *)
+            (* sync_fifo = 0 *)
+            (* rd_data_width = RD_DATA_WIDTH *) 
+            (* wr_data_width = WR_DATA_WIDTH *)
+            TDP36K U1 (
+              .RESET_ni(1'b1),
+              .WDATA_A1_i(in_reg[17:0]),
+              .WDATA_A2_i(in_reg[35:18]),
+              .RDATA_A1_o(fifo_flags),
+              .RDATA_A2_o(),
+              .ADDR_A1_i(14'h0),
+              .ADDR_A2_i(14'h0),
+              .CLK_A1_i(Push_Clk),
+              .CLK_A2_i(1'b0),
+              .REN_A1_i(1'b1),
+              .REN_A2_i(1'b0),
+              .WEN_A1_i(PUSH),
+              .WEN_A2_i(1'b0),
+              .BE_A1_i(2'b11),
+              .BE_A2_i(2'b11),
+          
+              .WDATA_B1_i(18'h0),
+              .WDATA_B2_i(18'h0),
+              .RDATA_B1_o(out_reg[17:0]),
+              .RDATA_B2_o(out_reg[35:18]),
+              .ADDR_B1_i(14'h0),
+              .ADDR_B2_i(14'h0),
+              .CLK_B1_i(Pop_Clk),
+              .CLK_B2_i(1'b0),
+              .REN_B1_i(POP),
+              .REN_B2_i(1'b0),
+              .WEN_B1_i(1'b0),
+              .WEN_B2_i(1'b0),
+              .BE_B1_i(2'b11),
+              .BE_B2_i(2'b11),
+          
+              .FLUSH1_i(Async_Flush),
+              .FLUSH2_i(1'b0)
+            );
+  
+			end
+			default: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_18, MODE_18, MODE_18, MODE_18, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, MODE_18, MODE_18, MODE_18, MODE_18, 1'b0
+				};
+        
+            (* is_fifo = 1 *)
+            (* sync_fifo = 0 *)
+            (* rd_data_width = RD_DATA_WIDTH *) 
+            (* wr_data_width = WR_DATA_WIDTH *)
+            TDP36K U1 (
+              .RESET_ni(1'b1),
+              .WDATA_A1_i(in_reg[17:0]),
+              .WDATA_A2_i(in_reg[35:18]),
+              .RDATA_A1_o(fifo_flags),
+              .RDATA_A2_o(),
+              .ADDR_A1_i(14'h0),
+              .ADDR_A2_i(14'h0),
+              .CLK_A1_i(Push_Clk),
+              .CLK_A2_i(1'b0),
+              .REN_A1_i(1'b1),
+              .REN_A2_i(1'b0),
+              .WEN_A1_i(PUSH),
+              .WEN_A2_i(1'b0),
+              .BE_A1_i(2'b11),
+              .BE_A2_i(2'b11),
+          
+              .WDATA_B1_i(18'h0),
+              .WDATA_B2_i(18'h0),
+              .RDATA_B1_o(out_reg[17:0]),
+              .RDATA_B2_o(out_reg[35:18]),
+              .ADDR_B1_i(14'h0),
+              .ADDR_B2_i(14'h0),
+              .CLK_B1_i(Pop_Clk),
+              .CLK_B2_i(1'b0),
+              .REN_B1_i(POP),
+              .REN_B2_i(1'b0),
+              .WEN_B1_i(1'b0),
+              .WEN_B2_i(1'b0),
+              .BE_B1_i(2'b11),
+              .BE_B2_i(2'b11),
+          
+              .FLUSH1_i(Async_Flush),
+              .FLUSH2_i(1'b0)
+            );
+  
+			end
+		endcase
+	end
+	32, 36: begin
+		case (WR_DATA_WIDTH)
+			8, 9: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_36, MODE_9, MODE_36, MODE_9, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, MODE_36, MODE_9, MODE_36, MODE_9, 1'b0
+				};
+        
+            (* is_fifo = 1 *)
+            (* sync_fifo = 0 *)
+            (* rd_data_width = RD_DATA_WIDTH *) 
+            (* wr_data_width = WR_DATA_WIDTH *)
+            TDP36K U1 (
+              .RESET_ni(1'b1),
+              .WDATA_A1_i(in_reg[17:0]),
+              .WDATA_A2_i(in_reg[35:18]),
+              .RDATA_A1_o(fifo_flags),
+              .RDATA_A2_o(),
+              .ADDR_A1_i(14'h0),
+              .ADDR_A2_i(14'h0),
+              .CLK_A1_i(Push_Clk),
+              .CLK_A2_i(1'b0),
+              .REN_A1_i(1'b1),
+              .REN_A2_i(1'b0),
+              .WEN_A1_i(PUSH),
+              .WEN_A2_i(1'b0),
+              .BE_A1_i(2'b11),
+              .BE_A2_i(2'b11),
+          
+              .WDATA_B1_i(18'h0),
+              .WDATA_B2_i(18'h0),
+              .RDATA_B1_o(out_reg[17:0]),
+              .RDATA_B2_o(out_reg[35:18]),
+              .ADDR_B1_i(14'h0),
+              .ADDR_B2_i(14'h0),
+              .CLK_B1_i(Pop_Clk),
+              .CLK_B2_i(1'b0),
+              .REN_B1_i(POP),
+              .REN_B2_i(1'b0),
+              .WEN_B1_i(1'b0),
+              .WEN_B2_i(1'b0),
+              .BE_B1_i(2'b11),
+              .BE_B2_i(2'b11),
+          
+              .FLUSH1_i(Async_Flush),
+              .FLUSH2_i(1'b0)
+            );
+  
+			end
+			16, 18: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_36, MODE_18, MODE_36, MODE_18, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, MODE_36, MODE_18, MODE_36, MODE_18, 1'b0
+				};
+        
+            (* is_fifo = 1 *)
+            (* sync_fifo = 0 *)
+            (* rd_data_width = RD_DATA_WIDTH *) 
+            (* wr_data_width = WR_DATA_WIDTH *)
+            TDP36K U1 (
+              .RESET_ni(1'b1),
+              .WDATA_A1_i(in_reg[17:0]),
+              .WDATA_A2_i(in_reg[35:18]),
+              .RDATA_A1_o(fifo_flags),
+              .RDATA_A2_o(),
+              .ADDR_A1_i(14'h0),
+              .ADDR_A2_i(14'h0),
+              .CLK_A1_i(Push_Clk),
+              .CLK_A2_i(1'b0),
+              .REN_A1_i(1'b1),
+              .REN_A2_i(1'b0),
+              .WEN_A1_i(PUSH),
+              .WEN_A2_i(1'b0),
+              .BE_A1_i(2'b11),
+              .BE_A2_i(2'b11),
+          
+              .WDATA_B1_i(18'h0),
+              .WDATA_B2_i(18'h0),
+              .RDATA_B1_o(out_reg[17:0]),
+              .RDATA_B2_o(out_reg[35:18]),
+              .ADDR_B1_i(14'h0),
+              .ADDR_B2_i(14'h0),
+              .CLK_B1_i(Pop_Clk),
+              .CLK_B2_i(1'b0),
+              .REN_B1_i(POP),
+              .REN_B2_i(1'b0),
+              .WEN_B1_i(1'b0),
+              .WEN_B2_i(1'b0),
+              .BE_B1_i(2'b11),
+              .BE_B2_i(2'b11),
+          
+              .FLUSH1_i(Async_Flush),
+              .FLUSH2_i(1'b0)
+            );
+  
+			end
+			32, 36: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_36, MODE_36, MODE_36, MODE_36, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, MODE_36, MODE_36, MODE_36, MODE_36, 1'b0
+				};
+        
+            (* is_fifo = 1 *)
+            (* sync_fifo = 0 *)
+            (* rd_data_width = RD_DATA_WIDTH *) 
+            (* wr_data_width = WR_DATA_WIDTH *)
+            TDP36K U1 (
+              .RESET_ni(1'b1),
+              .WDATA_A1_i(in_reg[17:0]),
+              .WDATA_A2_i(in_reg[35:18]),
+              .RDATA_A1_o(fifo_flags),
+              .RDATA_A2_o(),
+              .ADDR_A1_i(14'h0),
+              .ADDR_A2_i(14'h0),
+              .CLK_A1_i(Push_Clk),
+              .CLK_A2_i(1'b0),
+              .REN_A1_i(1'b1),
+              .REN_A2_i(1'b0),
+              .WEN_A1_i(PUSH),
+              .WEN_A2_i(1'b0),
+              .BE_A1_i(2'b11),
+              .BE_A2_i(2'b11),
+          
+              .WDATA_B1_i(18'h0),
+              .WDATA_B2_i(18'h0),
+              .RDATA_B1_o(out_reg[17:0]),
+              .RDATA_B2_o(out_reg[35:18]),
+              .ADDR_B1_i(14'h0),
+              .ADDR_B2_i(14'h0),
+              .CLK_B1_i(Pop_Clk),
+              .CLK_B2_i(1'b0),
+              .REN_B1_i(POP),
+              .REN_B2_i(1'b0),
+              .WEN_B1_i(1'b0),
+              .WEN_B2_i(1'b0),
+              .BE_B1_i(2'b11),
+              .BE_B2_i(2'b11),
+          
+              .FLUSH1_i(Async_Flush),
+              .FLUSH2_i(1'b0)
+            );
+  
+			end
+			default: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_36, MODE_36, MODE_36, MODE_36, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, MODE_36, MODE_36, MODE_36, MODE_36, 1'b0
+				};
+        
+            (* is_fifo = 1 *)
+            (* sync_fifo = 0 *)
+            (* rd_data_width = RD_DATA_WIDTH *) 
+            (* wr_data_width = WR_DATA_WIDTH *)
+            TDP36K U1 (
+              .RESET_ni(1'b1),
+              .WDATA_A1_i(in_reg[17:0]),
+              .WDATA_A2_i(in_reg[35:18]),
+              .RDATA_A1_o(fifo_flags),
+              .RDATA_A2_o(),
+              .ADDR_A1_i(14'h0),
+              .ADDR_A2_i(14'h0),
+              .CLK_A1_i(Push_Clk),
+              .CLK_A2_i(1'b0),
+              .REN_A1_i(1'b1),
+              .REN_A2_i(1'b0),
+              .WEN_A1_i(PUSH),
+              .WEN_A2_i(1'b0),
+              .BE_A1_i(2'b11),
+              .BE_A2_i(2'b11),
+          
+              .WDATA_B1_i(18'h0),
+              .WDATA_B2_i(18'h0),
+              .RDATA_B1_o(out_reg[17:0]),
+              .RDATA_B2_o(out_reg[35:18]),
+              .ADDR_B1_i(14'h0),
+              .ADDR_B2_i(14'h0),
+              .CLK_B1_i(Pop_Clk),
+              .CLK_B2_i(1'b0),
+              .REN_B1_i(POP),
+              .REN_B2_i(1'b0),
+              .WEN_B1_i(1'b0),
+              .WEN_B2_i(1'b0),
+              .BE_B1_i(2'b11),
+              .BE_B2_i(2'b11),
+          
+              .FLUSH1_i(Async_Flush),
+              .FLUSH2_i(1'b0)
+            );
+  
+			end
+		endcase
+	end
+	default: begin
+		case (WR_DATA_WIDTH)
+			8, 9: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_9, MODE_9, MODE_9, MODE_9, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, MODE_9, MODE_9, MODE_9, MODE_9, 1'b0
+				};
+        
+            (* is_fifo = 1 *)
+            (* sync_fifo = 0 *)
+            (* rd_data_width = RD_DATA_WIDTH *) 
+            (* wr_data_width = WR_DATA_WIDTH *)
+            TDP36K U1 (
+              .RESET_ni(1'b1),
+              .WDATA_A1_i(in_reg[17:0]),
+              .WDATA_A2_i(in_reg[35:18]),
+              .RDATA_A1_o(fifo_flags),
+              .RDATA_A2_o(),
+              .ADDR_A1_i(14'h0),
+              .ADDR_A2_i(14'h0),
+              .CLK_A1_i(Push_Clk),
+              .CLK_A2_i(1'b0),
+              .REN_A1_i(1'b1),
+              .REN_A2_i(1'b0),
+              .WEN_A1_i(PUSH),
+              .WEN_A2_i(1'b0),
+              .BE_A1_i(2'b11),
+              .BE_A2_i(2'b11),
+          
+              .WDATA_B1_i(18'h0),
+              .WDATA_B2_i(18'h0),
+              .RDATA_B1_o(out_reg[17:0]),
+              .RDATA_B2_o(out_reg[35:18]),
+              .ADDR_B1_i(14'h0),
+              .ADDR_B2_i(14'h0),
+              .CLK_B1_i(Pop_Clk),
+              .CLK_B2_i(1'b0),
+              .REN_B1_i(POP),
+              .REN_B2_i(1'b0),
+              .WEN_B1_i(1'b0),
+              .WEN_B2_i(1'b0),
+              .BE_B1_i(2'b11),
+              .BE_B2_i(2'b11),
+          
+              .FLUSH1_i(Async_Flush),
+              .FLUSH2_i(1'b0)
+            );
+  
+			end
+			16, 18: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_18, MODE_18, MODE_18, MODE_18, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, MODE_18, MODE_18, MODE_18, MODE_18, 1'b0
+				};
+        
+            (* is_fifo = 1 *)
+            (* sync_fifo = 0 *)
+            (* rd_data_width = RD_DATA_WIDTH *) 
+            (* wr_data_width = WR_DATA_WIDTH *)
+            TDP36K U1 (
+              .RESET_ni(1'b1),
+              .WDATA_A1_i(in_reg[17:0]),
+              .WDATA_A2_i(in_reg[35:18]),
+              .RDATA_A1_o(fifo_flags),
+              .RDATA_A2_o(),
+              .ADDR_A1_i(14'h0),
+              .ADDR_A2_i(14'h0),
+              .CLK_A1_i(Push_Clk),
+              .CLK_A2_i(1'b0),
+              .REN_A1_i(1'b1),
+              .REN_A2_i(1'b0),
+              .WEN_A1_i(PUSH),
+              .WEN_A2_i(1'b0),
+              .BE_A1_i(2'b11),
+              .BE_A2_i(2'b11),
+          
+              .WDATA_B1_i(18'h0),
+              .WDATA_B2_i(18'h0),
+              .RDATA_B1_o(out_reg[17:0]),
+              .RDATA_B2_o(out_reg[35:18]),
+              .ADDR_B1_i(14'h0),
+              .ADDR_B2_i(14'h0),
+              .CLK_B1_i(Pop_Clk),
+              .CLK_B2_i(1'b0),
+              .REN_B1_i(POP),
+              .REN_B2_i(1'b0),
+              .WEN_B1_i(1'b0),
+              .WEN_B2_i(1'b0),
+              .BE_B1_i(2'b11),
+              .BE_B2_i(2'b11),
+          
+              .FLUSH1_i(Async_Flush),
+              .FLUSH2_i(1'b0)
+            );
+  
+			end
+			32, 36: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_36, MODE_36, MODE_36, MODE_36, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, MODE_36, MODE_36, MODE_36, MODE_36, 1'b0
+				};
+        
+            (* is_fifo = 1 *)
+            (* sync_fifo = 0 *)
+            (* rd_data_width = RD_DATA_WIDTH *) 
+            (* wr_data_width = WR_DATA_WIDTH *)
+            TDP36K U1 (
+              .RESET_ni(1'b1),
+              .WDATA_A1_i(in_reg[17:0]),
+              .WDATA_A2_i(in_reg[35:18]),
+              .RDATA_A1_o(fifo_flags),
+              .RDATA_A2_o(),
+              .ADDR_A1_i(14'h0),
+              .ADDR_A2_i(14'h0),
+              .CLK_A1_i(Push_Clk),
+              .CLK_A2_i(1'b0),
+              .REN_A1_i(1'b1),
+              .REN_A2_i(1'b0),
+              .WEN_A1_i(PUSH),
+              .WEN_A2_i(1'b0),
+              .BE_A1_i(2'b11),
+              .BE_A2_i(2'b11),
+          
+              .WDATA_B1_i(18'h0),
+              .WDATA_B2_i(18'h0),
+              .RDATA_B1_o(out_reg[17:0]),
+              .RDATA_B2_o(out_reg[35:18]),
+              .ADDR_B1_i(14'h0),
+              .ADDR_B2_i(14'h0),
+              .CLK_B1_i(Pop_Clk),
+              .CLK_B2_i(1'b0),
+              .REN_B1_i(POP),
+              .REN_B2_i(1'b0),
+              .WEN_B1_i(1'b0),
+              .WEN_B2_i(1'b0),
+              .BE_B1_i(2'b11),
+              .BE_B2_i(2'b11),
+          
+              .FLUSH1_i(Async_Flush),
+              .FLUSH2_i(1'b0)
+            );
+  
+			end
+			default: begin
+				defparam U1.MODE_BITS = { 1'b0,
+					11'd10, 11'd10, 4'd0, MODE_36, MODE_36, MODE_36, MODE_36, 1'd0,
+					UPAF_DBITS, UPAE_DBITS, 4'h1, MODE_36, MODE_36, MODE_36, MODE_36, 1'b0
+				};
+        
+            (* is_fifo = 1 *)
+            (* sync_fifo = 0 *)
+            (* rd_data_width = RD_DATA_WIDTH *) 
+            (* wr_data_width = WR_DATA_WIDTH *)
+            TDP36K U1 (
+              .RESET_ni(1'b1),
+              .WDATA_A1_i(in_reg[17:0]),
+              .WDATA_A2_i(in_reg[35:18]),
+              .RDATA_A1_o(fifo_flags),
+              .RDATA_A2_o(),
+              .ADDR_A1_i(14'h0),
+              .ADDR_A2_i(14'h0),
+              .CLK_A1_i(Push_Clk),
+              .CLK_A2_i(1'b0),
+              .REN_A1_i(1'b1),
+              .REN_A2_i(1'b0),
+              .WEN_A1_i(PUSH),
+              .WEN_A2_i(1'b0),
+              .BE_A1_i(2'b11),
+              .BE_A2_i(2'b11),
+          
+              .WDATA_B1_i(18'h0),
+              .WDATA_B2_i(18'h0),
+              .RDATA_B1_o(out_reg[17:0]),
+              .RDATA_B2_o(out_reg[35:18]),
+              .ADDR_B1_i(14'h0),
+              .ADDR_B2_i(14'h0),
+              .CLK_B1_i(Pop_Clk),
+              .CLK_B2_i(1'b0),
+              .REN_B1_i(POP),
+              .REN_B2_i(1'b0),
+              .WEN_B1_i(1'b0),
+              .WEN_B2_i(1'b0),
+              .BE_B1_i(2'b11),
+              .BE_B2_i(2'b11),
+          
+              .FLUSH1_i(Async_Flush),
+              .FLUSH2_i(1'b0)
+            );
+  
+			end
+		endcase
+	end
+ endcase
+
+  assign DOUT[RD_DATA_WIDTH-1 : 0] = RD_DATA_CMPL[RD_DATA_WIDTH-1 : 0];
+
+endmodule  
+
+//===============================================================================
+module TDP36K_FIFO_ASYNC_WR_X9_RD_X9_nonsplit (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input wire  RESET_ni;
+    input wire  WEN_A1_i, WEN_B1_i;
+    input wire  REN_A1_i, REN_B1_i;
+    input wire  WEN_A2_i, WEN_B2_i;
+    input wire  REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input wire  CLK_A1_i;
+    (* clkbuf_sink *)
+    input wire  CLK_B1_i;
+    (* clkbuf_sink *)
+    input wire  CLK_A2_i;
+    (* clkbuf_sink *)
+    input wire  CLK_B2_i;
+
+    input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+    input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input wire  FLUSH1_i;
+
+    input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+    input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input wire  FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+    
+`ifdef SDF_SIM
+	specify
+    (FLUSH1_i => RDATA_A1_o[0]) = 0;
+    (FLUSH1_i => RDATA_A1_o[1]) = 0;
+    (FLUSH1_i => RDATA_A1_o[2]) = 0;
+    (FLUSH1_i => RDATA_A1_o[3]) = 0;
+    (FLUSH1_i => RDATA_A1_o[4]) = 0;
+    (FLUSH1_i => RDATA_A1_o[5]) = 0;
+    (FLUSH1_i => RDATA_A1_o[6]) = 0;
+    (FLUSH1_i => RDATA_A1_o[7]) = 0;
+    (FLUSH2_i => RDATA_A2_o[0]) = 0;
+    (FLUSH2_i => RDATA_A2_o[1]) = 0;
+    (FLUSH2_i => RDATA_A2_o[2]) = 0;
+    (FLUSH2_i => RDATA_A2_o[3]) = 0;
+    (FLUSH2_i => RDATA_A2_o[4]) = 0;
+    (FLUSH2_i => RDATA_A2_o[5]) = 0;
+    (FLUSH2_i => RDATA_A2_o[6]) = 0;
+    (FLUSH2_i => RDATA_A2_o[7]) = 0;    
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_ASYNC_WR_X9_RD_X18_nonsplit (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input wire  RESET_ni;
+    input wire  WEN_A1_i, WEN_B1_i;
+    input wire  REN_A1_i, REN_B1_i;
+    input wire  WEN_A2_i, WEN_B2_i;
+    input wire  REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input wire  CLK_A1_i;
+    (* clkbuf_sink *)
+    input wire  CLK_B1_i;
+    (* clkbuf_sink *)
+    input wire  CLK_A2_i;
+    (* clkbuf_sink *)
+    input wire  CLK_B2_i;
+
+    input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+    input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input wire  FLUSH1_i;
+
+    input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+    input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input wire  FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+ 
+`ifdef SDF_SIM
+	specify
+    (FLUSH1_i => RDATA_A1_o[0]) = 0;
+    (FLUSH1_i => RDATA_A1_o[1]) = 0;
+    (FLUSH1_i => RDATA_A1_o[2]) = 0;
+    (FLUSH1_i => RDATA_A1_o[3]) = 0;
+    (FLUSH1_i => RDATA_A1_o[4]) = 0;
+    (FLUSH1_i => RDATA_A1_o[5]) = 0;
+    (FLUSH1_i => RDATA_A1_o[6]) = 0;
+    (FLUSH1_i => RDATA_A1_o[7]) = 0;
+    (FLUSH2_i => RDATA_A2_o[0]) = 0;
+    (FLUSH2_i => RDATA_A2_o[1]) = 0;
+    (FLUSH2_i => RDATA_A2_o[2]) = 0;
+    (FLUSH2_i => RDATA_A2_o[3]) = 0;
+    (FLUSH2_i => RDATA_A2_o[4]) = 0;
+    (FLUSH2_i => RDATA_A2_o[5]) = 0;
+    (FLUSH2_i => RDATA_A2_o[6]) = 0;
+    (FLUSH2_i => RDATA_A2_o[7]) = 0;    
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_ASYNC_WR_X9_RD_X36_nonsplit (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input wire  RESET_ni;
+    input wire  WEN_A1_i, WEN_B1_i;
+    input wire  REN_A1_i, REN_B1_i;
+    input wire  WEN_A2_i, WEN_B2_i;
+    input wire  REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input wire  CLK_A1_i;
+    (* clkbuf_sink *)
+    input wire  CLK_B1_i;
+    (* clkbuf_sink *)
+    input wire  CLK_A2_i;
+    (* clkbuf_sink *)
+    input wire  CLK_B2_i;
+
+    input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+    input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input wire  FLUSH1_i;
+
+    input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+    input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input wire  FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+    
+`ifdef SDF_SIM
+	specify
+    (FLUSH1_i => RDATA_A1_o[0]) = 0;
+    (FLUSH1_i => RDATA_A1_o[1]) = 0;
+    (FLUSH1_i => RDATA_A1_o[2]) = 0;
+    (FLUSH1_i => RDATA_A1_o[3]) = 0;
+    (FLUSH1_i => RDATA_A1_o[4]) = 0;
+    (FLUSH1_i => RDATA_A1_o[5]) = 0;
+    (FLUSH1_i => RDATA_A1_o[6]) = 0;
+    (FLUSH1_i => RDATA_A1_o[7]) = 0;
+    (FLUSH2_i => RDATA_A2_o[0]) = 0;
+    (FLUSH2_i => RDATA_A2_o[1]) = 0;
+    (FLUSH2_i => RDATA_A2_o[2]) = 0;
+    (FLUSH2_i => RDATA_A2_o[3]) = 0;
+    (FLUSH2_i => RDATA_A2_o[4]) = 0;
+    (FLUSH2_i => RDATA_A2_o[5]) = 0;
+    (FLUSH2_i => RDATA_A2_o[6]) = 0;
+    (FLUSH2_i => RDATA_A2_o[7]) = 0;    
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_ASYNC_WR_X18_RD_X9_nonsplit (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input wire  RESET_ni;
+    input wire  WEN_A1_i, WEN_B1_i;
+    input wire  REN_A1_i, REN_B1_i;
+    input wire  WEN_A2_i, WEN_B2_i;
+    input wire  REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input wire  CLK_A1_i;
+    (* clkbuf_sink *)
+    input wire  CLK_B1_i;
+    (* clkbuf_sink *)
+    input wire  CLK_A2_i;
+    (* clkbuf_sink *)
+    input wire  CLK_B2_i;
+
+    input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+    input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input wire  FLUSH1_i;
+
+    input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+    input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input wire  FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+    
+`ifdef SDF_SIM
+	specify
+    (FLUSH1_i => RDATA_A1_o[0]) = 0;
+    (FLUSH1_i => RDATA_A1_o[1]) = 0;
+    (FLUSH1_i => RDATA_A1_o[2]) = 0;
+    (FLUSH1_i => RDATA_A1_o[3]) = 0;
+    (FLUSH1_i => RDATA_A1_o[4]) = 0;
+    (FLUSH1_i => RDATA_A1_o[5]) = 0;
+    (FLUSH1_i => RDATA_A1_o[6]) = 0;
+    (FLUSH1_i => RDATA_A1_o[7]) = 0;
+    (FLUSH2_i => RDATA_A2_o[0]) = 0;
+    (FLUSH2_i => RDATA_A2_o[1]) = 0;
+    (FLUSH2_i => RDATA_A2_o[2]) = 0;
+    (FLUSH2_i => RDATA_A2_o[3]) = 0;
+    (FLUSH2_i => RDATA_A2_o[4]) = 0;
+    (FLUSH2_i => RDATA_A2_o[5]) = 0;
+    (FLUSH2_i => RDATA_A2_o[6]) = 0;
+    (FLUSH2_i => RDATA_A2_o[7]) = 0;    
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_ASYNC_WR_X18_RD_X18_nonsplit (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input wire  RESET_ni;
+    input wire  WEN_A1_i, WEN_B1_i;
+    input wire  REN_A1_i, REN_B1_i;
+    input wire  WEN_A2_i, WEN_B2_i;
+    input wire  REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input wire  CLK_A1_i;
+    (* clkbuf_sink *)
+    input wire  CLK_B1_i;
+    (* clkbuf_sink *)
+    input wire  CLK_A2_i;
+    (* clkbuf_sink *)
+    input wire  CLK_B2_i;
+
+    input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+    input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input wire  FLUSH1_i;
+
+    input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+    input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input wire  FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+    
+`ifdef SDF_SIM
+	specify
+    (FLUSH1_i => RDATA_A1_o[0]) = 0;
+    (FLUSH1_i => RDATA_A1_o[1]) = 0;
+    (FLUSH1_i => RDATA_A1_o[2]) = 0;
+    (FLUSH1_i => RDATA_A1_o[3]) = 0;
+    (FLUSH1_i => RDATA_A1_o[4]) = 0;
+    (FLUSH1_i => RDATA_A1_o[5]) = 0;
+    (FLUSH1_i => RDATA_A1_o[6]) = 0;
+    (FLUSH1_i => RDATA_A1_o[7]) = 0;
+    (FLUSH2_i => RDATA_A2_o[0]) = 0;
+    (FLUSH2_i => RDATA_A2_o[1]) = 0;
+    (FLUSH2_i => RDATA_A2_o[2]) = 0;
+    (FLUSH2_i => RDATA_A2_o[3]) = 0;
+    (FLUSH2_i => RDATA_A2_o[4]) = 0;
+    (FLUSH2_i => RDATA_A2_o[5]) = 0;
+    (FLUSH2_i => RDATA_A2_o[6]) = 0;
+    (FLUSH2_i => RDATA_A2_o[7]) = 0;    
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_ASYNC_WR_X18_RD_X36_nonsplit (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input wire  RESET_ni;
+    input wire  WEN_A1_i, WEN_B1_i;
+    input wire  REN_A1_i, REN_B1_i;
+    input wire  WEN_A2_i, WEN_B2_i;
+    input wire  REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input wire  CLK_A1_i;
+    (* clkbuf_sink *)
+    input wire  CLK_B1_i;
+    (* clkbuf_sink *)
+    input wire  CLK_A2_i;
+    (* clkbuf_sink *)
+    input wire  CLK_B2_i;
+
+    input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+    input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input wire  FLUSH1_i;
+
+    input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+    input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input wire  FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+    
+`ifdef SDF_SIM
+	specify
+    (FLUSH1_i => RDATA_A1_o[0]) = 0;
+    (FLUSH1_i => RDATA_A1_o[1]) = 0;
+    (FLUSH1_i => RDATA_A1_o[2]) = 0;
+    (FLUSH1_i => RDATA_A1_o[3]) = 0;
+    (FLUSH1_i => RDATA_A1_o[4]) = 0;
+    (FLUSH1_i => RDATA_A1_o[5]) = 0;
+    (FLUSH1_i => RDATA_A1_o[6]) = 0;
+    (FLUSH1_i => RDATA_A1_o[7]) = 0;
+    (FLUSH2_i => RDATA_A2_o[0]) = 0;
+    (FLUSH2_i => RDATA_A2_o[1]) = 0;
+    (FLUSH2_i => RDATA_A2_o[2]) = 0;
+    (FLUSH2_i => RDATA_A2_o[3]) = 0;
+    (FLUSH2_i => RDATA_A2_o[4]) = 0;
+    (FLUSH2_i => RDATA_A2_o[5]) = 0;
+    (FLUSH2_i => RDATA_A2_o[6]) = 0;
+    (FLUSH2_i => RDATA_A2_o[7]) = 0;    
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_ASYNC_WR_X36_RD_X9_nonsplit (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input wire  RESET_ni;
+    input wire  WEN_A1_i, WEN_B1_i;
+    input wire  REN_A1_i, REN_B1_i;
+    input wire  WEN_A2_i, WEN_B2_i;
+    input wire  REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input wire  CLK_A1_i;
+    (* clkbuf_sink *)
+    input wire  CLK_B1_i;
+    (* clkbuf_sink *)
+    input wire  CLK_A2_i;
+    (* clkbuf_sink *)
+    input wire  CLK_B2_i;
+
+    input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+    input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input wire  FLUSH1_i;
+
+    input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+    input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input wire  FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+    
+`ifdef SDF_SIM
+	specify
+    (FLUSH1_i => RDATA_A1_o[0]) = 0;
+    (FLUSH1_i => RDATA_A1_o[1]) = 0;
+    (FLUSH1_i => RDATA_A1_o[2]) = 0;
+    (FLUSH1_i => RDATA_A1_o[3]) = 0;
+    (FLUSH1_i => RDATA_A1_o[4]) = 0;
+    (FLUSH1_i => RDATA_A1_o[5]) = 0;
+    (FLUSH1_i => RDATA_A1_o[6]) = 0;
+    (FLUSH1_i => RDATA_A1_o[7]) = 0;
+    (FLUSH2_i => RDATA_A2_o[0]) = 0;
+    (FLUSH2_i => RDATA_A2_o[1]) = 0;
+    (FLUSH2_i => RDATA_A2_o[2]) = 0;
+    (FLUSH2_i => RDATA_A2_o[3]) = 0;
+    (FLUSH2_i => RDATA_A2_o[4]) = 0;
+    (FLUSH2_i => RDATA_A2_o[5]) = 0;
+    (FLUSH2_i => RDATA_A2_o[6]) = 0;
+    (FLUSH2_i => RDATA_A2_o[7]) = 0;    
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_ASYNC_WR_X36_RD_X18_nonsplit (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input wire  RESET_ni;
+    input wire  WEN_A1_i, WEN_B1_i;
+    input wire  REN_A1_i, REN_B1_i;
+    input wire  WEN_A2_i, WEN_B2_i;
+    input wire  REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input wire  CLK_A1_i;
+    (* clkbuf_sink *)
+    input wire  CLK_B1_i;
+    (* clkbuf_sink *)
+    input wire  CLK_A2_i;
+    (* clkbuf_sink *)
+    input wire  CLK_B2_i;
+
+    input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+    input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input wire  FLUSH1_i;
+
+    input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+    input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input wire  FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+    
+`ifdef SDF_SIM
+	specify
+    (FLUSH1_i => RDATA_A1_o[0]) = 0;
+    (FLUSH1_i => RDATA_A1_o[1]) = 0;
+    (FLUSH1_i => RDATA_A1_o[2]) = 0;
+    (FLUSH1_i => RDATA_A1_o[3]) = 0;
+    (FLUSH1_i => RDATA_A1_o[4]) = 0;
+    (FLUSH1_i => RDATA_A1_o[5]) = 0;
+    (FLUSH1_i => RDATA_A1_o[6]) = 0;
+    (FLUSH1_i => RDATA_A1_o[7]) = 0;
+    (FLUSH2_i => RDATA_A2_o[0]) = 0;
+    (FLUSH2_i => RDATA_A2_o[1]) = 0;
+    (FLUSH2_i => RDATA_A2_o[2]) = 0;
+    (FLUSH2_i => RDATA_A2_o[3]) = 0;
+    (FLUSH2_i => RDATA_A2_o[4]) = 0;
+    (FLUSH2_i => RDATA_A2_o[5]) = 0;
+    (FLUSH2_i => RDATA_A2_o[6]) = 0;
+    (FLUSH2_i => RDATA_A2_o[7]) = 0;    
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_ASYNC_WR_X36_RD_X36_nonsplit (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input wire  RESET_ni;
+    input wire  WEN_A1_i, WEN_B1_i;
+    input wire  REN_A1_i, REN_B1_i;
+    input wire  WEN_A2_i, WEN_B2_i;
+    input wire  REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input wire  CLK_A1_i;
+    (* clkbuf_sink *)
+    input wire  CLK_B1_i;
+    (* clkbuf_sink *)
+    input wire  CLK_A2_i;
+    (* clkbuf_sink *)
+    input wire  CLK_B2_i;
+
+    input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+    input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input wire  FLUSH1_i;
+
+    input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+    input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input wire  FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+    
+`ifdef SDF_SIM
+	specify
+    (FLUSH1_i => RDATA_A1_o[0]) = 0;
+    (FLUSH1_i => RDATA_A1_o[1]) = 0;
+    (FLUSH1_i => RDATA_A1_o[2]) = 0;
+    (FLUSH1_i => RDATA_A1_o[3]) = 0;
+    (FLUSH1_i => RDATA_A1_o[4]) = 0;
+    (FLUSH1_i => RDATA_A1_o[5]) = 0;
+    (FLUSH1_i => RDATA_A1_o[6]) = 0;
+    (FLUSH1_i => RDATA_A1_o[7]) = 0;
+    (FLUSH2_i => RDATA_A2_o[0]) = 0;
+    (FLUSH2_i => RDATA_A2_o[1]) = 0;
+    (FLUSH2_i => RDATA_A2_o[2]) = 0;
+    (FLUSH2_i => RDATA_A2_o[3]) = 0;
+    (FLUSH2_i => RDATA_A2_o[4]) = 0;
+    (FLUSH2_i => RDATA_A2_o[5]) = 0;
+    (FLUSH2_i => RDATA_A2_o[6]) = 0;
+    (FLUSH2_i => RDATA_A2_o[7]) = 0;    
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+
+module TDP36K_FIFO_ASYNC_WR_X9_RD_X9_split (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input wire  RESET_ni;
+    input wire  WEN_A1_i, WEN_B1_i;
+    input wire  REN_A1_i, REN_B1_i;
+    input wire  WEN_A2_i, WEN_B2_i;
+    input wire  REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input wire  CLK_A1_i;
+    (* clkbuf_sink *)
+    input wire  CLK_B1_i;
+    (* clkbuf_sink *)
+    input wire  CLK_A2_i;
+    (* clkbuf_sink *)
+    input wire  CLK_B2_i;
+
+    input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+    input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input wire  FLUSH1_i;
+
+    input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+    input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input wire  FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+   
+`ifdef SDF_SIM
+	specify
+    (FLUSH1_i => RDATA_A1_o[0]) = 0;
+    (FLUSH1_i => RDATA_A1_o[1]) = 0;
+    (FLUSH1_i => RDATA_A1_o[2]) = 0;
+    (FLUSH1_i => RDATA_A1_o[3]) = 0;
+    (FLUSH1_i => RDATA_A1_o[4]) = 0;
+    (FLUSH1_i => RDATA_A1_o[5]) = 0;
+    (FLUSH1_i => RDATA_A1_o[6]) = 0;
+    (FLUSH1_i => RDATA_A1_o[7]) = 0;
+    (FLUSH2_i => RDATA_A2_o[0]) = 0;
+    (FLUSH2_i => RDATA_A2_o[1]) = 0;
+    (FLUSH2_i => RDATA_A2_o[2]) = 0;
+    (FLUSH2_i => RDATA_A2_o[3]) = 0;
+    (FLUSH2_i => RDATA_A2_o[4]) = 0;
+    (FLUSH2_i => RDATA_A2_o[5]) = 0;
+    (FLUSH2_i => RDATA_A2_o[6]) = 0;
+    (FLUSH2_i => RDATA_A2_o[7]) = 0;    
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_ASYNC_WR_X9_RD_X18_split (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input wire  RESET_ni;
+    input wire  WEN_A1_i, WEN_B1_i;
+    input wire  REN_A1_i, REN_B1_i;
+    input wire  WEN_A2_i, WEN_B2_i;
+    input wire  REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input wire  CLK_A1_i;
+    (* clkbuf_sink *)
+    input wire  CLK_B1_i;
+    (* clkbuf_sink *)
+    input wire  CLK_A2_i;
+    (* clkbuf_sink *)
+    input wire  CLK_B2_i;
+
+    input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+    input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input wire  FLUSH1_i;
+
+    input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+    input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input wire  FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+    
+`ifdef SDF_SIM
+	specify
+    (FLUSH1_i => RDATA_A1_o[0]) = 0;
+    (FLUSH1_i => RDATA_A1_o[1]) = 0;
+    (FLUSH1_i => RDATA_A1_o[2]) = 0;
+    (FLUSH1_i => RDATA_A1_o[3]) = 0;
+    (FLUSH1_i => RDATA_A1_o[4]) = 0;
+    (FLUSH1_i => RDATA_A1_o[5]) = 0;
+    (FLUSH1_i => RDATA_A1_o[6]) = 0;
+    (FLUSH1_i => RDATA_A1_o[7]) = 0;
+    (FLUSH2_i => RDATA_A2_o[0]) = 0;
+    (FLUSH2_i => RDATA_A2_o[1]) = 0;
+    (FLUSH2_i => RDATA_A2_o[2]) = 0;
+    (FLUSH2_i => RDATA_A2_o[3]) = 0;
+    (FLUSH2_i => RDATA_A2_o[4]) = 0;
+    (FLUSH2_i => RDATA_A2_o[5]) = 0;
+    (FLUSH2_i => RDATA_A2_o[6]) = 0;
+    (FLUSH2_i => RDATA_A2_o[7]) = 0;    
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_ASYNC_WR_X18_RD_X9_split (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input wire  RESET_ni;
+    input wire  WEN_A1_i, WEN_B1_i;
+    input wire  REN_A1_i, REN_B1_i;
+    input wire  WEN_A2_i, WEN_B2_i;
+    input wire  REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input wire  CLK_A1_i;
+    (* clkbuf_sink *)
+    input wire  CLK_B1_i;
+    (* clkbuf_sink *)
+    input wire  CLK_A2_i;
+    (* clkbuf_sink *)
+    input wire  CLK_B2_i;
+
+    input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+    input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input wire  FLUSH1_i;
+
+    input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+    input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input wire  FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+    (FLUSH1_i => RDATA_A1_o[0]) = 0;
+    (FLUSH1_i => RDATA_A1_o[1]) = 0;
+    (FLUSH1_i => RDATA_A1_o[2]) = 0;
+    (FLUSH1_i => RDATA_A1_o[3]) = 0;
+    (FLUSH1_i => RDATA_A1_o[4]) = 0;
+    (FLUSH1_i => RDATA_A1_o[5]) = 0;
+    (FLUSH1_i => RDATA_A1_o[6]) = 0;
+    (FLUSH1_i => RDATA_A1_o[7]) = 0;
+    (FLUSH2_i => RDATA_A2_o[0]) = 0;
+    (FLUSH2_i => RDATA_A2_o[1]) = 0;
+    (FLUSH2_i => RDATA_A2_o[2]) = 0;
+    (FLUSH2_i => RDATA_A2_o[3]) = 0;
+    (FLUSH2_i => RDATA_A2_o[4]) = 0;
+    (FLUSH2_i => RDATA_A2_o[5]) = 0;
+    (FLUSH2_i => RDATA_A2_o[6]) = 0;
+    (FLUSH2_i => RDATA_A2_o[7]) = 0;    
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_ASYNC_WR_X18_RD_X18_split (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input wire  RESET_ni;
+    input wire  WEN_A1_i, WEN_B1_i;
+    input wire  REN_A1_i, REN_B1_i;
+    input wire  WEN_A2_i, WEN_B2_i;
+    input wire  REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input wire  CLK_A1_i;
+    (* clkbuf_sink *)
+    input wire  CLK_B1_i;
+    (* clkbuf_sink *)
+    input wire  CLK_A2_i;
+    (* clkbuf_sink *)
+    input wire  CLK_B2_i;
+
+    input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+    input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input wire  FLUSH1_i;
+
+    input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+    input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input wire  FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+    (FLUSH1_i => RDATA_A1_o[0]) = 0;
+    (FLUSH1_i => RDATA_A1_o[1]) = 0;
+    (FLUSH1_i => RDATA_A1_o[2]) = 0;
+    (FLUSH1_i => RDATA_A1_o[3]) = 0;
+    (FLUSH1_i => RDATA_A1_o[4]) = 0;
+    (FLUSH1_i => RDATA_A1_o[5]) = 0;
+    (FLUSH1_i => RDATA_A1_o[6]) = 0;
+    (FLUSH1_i => RDATA_A1_o[7]) = 0;
+    (FLUSH2_i => RDATA_A2_o[0]) = 0;
+    (FLUSH2_i => RDATA_A2_o[1]) = 0;
+    (FLUSH2_i => RDATA_A2_o[2]) = 0;
+    (FLUSH2_i => RDATA_A2_o[3]) = 0;
+    (FLUSH2_i => RDATA_A2_o[4]) = 0;
+    (FLUSH2_i => RDATA_A2_o[5]) = 0;
+    (FLUSH2_i => RDATA_A2_o[6]) = 0;
+    (FLUSH2_i => RDATA_A2_o[7]) = 0;    
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_SYNC_WR_X9_RD_X9_nonsplit (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input wire  RESET_ni;
+    input wire  WEN_A1_i, WEN_B1_i;
+    input wire  REN_A1_i, REN_B1_i;
+    input wire  WEN_A2_i, WEN_B2_i;
+    input wire  REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input wire  CLK_A1_i;
+    (* clkbuf_sink *)
+    input wire  CLK_B1_i;
+    (* clkbuf_sink *)
+    input wire  CLK_A2_i;
+    (* clkbuf_sink *)
+    input wire  CLK_B2_i;
+
+    input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+    input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input wire  FLUSH1_i;
+
+    input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+    input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input wire  FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+    
+`ifdef SDF_SIM
+	specify
+    (FLUSH1_i => RDATA_A1_o[0]) = 0;
+    (FLUSH1_i => RDATA_A1_o[1]) = 0;
+    (FLUSH1_i => RDATA_A1_o[2]) = 0;
+    (FLUSH1_i => RDATA_A1_o[3]) = 0;
+    (FLUSH1_i => RDATA_A1_o[4]) = 0;
+    (FLUSH1_i => RDATA_A1_o[5]) = 0;
+    (FLUSH1_i => RDATA_A1_o[6]) = 0;
+    (FLUSH1_i => RDATA_A1_o[7]) = 0;
+    (FLUSH2_i => RDATA_A2_o[0]) = 0;
+    (FLUSH2_i => RDATA_A2_o[1]) = 0;
+    (FLUSH2_i => RDATA_A2_o[2]) = 0;
+    (FLUSH2_i => RDATA_A2_o[3]) = 0;
+    (FLUSH2_i => RDATA_A2_o[4]) = 0;
+    (FLUSH2_i => RDATA_A2_o[5]) = 0;
+    (FLUSH2_i => RDATA_A2_o[6]) = 0;
+    (FLUSH2_i => RDATA_A2_o[7]) = 0;    
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_SYNC_WR_X9_RD_X18_nonsplit (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input wire  RESET_ni;
+    input wire  WEN_A1_i, WEN_B1_i;
+    input wire  REN_A1_i, REN_B1_i;
+    input wire  WEN_A2_i, WEN_B2_i;
+    input wire  REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input wire  CLK_A1_i;
+    (* clkbuf_sink *)
+    input wire  CLK_B1_i;
+    (* clkbuf_sink *)
+    input wire  CLK_A2_i;
+    (* clkbuf_sink *)
+    input wire  CLK_B2_i;
+
+    input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+    input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input wire  FLUSH1_i;
+
+    input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+    input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input wire  FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+    (FLUSH1_i => RDATA_A1_o[0]) = 0;
+    (FLUSH1_i => RDATA_A1_o[1]) = 0;
+    (FLUSH1_i => RDATA_A1_o[2]) = 0;
+    (FLUSH1_i => RDATA_A1_o[3]) = 0;
+    (FLUSH1_i => RDATA_A1_o[4]) = 0;
+    (FLUSH1_i => RDATA_A1_o[5]) = 0;
+    (FLUSH1_i => RDATA_A1_o[6]) = 0;
+    (FLUSH1_i => RDATA_A1_o[7]) = 0;
+    (FLUSH2_i => RDATA_A2_o[0]) = 0;
+    (FLUSH2_i => RDATA_A2_o[1]) = 0;
+    (FLUSH2_i => RDATA_A2_o[2]) = 0;
+    (FLUSH2_i => RDATA_A2_o[3]) = 0;
+    (FLUSH2_i => RDATA_A2_o[4]) = 0;
+    (FLUSH2_i => RDATA_A2_o[5]) = 0;
+    (FLUSH2_i => RDATA_A2_o[6]) = 0;
+    (FLUSH2_i => RDATA_A2_o[7]) = 0;    
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_SYNC_WR_X9_RD_X36_nonsplit (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input wire  RESET_ni;
+    input wire  WEN_A1_i, WEN_B1_i;
+    input wire  REN_A1_i, REN_B1_i;
+    input wire  WEN_A2_i, WEN_B2_i;
+    input wire  REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input wire  CLK_A1_i;
+    (* clkbuf_sink *)
+    input wire  CLK_B1_i;
+    (* clkbuf_sink *)
+    input wire  CLK_A2_i;
+    (* clkbuf_sink *)
+    input wire  CLK_B2_i;
+
+    input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+    input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input wire  FLUSH1_i;
+
+    input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+    input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input wire  FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+    (FLUSH1_i => RDATA_A1_o[0]) = 0;
+    (FLUSH1_i => RDATA_A1_o[1]) = 0;
+    (FLUSH1_i => RDATA_A1_o[2]) = 0;
+    (FLUSH1_i => RDATA_A1_o[3]) = 0;
+    (FLUSH1_i => RDATA_A1_o[4]) = 0;
+    (FLUSH1_i => RDATA_A1_o[5]) = 0;
+    (FLUSH1_i => RDATA_A1_o[6]) = 0;
+    (FLUSH1_i => RDATA_A1_o[7]) = 0;
+    (FLUSH2_i => RDATA_A2_o[0]) = 0;
+    (FLUSH2_i => RDATA_A2_o[1]) = 0;
+    (FLUSH2_i => RDATA_A2_o[2]) = 0;
+    (FLUSH2_i => RDATA_A2_o[3]) = 0;
+    (FLUSH2_i => RDATA_A2_o[4]) = 0;
+    (FLUSH2_i => RDATA_A2_o[5]) = 0;
+    (FLUSH2_i => RDATA_A2_o[6]) = 0;
+    (FLUSH2_i => RDATA_A2_o[7]) = 0;    
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_SYNC_WR_X18_RD_X9_nonsplit (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input wire  RESET_ni;
+    input wire  WEN_A1_i, WEN_B1_i;
+    input wire  REN_A1_i, REN_B1_i;
+    input wire  WEN_A2_i, WEN_B2_i;
+    input wire  REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input wire  CLK_A1_i;
+    (* clkbuf_sink *)
+    input wire  CLK_B1_i;
+    (* clkbuf_sink *)
+    input wire  CLK_A2_i;
+    (* clkbuf_sink *)
+    input wire  CLK_B2_i;
+
+    input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+    input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input wire  FLUSH1_i;
+
+    input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+    input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input wire  FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+    (FLUSH1_i => RDATA_A1_o[0]) = 0;
+    (FLUSH1_i => RDATA_A1_o[1]) = 0;
+    (FLUSH1_i => RDATA_A1_o[2]) = 0;
+    (FLUSH1_i => RDATA_A1_o[3]) = 0;
+    (FLUSH1_i => RDATA_A1_o[4]) = 0;
+    (FLUSH1_i => RDATA_A1_o[5]) = 0;
+    (FLUSH1_i => RDATA_A1_o[6]) = 0;
+    (FLUSH1_i => RDATA_A1_o[7]) = 0;
+    (FLUSH2_i => RDATA_A2_o[0]) = 0;
+    (FLUSH2_i => RDATA_A2_o[1]) = 0;
+    (FLUSH2_i => RDATA_A2_o[2]) = 0;
+    (FLUSH2_i => RDATA_A2_o[3]) = 0;
+    (FLUSH2_i => RDATA_A2_o[4]) = 0;
+    (FLUSH2_i => RDATA_A2_o[5]) = 0;
+    (FLUSH2_i => RDATA_A2_o[6]) = 0;
+    (FLUSH2_i => RDATA_A2_o[7]) = 0;    
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_SYNC_WR_X18_RD_X18_nonsplit (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input wire  RESET_ni;
+    input wire  WEN_A1_i, WEN_B1_i;
+    input wire  REN_A1_i, REN_B1_i;
+    input wire  WEN_A2_i, WEN_B2_i;
+    input wire  REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input wire  CLK_A1_i;
+    (* clkbuf_sink *)
+    input wire  CLK_B1_i;
+    (* clkbuf_sink *)
+    input wire  CLK_A2_i;
+    (* clkbuf_sink *)
+    input wire  CLK_B2_i;
+
+    input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+    input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input wire  FLUSH1_i;
+
+    input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+    input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input wire  FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+    (FLUSH1_i => RDATA_A1_o[0]) = 0;
+    (FLUSH1_i => RDATA_A1_o[1]) = 0;
+    (FLUSH1_i => RDATA_A1_o[2]) = 0;
+    (FLUSH1_i => RDATA_A1_o[3]) = 0;
+    (FLUSH1_i => RDATA_A1_o[4]) = 0;
+    (FLUSH1_i => RDATA_A1_o[5]) = 0;
+    (FLUSH1_i => RDATA_A1_o[6]) = 0;
+    (FLUSH1_i => RDATA_A1_o[7]) = 0;
+    (FLUSH2_i => RDATA_A2_o[0]) = 0;
+    (FLUSH2_i => RDATA_A2_o[1]) = 0;
+    (FLUSH2_i => RDATA_A2_o[2]) = 0;
+    (FLUSH2_i => RDATA_A2_o[3]) = 0;
+    (FLUSH2_i => RDATA_A2_o[4]) = 0;
+    (FLUSH2_i => RDATA_A2_o[5]) = 0;
+    (FLUSH2_i => RDATA_A2_o[6]) = 0;
+    (FLUSH2_i => RDATA_A2_o[7]) = 0;    
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_SYNC_WR_X18_RD_X36_nonsplit (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input wire  RESET_ni;
+    input wire  WEN_A1_i, WEN_B1_i;
+    input wire  REN_A1_i, REN_B1_i;
+    input wire  WEN_A2_i, WEN_B2_i;
+    input wire  REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input wire  CLK_A1_i;
+    (* clkbuf_sink *)
+    input wire  CLK_B1_i;
+    (* clkbuf_sink *)
+    input wire  CLK_A2_i;
+    (* clkbuf_sink *)
+    input wire  CLK_B2_i;
+
+    input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+    input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input wire  FLUSH1_i;
+
+    input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+    input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input wire  FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+    (FLUSH1_i => RDATA_A1_o[0]) = 0;
+    (FLUSH1_i => RDATA_A1_o[1]) = 0;
+    (FLUSH1_i => RDATA_A1_o[2]) = 0;
+    (FLUSH1_i => RDATA_A1_o[3]) = 0;
+    (FLUSH1_i => RDATA_A1_o[4]) = 0;
+    (FLUSH1_i => RDATA_A1_o[5]) = 0;
+    (FLUSH1_i => RDATA_A1_o[6]) = 0;
+    (FLUSH1_i => RDATA_A1_o[7]) = 0;
+    (FLUSH2_i => RDATA_A2_o[0]) = 0;
+    (FLUSH2_i => RDATA_A2_o[1]) = 0;
+    (FLUSH2_i => RDATA_A2_o[2]) = 0;
+    (FLUSH2_i => RDATA_A2_o[3]) = 0;
+    (FLUSH2_i => RDATA_A2_o[4]) = 0;
+    (FLUSH2_i => RDATA_A2_o[5]) = 0;
+    (FLUSH2_i => RDATA_A2_o[6]) = 0;
+    (FLUSH2_i => RDATA_A2_o[7]) = 0;    
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_SYNC_WR_X36_RD_X9_nonsplit (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input wire  RESET_ni;
+    input wire  WEN_A1_i, WEN_B1_i;
+    input wire  REN_A1_i, REN_B1_i;
+    input wire  WEN_A2_i, WEN_B2_i;
+    input wire  REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input wire  CLK_A1_i;
+    (* clkbuf_sink *)
+    input wire  CLK_B1_i;
+    (* clkbuf_sink *)
+    input wire  CLK_A2_i;
+    (* clkbuf_sink *)
+    input wire  CLK_B2_i;
+
+    input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+    input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input wire  FLUSH1_i;
+
+    input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+    input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input wire  FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+    (FLUSH1_i => RDATA_A1_o[0]) = 0;
+    (FLUSH1_i => RDATA_A1_o[1]) = 0;
+    (FLUSH1_i => RDATA_A1_o[2]) = 0;
+    (FLUSH1_i => RDATA_A1_o[3]) = 0;
+    (FLUSH1_i => RDATA_A1_o[4]) = 0;
+    (FLUSH1_i => RDATA_A1_o[5]) = 0;
+    (FLUSH1_i => RDATA_A1_o[6]) = 0;
+    (FLUSH1_i => RDATA_A1_o[7]) = 0;
+    (FLUSH2_i => RDATA_A2_o[0]) = 0;
+    (FLUSH2_i => RDATA_A2_o[1]) = 0;
+    (FLUSH2_i => RDATA_A2_o[2]) = 0;
+    (FLUSH2_i => RDATA_A2_o[3]) = 0;
+    (FLUSH2_i => RDATA_A2_o[4]) = 0;
+    (FLUSH2_i => RDATA_A2_o[5]) = 0;
+    (FLUSH2_i => RDATA_A2_o[6]) = 0;
+    (FLUSH2_i => RDATA_A2_o[7]) = 0;    
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_SYNC_WR_X36_RD_X18_nonsplit (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input wire  RESET_ni;
+    input wire  WEN_A1_i, WEN_B1_i;
+    input wire  REN_A1_i, REN_B1_i;
+    input wire  WEN_A2_i, WEN_B2_i;
+    input wire  REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input wire  CLK_A1_i;
+    (* clkbuf_sink *)
+    input wire  CLK_B1_i;
+    (* clkbuf_sink *)
+    input wire  CLK_A2_i;
+    (* clkbuf_sink *)
+    input wire  CLK_B2_i;
+
+    input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+    input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input wire  FLUSH1_i;
+
+    input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+    input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input wire  FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+    (FLUSH1_i => RDATA_A1_o[0]) = 0;
+    (FLUSH1_i => RDATA_A1_o[1]) = 0;
+    (FLUSH1_i => RDATA_A1_o[2]) = 0;
+    (FLUSH1_i => RDATA_A1_o[3]) = 0;
+    (FLUSH1_i => RDATA_A1_o[4]) = 0;
+    (FLUSH1_i => RDATA_A1_o[5]) = 0;
+    (FLUSH1_i => RDATA_A1_o[6]) = 0;
+    (FLUSH1_i => RDATA_A1_o[7]) = 0;
+    (FLUSH2_i => RDATA_A2_o[0]) = 0;
+    (FLUSH2_i => RDATA_A2_o[1]) = 0;
+    (FLUSH2_i => RDATA_A2_o[2]) = 0;
+    (FLUSH2_i => RDATA_A2_o[3]) = 0;
+    (FLUSH2_i => RDATA_A2_o[4]) = 0;
+    (FLUSH2_i => RDATA_A2_o[5]) = 0;
+    (FLUSH2_i => RDATA_A2_o[6]) = 0;
+    (FLUSH2_i => RDATA_A2_o[7]) = 0;    
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_SYNC_WR_X36_RD_X36_nonsplit (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input wire  RESET_ni;
+    input wire  WEN_A1_i, WEN_B1_i;
+    input wire  REN_A1_i, REN_B1_i;
+    input wire  WEN_A2_i, WEN_B2_i;
+    input wire  REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input wire  CLK_A1_i;
+    (* clkbuf_sink *)
+    input wire  CLK_B1_i;
+    (* clkbuf_sink *)
+    input wire  CLK_A2_i;
+    (* clkbuf_sink *)
+    input wire  CLK_B2_i;
+
+    input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+    input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input wire  FLUSH1_i;
+
+    input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+    input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input wire  FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+    (FLUSH1_i => RDATA_A1_o[0]) = 0;
+    (FLUSH1_i => RDATA_A1_o[1]) = 0;
+    (FLUSH1_i => RDATA_A1_o[2]) = 0;
+    (FLUSH1_i => RDATA_A1_o[3]) = 0;
+    (FLUSH1_i => RDATA_A1_o[4]) = 0;
+    (FLUSH1_i => RDATA_A1_o[5]) = 0;
+    (FLUSH1_i => RDATA_A1_o[6]) = 0;
+    (FLUSH1_i => RDATA_A1_o[7]) = 0;
+    (FLUSH2_i => RDATA_A2_o[0]) = 0;
+    (FLUSH2_i => RDATA_A2_o[1]) = 0;
+    (FLUSH2_i => RDATA_A2_o[2]) = 0;
+    (FLUSH2_i => RDATA_A2_o[3]) = 0;
+    (FLUSH2_i => RDATA_A2_o[4]) = 0;
+    (FLUSH2_i => RDATA_A2_o[5]) = 0;
+    (FLUSH2_i => RDATA_A2_o[6]) = 0;
+    (FLUSH2_i => RDATA_A2_o[7]) = 0;    
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+
+module TDP36K_FIFO_SYNC_WR_X9_RD_X9_split (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input wire  RESET_ni;
+    input wire  WEN_A1_i, WEN_B1_i;
+    input wire  REN_A1_i, REN_B1_i;
+    input wire  WEN_A2_i, WEN_B2_i;
+    input wire  REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input wire  CLK_A1_i;
+    (* clkbuf_sink *)
+    input wire  CLK_B1_i;
+    (* clkbuf_sink *)
+    input wire  CLK_A2_i;
+    (* clkbuf_sink *)
+    input wire  CLK_B2_i;
+
+    input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+    input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input wire  FLUSH1_i;
+
+    input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+    input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input wire  FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+    (FLUSH1_i => RDATA_A1_o[0]) = 0;
+    (FLUSH1_i => RDATA_A1_o[1]) = 0;
+    (FLUSH1_i => RDATA_A1_o[2]) = 0;
+    (FLUSH1_i => RDATA_A1_o[3]) = 0;
+    (FLUSH1_i => RDATA_A1_o[4]) = 0;
+    (FLUSH1_i => RDATA_A1_o[5]) = 0;
+    (FLUSH1_i => RDATA_A1_o[6]) = 0;
+    (FLUSH1_i => RDATA_A1_o[7]) = 0;
+    (FLUSH2_i => RDATA_A2_o[0]) = 0;
+    (FLUSH2_i => RDATA_A2_o[1]) = 0;
+    (FLUSH2_i => RDATA_A2_o[2]) = 0;
+    (FLUSH2_i => RDATA_A2_o[3]) = 0;
+    (FLUSH2_i => RDATA_A2_o[4]) = 0;
+    (FLUSH2_i => RDATA_A2_o[5]) = 0;
+    (FLUSH2_i => RDATA_A2_o[6]) = 0;
+    (FLUSH2_i => RDATA_A2_o[7]) = 0;    
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_SYNC_WR_X9_RD_X18_split (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input wire  RESET_ni;
+    input wire  WEN_A1_i, WEN_B1_i;
+    input wire  REN_A1_i, REN_B1_i;
+    input wire  WEN_A2_i, WEN_B2_i;
+    input wire  REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input wire  CLK_A1_i;
+    (* clkbuf_sink *)
+    input wire  CLK_B1_i;
+    (* clkbuf_sink *)
+    input wire  CLK_A2_i;
+    (* clkbuf_sink *)
+    input wire  CLK_B2_i;
+
+    input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+    input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input wire  FLUSH1_i;
+
+    input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+    input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input wire  FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+    (FLUSH1_i => RDATA_A1_o[0]) = 0;
+    (FLUSH1_i => RDATA_A1_o[1]) = 0;
+    (FLUSH1_i => RDATA_A1_o[2]) = 0;
+    (FLUSH1_i => RDATA_A1_o[3]) = 0;
+    (FLUSH1_i => RDATA_A1_o[4]) = 0;
+    (FLUSH1_i => RDATA_A1_o[5]) = 0;
+    (FLUSH1_i => RDATA_A1_o[6]) = 0;
+    (FLUSH1_i => RDATA_A1_o[7]) = 0;
+    (FLUSH2_i => RDATA_A2_o[0]) = 0;
+    (FLUSH2_i => RDATA_A2_o[1]) = 0;
+    (FLUSH2_i => RDATA_A2_o[2]) = 0;
+    (FLUSH2_i => RDATA_A2_o[3]) = 0;
+    (FLUSH2_i => RDATA_A2_o[4]) = 0;
+    (FLUSH2_i => RDATA_A2_o[5]) = 0;
+    (FLUSH2_i => RDATA_A2_o[6]) = 0;
+    (FLUSH2_i => RDATA_A2_o[7]) = 0;    
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_SYNC_WR_X18_RD_X9_split (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input wire  RESET_ni;
+    input wire  WEN_A1_i, WEN_B1_i;
+    input wire  REN_A1_i, REN_B1_i;
+    input wire  WEN_A2_i, WEN_B2_i;
+    input wire  REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input wire  CLK_A1_i;
+    (* clkbuf_sink *)
+    input wire  CLK_B1_i;
+    (* clkbuf_sink *)
+    input wire  CLK_A2_i;
+    (* clkbuf_sink *)
+    input wire  CLK_B2_i;
+
+    input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+    input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input wire  FLUSH1_i;
+
+    input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+    input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input wire  FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+    (FLUSH1_i => RDATA_A1_o[0]) = 0;
+    (FLUSH1_i => RDATA_A1_o[1]) = 0;
+    (FLUSH1_i => RDATA_A1_o[2]) = 0;
+    (FLUSH1_i => RDATA_A1_o[3]) = 0;
+    (FLUSH1_i => RDATA_A1_o[4]) = 0;
+    (FLUSH1_i => RDATA_A1_o[5]) = 0;
+    (FLUSH1_i => RDATA_A1_o[6]) = 0;
+    (FLUSH1_i => RDATA_A1_o[7]) = 0;
+    (FLUSH2_i => RDATA_A2_o[0]) = 0;
+    (FLUSH2_i => RDATA_A2_o[1]) = 0;
+    (FLUSH2_i => RDATA_A2_o[2]) = 0;
+    (FLUSH2_i => RDATA_A2_o[3]) = 0;
+    (FLUSH2_i => RDATA_A2_o[4]) = 0;
+    (FLUSH2_i => RDATA_A2_o[5]) = 0;
+    (FLUSH2_i => RDATA_A2_o[6]) = 0;
+    (FLUSH2_i => RDATA_A2_o[7]) = 0;    
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_SYNC_WR_X18_RD_X18_split (
+    RESET_ni,
+    WEN_A1_i,   WEN_B1_i,
+    REN_A1_i,   REN_B1_i,
+    CLK_A1_i,   CLK_B1_i,
+    BE_A1_i,    BE_B1_i,
+    ADDR_A1_i,  ADDR_B1_i,
+    WDATA_A1_i, WDATA_B1_i,
+    RDATA_A1_o, RDATA_B1_o,
+    FLUSH1_i,
+    WEN_A2_i,   WEN_B2_i,
+    REN_A2_i,   REN_B2_i,
+    CLK_A2_i,   CLK_B2_i,
+    BE_A2_i,    BE_B2_i,
+    ADDR_A2_i,  ADDR_B2_i,
+    WDATA_A2_i, WDATA_B2_i,
+    RDATA_A2_o, RDATA_B2_o,
+    FLUSH2_i
+);
+    parameter [80:0] MODE_BITS = 81'd0;
+
+    input wire  RESET_ni;
+    input wire  WEN_A1_i, WEN_B1_i;
+    input wire  REN_A1_i, REN_B1_i;
+    input wire  WEN_A2_i, WEN_B2_i;
+    input wire  REN_A2_i, REN_B2_i;
+
+    (* clkbuf_sink *)
+    input wire  CLK_A1_i;
+    (* clkbuf_sink *)
+    input wire  CLK_B1_i;
+    (* clkbuf_sink *)
+    input wire  CLK_A2_i;
+    (* clkbuf_sink *)
+    input wire  CLK_B2_i;
+
+    input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+    input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+    input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+    output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+    input wire  FLUSH1_i;
+
+    input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+    input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+    input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+    output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+    input wire  FLUSH2_i;
+
+    TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+        .RESET_ni   (RESET_ni),   
+        .WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+        .REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+        .CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+        .BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+        .ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+        .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+        .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+        .FLUSH1_i   (FLUSH1_i),
+        .WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+        .REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+        .CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+        .BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+        .ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+        .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+        .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+        .FLUSH2_i   (FLUSH2_i)
+    );
+
+`ifdef SDF_SIM
+	specify
+    (FLUSH1_i => RDATA_A1_o[0]) = 0;
+    (FLUSH1_i => RDATA_A1_o[1]) = 0;
+    (FLUSH1_i => RDATA_A1_o[2]) = 0;
+    (FLUSH1_i => RDATA_A1_o[3]) = 0;
+    (FLUSH1_i => RDATA_A1_o[4]) = 0;
+    (FLUSH1_i => RDATA_A1_o[5]) = 0;
+    (FLUSH1_i => RDATA_A1_o[6]) = 0;
+    (FLUSH1_i => RDATA_A1_o[7]) = 0;
+    (FLUSH2_i => RDATA_A2_o[0]) = 0;
+    (FLUSH2_i => RDATA_A2_o[1]) = 0;
+    (FLUSH2_i => RDATA_A2_o[2]) = 0;
+    (FLUSH2_i => RDATA_A2_o[3]) = 0;
+    (FLUSH2_i => RDATA_A2_o[4]) = 0;
+    (FLUSH2_i => RDATA_A2_o[5]) = 0;
+    (FLUSH2_i => RDATA_A2_o[6]) = 0;
+    (FLUSH2_i => RDATA_A2_o[7]) = 0;    
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+    $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+    $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+    $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+    $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
\ No newline at end of file
diff --git a/ql-qlf-plugin/qlf_k6n10f/cells_sim.v b/ql-qlf-plugin/qlf_k6n10f/cells_sim.v
index 26ac9ae..d2fc0a7 100644
--- a/ql-qlf-plugin/qlf_k6n10f/cells_sim.v
+++ b/ql-qlf-plugin/qlf_k6n10f/cells_sim.v
@@ -14,6 +14,8 @@
 //
 // SPDX-License-Identifier: Apache-2.0
 
+`timescale 1ps/1ps
+
 `default_nettype none
 
 (* abc9_flop, lib_whitebox *)
@@ -27,6 +29,11 @@
     initial Q <= 1'b0;
     always @(posedge C)
         Q <= D;
+		
+    specify
+      (posedge C => (Q +: D)) = 0;
+      $setuphold(posedge C, D, 0, 0);
+    endspecify
 
 endmodule
 
@@ -40,87 +47,15 @@
 );
     assign sumout = p ^ cin;
     assign cout = p ? cin : g;
-
-endmodule
-
-(* abc9_box, lib_whitebox *)
-module adder_lut5(
-   output wire lut5_out,
-   (* abc9_carry *)
-   output wire cout,
-   input wire [0:4] in,
-   (* abc9_carry *)
-   input wire cin
-);
-    parameter [0:15] LUT=0;
-    parameter IN2_IS_CIN = 0;
-
-    wire [0:4] li = (IN2_IS_CIN) ? {in[0], in[1], cin, in[3], in[4]} : {in[0], in[1], in[2], in[3],in[4]};
-
-    // Output function
-    wire [0:15] s1 = li[0] ?
-        {LUT[0], LUT[2], LUT[4], LUT[6], LUT[8], LUT[10], LUT[12], LUT[14], LUT[16], LUT[18], LUT[20], LUT[22], LUT[24], LUT[26], LUT[28], LUT[30]}:
-        {LUT[1], LUT[3], LUT[5], LUT[7], LUT[9], LUT[11], LUT[13], LUT[15], LUT[17], LUT[19], LUT[21], LUT[23], LUT[25], LUT[27], LUT[29], LUT[31]};
-
-    wire [0:7] s2 = li[1] ? {s1[0], s1[2], s1[4], s1[6], s1[8], s1[10], s1[12], s1[14]} :
-                            {s1[1], s1[3], s1[5], s1[7], s1[9], s1[11], s1[13], s1[15]};
-
-    wire [0:3] s3 = li[2] ? {s2[0], s2[2], s2[4], s2[6]} : {s2[1], s2[3], s2[5], s2[7]};
-    wire [0:1] s4 = li[3] ? {s3[0], s3[2]} : {s3[1], s3[3]};
-
-    assign lut5_out = li[4] ? s4[0] : s4[1];
-
-    // Carry out function
-    assign cout = (s3[2]) ? cin : s3[3];
-
-endmodule
-
-(* abc9_lut=1, lib_whitebox *)
-module frac_lut6(
-    input wire [0:5] in,
-    output wire [0:3] lut4_out,
-    output wire [0:1] lut5_out,
-    output wire lut6_out
-);
-    parameter [0:63] LUT = 0;
-    // Effective LUT input
-    wire [0:5] li = in;
-
-    // Output function
-    wire [0:31] s1 = li[0] ?
-    {LUT[0] , LUT[2] , LUT[4] , LUT[6] , LUT[8] , LUT[10], LUT[12], LUT[14], 
-     LUT[16], LUT[18], LUT[20], LUT[22], LUT[24], LUT[26], LUT[28], LUT[30],
-     LUT[32], LUT[34], LUT[36], LUT[38], LUT[40], LUT[42], LUT[44], LUT[46],
-     LUT[48], LUT[50], LUT[52], LUT[54], LUT[56], LUT[58], LUT[60], LUT[62]}:
-    {LUT[1] , LUT[3] , LUT[5] , LUT[7] , LUT[9] , LUT[11], LUT[13], LUT[15], 
-     LUT[17], LUT[19], LUT[21], LUT[23], LUT[25], LUT[27], LUT[29], LUT[31],
-     LUT[33], LUT[35], LUT[37], LUT[39], LUT[41], LUT[43], LUT[45], LUT[47],
-     LUT[49], LUT[51], LUT[53], LUT[55], LUT[57], LUT[59], LUT[61], LUT[63]};
-
-    wire [0:15] s2 = li[1] ?
-    {s1[0] , s1[2] , s1[4] , s1[6] , s1[8] , s1[10], s1[12], s1[14],
-     s1[16], s1[18], s1[20], s1[22], s1[24], s1[26], s1[28], s1[30]}:
-    {s1[1] , s1[3] , s1[5] , s1[7] , s1[9] , s1[11], s1[13], s1[15],
-     s1[17], s1[19], s1[21], s1[23], s1[25], s1[27], s1[29], s1[31]};
-
-    wire [0:7] s3 = li[2] ?
-    {s2[0], s2[2], s2[4], s2[6], s2[8], s2[10], s2[12], s2[14]}:
-    {s2[1], s2[3], s2[5], s2[7], s2[9], s2[11], s2[13], s2[15]};
-
-    wire [0:3] s4 = li[3] ? {s3[0], s3[2], s3[4], s3[6]}:
-                            {s3[1], s3[3], s3[5], s3[7]};
-
-    wire [0:1] s5 = li[4] ? {s4[0], s4[2]} : {s4[1], s4[3]};
-
-    assign lut4_out[0] = s4[0];
-    assign lut4_out[1] = s4[1];
-    assign lut4_out[2] = s4[2];
-    assign lut4_out[3] = s4[3];
-
-    assign lut5_out[0] = s5[0];
-    assign lut5_out[1] = s5[1];
-
-    assign lut6_out = li[5] ? s5[0] : s5[1];
+	
+    specify
+        (p => sumout) = 0;
+        (g => sumout) = 0;
+        (cin => sumout) = 0;
+        (p => cout) = 0;
+        (g => cout) = 0;
+        (cin => cout) = 0;
+    endspecify
 
 endmodule
 
@@ -136,6 +71,11 @@
     always @(posedge C)
       Q <= D;
 
+    specify
+	    (posedge C=>(Q+:D)) = 0;
+	    $setuphold(posedge C, D, 0, 0);
+    endspecify
+
 endmodule
 
 (* abc9_flop, lib_whitebox *)
@@ -149,6 +89,11 @@
 
     always @(negedge C)
       Q <= D;
+	  
+    specify
+	    (negedge C=>(Q+:D)) = 0;
+	    $setuphold(negedge C, D, 0, 0);
+    endspecify
 
 endmodule
 
@@ -172,6 +117,18 @@
       else if (E)
         Q <= D;
 
+    specify
+      (posedge C => (Q +: D)) = 0;
+      (R => Q) = 0;
+      (S => Q) = 0;
+      $setuphold(posedge C, D, 0, 0);
+      $setuphold(posedge C, E, 0, 0);
+      $setuphold(posedge C, R, 0, 0);
+      $setuphold(posedge C, S, 0, 0);
+      $recrem(posedge R, posedge C, 0, 0);
+      $recrem(posedge S, posedge C, 0, 0);
+    endspecify
+
 endmodule
 
 (* abc9_flop, lib_whitebox *)
@@ -193,6 +150,18 @@
         Q <= 1'b1;
       else if (E)
         Q <= D;
+		
+    specify
+      (negedge C => (Q +: D)) = 0;
+      (R => Q) = 0;
+      (S => Q) = 0;
+      $setuphold(negedge C, D, 0, 0);
+      $setuphold(negedge C, E, 0, 0);
+      $setuphold(negedge C, R, 0, 0);
+      $setuphold(negedge C, S, 0, 0);
+      $recrem(posedge R, negedge C, 0, 0);
+      $recrem(posedge S, negedge C, 0, 0);
+    endspecify
 
 endmodule
 
@@ -215,6 +184,14 @@
         Q <= 1'b1;
       else if (E)
         Q <= D;
+		
+    specify
+        (posedge C => (Q +: D)) = 0;
+        $setuphold(posedge C, D, 0, 0);
+        $setuphold(posedge C, R, 0, 0);
+        $setuphold(posedge C, S, 0, 0);
+        $setuphold(posedge C, E, 0, 0);
+    endspecify
 
 endmodule
 
@@ -237,6 +214,14 @@
         Q <= 1'b1;
       else if (E)
         Q <= D;
+		
+    specify
+        (negedge C => (Q +: D)) = 0;
+        $setuphold(negedge C, D, 0, 0);
+        $setuphold(negedge C, R, 0, 0);
+        $setuphold(negedge C, S, 0, 0);
+        $setuphold(negedge C, E, 0, 0);
+    endspecify
 
 endmodule
 
@@ -260,6 +245,14 @@
         else if (E && G)
           Q <= D;
       end
+	  
+    specify
+      (posedge G => (Q +: D)) = 0;
+      $setuphold(posedge G, D, 0, 0);
+      $setuphold(posedge G, E, 0, 0);
+      $setuphold(posedge G, R, 0, 0);
+      $setuphold(posedge G, S, 0, 0);
+    endspecify      
 
 endmodule
 
@@ -283,1409 +276,14 @@
         else if (E && !G)
           Q <= D;
       end
+	  
+    specify
+      (negedge G => (Q +: D)) = 0;
+      $setuphold(negedge G, D, 0, 0);
+      $setuphold(negedge G, E, 0, 0);
+      $setuphold(negedge G, R, 0, 0);
+      $setuphold(negedge G, S, 0, 0);
+    endspecify 
 
 endmodule
 
-
-module TDP_BRAM18 (
-    (* clkbuf_sink *)
-    input wire CLOCKA,
-    (* clkbuf_sink *)
-    input wire CLOCKB,
-    input wire READENABLEA,
-    input wire READENABLEB,
-    input wire [13:0] ADDRA,
-    input wire [13:0] ADDRB,
-    input wire [15:0] WRITEDATAA,
-    input wire [15:0] WRITEDATAB,
-    input wire [1:0] WRITEDATAAP,
-    input wire [1:0] WRITEDATABP,
-    input wire WRITEENABLEA,
-    input wire WRITEENABLEB,
-    input wire [1:0] BYTEENABLEA,
-    input wire [1:0] BYTEENABLEB,
-    //input wire [2:0] WRITEDATAWIDTHA,
-    //input wire [2:0] WRITEDATAWIDTHB,
-    //input wire [2:0] READDATAWIDTHA,
-    //input wire [2:0] READDATAWIDTHB,
-    output wire [15:0] READDATAA,
-    output wire [15:0] READDATAB,
-    output wire [1:0] READDATAAP,
-    output wire [1:0] READDATABP
-);
-    parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter integer READ_WIDTH_A = 0;
-    parameter integer READ_WIDTH_B = 0;
-    parameter integer WRITE_WIDTH_A = 0;
-    parameter integer WRITE_WIDTH_B = 0;
-
-endmodule
-
-module TDP36K (
-    RESET_ni,
-    WEN_A1_i,
-    WEN_B1_i,
-    REN_A1_i,
-    REN_B1_i,
-    CLK_A1_i,
-    CLK_B1_i,
-    BE_A1_i,
-    BE_B1_i,
-    ADDR_A1_i,
-    ADDR_B1_i,
-    WDATA_A1_i,
-    WDATA_B1_i,
-    RDATA_A1_o,
-    RDATA_B1_o,
-    FLUSH1_i,
-    WEN_A2_i,
-    WEN_B2_i,
-    REN_A2_i,
-    REN_B2_i,
-    CLK_A2_i,
-    CLK_B2_i,
-    BE_A2_i,
-    BE_B2_i,
-    ADDR_A2_i,
-    ADDR_B2_i,
-    WDATA_A2_i,
-    WDATA_B2_i,
-    RDATA_A2_o,
-    RDATA_B2_o,
-    FLUSH2_i
-);
-    parameter [80:0] MODE_BITS = 81'd0;
-
-    // First 18K RAMFIFO (41 bits)
-    localparam [ 0:0] SYNC_FIFO1_i  = MODE_BITS[0];
-    localparam [ 2:0] RMODE_A1_i    = MODE_BITS[3 : 1];
-    localparam [ 2:0] RMODE_B1_i    = MODE_BITS[6 : 4];
-    localparam [ 2:0] WMODE_A1_i    = MODE_BITS[9 : 7];
-    localparam [ 2:0] WMODE_B1_i    = MODE_BITS[12:10];
-    localparam [ 0:0] FMODE1_i      = MODE_BITS[13];
-    localparam [ 0:0] POWERDN1_i    = MODE_BITS[14];
-    localparam [ 0:0] SLEEP1_i      = MODE_BITS[15];
-    localparam [ 0:0] PROTECT1_i    = MODE_BITS[16];
-    localparam [11:0] UPAE1_i       = MODE_BITS[28:17];
-    localparam [11:0] UPAF1_i       = MODE_BITS[40:29];
-
-    // Second 18K RAMFIFO (39 bits)
-    localparam [ 0:0] SYNC_FIFO2_i  = MODE_BITS[41];
-    localparam [ 2:0] RMODE_A2_i    = MODE_BITS[44:42];
-    localparam [ 2:0] RMODE_B2_i    = MODE_BITS[47:45];
-    localparam [ 2:0] WMODE_A2_i    = MODE_BITS[50:48];
-    localparam [ 2:0] WMODE_B2_i    = MODE_BITS[53:51];
-    localparam [ 0:0] FMODE2_i      = MODE_BITS[54];
-    localparam [ 0:0] POWERDN2_i    = MODE_BITS[55];
-    localparam [ 0:0] SLEEP2_i      = MODE_BITS[56];
-    localparam [ 0:0] PROTECT2_i    = MODE_BITS[57];
-    localparam [10:0] UPAE2_i       = MODE_BITS[68:58];
-    localparam [10:0] UPAF2_i       = MODE_BITS[79:69];
-
-    // Split (1 bit)
-    localparam [ 0:0] SPLIT_i       = MODE_BITS[80];
-
-    parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-
-    input wire RESET_ni;
-    input wire WEN_A1_i;
-    input wire WEN_B1_i;
-    input wire REN_A1_i;
-    input wire REN_B1_i;
-    (* clkbuf_sink *)
-    input wire CLK_A1_i;
-    (* clkbuf_sink *)
-    input wire CLK_B1_i;
-    input wire [1:0] BE_A1_i;
-    input wire [1:0] BE_B1_i;
-    input wire [14:0] ADDR_A1_i;
-    input wire [14:0] ADDR_B1_i;
-    input wire [17:0] WDATA_A1_i;
-    input wire [17:0] WDATA_B1_i;
-    output reg [17:0] RDATA_A1_o;
-    output reg [17:0] RDATA_B1_o;
-    input wire FLUSH1_i;
-    input wire WEN_A2_i;
-    input wire WEN_B2_i;
-    input wire REN_A2_i;
-    input wire REN_B2_i;
-    (* clkbuf_sink *)
-    input wire CLK_A2_i;
-    (* clkbuf_sink *)
-    input wire CLK_B2_i;
-    input wire [1:0] BE_A2_i;
-    input wire [1:0] BE_B2_i;
-    input wire [13:0] ADDR_A2_i;
-    input wire [13:0] ADDR_B2_i;
-    input wire [17:0] WDATA_A2_i;
-    input wire [17:0] WDATA_B2_i;
-    output reg [17:0] RDATA_A2_o;
-    output reg [17:0] RDATA_B2_o;
-    input wire FLUSH2_i;
-    wire EMPTY2;
-    wire EPO2;
-    wire EWM2;
-    wire FULL2;
-    wire FMO2;
-    wire FWM2;
-    wire EMPTY1;
-    wire EPO1;
-    wire EWM1;
-    wire FULL1;
-    wire FMO1;
-    wire FWM1;
-    wire UNDERRUN1;
-    wire OVERRUN1;
-    wire UNDERRUN2;
-    wire OVERRUN2;
-    wire UNDERRUN3;
-    wire OVERRUN3;
-    wire EMPTY3;
-    wire EPO3;
-    wire EWM3;
-    wire FULL3;
-    wire FMO3;
-    wire FWM3;
-    wire ram_fmode1;
-    wire ram_fmode2;
-    wire [17:0] ram_rdata_a1;
-    wire [17:0] ram_rdata_b1;
-    wire [17:0] ram_rdata_a2;
-    wire [17:0] ram_rdata_b2;
-    reg [17:0] ram_wdata_a1;
-    reg [17:0] ram_wdata_b1;
-    reg [17:0] ram_wdata_a2;
-    reg [17:0] ram_wdata_b2;
-    reg [14:0] laddr_a1;
-    reg [14:0] laddr_b1;
-    wire [13:0] ram_addr_a1;
-    wire [13:0] ram_addr_b1;
-    wire [13:0] ram_addr_a2;
-    wire [13:0] ram_addr_b2;
-    wire smux_clk_a1;
-    wire smux_clk_b1;
-    wire smux_clk_a2;
-    wire smux_clk_b2;
-    reg [1:0] ram_be_a1;
-    reg [1:0] ram_be_a2;
-    reg [1:0] ram_be_b1;
-    reg [1:0] ram_be_b2;
-    wire [2:0] ram_rmode_a1;
-    wire [2:0] ram_wmode_a1;
-    wire [2:0] ram_rmode_b1;
-    wire [2:0] ram_wmode_b1;
-    wire [2:0] ram_rmode_a2;
-    wire [2:0] ram_wmode_a2;
-    wire [2:0] ram_rmode_b2;
-    wire [2:0] ram_wmode_b2;
-    wire ram_ren_a1;
-    wire ram_ren_b1;
-    wire ram_ren_a2;
-    wire ram_ren_b2;
-    wire ram_wen_a1;
-    wire ram_wen_b1;
-    wire ram_wen_a2;
-    wire ram_wen_b2;
-    wire ren_o;
-    wire [11:0] ff_raddr;
-    wire [11:0] ff_waddr;
-    reg [35:0] fifo_rdata;
-    wire [1:0] fifo_rmode;
-    wire [1:0] fifo_wmode;
-    wire [1:0] bwl;
-    wire [17:0] pl_dout0;
-    wire [17:0] pl_dout1;
-    wire sclk_a1;
-    wire sclk_b1;
-    wire sclk_a2;
-    wire sclk_b2;
-    wire sreset;
-    wire flush1;
-    wire flush2;
-    assign sreset = RESET_ni;
-    assign flush1 = ~FLUSH1_i;
-    assign flush2 = ~FLUSH2_i;
-    assign ram_fmode1 = FMODE1_i & SPLIT_i;
-    assign ram_fmode2 = FMODE2_i & SPLIT_i;
-    assign smux_clk_a1 = CLK_A1_i;
-    assign smux_clk_b1 = (FMODE1_i ? (SYNC_FIFO1_i ? CLK_A1_i : CLK_B1_i) : CLK_B1_i);
-    assign smux_clk_a2 = (SPLIT_i ? CLK_A2_i : CLK_A1_i);
-    assign smux_clk_b2 = (SPLIT_i ? (FMODE2_i ? (SYNC_FIFO2_i ? CLK_A2_i : CLK_B2_i) : CLK_B2_i) : (FMODE1_i ? (SYNC_FIFO1_i ? CLK_A1_i : CLK_B1_i) : CLK_B1_i));
-    assign sclk_a1 = smux_clk_a1;
-    assign sclk_a2 = smux_clk_a2;
-    assign sclk_b1 = smux_clk_b1;
-    assign sclk_b2 = smux_clk_b2;
-    assign ram_ren_a1 = (SPLIT_i ? REN_A1_i : (FMODE1_i ? 0 : REN_A1_i));
-    assign ram_ren_a2 = (SPLIT_i ? REN_A2_i : (FMODE1_i ? 0 : REN_A1_i));
-    assign ram_ren_b1 = (SPLIT_i ? REN_B1_i : (FMODE1_i ? ren_o : REN_B1_i));
-    assign ram_ren_b2 = (SPLIT_i ? REN_B2_i : (FMODE1_i ? ren_o : REN_B1_i));
-    localparam MODE_36 = 3'b011;
-    assign ram_wen_a1 = (SPLIT_i ? WEN_A1_i : (FMODE1_i ? ~FULL3 & WEN_A1_i : (WMODE_A1_i == MODE_36 ? WEN_A1_i : WEN_A1_i & ~ADDR_A1_i[4])));
-    assign ram_wen_a2 = (SPLIT_i ? WEN_A2_i : (FMODE1_i ? ~FULL3 & WEN_A1_i : (WMODE_A1_i == MODE_36 ? WEN_A1_i : WEN_A1_i & ADDR_A1_i[4])));
-    assign ram_wen_b1 = (SPLIT_i ? WEN_B1_i : (WMODE_B1_i == MODE_36 ? WEN_B1_i : WEN_B1_i & ~ADDR_B1_i[4]));
-    assign ram_wen_b2 = (SPLIT_i ? WEN_B2_i : (WMODE_B1_i == MODE_36 ? WEN_B1_i : WEN_B1_i & ADDR_B1_i[4]));
-    assign ram_addr_a1 = (SPLIT_i ? ADDR_A1_i[13:0] : (FMODE1_i ? {ff_waddr[11:2], ff_waddr[0], 3'b000} : {ADDR_A1_i[14:5], ADDR_A1_i[3:0]}));
-    assign ram_addr_b1 = (SPLIT_i ? ADDR_B1_i[13:0] : (FMODE1_i ? {ff_raddr[11:2], ff_raddr[0], 3'b000} : {ADDR_B1_i[14:5], ADDR_B1_i[3:0]}));
-    assign ram_addr_a2 = (SPLIT_i ? ADDR_A2_i[13:0] : (FMODE1_i ? {ff_waddr[11:2], ff_waddr[0], 3'b000} : {ADDR_A1_i[14:5], ADDR_A1_i[3:0]}));
-    assign ram_addr_b2 = (SPLIT_i ? ADDR_B2_i[13:0] : (FMODE1_i ? {ff_raddr[11:2], ff_raddr[0], 3'b000} : {ADDR_B1_i[14:5], ADDR_B1_i[3:0]}));
-    assign bwl = (SPLIT_i ? ADDR_A1_i[4:3] : (FMODE1_i ? ff_waddr[1:0] : ADDR_A1_i[4:3]));
-    localparam MODE_18 = 3'b010;
-    localparam MODE_9 = 3'b001;
-    always @(*) begin : WDATA_SEL
-        case (SPLIT_i)
-            1: begin
-                ram_wdata_a1 = WDATA_A1_i;
-                ram_wdata_a2 = WDATA_A2_i;
-                ram_wdata_b1 = WDATA_B1_i;
-                ram_wdata_b2 = WDATA_B2_i;
-                ram_be_a2 = BE_A2_i;
-                ram_be_b2 = BE_B2_i;
-                ram_be_a1 = BE_A1_i;
-                ram_be_b1 = BE_B1_i;
-            end
-            0: begin
-                case (WMODE_A1_i)
-                    MODE_36: begin
-                        ram_wdata_a1 = WDATA_A1_i;
-                        ram_wdata_a2 = WDATA_A2_i;
-                        ram_be_a2 = (FMODE1_i ? 2'b11 : BE_A2_i);
-                        ram_be_a1 = (FMODE1_i ? 2'b11 : BE_A1_i);
-                    end
-                    MODE_18: begin
-                        ram_wdata_a1 = WDATA_A1_i;
-                        ram_wdata_a2 = WDATA_A1_i;
-                        ram_be_a1 = (FMODE1_i ? (ff_waddr[1] ? 2'b00 : 2'b11) : BE_A1_i);
-                        ram_be_a2 = (FMODE1_i ? (ff_waddr[1] ? 2'b11 : 2'b00) : BE_A1_i);
-                    end
-                    MODE_9: begin
-                        ram_wdata_a1[7:0] = WDATA_A1_i[7:0];
-                        ram_wdata_a1[16] = WDATA_A1_i[16];
-                        ram_wdata_a1[15:8] = WDATA_A1_i[7:0];
-                        ram_wdata_a1[17] = WDATA_A1_i[16];
-                        ram_wdata_a2[7:0] = WDATA_A1_i[7:0];
-                        ram_wdata_a2[16] = WDATA_A1_i[16];
-                        ram_wdata_a2[15:8] = WDATA_A1_i[7:0];
-                        ram_wdata_a2[17] = WDATA_A1_i[16];
-                        case (bwl)
-                            0: {ram_be_a2, ram_be_a1} = 4'b0001;
-                            1: {ram_be_a2, ram_be_a1} = 4'b0010;
-                            2: {ram_be_a2, ram_be_a1} = 4'b0100;
-                            3: {ram_be_a2, ram_be_a1} = 4'b1000;
-                        endcase
-                    end
-                    default: begin
-                        ram_wdata_a1 = WDATA_A1_i;
-                        ram_wdata_a2 = WDATA_A1_i;
-                        ram_be_a2 = (FMODE1_i ? 2'b11 : BE_A1_i);
-                        ram_be_a1 = (FMODE1_i ? 2'b11 : BE_A1_i);
-                    end
-                endcase
-                case (WMODE_B1_i)
-                    MODE_36: begin
-                        ram_wdata_b1 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i);
-                        ram_wdata_b2 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B2_i);
-                        ram_be_b2 = BE_B2_i;
-                        ram_be_b1 = BE_B1_i;
-                    end
-                    MODE_18: begin
-                        ram_wdata_b1 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i);
-                        ram_wdata_b2 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i);
-                        ram_be_b1 = BE_B1_i;
-                        ram_be_b2 = BE_B1_i;
-                    end
-                    MODE_9: begin
-                        ram_wdata_b1[7:0] = WDATA_B1_i[7:0];
-                        ram_wdata_b1[16] = WDATA_B1_i[16];
-                        ram_wdata_b1[15:8] = WDATA_B1_i[7:0];
-                        ram_wdata_b1[17] = WDATA_B1_i[16];
-                        ram_wdata_b2[7:0] = WDATA_B1_i[7:0];
-                        ram_wdata_b2[16] = WDATA_B1_i[16];
-                        ram_wdata_b2[15:8] = WDATA_B1_i[7:0];
-                        ram_wdata_b2[17] = WDATA_B1_i[16];
-                        case (ADDR_B1_i[4:3])
-                            0: {ram_be_b2, ram_be_b1} = 4'b0001;
-                            1: {ram_be_b2, ram_be_b1} = 4'b0010;
-                            2: {ram_be_b2, ram_be_b1} = 4'b0100;
-                            3: {ram_be_b2, ram_be_b1} = 4'b1000;
-                        endcase
-                    end
-                    default: begin
-                        ram_wdata_b1 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i);
-                        ram_wdata_b2 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i);
-                        ram_be_b2 = BE_B1_i;
-                        ram_be_b1 = BE_B1_i;
-                    end
-                endcase
-            end
-        endcase
-    end
-    assign ram_rmode_a1 = (SPLIT_i ? (RMODE_A1_i == MODE_36 ? MODE_18 : RMODE_A1_i) : (RMODE_A1_i == MODE_36 ? MODE_18 : RMODE_A1_i));
-    assign ram_rmode_a2 = (SPLIT_i ? (RMODE_A2_i == MODE_36 ? MODE_18 : RMODE_A2_i) : (RMODE_A1_i == MODE_36 ? MODE_18 : RMODE_A1_i));
-    assign ram_wmode_a1 = (SPLIT_i ? (WMODE_A1_i == MODE_36 ? MODE_18 : WMODE_A1_i) : (WMODE_A1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : WMODE_A1_i)));
-    assign ram_wmode_a2 = (SPLIT_i ? (WMODE_A2_i == MODE_36 ? MODE_18 : WMODE_A2_i) : (WMODE_A1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : WMODE_A1_i)));
-    assign ram_rmode_b1 = (SPLIT_i ? (RMODE_B1_i == MODE_36 ? MODE_18 : RMODE_B1_i) : (RMODE_B1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : RMODE_B1_i)));
-    assign ram_rmode_b2 = (SPLIT_i ? (RMODE_B2_i == MODE_36 ? MODE_18 : RMODE_B2_i) : (RMODE_B1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : RMODE_B1_i)));
-    assign ram_wmode_b1 = (SPLIT_i ? (WMODE_B1_i == MODE_36 ? MODE_18 : WMODE_B1_i) : (WMODE_B1_i == MODE_36 ? MODE_18 : WMODE_B1_i));
-    assign ram_wmode_b2 = (SPLIT_i ? (WMODE_B2_i == MODE_36 ? MODE_18 : WMODE_B2_i) : (WMODE_B1_i == MODE_36 ? MODE_18 : WMODE_B1_i));
-    always @(*) begin : FIFO_READ_SEL
-        case (RMODE_B1_i)
-            MODE_36: fifo_rdata = {ram_rdata_b2[17:16], ram_rdata_b1[17:16], ram_rdata_b2[15:0], ram_rdata_b1[15:0]};
-            MODE_18: fifo_rdata = (ff_raddr[1] ? {18'b000000000000000000, ram_rdata_b2} : {18'b000000000000000000, ram_rdata_b1});
-            MODE_9:
-                case (ff_raddr[1:0])
-                    0: fifo_rdata = {19'b0000000000000000000, ram_rdata_b1[16], 8'b00000000, ram_rdata_b1[7:0]};
-                    1: fifo_rdata = {19'b0000000000000000000, ram_rdata_b1[17], 8'b00000000, ram_rdata_b1[15:8]};
-                    2: fifo_rdata = {19'b0000000000000000000, ram_rdata_b2[16], 8'b00000000, ram_rdata_b2[7:0]};
-                    3: fifo_rdata = {19'b0000000000000000000, ram_rdata_b2[17], 8'b00000000, ram_rdata_b2[15:8]};
-                endcase
-            default: fifo_rdata = {ram_rdata_b2, ram_rdata_b1};
-        endcase
-    end
-    localparam MODE_1 = 3'b101;
-    localparam MODE_2 = 3'b110;
-    localparam MODE_4 = 3'b100;
-    always @(*) begin : RDATA_SEL
-        case (SPLIT_i)
-            1: begin
-                RDATA_A1_o = (FMODE1_i ? {10'b0000000000, EMPTY1, EPO1, EWM1, UNDERRUN1, FULL1, FMO1, FWM1, OVERRUN1} : ram_rdata_a1);
-                RDATA_B1_o = ram_rdata_b1;
-                RDATA_A2_o = (FMODE2_i ? {10'b0000000000, EMPTY2, EPO2, EWM2, UNDERRUN2, FULL2, FMO2, FWM2, OVERRUN2} : ram_rdata_a2);
-                RDATA_B2_o = ram_rdata_b2;
-            end
-            0: begin
-                if (FMODE1_i) begin
-                    RDATA_A1_o = {10'b0000000000, EMPTY3, EPO3, EWM3, UNDERRUN3, FULL3, FMO3, FWM3, OVERRUN3};
-                    RDATA_A2_o = 18'b000000000000000000;
-                end
-                else
-                    case (RMODE_A1_i)
-                        MODE_36: begin
-                            RDATA_A1_o = {ram_rdata_a1[17:0]};
-                            RDATA_A2_o = {ram_rdata_a2[17:0]};
-                        end
-                        MODE_18: begin
-                            RDATA_A1_o = (laddr_a1[4] ? ram_rdata_a2 : ram_rdata_a1);
-                            RDATA_A2_o = 18'b000000000000000000;
-                        end
-                        MODE_9: begin
-                            RDATA_A1_o = (laddr_a1[4] ? {{2 {ram_rdata_a2[16]}}, {2 {ram_rdata_a2[7:0]}}} : {{2 {ram_rdata_a1[16]}}, {2 {ram_rdata_a1[7:0]}}});
-                            RDATA_A2_o = 18'b000000000000000000;
-                        end
-                        MODE_4: begin
-                            RDATA_A2_o = 18'b000000000000000000;
-                            RDATA_A1_o[17:4] = 14'b00000000000000;
-                            RDATA_A1_o[3:0] = (laddr_a1[4] ? ram_rdata_a2[3:0] : ram_rdata_a1[3:0]);
-                        end
-                        MODE_2: begin
-                            RDATA_A2_o = 18'b000000000000000000;
-                            RDATA_A1_o[17:2] = 16'b0000000000000000;
-                            RDATA_A1_o[1:0] = (laddr_a1[4] ? ram_rdata_a2[1:0] : ram_rdata_a1[1:0]);
-                        end
-                        MODE_1: begin
-                            RDATA_A2_o = 18'b000000000000000000;
-                            RDATA_A1_o[17:1] = 17'b00000000000000000;
-                            RDATA_A1_o[0] = (laddr_a1[4] ? ram_rdata_a2[0] : ram_rdata_a1[0]);
-                        end
-                        default: begin
-                            RDATA_A1_o = {ram_rdata_a2[1:0], ram_rdata_a1[15:0]};
-                            RDATA_A2_o = {ram_rdata_a2[17:16], ram_rdata_a1[17:16], ram_rdata_a2[15:2]};
-                        end
-                    endcase
-                case (RMODE_B1_i)
-                    MODE_36: begin
-                        RDATA_B1_o = {ram_rdata_b1};
-                        RDATA_B2_o = {ram_rdata_b2};
-                    end
-                    MODE_18: begin
-                        RDATA_B1_o = (FMODE1_i ? fifo_rdata[17:0] : (laddr_b1[4] ? ram_rdata_b2 : ram_rdata_b1));
-                        RDATA_B2_o = 18'b000000000000000000;
-                    end
-                    MODE_9: begin
-                        RDATA_B1_o = (FMODE1_i ? {fifo_rdata[17:0]} : (laddr_b1[4] ? {1'b0, ram_rdata_b2[16], 8'b00000000, ram_rdata_b2[7:0]} : {1'b0, ram_rdata_b1[16], 8'b00000000, ram_rdata_b1[7:0]}));
-                        RDATA_B2_o = 18'b000000000000000000;
-                    end
-                    MODE_4: begin
-                        RDATA_B2_o = 18'b000000000000000000;
-                        RDATA_B1_o[17:4] = 14'b00000000000000;
-                        RDATA_B1_o[3:0] = (laddr_b1[4] ? ram_rdata_b2[3:0] : ram_rdata_b1[3:0]);
-                    end
-                    MODE_2: begin
-                        RDATA_B2_o = 18'b000000000000000000;
-                        RDATA_B1_o[17:2] = 16'b0000000000000000;
-                        RDATA_B1_o[1:0] = (laddr_b1[4] ? ram_rdata_b2[1:0] : ram_rdata_b1[1:0]);
-                    end
-                    MODE_1: begin
-                        RDATA_B2_o = 18'b000000000000000000;
-                        RDATA_B1_o[17:1] = 17'b00000000000000000;
-                        RDATA_B1_o[0] = (laddr_b1[4] ? ram_rdata_b2[0] : ram_rdata_b1[0]);
-                    end
-                    default: begin
-                        RDATA_B1_o = ram_rdata_b1;
-                        RDATA_B2_o = ram_rdata_b2;
-                    end
-                endcase
-            end
-        endcase
-    end
-    always @(posedge sclk_a1 or negedge sreset)
-        if (sreset == 0)
-            laddr_a1 <= 1'sb0;
-        else
-            laddr_a1 <= ADDR_A1_i;
-    always @(posedge sclk_b1 or negedge sreset)
-        if (sreset == 0)
-            laddr_b1 <= 1'sb0;
-        else
-            laddr_b1 <= ADDR_B1_i;
-    assign fifo_wmode = ((WMODE_A1_i == MODE_36) ? 2'b00 : ((WMODE_A1_i == MODE_18) ? 2'b01 : ((WMODE_A1_i == MODE_9) ? 2'b10 : 2'b00)));
-    assign fifo_rmode = ((RMODE_B1_i == MODE_36) ? 2'b00 : ((RMODE_B1_i == MODE_18) ? 2'b01 : ((RMODE_B1_i == MODE_9) ? 2'b10 : 2'b00)));
-    fifo_ctl #(
-        .ADDR_WIDTH(12),
-        .FIFO_WIDTH(3'd4),
-        .DEPTH(7)
-    ) fifo36_ctl(
-        .rclk(sclk_b1),
-        .rst_R_n(flush1),
-        .wclk(sclk_a1),
-        .rst_W_n(flush1),
-        .ren(REN_B1_i),
-        .wen(ram_wen_a1),
-        .sync(SYNC_FIFO1_i),
-        .rmode(fifo_rmode),
-        .wmode(fifo_wmode),
-        .ren_o(ren_o),
-        .fflags({FULL3, FMO3, FWM3, OVERRUN3, EMPTY3, EPO3, EWM3, UNDERRUN3}),
-        .raddr(ff_raddr),
-        .waddr(ff_waddr),
-        .upaf(UPAF1_i),
-        .upae(UPAE1_i)
-    );
-    TDP18K_FIFO #(
-        .UPAF_i(UPAF1_i[10:0]),
-        .UPAE_i(UPAE1_i[10:0]),
-        .SYNC_FIFO_i(SYNC_FIFO1_i),
-        .POWERDN_i(POWERDN1_i),
-        .SLEEP_i(SLEEP1_i),
-        .PROTECT_i(PROTECT1_i)
-    )u1(
-        .RMODE_A_i(ram_rmode_a1),
-        .RMODE_B_i(ram_rmode_b1),
-        .WMODE_A_i(ram_wmode_a1),
-        .WMODE_B_i(ram_wmode_b1),
-        .WEN_A_i(ram_wen_a1),
-        .WEN_B_i(ram_wen_b1),
-        .REN_A_i(ram_ren_a1),
-        .REN_B_i(ram_ren_b1),
-        .CLK_A_i(sclk_a1),
-        .CLK_B_i(sclk_b1),
-        .BE_A_i(ram_be_a1),
-        .BE_B_i(ram_be_b1),
-        .ADDR_A_i(ram_addr_a1),
-        .ADDR_B_i(ram_addr_b1),
-        .WDATA_A_i(ram_wdata_a1),
-        .WDATA_B_i(ram_wdata_b1),
-        .RDATA_A_o(ram_rdata_a1),
-        .RDATA_B_o(ram_rdata_b1),
-        .EMPTY_o(EMPTY1),
-        .EPO_o(EPO1),
-        .EWM_o(EWM1),
-        .UNDERRUN_o(UNDERRUN1),
-        .FULL_o(FULL1),
-        .FMO_o(FMO1),
-        .FWM_o(FWM1),
-        .OVERRUN_o(OVERRUN1),
-        .FLUSH_ni(flush1),
-        .FMODE_i(ram_fmode1)
-    );
-    TDP18K_FIFO #(
-        .UPAF_i(UPAF2_i),
-        .UPAE_i(UPAE2_i),
-        .SYNC_FIFO_i(SYNC_FIFO2_i),
-        .POWERDN_i(POWERDN2_i),
-        .SLEEP_i(SLEEP2_i),
-        .PROTECT_i(PROTECT2_i)
-    )u2(
-        .RMODE_A_i(ram_rmode_a2),
-        .RMODE_B_i(ram_rmode_b2),
-        .WMODE_A_i(ram_wmode_a2),
-        .WMODE_B_i(ram_wmode_b2),
-        .WEN_A_i(ram_wen_a2),
-        .WEN_B_i(ram_wen_b2),
-        .REN_A_i(ram_ren_a2),
-        .REN_B_i(ram_ren_b2),
-        .CLK_A_i(sclk_a2),
-        .CLK_B_i(sclk_b2),
-        .BE_A_i(ram_be_a2),
-        .BE_B_i(ram_be_b2),
-        .ADDR_A_i(ram_addr_a2),
-        .ADDR_B_i(ram_addr_b2),
-        .WDATA_A_i(ram_wdata_a2),
-        .WDATA_B_i(ram_wdata_b2),
-        .RDATA_A_o(ram_rdata_a2),
-        .RDATA_B_o(ram_rdata_b2),
-        .EMPTY_o(EMPTY2),
-        .EPO_o(EPO2),
-        .EWM_o(EWM2),
-        .UNDERRUN_o(UNDERRUN2),
-        .FULL_o(FULL2),
-        .FMO_o(FMO2),
-        .FWM_o(FWM2),
-        .OVERRUN_o(OVERRUN2),
-        .FLUSH_ni(flush2),
-        .FMODE_i(ram_fmode2)
-    );
-endmodule
-
-module BRAM2x18_TDP (A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN, C1ADDR, C1DATA, C1EN, CLK1, CLK2, CLK3, CLK4, D1ADDR, D1DATA, D1EN, E1ADDR, E1DATA, E1EN, F1ADDR, F1DATA, F1EN, G1ADDR, G1DATA, G1EN, H1ADDR, H1DATA, H1EN);
-    parameter CFG_ABITS = 11;
-    parameter CFG_DBITS = 18;
-    parameter CFG_ENABLE_B = 4;
-    parameter CFG_ENABLE_D = 4;
-    parameter CFG_ENABLE_F = 4;
-    parameter CFG_ENABLE_H = 4;
-
-    parameter CLKPOL2 = 1;
-    parameter CLKPOL3 = 1;
-    parameter [18431:0] INIT0 = 18432'bx;
-    parameter [18431:0] INIT1 = 18432'bx;
-
-    localparam MODE_36 = 3'b011; // 36- or 32-bit
-    localparam MODE_18 = 3'b010; // 18- or 16-bit
-    localparam MODE_9 = 3'b001; // 9- or 8-bit
-    localparam MODE_4 = 3'b100; // 4-bit
-    localparam MODE_2 = 3'b110; // 2-bit
-    localparam MODE_1 = 3'b101; // 1-bit
-
-    input CLK1;
-    input CLK2;
-    input CLK3;
-    input CLK4;
-
-    input [CFG_ABITS-1:0] A1ADDR;
-    output [CFG_DBITS-1:0] A1DATA;
-    input A1EN;
-
-    input [CFG_ABITS-1:0] B1ADDR;
-    input [CFG_DBITS-1:0] B1DATA;
-    input [CFG_ENABLE_B-1:0] B1EN;
-
-    input [CFG_ABITS-1:0] C1ADDR;
-    output [CFG_DBITS-1:0] C1DATA;
-    input C1EN;
-
-    input [CFG_ABITS-1:0] D1ADDR;
-    input [CFG_DBITS-1:0] D1DATA;
-    input [CFG_ENABLE_D-1:0] D1EN;
-
-    input [CFG_ABITS-1:0] E1ADDR;
-    output [CFG_DBITS-1:0] E1DATA;
-    input E1EN;
-
-    input [CFG_ABITS-1:0] F1ADDR;
-    input [CFG_DBITS-1:0] F1DATA;
-    input [CFG_ENABLE_F-1:0] F1EN;
-
-    input [CFG_ABITS-1:0] G1ADDR;
-    output [CFG_DBITS-1:0] G1DATA;
-    input G1EN;
-
-    input [CFG_ABITS-1:0] H1ADDR;
-    input [CFG_DBITS-1:0] H1DATA;
-    input [CFG_ENABLE_H-1:0] H1EN;
-
-    wire FLUSH1;
-    wire FLUSH2;
-    wire SPLIT;
-
-    wire [13:CFG_ABITS] A1ADDR_CMPL = {14-CFG_ABITS{1'b0}};
-    wire [13:CFG_ABITS] B1ADDR_CMPL = {14-CFG_ABITS{1'b0}};
-    wire [13:CFG_ABITS] C1ADDR_CMPL = {14-CFG_ABITS{1'b0}};
-    wire [13:CFG_ABITS] D1ADDR_CMPL = {14-CFG_ABITS{1'b0}};
-    wire [13:CFG_ABITS] E1ADDR_CMPL = {14-CFG_ABITS{1'b0}};
-    wire [13:CFG_ABITS] F1ADDR_CMPL = {14-CFG_ABITS{1'b0}};
-    wire [13:CFG_ABITS] G1ADDR_CMPL = {14-CFG_ABITS{1'b0}};
-    wire [13:CFG_ABITS] H1ADDR_CMPL = {14-CFG_ABITS{1'b0}};
-
-    wire [13:0] A1ADDR_TOTAL = {A1ADDR_CMPL, A1ADDR};
-    wire [13:0] B1ADDR_TOTAL = {B1ADDR_CMPL, B1ADDR};
-    wire [13:0] C1ADDR_TOTAL = {C1ADDR_CMPL, C1ADDR};
-    wire [13:0] D1ADDR_TOTAL = {D1ADDR_CMPL, D1ADDR};
-    wire [13:0] E1ADDR_TOTAL = {E1ADDR_CMPL, E1ADDR};
-    wire [13:0] F1ADDR_TOTAL = {F1ADDR_CMPL, F1ADDR};
-    wire [13:0] G1ADDR_TOTAL = {G1ADDR_CMPL, G1ADDR};
-    wire [13:0] H1ADDR_TOTAL = {H1ADDR_CMPL, H1ADDR};
-
-    wire [17:CFG_DBITS] A1_RDATA_CMPL;
-    wire [17:CFG_DBITS] C1_RDATA_CMPL;
-    wire [17:CFG_DBITS] E1_RDATA_CMPL;
-    wire [17:CFG_DBITS] G1_RDATA_CMPL;
-
-    wire [17:CFG_DBITS] B1_WDATA_CMPL;
-    wire [17:CFG_DBITS] D1_WDATA_CMPL;
-    wire [17:CFG_DBITS] F1_WDATA_CMPL;
-    wire [17:CFG_DBITS] H1_WDATA_CMPL;
-
-    wire [13:0] PORT_A1_ADDR;
-    wire [13:0] PORT_A2_ADDR;
-    wire [13:0] PORT_B1_ADDR;
-    wire [13:0] PORT_B2_ADDR;
-
-    case (CFG_DBITS)
-        1: begin
-            assign PORT_A1_ADDR = A1EN ? A1ADDR_TOTAL : (B1EN ? B1ADDR_TOTAL : 14'd0);
-            assign PORT_B1_ADDR = C1EN ? C1ADDR_TOTAL : (D1EN ? D1ADDR_TOTAL : 14'd0);
-            assign PORT_A2_ADDR = E1EN ? E1ADDR_TOTAL : (F1EN ? F1ADDR_TOTAL : 14'd0);
-            assign PORT_B2_ADDR = G1EN ? G1ADDR_TOTAL : (H1EN ? H1ADDR_TOTAL : 14'd0);
-            defparam bram_2x18k.MODE_BITS = { 1'b1,
-                11'd10, 11'd10, 4'd0, MODE_1, MODE_1, MODE_1, MODE_1, 1'd0,
-                12'd10, 12'd10, 4'd0, MODE_1, MODE_1, MODE_1, MODE_1, 1'd0
-            };
-        end
-
-        2: begin
-            assign PORT_A1_ADDR = A1EN ? (A1ADDR_TOTAL << 1) : (B1EN ? (B1ADDR_TOTAL << 1) : 14'd0);
-            assign PORT_B1_ADDR = C1EN ? (C1ADDR_TOTAL << 1) : (D1EN ? (D1ADDR_TOTAL << 1) : 14'd0);
-            assign PORT_A2_ADDR = E1EN ? (E1ADDR_TOTAL << 1) : (F1EN ? (F1ADDR_TOTAL << 1) : 14'd0);
-            assign PORT_B2_ADDR = G1EN ? (G1ADDR_TOTAL << 1) : (H1EN ? (H1ADDR_TOTAL << 1) : 14'd0);
-            defparam bram_2x18k.MODE_BITS = { 1'b1,
-                11'd10, 11'd10, 4'd0, MODE_2, MODE_2, MODE_2, MODE_2, 1'd0,
-                12'd10, 12'd10, 4'd0, MODE_2, MODE_2, MODE_2, MODE_2, 1'd0
-            };
-        end
-
-        4: begin
-            assign PORT_A1_ADDR = A1EN ? (A1ADDR_TOTAL << 2) : (B1EN ? (B1ADDR_TOTAL << 2) : 14'd0);
-            assign PORT_B1_ADDR = C1EN ? (C1ADDR_TOTAL << 2) : (D1EN ? (D1ADDR_TOTAL << 2) : 14'd0);
-            assign PORT_A2_ADDR = E1EN ? (E1ADDR_TOTAL << 2) : (F1EN ? (F1ADDR_TOTAL << 2) : 14'd0);
-            assign PORT_B2_ADDR = G1EN ? (G1ADDR_TOTAL << 2) : (H1EN ? (H1ADDR_TOTAL << 2) : 14'd0);
-            defparam bram_2x18k.MODE_BITS = { 1'b1,
-                11'd10, 11'd10, 4'd0, MODE_4, MODE_4, MODE_4, MODE_4, 1'd0,
-                12'd10, 12'd10, 4'd0, MODE_4, MODE_4, MODE_4, MODE_4, 1'd0
-            };
-        end
-
-        8, 9: begin
-            assign PORT_A1_ADDR = A1EN ? (A1ADDR_TOTAL << 3) : (B1EN ? (B1ADDR_TOTAL << 3) : 14'd0);
-            assign PORT_B1_ADDR = C1EN ? (C1ADDR_TOTAL << 3) : (D1EN ? (D1ADDR_TOTAL << 3) : 14'd0);
-            assign PORT_A2_ADDR = E1EN ? (E1ADDR_TOTAL << 3) : (F1EN ? (F1ADDR_TOTAL << 3) : 14'd0);
-            assign PORT_B2_ADDR = G1EN ? (G1ADDR_TOTAL << 3) : (H1EN ? (H1ADDR_TOTAL << 3) : 14'd0);
-            defparam bram_2x18k.MODE_BITS = { 1'b1,
-                11'd10, 11'd10, 4'd0, MODE_9, MODE_9, MODE_9, MODE_9, 1'd0,
-                12'd10, 12'd10, 4'd0, MODE_9, MODE_9, MODE_9, MODE_9, 1'd0
-            };
-        end
-
-        16, 18: begin
-            assign PORT_A1_ADDR = A1EN ? (A1ADDR_TOTAL << 4) : (B1EN ? (B1ADDR_TOTAL << 4) : 14'd0);
-            assign PORT_B1_ADDR = C1EN ? (C1ADDR_TOTAL << 4) : (D1EN ? (D1ADDR_TOTAL << 4) : 14'd0);
-            assign PORT_A2_ADDR = E1EN ? (E1ADDR_TOTAL << 4) : (F1EN ? (F1ADDR_TOTAL << 4) : 14'd0);
-            assign PORT_B2_ADDR = G1EN ? (G1ADDR_TOTAL << 4) : (H1EN ? (H1ADDR_TOTAL << 4) : 14'd0);
-            defparam bram_2x18k.MODE_BITS = { 1'b1,
-                11'd10, 11'd10, 4'd0, MODE_18, MODE_18, MODE_18, MODE_18, 1'd0,
-                12'd10, 12'd10, 4'd0, MODE_18, MODE_18, MODE_18, MODE_18, 1'd0
-            };
-        end
-
-        default: begin
-            assign PORT_A1_ADDR = A1EN ? A1ADDR_TOTAL : (B1EN ? B1ADDR_TOTAL : 14'd0);
-            assign PORT_B1_ADDR = C1EN ? C1ADDR_TOTAL : (D1EN ? D1ADDR_TOTAL : 14'd0);
-            assign PORT_A2_ADDR = E1EN ? E1ADDR_TOTAL : (F1EN ? F1ADDR_TOTAL : 14'd0);
-            assign PORT_B2_ADDR = G1EN ? G1ADDR_TOTAL : (H1EN ? H1ADDR_TOTAL : 14'd0);
-            defparam bram_2x18k.MODE_BITS = { 1'b1,
-                11'd10, 11'd10, 4'd0, MODE_36, MODE_36, MODE_36, MODE_36, 1'd0,
-                12'd10, 12'd10, 4'd0, MODE_36, MODE_36, MODE_36, MODE_36, 1'd0
-            };
-        end
-    endcase
-
-    assign FLUSH1 = 1'b0;
-    assign FLUSH2 = 1'b0;
-
-    wire [17:0] PORT_A1_RDATA = {A1_RDATA_CMPL, A1DATA};
-    wire [17:0] PORT_B1_RDATA = {C1_RDATA_CMPL, C1DATA};
-    wire [17:0] PORT_A2_RDATA = {E1_RDATA_CMPL, E1DATA};
-    wire [17:0] PORT_B2_RDATA = {G1_RDATA_CMPL, G1DATA};
-
-    wire [17:0] PORT_A1_WDATA = {B1_WDATA_CMPL, B1DATA};
-    wire [17:0] PORT_B1_WDATA = {D1_WDATA_CMPL, D1DATA};
-    wire [17:0] PORT_A2_WDATA = {F1_WDATA_CMPL, F1DATA};
-    wire [17:0] PORT_B2_WDATA = {H1_WDATA_CMPL, H1DATA};
-
-    wire PORT_A1_CLK = CLK1;
-    wire PORT_A2_CLK = CLK3;
-    wire PORT_B1_CLK = CLK2;
-    wire PORT_B2_CLK = CLK4;
-
-    wire PORT_A1_REN = A1EN;
-    wire PORT_A1_WEN = B1EN[0];
-    wire [CFG_ENABLE_B-1:0] PORT_A1_BE = {B1EN[1],B1EN[0]};
-
-    wire PORT_A2_REN = E1EN;
-    wire PORT_A2_WEN = F1EN[0];
-    wire [CFG_ENABLE_F-1:0] PORT_A2_BE = {F1EN[1],F1EN[0]};
-
-    wire PORT_B1_REN = C1EN;
-    wire PORT_B1_WEN = D1EN[0];
-    wire [CFG_ENABLE_D-1:0] PORT_B1_BE = {D1EN[1],D1EN[0]};
-
-    wire PORT_B2_REN = G1EN;
-    wire PORT_B2_WEN = H1EN[0];
-    wire [CFG_ENABLE_H-1:0] PORT_B2_BE = {H1EN[1],H1EN[0]};
-
-    TDP36K bram_2x18k (
-        .WDATA_A1_i(PORT_A1_WDATA),
-        .RDATA_A1_o(PORT_A1_RDATA),
-        .ADDR_A1_i(PORT_A1_ADDR),
-        .CLK_A1_i(PORT_A1_CLK),
-        .REN_A1_i(PORT_A1_REN),
-        .WEN_A1_i(PORT_A1_WEN),
-        .BE_A1_i(PORT_A1_BE),
-
-        .WDATA_A2_i(PORT_A2_WDATA),
-        .RDATA_A2_o(PORT_A2_RDATA),
-        .ADDR_A2_i(PORT_A2_ADDR),
-        .CLK_A2_i(PORT_A2_CLK),
-        .REN_A2_i(PORT_A2_REN),
-        .WEN_A2_i(PORT_A2_WEN),
-        .BE_A2_i(PORT_A2_BE),
-
-        .WDATA_B1_i(PORT_B1_WDATA),
-        .RDATA_B1_o(PORT_B1_RDATA),
-        .ADDR_B1_i(PORT_B1_ADDR),
-        .CLK_B1_i(PORT_B1_CLK),
-        .REN_B1_i(PORT_B1_REN),
-        .WEN_B1_i(PORT_B1_WEN),
-        .BE_B1_i(PORT_B1_BE),
-
-        .WDATA_B2_i(PORT_B2_WDATA),
-        .RDATA_B2_o(PORT_B2_RDATA),
-        .ADDR_B2_i(PORT_B2_ADDR),
-        .CLK_B2_i(PORT_B2_CLK),
-        .REN_B2_i(PORT_B2_REN),
-        .WEN_B2_i(PORT_B2_WEN),
-        .BE_B2_i(PORT_B2_BE),
-
-        .FLUSH1_i(FLUSH1),
-        .FLUSH2_i(FLUSH2)
-    );
-endmodule
-
-module BRAM2x18_SDP (A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN, C1ADDR, C1DATA, C1EN, CLK1, CLK2, D1ADDR, D1DATA, D1EN);
-    parameter CFG_ABITS = 11;
-    parameter CFG_DBITS = 18;
-    parameter CFG_ENABLE_B = 4;
-    parameter CFG_ENABLE_D = 4;
-
-    parameter CLKPOL2 = 1;
-    parameter CLKPOL3 = 1;
-    parameter [18431:0] INIT0 = 18432'bx;
-    parameter [18431:0] INIT1 = 18432'bx;
-
-    localparam MODE_36 = 3'b011; // 36- or 32-bit
-    localparam MODE_18 = 3'b010; // 18- or 16-bit
-    localparam MODE_9 = 3'b001; // 9- or 8-bit
-    localparam MODE_4 = 3'b100; // 4-bit
-    localparam MODE_2 = 3'b110; // 2-bit
-    localparam MODE_1 = 3'b101; // 1-bit
-
-    input CLK1;
-    input CLK2;
-
-    input [CFG_ABITS-1:0] A1ADDR;
-    output [CFG_DBITS-1:0] A1DATA;
-    input A1EN;
-
-    input [CFG_ABITS-1:0] B1ADDR;
-    input [CFG_DBITS-1:0] B1DATA;
-    input [CFG_ENABLE_B-1:0] B1EN;
-
-    input [CFG_ABITS-1:0] C1ADDR;
-    output [CFG_DBITS-1:0] C1DATA;
-    input C1EN;
-
-    input [CFG_ABITS-1:0] D1ADDR;
-    input [CFG_DBITS-1:0] D1DATA;
-    input [CFG_ENABLE_D-1:0] D1EN;
-
-    wire FLUSH1;
-    wire FLUSH2;
-
-    wire [13:CFG_ABITS] A1ADDR_CMPL = {14-CFG_ABITS{1'b0}};
-    wire [13:CFG_ABITS] B1ADDR_CMPL = {14-CFG_ABITS{1'b0}};
-    wire [13:CFG_ABITS] C1ADDR_CMPL = {14-CFG_ABITS{1'b0}};
-    wire [13:CFG_ABITS] D1ADDR_CMPL = {14-CFG_ABITS{1'b0}};
-
-    wire [13:0] A1ADDR_TOTAL = {A1ADDR_CMPL, A1ADDR};
-    wire [13:0] B1ADDR_TOTAL = {B1ADDR_CMPL, B1ADDR};
-    wire [13:0] C1ADDR_TOTAL = {C1ADDR_CMPL, C1ADDR};
-    wire [13:0] D1ADDR_TOTAL = {D1ADDR_CMPL, D1ADDR};
-
-    wire [17:CFG_DBITS] A1_RDATA_CMPL;
-    wire [17:CFG_DBITS] C1_RDATA_CMPL;
-
-    wire [17:CFG_DBITS] B1_WDATA_CMPL;
-    wire [17:CFG_DBITS] D1_WDATA_CMPL;
-
-    wire [13:0] PORT_A1_ADDR;
-    wire [13:0] PORT_A2_ADDR;
-    wire [13:0] PORT_B1_ADDR;
-    wire [13:0] PORT_B2_ADDR;
-
-    case (CFG_DBITS)
-        1: begin
-            assign PORT_A1_ADDR = A1ADDR_TOTAL;
-            assign PORT_B1_ADDR = B1ADDR_TOTAL;
-            assign PORT_A2_ADDR = C1ADDR_TOTAL;
-            assign PORT_B2_ADDR = D1ADDR_TOTAL;
-            defparam bram_2x18k.MODE_BITS = { 1'b1,
-                11'd10, 11'd10, 4'd0, MODE_1, MODE_1, MODE_1, MODE_1, 1'd0,
-                12'd10, 12'd10, 4'd0, MODE_1, MODE_1, MODE_1, MODE_1, 1'd0
-            };
-        end
-
-        2: begin
-            assign PORT_A1_ADDR = A1ADDR_TOTAL << 1;
-            assign PORT_B1_ADDR = B1ADDR_TOTAL << 1;
-            assign PORT_A2_ADDR = C1ADDR_TOTAL << 1;
-            assign PORT_B2_ADDR = D1ADDR_TOTAL << 1;
-            defparam bram_2x18k.MODE_BITS = { 1'b1,
-                11'd10, 11'd10, 4'd0, MODE_2, MODE_2, MODE_2, MODE_2, 1'd0,
-                12'd10, 12'd10, 4'd0, MODE_2, MODE_2, MODE_2, MODE_2, 1'd0
-            };
-        end
-
-        4: begin
-            assign PORT_A1_ADDR = A1ADDR_TOTAL << 2;
-            assign PORT_B1_ADDR = B1ADDR_TOTAL << 2;
-            assign PORT_A2_ADDR = C1ADDR_TOTAL << 2;
-            assign PORT_B2_ADDR = D1ADDR_TOTAL << 2;
-            defparam bram_2x18k.MODE_BITS = { 1'b1,
-                11'd10, 11'd10, 4'd0, MODE_4, MODE_4, MODE_4, MODE_4, 1'd0,
-                12'd10, 12'd10, 4'd0, MODE_4, MODE_4, MODE_4, MODE_4, 1'd0
-            };
-        end
-
-        8, 9: begin
-            assign PORT_A1_ADDR = A1ADDR_TOTAL << 3;
-            assign PORT_B1_ADDR = B1ADDR_TOTAL << 3;
-            assign PORT_A2_ADDR = C1ADDR_TOTAL << 3;
-            assign PORT_B2_ADDR = D1ADDR_TOTAL << 3;
-            defparam bram_2x18k.MODE_BITS = { 1'b1,
-                11'd10, 11'd10, 4'd0, MODE_9, MODE_9, MODE_9, MODE_9, 1'd0,
-                12'd10, 12'd10, 4'd0, MODE_9, MODE_9, MODE_9, MODE_9, 1'd0
-            };
-        end
-
-        16, 18: begin
-            assign PORT_A1_ADDR = A1ADDR_TOTAL << 4;
-            assign PORT_B1_ADDR = B1ADDR_TOTAL << 4;
-            assign PORT_A2_ADDR = C1ADDR_TOTAL << 4;
-            assign PORT_B2_ADDR = D1ADDR_TOTAL << 4;
-            defparam bram_2x18k.MODE_BITS = { 1'b1,
-                11'd10, 11'd10, 4'd0, MODE_18, MODE_18, MODE_18, MODE_18, 1'd0,
-                12'd10, 12'd10, 4'd0, MODE_18, MODE_18, MODE_18, MODE_18, 1'd0
-            };
-        end
-
-        default: begin
-            assign PORT_A1_ADDR = A1ADDR_TOTAL;
-            assign PORT_B1_ADDR = B1ADDR_TOTAL;
-            assign PORT_A2_ADDR = D1ADDR_TOTAL;
-            assign PORT_B2_ADDR = C1ADDR_TOTAL;
-            defparam bram_2x18k.MODE_BITS = { 1'b1,
-                11'd10, 11'd10, 4'd0, MODE_36, MODE_36, MODE_36, MODE_36, 1'd0,
-                12'd10, 12'd10, 4'd0, MODE_36, MODE_36, MODE_36, MODE_36, 1'd0
-            };
-        end
-    endcase
-
-    assign FLUSH1 = 1'b0;
-    assign FLUSH2 = 1'b0;
-
-    wire [17:0] PORT_A1_RDATA;
-    wire [17:0] PORT_B1_RDATA;
-    wire [17:0] PORT_A2_RDATA;
-    wire [17:0] PORT_B2_RDATA;
-
-    wire [17:0] PORT_A1_WDATA;
-    wire [17:0] PORT_B1_WDATA;
-    wire [17:0] PORT_A2_WDATA;
-    wire [17:0] PORT_B2_WDATA;
-
-    // Assign read/write data - handle special case for 9bit mode
-    // parity bit for 9bit mode is placed in R/W port on bit #16
-    case (CFG_DBITS)
-        9: begin
-            assign A1DATA = {PORT_A1_RDATA[16], PORT_A1_RDATA[7:0]};
-            assign C1DATA = {PORT_A2_RDATA[16], PORT_A2_RDATA[7:0]};
-            assign PORT_A1_WDATA = {18{1'b0}};
-            assign PORT_B1_WDATA = {B1_WDATA_CMPL[17], B1DATA[8], B1_WDATA_CMPL[16:9], B1DATA[7:0]};
-            assign PORT_A2_WDATA = {18{1'b0}};
-            assign PORT_B2_WDATA = {D1_WDATA_CMPL[17], D1DATA[8], D1_WDATA_CMPL[16:9], D1DATA[7:0]};
-        end
-        default: begin
-            assign A1DATA = PORT_A1_RDATA[CFG_DBITS-1:0];
-            assign C1DATA = PORT_A2_RDATA[CFG_DBITS-1:0];
-            assign PORT_A1_WDATA = {18{1'b1}};
-            assign PORT_B1_WDATA = {B1_WDATA_CMPL, B1DATA};
-            assign PORT_A2_WDATA = {18{1'b1}};
-            assign PORT_B2_WDATA = {D1_WDATA_CMPL, D1DATA};
-
-        end
-    endcase
-
-    wire PORT_A1_CLK = CLK1;
-    wire PORT_A2_CLK = CLK2;
-    wire PORT_B1_CLK = CLK1;
-    wire PORT_B2_CLK = CLK2;
-
-    wire PORT_A1_REN = A1EN;
-    wire PORT_A1_WEN = 1'b0;
-    wire [CFG_ENABLE_B-1:0] PORT_A1_BE = {PORT_A1_WEN,PORT_A1_WEN};
-
-    wire PORT_A2_REN = C1EN;
-    wire PORT_A2_WEN = 1'b0;
-    wire [CFG_ENABLE_D-1:0] PORT_A2_BE = {PORT_A2_WEN,PORT_A2_WEN};
-
-    wire PORT_B1_REN = 1'b0;
-    wire PORT_B1_WEN = B1EN[0];
-    wire [CFG_ENABLE_B-1:0] PORT_B1_BE = {B1EN[1],B1EN[0]};
-
-    wire PORT_B2_REN = 1'b0;
-    wire PORT_B2_WEN = D1EN[0];
-    wire [CFG_ENABLE_D-1:0] PORT_B2_BE = {D1EN[1],D1EN[0]};
-
-    TDP36K  bram_2x18k (
-        .WDATA_A1_i(PORT_A1_WDATA),
-        .RDATA_A1_o(PORT_A1_RDATA),
-        .ADDR_A1_i(PORT_A1_ADDR),
-        .CLK_A1_i(PORT_A1_CLK),
-        .REN_A1_i(PORT_A1_REN),
-        .WEN_A1_i(PORT_A1_WEN),
-        .BE_A1_i(PORT_A1_BE),
-
-        .WDATA_A2_i(PORT_A2_WDATA),
-        .RDATA_A2_o(PORT_A2_RDATA),
-        .ADDR_A2_i(PORT_A2_ADDR),
-        .CLK_A2_i(PORT_A2_CLK),
-        .REN_A2_i(PORT_A2_REN),
-        .WEN_A2_i(PORT_A2_WEN),
-        .BE_A2_i(PORT_A2_BE),
-
-        .WDATA_B1_i(PORT_B1_WDATA),
-        .RDATA_B1_o(PORT_B1_RDATA),
-        .ADDR_B1_i(PORT_B1_ADDR),
-        .CLK_B1_i(PORT_B1_CLK),
-        .REN_B1_i(PORT_B1_REN),
-        .WEN_B1_i(PORT_B1_WEN),
-        .BE_B1_i(PORT_B1_BE),
-
-        .WDATA_B2_i(PORT_B2_WDATA),
-        .RDATA_B2_o(PORT_B2_RDATA),
-        .ADDR_B2_i(PORT_B2_ADDR),
-        .CLK_B2_i(PORT_B2_CLK),
-        .REN_B2_i(PORT_B2_REN),
-        .WEN_B2_i(PORT_B2_WEN),
-        .BE_B2_i(PORT_B2_BE),
-
-        .FLUSH1_i(FLUSH1),
-        .FLUSH2_i(FLUSH2)
-    );
-endmodule
-
-module \_$_mem_v2_asymmetric (RD_ADDR, RD_ARST, RD_CLK, RD_DATA, RD_EN, RD_SRST, WR_ADDR, WR_CLK, WR_DATA, WR_EN);
-    localparam CFG_ABITS = 10;
-    localparam CFG_DBITS = 36;
-    localparam CFG_ENABLE_B = 4;
-
-    localparam CLKPOL2 = 1;
-    localparam CLKPOL3 = 1;
-
-    parameter READ_ADDR_WIDTH = 11;
-    parameter READ_DATA_WIDTH = 16;
-    parameter WRITE_ADDR_WIDTH = 10;
-    parameter WRITE_DATA_WIDTH = 32;
-    parameter ABITS = 0;
-    parameter MEMID = 0;
-    parameter [36863:0] INIT = 36864'bx;
-    parameter OFFSET = 0;
-    parameter RD_ARST_VALUE = 0;
-    parameter RD_CE_OVER_SRST = 0;
-    parameter RD_CLK_ENABLE = 0;
-    parameter RD_CLK_POLARITY = 0;
-    parameter RD_COLLISION_X_MASK = 0;
-    parameter RD_INIT_VALUE = 0;
-    parameter RD_PORTS = 0;
-    parameter RD_SRST_VALUE = 0;
-    parameter RD_TRANSPARENCY_MASK = 0;
-    parameter RD_WIDE_CONTINUATION = 0;
-    parameter SIZE = 0;
-    parameter WIDTH = 0;
-    parameter WR_CLK_ENABLE = 0;
-    parameter WR_CLK_POLARITY = 0;
-    parameter WR_PORTS = 0;
-    parameter WR_PRIORITY_MASK = 0;
-    parameter WR_WIDE_CONTINUATION = 0;
-
-    localparam MODE_36  = 3'b111;   // 36 or 32-bit
-    localparam MODE_18  = 3'b110;   // 18 or 16-bit
-    localparam MODE_9   = 3'b101;   // 9 or 8-bit
-    localparam MODE_4   = 3'b100;   // 4-bit
-    localparam MODE_2   = 3'b010;   // 32-bit
-    localparam MODE_1   = 3'b001;   // 32-bit
-
-    input RD_CLK;
-    input WR_CLK;
-    input RD_ARST;
-    input RD_SRST;
-
-    input [CFG_ABITS-1:0] RD_ADDR;
-    output [CFG_DBITS-1:0] RD_DATA;
-    input RD_EN;
-
-    input [CFG_ABITS-1:0] WR_ADDR;
-    input [CFG_DBITS-1:0] WR_DATA;
-    input [CFG_ENABLE_B-1:0] WR_EN;
-
-    wire [14:0] RD_ADDR_15;
-    wire [14:0] WR_ADDR_15;
-
-    wire [35:0] DOBDO;
-
-    wire [14:CFG_ABITS] RD_ADDR_CMPL;
-    wire [14:CFG_ABITS] WR_ADDR_CMPL;
-    wire [35:CFG_DBITS] RD_DATA_CMPL;
-    wire [35:CFG_DBITS] WR_DATA_CMPL;
-
-    wire [14:0] RD_ADDR_TOTAL;
-    wire [14:0] WR_ADDR_TOTAL;
-    wire [35:0] RD_DATA_TOTAL;
-    wire [35:0] WR_DATA_TOTAL;
-
-    wire FLUSH1;
-    wire FLUSH2;
-
-    assign RD_ADDR_CMPL = {15-CFG_ABITS{1'b0}};
-    assign WR_ADDR_CMPL = {15-CFG_ABITS{1'b0}};
-
-    assign RD_ADDR_TOTAL = {RD_ADDR_CMPL, RD_ADDR};
-    assign WR_ADDR_TOTAL = {WR_ADDR_CMPL, WR_ADDR};
-
-    assign RD_DATA_TOTAL = {RD_DATA_CMPL, RD_DATA};
-    assign WR_DATA_TOTAL = {WR_DATA_CMPL, WR_DATA};
-
-    case (CFG_DBITS)
-        1: begin
-            assign RD_ADDR_15 = RD_ADDR_TOTAL;
-            assign WR_ADDR_15 = WR_ADDR_TOTAL;
-            defparam bram_asymmetric.MODE_BITS = { 1'b0,
-                11'd10, 11'd10, 4'd0, MODE_1, MODE_1, MODE_1, MODE_1, 1'd0,
-                12'd10, 12'd10, 4'd0, MODE_1, MODE_1, MODE_1, MODE_1, 1'd0
-            };
-        end
-
-        2: begin
-            assign RD_ADDR_15 = RD_ADDR_TOTAL << 1;
-            assign WR_ADDR_15 = WR_ADDR_TOTAL << 1;
-            defparam bram_asymmetric.MODE_BITS = { 1'b0,
-                11'd10, 11'd10, 4'd0, MODE_2, MODE_2, MODE_2, MODE_2, 1'd0,
-                12'd10, 12'd10, 4'd0, MODE_2, MODE_2, MODE_2, MODE_2, 1'd0
-            };
-        end
-
-        4: begin
-            assign RD_ADDR_15 = RD_ADDR_TOTAL << 2;
-            assign WR_ADDR_15 = WR_ADDR_TOTAL << 2;
-            defparam bram_asymmetric.MODE_BITS = { 1'b0,
-                11'd10, 11'd10, 4'd0, MODE_4, MODE_4, MODE_4, MODE_4, 1'd0,
-                12'd10, 12'd10, 4'd0, MODE_4, MODE_4, MODE_4, MODE_4, 1'd0
-            };
-        end
-        8, 9: begin
-            assign RD_ADDR_15 = RD_ADDR_TOTAL << 3;
-            assign WR_ADDR_15 = WR_ADDR_TOTAL << 3;
-            defparam bram_asymmetric.MODE_BITS = { 1'b0,
-                11'd10, 11'd10, 4'd0, MODE_9, MODE_9, MODE_9, MODE_9, 1'd0,
-                12'd10, 12'd10, 4'd0, MODE_9, MODE_9, MODE_9, MODE_9, 1'd0
-            };
-        end
-
-        16, 18: begin
-            assign RD_ADDR_15 = RD_ADDR_TOTAL << 4;
-            assign WR_ADDR_15 = WR_ADDR_TOTAL << 4;
-            defparam bram_asymmetric.MODE_BITS = { 1'b0,
-                11'd10, 11'd10, 4'd0, MODE_18, MODE_18, MODE_18, MODE_18, 1'd0,
-                12'd10, 12'd10, 4'd0, MODE_18, MODE_18, MODE_18, MODE_18, 1'd0
-            };
-        end
-        32, 36: begin
-            assign RD_ADDR_15 = RD_ADDR_TOTAL << 5;
-            assign WR_ADDR_15 = WR_ADDR_TOTAL << 5;
-            defparam bram_asymmetric.MODE_BITS = { 1'b0,
-                11'd10, 11'd10, 4'd0, MODE_36, MODE_36, MODE_36, MODE_36, 1'd0,
-                12'd10, 12'd10, 4'd0, MODE_36, MODE_36, MODE_36, MODE_36, 1'd0
-            };
-        end
-        default: begin
-            assign RD_ADDR_15 = RD_ADDR_TOTAL;
-            assign WR_ADDR_15 = WR_ADDR_TOTAL;
-            defparam bram_asymmetric.MODE_BITS = { 1'b0,
-                11'd10, 11'd10, 4'd0, MODE_36, MODE_36, MODE_36, MODE_36, 1'd0,
-                12'd10, 12'd10, 4'd0, MODE_36, MODE_36, MODE_36, MODE_36, 1'd0
-            };
-        end
-    endcase
-
-    assign FLUSH1 = 1'b0;
-    assign FLUSH2 = 1'b0;
-
-    TDP36K bram_asymmetric (
-        .RESET_ni(1'b1),
-        .WDATA_A1_i(18'h3FFFF),
-        .WDATA_A2_i(18'h3FFFF),
-        .RDATA_A1_o(RD_DATA_TOTAL[17:0]),
-        .RDATA_A2_o(RD_DATA_TOTAL[35:18]),
-        .ADDR_A1_i(RD_ADDR_15),
-        .ADDR_A2_i(RD_ADDR_15),
-        .CLK_A1_i(RD_CLK),
-        .CLK_A2_i(RD_CLK),
-        .REN_A1_i(RD_EN),
-        .REN_A2_i(RD_EN),
-        .WEN_A1_i(1'b0),
-        .WEN_A2_i(1'b0),
-        .BE_A1_i({RD_EN, RD_EN}),
-        .BE_A2_i({RD_EN, RD_EN}),
-
-        .WDATA_B1_i(WR_DATA[17:0]),
-        .WDATA_B2_i(WR_DATA[35:18]),
-        .RDATA_B1_o(DOBDO[17:0]),
-        .RDATA_B2_o(DOBDO[35:18]),
-        .ADDR_B1_i(WR_ADDR_15),
-        .ADDR_B2_i(WR_ADDR_15),
-        .CLK_B1_i(WR_CLK),
-        .CLK_B2_i(WR_CLK),
-        .REN_B1_i(1'b0),
-        .REN_B2_i(1'b0),
-        .WEN_B1_i(WR_EN[0]),
-        .WEN_B2_i(WR_EN[0]),
-        .BE_B1_i(WR_EN[1:0]),
-        .BE_B2_i(WR_EN[3:2]),
-
-        .FLUSH1_i(FLUSH1),
-        .FLUSH2_i(FLUSH2)
-    );
-endmodule
diff --git a/ql-qlf-plugin/qlf_k6n10f/dsp_sim.v b/ql-qlf-plugin/qlf_k6n10f/dsp_sim.v
index 14ec751..cdaa81b 100644
--- a/ql-qlf-plugin/qlf_k6n10f/dsp_sim.v
+++ b/ql-qlf-plugin/qlf_k6n10f/dsp_sim.v
@@ -14,6 +14,8 @@
 //
 // SPDX-License-Identifier: Apache-2.0
 
+`timescale 1ps/1ps
+
 `default_nettype none
 
 (* blackbox *)
@@ -221,20 +223,1478 @@
     ) dsp (
         .a(a),
         .b(b),
+        .acc_fir(6'b0),
         .z(z),
+        .dly_b(),
 
+        .clk(1'b0),
         .reset(reset),
 
         .f_mode(f_mode),
 
         .feedback(feedback),
+        .load_acc(1'b0),
 
         .unsigned_a(unsigned_a),
         .unsigned_b(unsigned_b),
 
         .output_select(output_select),      // unregistered output: a * b (0)
+        .saturate_enable(1'b0),
+        .shift_right(6'b0),
+        .round(1'b0),
+        .subtract(1'b0),
         .register_inputs(register_inputs)   // unregistered inputs
     );
+	
+`ifdef SDF_SIM	
+	specify
+        (a[0] => z[0]) = 0;
+        (a[1] => z[0]) = 0;
+        (a[2] => z[0]) = 0;
+        (a[3] => z[0]) = 0;
+        (a[4] => z[0]) = 0;
+        (a[5] => z[0]) = 0;
+        (a[6] => z[0]) = 0;
+        (a[7] => z[0]) = 0;
+        (a[8] => z[0]) = 0;
+        (a[9] => z[0]) = 0;
+        (a[10] => z[0]) = 0;
+        (a[11] => z[0]) = 0;
+        (a[12] => z[0]) = 0;
+        (a[13] => z[0]) = 0;
+        (a[14] => z[0]) = 0;
+        (a[15] => z[0]) = 0;
+        (a[16] => z[0]) = 0;
+        (a[17] => z[0]) = 0;
+        (a[18] => z[0]) = 0;
+        (a[19] => z[0]) = 0;
+        (b[0] => z[0]) = 0;
+        (b[1] => z[0]) = 0;
+        (b[2] => z[0]) = 0;
+        (b[3] => z[0]) = 0;
+        (b[4] => z[0]) = 0;
+        (b[5] => z[0]) = 0;
+        (b[6] => z[0]) = 0;
+        (b[7] => z[0]) = 0;
+        (b[8] => z[0]) = 0;
+        (b[9] => z[0]) = 0;
+        (b[10] => z[0]) = 0;
+        (b[11] => z[0]) = 0;
+        (b[12] => z[0]) = 0;
+        (b[13] => z[0]) = 0;
+        (b[14] => z[0]) = 0;
+        (b[15] => z[0]) = 0;
+        (b[16] => z[0]) = 0;
+        (b[17] => z[0]) = 0;
+        (a[0] => z[1]) = 0;
+        (a[1] => z[1]) = 0;
+        (a[2] => z[1]) = 0;
+        (a[3] => z[1]) = 0;
+        (a[4] => z[1]) = 0;
+        (a[5] => z[1]) = 0;
+        (a[6] => z[1]) = 0;
+        (a[7] => z[1]) = 0;
+        (a[8] => z[1]) = 0;
+        (a[9] => z[1]) = 0;
+        (a[10] => z[1]) = 0;
+        (a[11] => z[1]) = 0;
+        (a[12] => z[1]) = 0;
+        (a[13] => z[1]) = 0;
+        (a[14] => z[1]) = 0;
+        (a[15] => z[1]) = 0;
+        (a[16] => z[1]) = 0;
+        (a[17] => z[1]) = 0;
+        (a[18] => z[1]) = 0;
+        (a[19] => z[1]) = 0;
+        (b[0] => z[1]) = 0;
+        (b[1] => z[1]) = 0;
+        (b[2] => z[1]) = 0;
+        (b[3] => z[1]) = 0;
+        (b[4] => z[1]) = 0;
+        (b[5] => z[1]) = 0;
+        (b[6] => z[1]) = 0;
+        (b[7] => z[1]) = 0;
+        (b[8] => z[1]) = 0;
+        (b[9] => z[1]) = 0;
+        (b[10] => z[1]) = 0;
+        (b[11] => z[1]) = 0;
+        (b[12] => z[1]) = 0;
+        (b[13] => z[1]) = 0;
+        (b[14] => z[1]) = 0;
+        (b[15] => z[1]) = 0;
+        (b[16] => z[1]) = 0;
+        (b[17] => z[1]) = 0;
+        (a[0] => z[2]) = 0;
+        (a[1] => z[2]) = 0;
+        (a[2] => z[2]) = 0;
+        (a[3] => z[2]) = 0;
+        (a[4] => z[2]) = 0;
+        (a[5] => z[2]) = 0;
+        (a[6] => z[2]) = 0;
+        (a[7] => z[2]) = 0;
+        (a[8] => z[2]) = 0;
+        (a[9] => z[2]) = 0;
+        (a[10] => z[2]) = 0;
+        (a[11] => z[2]) = 0;
+        (a[12] => z[2]) = 0;
+        (a[13] => z[2]) = 0;
+        (a[14] => z[2]) = 0;
+        (a[15] => z[2]) = 0;
+        (a[16] => z[2]) = 0;
+        (a[17] => z[2]) = 0;
+        (a[18] => z[2]) = 0;
+        (a[19] => z[2]) = 0;
+        (b[0] => z[2]) = 0;
+        (b[1] => z[2]) = 0;
+        (b[2] => z[2]) = 0;
+        (b[3] => z[2]) = 0;
+        (b[4] => z[2]) = 0;
+        (b[5] => z[2]) = 0;
+        (b[6] => z[2]) = 0;
+        (b[7] => z[2]) = 0;
+        (b[8] => z[2]) = 0;
+        (b[9] => z[2]) = 0;
+        (b[10] => z[2]) = 0;
+        (b[11] => z[2]) = 0;
+        (b[12] => z[2]) = 0;
+        (b[13] => z[2]) = 0;
+        (b[14] => z[2]) = 0;
+        (b[15] => z[2]) = 0;
+        (b[16] => z[2]) = 0;
+        (b[17] => z[2]) = 0;
+        (a[0] => z[3]) = 0;
+        (a[1] => z[3]) = 0;
+        (a[2] => z[3]) = 0;
+        (a[3] => z[3]) = 0;
+        (a[4] => z[3]) = 0;
+        (a[5] => z[3]) = 0;
+        (a[6] => z[3]) = 0;
+        (a[7] => z[3]) = 0;
+        (a[8] => z[3]) = 0;
+        (a[9] => z[3]) = 0;
+        (a[10] => z[3]) = 0;
+        (a[11] => z[3]) = 0;
+        (a[12] => z[3]) = 0;
+        (a[13] => z[3]) = 0;
+        (a[14] => z[3]) = 0;
+        (a[15] => z[3]) = 0;
+        (a[16] => z[3]) = 0;
+        (a[17] => z[3]) = 0;
+        (a[18] => z[3]) = 0;
+        (a[19] => z[3]) = 0;
+        (b[0] => z[3]) = 0;
+        (b[1] => z[3]) = 0;
+        (b[2] => z[3]) = 0;
+        (b[3] => z[3]) = 0;
+        (b[4] => z[3]) = 0;
+        (b[5] => z[3]) = 0;
+        (b[6] => z[3]) = 0;
+        (b[7] => z[3]) = 0;
+        (b[8] => z[3]) = 0;
+        (b[9] => z[3]) = 0;
+        (b[10] => z[3]) = 0;
+        (b[11] => z[3]) = 0;
+        (b[12] => z[3]) = 0;
+        (b[13] => z[3]) = 0;
+        (b[14] => z[3]) = 0;
+        (b[15] => z[3]) = 0;
+        (b[16] => z[3]) = 0;
+        (b[17] => z[3]) = 0;
+        (a[0] => z[4]) = 0;
+        (a[1] => z[4]) = 0;
+        (a[2] => z[4]) = 0;
+        (a[3] => z[4]) = 0;
+        (a[4] => z[4]) = 0;
+        (a[5] => z[4]) = 0;
+        (a[6] => z[4]) = 0;
+        (a[7] => z[4]) = 0;
+        (a[8] => z[4]) = 0;
+        (a[9] => z[4]) = 0;
+        (a[10] => z[4]) = 0;
+        (a[11] => z[4]) = 0;
+        (a[12] => z[4]) = 0;
+        (a[13] => z[4]) = 0;
+        (a[14] => z[4]) = 0;
+        (a[15] => z[4]) = 0;
+        (a[16] => z[4]) = 0;
+        (a[17] => z[4]) = 0;
+        (a[18] => z[4]) = 0;
+        (a[19] => z[4]) = 0;
+        (b[0] => z[4]) = 0;
+        (b[1] => z[4]) = 0;
+        (b[2] => z[4]) = 0;
+        (b[3] => z[4]) = 0;
+        (b[4] => z[4]) = 0;
+        (b[5] => z[4]) = 0;
+        (b[6] => z[4]) = 0;
+        (b[7] => z[4]) = 0;
+        (b[8] => z[4]) = 0;
+        (b[9] => z[4]) = 0;
+        (b[10] => z[4]) = 0;
+        (b[11] => z[4]) = 0;
+        (b[12] => z[4]) = 0;
+        (b[13] => z[4]) = 0;
+        (b[14] => z[4]) = 0;
+        (b[15] => z[4]) = 0;
+        (b[16] => z[4]) = 0;
+        (b[17] => z[4]) = 0;
+        (a[0] => z[5]) = 0;
+        (a[1] => z[5]) = 0;
+        (a[2] => z[5]) = 0;
+        (a[3] => z[5]) = 0;
+        (a[4] => z[5]) = 0;
+        (a[5] => z[5]) = 0;
+        (a[6] => z[5]) = 0;
+        (a[7] => z[5]) = 0;
+        (a[8] => z[5]) = 0;
+        (a[9] => z[5]) = 0;
+        (a[10] => z[5]) = 0;
+        (a[11] => z[5]) = 0;
+        (a[12] => z[5]) = 0;
+        (a[13] => z[5]) = 0;
+        (a[14] => z[5]) = 0;
+        (a[15] => z[5]) = 0;
+        (a[16] => z[5]) = 0;
+        (a[17] => z[5]) = 0;
+        (a[18] => z[5]) = 0;
+        (a[19] => z[5]) = 0;
+        (b[0] => z[5]) = 0;
+        (b[1] => z[5]) = 0;
+        (b[2] => z[5]) = 0;
+        (b[3] => z[5]) = 0;
+        (b[4] => z[5]) = 0;
+        (b[5] => z[5]) = 0;
+        (b[6] => z[5]) = 0;
+        (b[7] => z[5]) = 0;
+        (b[8] => z[5]) = 0;
+        (b[9] => z[5]) = 0;
+        (b[10] => z[5]) = 0;
+        (b[11] => z[5]) = 0;
+        (b[12] => z[5]) = 0;
+        (b[13] => z[5]) = 0;
+        (b[14] => z[5]) = 0;
+        (b[15] => z[5]) = 0;
+        (b[16] => z[5]) = 0;
+        (b[17] => z[5]) = 0;
+        (a[0] => z[6]) = 0;
+        (a[1] => z[6]) = 0;
+        (a[2] => z[6]) = 0;
+        (a[3] => z[6]) = 0;
+        (a[4] => z[6]) = 0;
+        (a[5] => z[6]) = 0;
+        (a[6] => z[6]) = 0;
+        (a[7] => z[6]) = 0;
+        (a[8] => z[6]) = 0;
+        (a[9] => z[6]) = 0;
+        (a[10] => z[6]) = 0;
+        (a[11] => z[6]) = 0;
+        (a[12] => z[6]) = 0;
+        (a[13] => z[6]) = 0;
+        (a[14] => z[6]) = 0;
+        (a[15] => z[6]) = 0;
+        (a[16] => z[6]) = 0;
+        (a[17] => z[6]) = 0;
+        (a[18] => z[6]) = 0;
+        (a[19] => z[6]) = 0;
+        (b[0] => z[6]) = 0;
+        (b[1] => z[6]) = 0;
+        (b[2] => z[6]) = 0;
+        (b[3] => z[6]) = 0;
+        (b[4] => z[6]) = 0;
+        (b[5] => z[6]) = 0;
+        (b[6] => z[6]) = 0;
+        (b[7] => z[6]) = 0;
+        (b[8] => z[6]) = 0;
+        (b[9] => z[6]) = 0;
+        (b[10] => z[6]) = 0;
+        (b[11] => z[6]) = 0;
+        (b[12] => z[6]) = 0;
+        (b[13] => z[6]) = 0;
+        (b[14] => z[6]) = 0;
+        (b[15] => z[6]) = 0;
+        (b[16] => z[6]) = 0;
+        (b[17] => z[6]) = 0;
+        (a[0] => z[7]) = 0;
+        (a[1] => z[7]) = 0;
+        (a[2] => z[7]) = 0;
+        (a[3] => z[7]) = 0;
+        (a[4] => z[7]) = 0;
+        (a[5] => z[7]) = 0;
+        (a[6] => z[7]) = 0;
+        (a[7] => z[7]) = 0;
+        (a[8] => z[7]) = 0;
+        (a[9] => z[7]) = 0;
+        (a[10] => z[7]) = 0;
+        (a[11] => z[7]) = 0;
+        (a[12] => z[7]) = 0;
+        (a[13] => z[7]) = 0;
+        (a[14] => z[7]) = 0;
+        (a[15] => z[7]) = 0;
+        (a[16] => z[7]) = 0;
+        (a[17] => z[7]) = 0;
+        (a[18] => z[7]) = 0;
+        (a[19] => z[7]) = 0;
+        (b[0] => z[7]) = 0;
+        (b[1] => z[7]) = 0;
+        (b[2] => z[7]) = 0;
+        (b[3] => z[7]) = 0;
+        (b[4] => z[7]) = 0;
+        (b[5] => z[7]) = 0;
+        (b[6] => z[7]) = 0;
+        (b[7] => z[7]) = 0;
+        (b[8] => z[7]) = 0;
+        (b[9] => z[7]) = 0;
+        (b[10] => z[7]) = 0;
+        (b[11] => z[7]) = 0;
+        (b[12] => z[7]) = 0;
+        (b[13] => z[7]) = 0;
+        (b[14] => z[7]) = 0;
+        (b[15] => z[7]) = 0;
+        (b[16] => z[7]) = 0;
+        (b[17] => z[7]) = 0;
+        (a[0] => z[8]) = 0;
+        (a[1] => z[8]) = 0;
+        (a[2] => z[8]) = 0;
+        (a[3] => z[8]) = 0;
+        (a[4] => z[8]) = 0;
+        (a[5] => z[8]) = 0;
+        (a[6] => z[8]) = 0;
+        (a[7] => z[8]) = 0;
+        (a[8] => z[8]) = 0;
+        (a[9] => z[8]) = 0;
+        (a[10] => z[8]) = 0;
+        (a[11] => z[8]) = 0;
+        (a[12] => z[8]) = 0;
+        (a[13] => z[8]) = 0;
+        (a[14] => z[8]) = 0;
+        (a[15] => z[8]) = 0;
+        (a[16] => z[8]) = 0;
+        (a[17] => z[8]) = 0;
+        (a[18] => z[8]) = 0;
+        (a[19] => z[8]) = 0;
+        (b[0] => z[8]) = 0;
+        (b[1] => z[8]) = 0;
+        (b[2] => z[8]) = 0;
+        (b[3] => z[8]) = 0;
+        (b[4] => z[8]) = 0;
+        (b[5] => z[8]) = 0;
+        (b[6] => z[8]) = 0;
+        (b[7] => z[8]) = 0;
+        (b[8] => z[8]) = 0;
+        (b[9] => z[8]) = 0;
+        (b[10] => z[8]) = 0;
+        (b[11] => z[8]) = 0;
+        (b[12] => z[8]) = 0;
+        (b[13] => z[8]) = 0;
+        (b[14] => z[8]) = 0;
+        (b[15] => z[8]) = 0;
+        (b[16] => z[8]) = 0;
+        (b[17] => z[8]) = 0;
+        (a[0] => z[9]) = 0;
+        (a[1] => z[9]) = 0;
+        (a[2] => z[9]) = 0;
+        (a[3] => z[9]) = 0;
+        (a[4] => z[9]) = 0;
+        (a[5] => z[9]) = 0;
+        (a[6] => z[9]) = 0;
+        (a[7] => z[9]) = 0;
+        (a[8] => z[9]) = 0;
+        (a[9] => z[9]) = 0;
+        (a[10] => z[9]) = 0;
+        (a[11] => z[9]) = 0;
+        (a[12] => z[9]) = 0;
+        (a[13] => z[9]) = 0;
+        (a[14] => z[9]) = 0;
+        (a[15] => z[9]) = 0;
+        (a[16] => z[9]) = 0;
+        (a[17] => z[9]) = 0;
+        (a[18] => z[9]) = 0;
+        (a[19] => z[9]) = 0;
+        (b[0] => z[9]) = 0;
+        (b[1] => z[9]) = 0;
+        (b[2] => z[9]) = 0;
+        (b[3] => z[9]) = 0;
+        (b[4] => z[9]) = 0;
+        (b[5] => z[9]) = 0;
+        (b[6] => z[9]) = 0;
+        (b[7] => z[9]) = 0;
+        (b[8] => z[9]) = 0;
+        (b[9] => z[9]) = 0;
+        (b[10] => z[9]) = 0;
+        (b[11] => z[9]) = 0;
+        (b[12] => z[9]) = 0;
+        (b[13] => z[9]) = 0;
+        (b[14] => z[9]) = 0;
+        (b[15] => z[9]) = 0;
+        (b[16] => z[9]) = 0;
+        (b[17] => z[9]) = 0;
+        (a[0] => z[10]) = 0;
+        (a[1] => z[10]) = 0;
+        (a[2] => z[10]) = 0;
+        (a[3] => z[10]) = 0;
+        (a[4] => z[10]) = 0;
+        (a[5] => z[10]) = 0;
+        (a[6] => z[10]) = 0;
+        (a[7] => z[10]) = 0;
+        (a[8] => z[10]) = 0;
+        (a[9] => z[10]) = 0;
+        (a[10] => z[10]) = 0;
+        (a[11] => z[10]) = 0;
+        (a[12] => z[10]) = 0;
+        (a[13] => z[10]) = 0;
+        (a[14] => z[10]) = 0;
+        (a[15] => z[10]) = 0;
+        (a[16] => z[10]) = 0;
+        (a[17] => z[10]) = 0;
+        (a[18] => z[10]) = 0;
+        (a[19] => z[10]) = 0;
+        (b[0] => z[10]) = 0;
+        (b[1] => z[10]) = 0;
+        (b[2] => z[10]) = 0;
+        (b[3] => z[10]) = 0;
+        (b[4] => z[10]) = 0;
+        (b[5] => z[10]) = 0;
+        (b[6] => z[10]) = 0;
+        (b[7] => z[10]) = 0;
+        (b[8] => z[10]) = 0;
+        (b[9] => z[10]) = 0;
+        (b[10] => z[10]) = 0;
+        (b[11] => z[10]) = 0;
+        (b[12] => z[10]) = 0;
+        (b[13] => z[10]) = 0;
+        (b[14] => z[10]) = 0;
+        (b[15] => z[10]) = 0;
+        (b[16] => z[10]) = 0;
+        (b[17] => z[10]) = 0;
+        (a[0] => z[11]) = 0;
+        (a[1] => z[11]) = 0;
+        (a[2] => z[11]) = 0;
+        (a[3] => z[11]) = 0;
+        (a[4] => z[11]) = 0;
+        (a[5] => z[11]) = 0;
+        (a[6] => z[11]) = 0;
+        (a[7] => z[11]) = 0;
+        (a[8] => z[11]) = 0;
+        (a[9] => z[11]) = 0;
+        (a[10] => z[11]) = 0;
+        (a[11] => z[11]) = 0;
+        (a[12] => z[11]) = 0;
+        (a[13] => z[11]) = 0;
+        (a[14] => z[11]) = 0;
+        (a[15] => z[11]) = 0;
+        (a[16] => z[11]) = 0;
+        (a[17] => z[11]) = 0;
+        (a[18] => z[11]) = 0;
+        (a[19] => z[11]) = 0;
+        (b[0] => z[11]) = 0;
+        (b[1] => z[11]) = 0;
+        (b[2] => z[11]) = 0;
+        (b[3] => z[11]) = 0;
+        (b[4] => z[11]) = 0;
+        (b[5] => z[11]) = 0;
+        (b[6] => z[11]) = 0;
+        (b[7] => z[11]) = 0;
+        (b[8] => z[11]) = 0;
+        (b[9] => z[11]) = 0;
+        (b[10] => z[11]) = 0;
+        (b[11] => z[11]) = 0;
+        (b[12] => z[11]) = 0;
+        (b[13] => z[11]) = 0;
+        (b[14] => z[11]) = 0;
+        (b[15] => z[11]) = 0;
+        (b[16] => z[11]) = 0;
+        (b[17] => z[11]) = 0;
+        (a[0] => z[12]) = 0;
+        (a[1] => z[12]) = 0;
+        (a[2] => z[12]) = 0;
+        (a[3] => z[12]) = 0;
+        (a[4] => z[12]) = 0;
+        (a[5] => z[12]) = 0;
+        (a[6] => z[12]) = 0;
+        (a[7] => z[12]) = 0;
+        (a[8] => z[12]) = 0;
+        (a[9] => z[12]) = 0;
+        (a[10] => z[12]) = 0;
+        (a[11] => z[12]) = 0;
+        (a[12] => z[12]) = 0;
+        (a[13] => z[12]) = 0;
+        (a[14] => z[12]) = 0;
+        (a[15] => z[12]) = 0;
+        (a[16] => z[12]) = 0;
+        (a[17] => z[12]) = 0;
+        (a[18] => z[12]) = 0;
+        (a[19] => z[12]) = 0;
+        (b[0] => z[12]) = 0;
+        (b[1] => z[12]) = 0;
+        (b[2] => z[12]) = 0;
+        (b[3] => z[12]) = 0;
+        (b[4] => z[12]) = 0;
+        (b[5] => z[12]) = 0;
+        (b[6] => z[12]) = 0;
+        (b[7] => z[12]) = 0;
+        (b[8] => z[12]) = 0;
+        (b[9] => z[12]) = 0;
+        (b[10] => z[12]) = 0;
+        (b[11] => z[12]) = 0;
+        (b[12] => z[12]) = 0;
+        (b[13] => z[12]) = 0;
+        (b[14] => z[12]) = 0;
+        (b[15] => z[12]) = 0;
+        (b[16] => z[12]) = 0;
+        (b[17] => z[12]) = 0;
+        (a[0] => z[13]) = 0;
+        (a[1] => z[13]) = 0;
+        (a[2] => z[13]) = 0;
+        (a[3] => z[13]) = 0;
+        (a[4] => z[13]) = 0;
+        (a[5] => z[13]) = 0;
+        (a[6] => z[13]) = 0;
+        (a[7] => z[13]) = 0;
+        (a[8] => z[13]) = 0;
+        (a[9] => z[13]) = 0;
+        (a[10] => z[13]) = 0;
+        (a[11] => z[13]) = 0;
+        (a[12] => z[13]) = 0;
+        (a[13] => z[13]) = 0;
+        (a[14] => z[13]) = 0;
+        (a[15] => z[13]) = 0;
+        (a[16] => z[13]) = 0;
+        (a[17] => z[13]) = 0;
+        (a[18] => z[13]) = 0;
+        (a[19] => z[13]) = 0;
+        (b[0] => z[13]) = 0;
+        (b[1] => z[13]) = 0;
+        (b[2] => z[13]) = 0;
+        (b[3] => z[13]) = 0;
+        (b[4] => z[13]) = 0;
+        (b[5] => z[13]) = 0;
+        (b[6] => z[13]) = 0;
+        (b[7] => z[13]) = 0;
+        (b[8] => z[13]) = 0;
+        (b[9] => z[13]) = 0;
+        (b[10] => z[13]) = 0;
+        (b[11] => z[13]) = 0;
+        (b[12] => z[13]) = 0;
+        (b[13] => z[13]) = 0;
+        (b[14] => z[13]) = 0;
+        (b[15] => z[13]) = 0;
+        (b[16] => z[13]) = 0;
+        (b[17] => z[13]) = 0;
+        (a[0] => z[14]) = 0;
+        (a[1] => z[14]) = 0;
+        (a[2] => z[14]) = 0;
+        (a[3] => z[14]) = 0;
+        (a[4] => z[14]) = 0;
+        (a[5] => z[14]) = 0;
+        (a[6] => z[14]) = 0;
+        (a[7] => z[14]) = 0;
+        (a[8] => z[14]) = 0;
+        (a[9] => z[14]) = 0;
+        (a[10] => z[14]) = 0;
+        (a[11] => z[14]) = 0;
+        (a[12] => z[14]) = 0;
+        (a[13] => z[14]) = 0;
+        (a[14] => z[14]) = 0;
+        (a[15] => z[14]) = 0;
+        (a[16] => z[14]) = 0;
+        (a[17] => z[14]) = 0;
+        (a[18] => z[14]) = 0;
+        (a[19] => z[14]) = 0;
+        (b[0] => z[14]) = 0;
+        (b[1] => z[14]) = 0;
+        (b[2] => z[14]) = 0;
+        (b[3] => z[14]) = 0;
+        (b[4] => z[14]) = 0;
+        (b[5] => z[14]) = 0;
+        (b[6] => z[14]) = 0;
+        (b[7] => z[14]) = 0;
+        (b[8] => z[14]) = 0;
+        (b[9] => z[14]) = 0;
+        (b[10] => z[14]) = 0;
+        (b[11] => z[14]) = 0;
+        (b[12] => z[14]) = 0;
+        (b[13] => z[14]) = 0;
+        (b[14] => z[14]) = 0;
+        (b[15] => z[14]) = 0;
+        (b[16] => z[14]) = 0;
+        (b[17] => z[14]) = 0;
+        (a[0] => z[15]) = 0;
+        (a[1] => z[15]) = 0;
+        (a[2] => z[15]) = 0;
+        (a[3] => z[15]) = 0;
+        (a[4] => z[15]) = 0;
+        (a[5] => z[15]) = 0;
+        (a[6] => z[15]) = 0;
+        (a[7] => z[15]) = 0;
+        (a[8] => z[15]) = 0;
+        (a[9] => z[15]) = 0;
+        (a[10] => z[15]) = 0;
+        (a[11] => z[15]) = 0;
+        (a[12] => z[15]) = 0;
+        (a[13] => z[15]) = 0;
+        (a[14] => z[15]) = 0;
+        (a[15] => z[15]) = 0;
+        (a[16] => z[15]) = 0;
+        (a[17] => z[15]) = 0;
+        (a[18] => z[15]) = 0;
+        (a[19] => z[15]) = 0;
+        (b[0] => z[15]) = 0;
+        (b[1] => z[15]) = 0;
+        (b[2] => z[15]) = 0;
+        (b[3] => z[15]) = 0;
+        (b[4] => z[15]) = 0;
+        (b[5] => z[15]) = 0;
+        (b[6] => z[15]) = 0;
+        (b[7] => z[15]) = 0;
+        (b[8] => z[15]) = 0;
+        (b[9] => z[15]) = 0;
+        (b[10] => z[15]) = 0;
+        (b[11] => z[15]) = 0;
+        (b[12] => z[15]) = 0;
+        (b[13] => z[15]) = 0;
+        (b[14] => z[15]) = 0;
+        (b[15] => z[15]) = 0;
+        (b[16] => z[15]) = 0;
+        (b[17] => z[15]) = 0;
+        (a[0] => z[16]) = 0;
+        (a[1] => z[16]) = 0;
+        (a[2] => z[16]) = 0;
+        (a[3] => z[16]) = 0;
+        (a[4] => z[16]) = 0;
+        (a[5] => z[16]) = 0;
+        (a[6] => z[16]) = 0;
+        (a[7] => z[16]) = 0;
+        (a[8] => z[16]) = 0;
+        (a[9] => z[16]) = 0;
+        (a[10] => z[16]) = 0;
+        (a[11] => z[16]) = 0;
+        (a[12] => z[16]) = 0;
+        (a[13] => z[16]) = 0;
+        (a[14] => z[16]) = 0;
+        (a[15] => z[16]) = 0;
+        (a[16] => z[16]) = 0;
+        (a[17] => z[16]) = 0;
+        (a[18] => z[16]) = 0;
+        (a[19] => z[16]) = 0;
+        (b[0] => z[16]) = 0;
+        (b[1] => z[16]) = 0;
+        (b[2] => z[16]) = 0;
+        (b[3] => z[16]) = 0;
+        (b[4] => z[16]) = 0;
+        (b[5] => z[16]) = 0;
+        (b[6] => z[16]) = 0;
+        (b[7] => z[16]) = 0;
+        (b[8] => z[16]) = 0;
+        (b[9] => z[16]) = 0;
+        (b[10] => z[16]) = 0;
+        (b[11] => z[16]) = 0;
+        (b[12] => z[16]) = 0;
+        (b[13] => z[16]) = 0;
+        (b[14] => z[16]) = 0;
+        (b[15] => z[16]) = 0;
+        (b[16] => z[16]) = 0;
+        (b[17] => z[16]) = 0;
+        (a[0] => z[17]) = 0;
+        (a[1] => z[17]) = 0;
+        (a[2] => z[17]) = 0;
+        (a[3] => z[17]) = 0;
+        (a[4] => z[17]) = 0;
+        (a[5] => z[17]) = 0;
+        (a[6] => z[17]) = 0;
+        (a[7] => z[17]) = 0;
+        (a[8] => z[17]) = 0;
+        (a[9] => z[17]) = 0;
+        (a[10] => z[17]) = 0;
+        (a[11] => z[17]) = 0;
+        (a[12] => z[17]) = 0;
+        (a[13] => z[17]) = 0;
+        (a[14] => z[17]) = 0;
+        (a[15] => z[17]) = 0;
+        (a[16] => z[17]) = 0;
+        (a[17] => z[17]) = 0;
+        (a[18] => z[17]) = 0;
+        (a[19] => z[17]) = 0;
+        (b[0] => z[17]) = 0;
+        (b[1] => z[17]) = 0;
+        (b[2] => z[17]) = 0;
+        (b[3] => z[17]) = 0;
+        (b[4] => z[17]) = 0;
+        (b[5] => z[17]) = 0;
+        (b[6] => z[17]) = 0;
+        (b[7] => z[17]) = 0;
+        (b[8] => z[17]) = 0;
+        (b[9] => z[17]) = 0;
+        (b[10] => z[17]) = 0;
+        (b[11] => z[17]) = 0;
+        (b[12] => z[17]) = 0;
+        (b[13] => z[17]) = 0;
+        (b[14] => z[17]) = 0;
+        (b[15] => z[17]) = 0;
+        (b[16] => z[17]) = 0;
+        (b[17] => z[17]) = 0;
+        (a[0] => z[18]) = 0;
+        (a[1] => z[18]) = 0;
+        (a[2] => z[18]) = 0;
+        (a[3] => z[18]) = 0;
+        (a[4] => z[18]) = 0;
+        (a[5] => z[18]) = 0;
+        (a[6] => z[18]) = 0;
+        (a[7] => z[18]) = 0;
+        (a[8] => z[18]) = 0;
+        (a[9] => z[18]) = 0;
+        (a[10] => z[18]) = 0;
+        (a[11] => z[18]) = 0;
+        (a[12] => z[18]) = 0;
+        (a[13] => z[18]) = 0;
+        (a[14] => z[18]) = 0;
+        (a[15] => z[18]) = 0;
+        (a[16] => z[18]) = 0;
+        (a[17] => z[18]) = 0;
+        (a[18] => z[18]) = 0;
+        (a[19] => z[18]) = 0;
+        (b[0] => z[18]) = 0;
+        (b[1] => z[18]) = 0;
+        (b[2] => z[18]) = 0;
+        (b[3] => z[18]) = 0;
+        (b[4] => z[18]) = 0;
+        (b[5] => z[18]) = 0;
+        (b[6] => z[18]) = 0;
+        (b[7] => z[18]) = 0;
+        (b[8] => z[18]) = 0;
+        (b[9] => z[18]) = 0;
+        (b[10] => z[18]) = 0;
+        (b[11] => z[18]) = 0;
+        (b[12] => z[18]) = 0;
+        (b[13] => z[18]) = 0;
+        (b[14] => z[18]) = 0;
+        (b[15] => z[18]) = 0;
+        (b[16] => z[18]) = 0;
+        (b[17] => z[18]) = 0;
+        (a[0] => z[19]) = 0;
+        (a[1] => z[19]) = 0;
+        (a[2] => z[19]) = 0;
+        (a[3] => z[19]) = 0;
+        (a[4] => z[19]) = 0;
+        (a[5] => z[19]) = 0;
+        (a[6] => z[19]) = 0;
+        (a[7] => z[19]) = 0;
+        (a[8] => z[19]) = 0;
+        (a[9] => z[19]) = 0;
+        (a[10] => z[19]) = 0;
+        (a[11] => z[19]) = 0;
+        (a[12] => z[19]) = 0;
+        (a[13] => z[19]) = 0;
+        (a[14] => z[19]) = 0;
+        (a[15] => z[19]) = 0;
+        (a[16] => z[19]) = 0;
+        (a[17] => z[19]) = 0;
+        (a[18] => z[19]) = 0;
+        (a[19] => z[19]) = 0;
+        (b[0] => z[19]) = 0;
+        (b[1] => z[19]) = 0;
+        (b[2] => z[19]) = 0;
+        (b[3] => z[19]) = 0;
+        (b[4] => z[19]) = 0;
+        (b[5] => z[19]) = 0;
+        (b[6] => z[19]) = 0;
+        (b[7] => z[19]) = 0;
+        (b[8] => z[19]) = 0;
+        (b[9] => z[19]) = 0;
+        (b[10] => z[19]) = 0;
+        (b[11] => z[19]) = 0;
+        (b[12] => z[19]) = 0;
+        (b[13] => z[19]) = 0;
+        (b[14] => z[19]) = 0;
+        (b[15] => z[19]) = 0;
+        (b[16] => z[19]) = 0;
+        (b[17] => z[19]) = 0;
+        (a[0] => z[20]) = 0;
+        (a[1] => z[20]) = 0;
+        (a[2] => z[20]) = 0;
+        (a[3] => z[20]) = 0;
+        (a[4] => z[20]) = 0;
+        (a[5] => z[20]) = 0;
+        (a[6] => z[20]) = 0;
+        (a[7] => z[20]) = 0;
+        (a[8] => z[20]) = 0;
+        (a[9] => z[20]) = 0;
+        (a[10] => z[20]) = 0;
+        (a[11] => z[20]) = 0;
+        (a[12] => z[20]) = 0;
+        (a[13] => z[20]) = 0;
+        (a[14] => z[20]) = 0;
+        (a[15] => z[20]) = 0;
+        (a[16] => z[20]) = 0;
+        (a[17] => z[20]) = 0;
+        (a[18] => z[20]) = 0;
+        (a[19] => z[20]) = 0;
+        (b[0] => z[20]) = 0;
+        (b[1] => z[20]) = 0;
+        (b[2] => z[20]) = 0;
+        (b[3] => z[20]) = 0;
+        (b[4] => z[20]) = 0;
+        (b[5] => z[20]) = 0;
+        (b[6] => z[20]) = 0;
+        (b[7] => z[20]) = 0;
+        (b[8] => z[20]) = 0;
+        (b[9] => z[20]) = 0;
+        (b[10] => z[20]) = 0;
+        (b[11] => z[20]) = 0;
+        (b[12] => z[20]) = 0;
+        (b[13] => z[20]) = 0;
+        (b[14] => z[20]) = 0;
+        (b[15] => z[20]) = 0;
+        (b[16] => z[20]) = 0;
+        (b[17] => z[20]) = 0;
+        (a[0] => z[21]) = 0;
+        (a[1] => z[21]) = 0;
+        (a[2] => z[21]) = 0;
+        (a[3] => z[21]) = 0;
+        (a[4] => z[21]) = 0;
+        (a[5] => z[21]) = 0;
+        (a[6] => z[21]) = 0;
+        (a[7] => z[21]) = 0;
+        (a[8] => z[21]) = 0;
+        (a[9] => z[21]) = 0;
+        (a[10] => z[21]) = 0;
+        (a[11] => z[21]) = 0;
+        (a[12] => z[21]) = 0;
+        (a[13] => z[21]) = 0;
+        (a[14] => z[21]) = 0;
+        (a[15] => z[21]) = 0;
+        (a[16] => z[21]) = 0;
+        (a[17] => z[21]) = 0;
+        (a[18] => z[21]) = 0;
+        (a[19] => z[21]) = 0;
+        (b[0] => z[21]) = 0;
+        (b[1] => z[21]) = 0;
+        (b[2] => z[21]) = 0;
+        (b[3] => z[21]) = 0;
+        (b[4] => z[21]) = 0;
+        (b[5] => z[21]) = 0;
+        (b[6] => z[21]) = 0;
+        (b[7] => z[21]) = 0;
+        (b[8] => z[21]) = 0;
+        (b[9] => z[21]) = 0;
+        (b[10] => z[21]) = 0;
+        (b[11] => z[21]) = 0;
+        (b[12] => z[21]) = 0;
+        (b[13] => z[21]) = 0;
+        (b[14] => z[21]) = 0;
+        (b[15] => z[21]) = 0;
+        (b[16] => z[21]) = 0;
+        (b[17] => z[21]) = 0;
+        (a[0] => z[22]) = 0;
+        (a[1] => z[22]) = 0;
+        (a[2] => z[22]) = 0;
+        (a[3] => z[22]) = 0;
+        (a[4] => z[22]) = 0;
+        (a[5] => z[22]) = 0;
+        (a[6] => z[22]) = 0;
+        (a[7] => z[22]) = 0;
+        (a[8] => z[22]) = 0;
+        (a[9] => z[22]) = 0;
+        (a[10] => z[22]) = 0;
+        (a[11] => z[22]) = 0;
+        (a[12] => z[22]) = 0;
+        (a[13] => z[22]) = 0;
+        (a[14] => z[22]) = 0;
+        (a[15] => z[22]) = 0;
+        (a[16] => z[22]) = 0;
+        (a[17] => z[22]) = 0;
+        (a[18] => z[22]) = 0;
+        (a[19] => z[22]) = 0;
+        (b[0] => z[22]) = 0;
+        (b[1] => z[22]) = 0;
+        (b[2] => z[22]) = 0;
+        (b[3] => z[22]) = 0;
+        (b[4] => z[22]) = 0;
+        (b[5] => z[22]) = 0;
+        (b[6] => z[22]) = 0;
+        (b[7] => z[22]) = 0;
+        (b[8] => z[22]) = 0;
+        (b[9] => z[22]) = 0;
+        (b[10] => z[22]) = 0;
+        (b[11] => z[22]) = 0;
+        (b[12] => z[22]) = 0;
+        (b[13] => z[22]) = 0;
+        (b[14] => z[22]) = 0;
+        (b[15] => z[22]) = 0;
+        (b[16] => z[22]) = 0;
+        (b[17] => z[22]) = 0;
+        (a[0] => z[23]) = 0;
+        (a[1] => z[23]) = 0;
+        (a[2] => z[23]) = 0;
+        (a[3] => z[23]) = 0;
+        (a[4] => z[23]) = 0;
+        (a[5] => z[23]) = 0;
+        (a[6] => z[23]) = 0;
+        (a[7] => z[23]) = 0;
+        (a[8] => z[23]) = 0;
+        (a[9] => z[23]) = 0;
+        (a[10] => z[23]) = 0;
+        (a[11] => z[23]) = 0;
+        (a[12] => z[23]) = 0;
+        (a[13] => z[23]) = 0;
+        (a[14] => z[23]) = 0;
+        (a[15] => z[23]) = 0;
+        (a[16] => z[23]) = 0;
+        (a[17] => z[23]) = 0;
+        (a[18] => z[23]) = 0;
+        (a[19] => z[23]) = 0;
+        (b[0] => z[23]) = 0;
+        (b[1] => z[23]) = 0;
+        (b[2] => z[23]) = 0;
+        (b[3] => z[23]) = 0;
+        (b[4] => z[23]) = 0;
+        (b[5] => z[23]) = 0;
+        (b[6] => z[23]) = 0;
+        (b[7] => z[23]) = 0;
+        (b[8] => z[23]) = 0;
+        (b[9] => z[23]) = 0;
+        (b[10] => z[23]) = 0;
+        (b[11] => z[23]) = 0;
+        (b[12] => z[23]) = 0;
+        (b[13] => z[23]) = 0;
+        (b[14] => z[23]) = 0;
+        (b[15] => z[23]) = 0;
+        (b[16] => z[23]) = 0;
+        (b[17] => z[23]) = 0;
+        (a[0] => z[24]) = 0;
+        (a[1] => z[24]) = 0;
+        (a[2] => z[24]) = 0;
+        (a[3] => z[24]) = 0;
+        (a[4] => z[24]) = 0;
+        (a[5] => z[24]) = 0;
+        (a[6] => z[24]) = 0;
+        (a[7] => z[24]) = 0;
+        (a[8] => z[24]) = 0;
+        (a[9] => z[24]) = 0;
+        (a[10] => z[24]) = 0;
+        (a[11] => z[24]) = 0;
+        (a[12] => z[24]) = 0;
+        (a[13] => z[24]) = 0;
+        (a[14] => z[24]) = 0;
+        (a[15] => z[24]) = 0;
+        (a[16] => z[24]) = 0;
+        (a[17] => z[24]) = 0;
+        (a[18] => z[24]) = 0;
+        (a[19] => z[24]) = 0;
+        (b[0] => z[24]) = 0;
+        (b[1] => z[24]) = 0;
+        (b[2] => z[24]) = 0;
+        (b[3] => z[24]) = 0;
+        (b[4] => z[24]) = 0;
+        (b[5] => z[24]) = 0;
+        (b[6] => z[24]) = 0;
+        (b[7] => z[24]) = 0;
+        (b[8] => z[24]) = 0;
+        (b[9] => z[24]) = 0;
+        (b[10] => z[24]) = 0;
+        (b[11] => z[24]) = 0;
+        (b[12] => z[24]) = 0;
+        (b[13] => z[24]) = 0;
+        (b[14] => z[24]) = 0;
+        (b[15] => z[24]) = 0;
+        (b[16] => z[24]) = 0;
+        (b[17] => z[24]) = 0;
+        (a[0] => z[25]) = 0;
+        (a[1] => z[25]) = 0;
+        (a[2] => z[25]) = 0;
+        (a[3] => z[25]) = 0;
+        (a[4] => z[25]) = 0;
+        (a[5] => z[25]) = 0;
+        (a[6] => z[25]) = 0;
+        (a[7] => z[25]) = 0;
+        (a[8] => z[25]) = 0;
+        (a[9] => z[25]) = 0;
+        (a[10] => z[25]) = 0;
+        (a[11] => z[25]) = 0;
+        (a[12] => z[25]) = 0;
+        (a[13] => z[25]) = 0;
+        (a[14] => z[25]) = 0;
+        (a[15] => z[25]) = 0;
+        (a[16] => z[25]) = 0;
+        (a[17] => z[25]) = 0;
+        (a[18] => z[25]) = 0;
+        (a[19] => z[25]) = 0;
+        (b[0] => z[25]) = 0;
+        (b[1] => z[25]) = 0;
+        (b[2] => z[25]) = 0;
+        (b[3] => z[25]) = 0;
+        (b[4] => z[25]) = 0;
+        (b[5] => z[25]) = 0;
+        (b[6] => z[25]) = 0;
+        (b[7] => z[25]) = 0;
+        (b[8] => z[25]) = 0;
+        (b[9] => z[25]) = 0;
+        (b[10] => z[25]) = 0;
+        (b[11] => z[25]) = 0;
+        (b[12] => z[25]) = 0;
+        (b[13] => z[25]) = 0;
+        (b[14] => z[25]) = 0;
+        (b[15] => z[25]) = 0;
+        (b[16] => z[25]) = 0;
+        (b[17] => z[25]) = 0;
+        (a[0] => z[26]) = 0;
+        (a[1] => z[26]) = 0;
+        (a[2] => z[26]) = 0;
+        (a[3] => z[26]) = 0;
+        (a[4] => z[26]) = 0;
+        (a[5] => z[26]) = 0;
+        (a[6] => z[26]) = 0;
+        (a[7] => z[26]) = 0;
+        (a[8] => z[26]) = 0;
+        (a[9] => z[26]) = 0;
+        (a[10] => z[26]) = 0;
+        (a[11] => z[26]) = 0;
+        (a[12] => z[26]) = 0;
+        (a[13] => z[26]) = 0;
+        (a[14] => z[26]) = 0;
+        (a[15] => z[26]) = 0;
+        (a[16] => z[26]) = 0;
+        (a[17] => z[26]) = 0;
+        (a[18] => z[26]) = 0;
+        (a[19] => z[26]) = 0;
+        (b[0] => z[26]) = 0;
+        (b[1] => z[26]) = 0;
+        (b[2] => z[26]) = 0;
+        (b[3] => z[26]) = 0;
+        (b[4] => z[26]) = 0;
+        (b[5] => z[26]) = 0;
+        (b[6] => z[26]) = 0;
+        (b[7] => z[26]) = 0;
+        (b[8] => z[26]) = 0;
+        (b[9] => z[26]) = 0;
+        (b[10] => z[26]) = 0;
+        (b[11] => z[26]) = 0;
+        (b[12] => z[26]) = 0;
+        (b[13] => z[26]) = 0;
+        (b[14] => z[26]) = 0;
+        (b[15] => z[26]) = 0;
+        (b[16] => z[26]) = 0;
+        (b[17] => z[26]) = 0;
+        (a[0] => z[27]) = 0;
+        (a[1] => z[27]) = 0;
+        (a[2] => z[27]) = 0;
+        (a[3] => z[27]) = 0;
+        (a[4] => z[27]) = 0;
+        (a[5] => z[27]) = 0;
+        (a[6] => z[27]) = 0;
+        (a[7] => z[27]) = 0;
+        (a[8] => z[27]) = 0;
+        (a[9] => z[27]) = 0;
+        (a[10] => z[27]) = 0;
+        (a[11] => z[27]) = 0;
+        (a[12] => z[27]) = 0;
+        (a[13] => z[27]) = 0;
+        (a[14] => z[27]) = 0;
+        (a[15] => z[27]) = 0;
+        (a[16] => z[27]) = 0;
+        (a[17] => z[27]) = 0;
+        (a[18] => z[27]) = 0;
+        (a[19] => z[27]) = 0;
+        (b[0] => z[27]) = 0;
+        (b[1] => z[27]) = 0;
+        (b[2] => z[27]) = 0;
+        (b[3] => z[27]) = 0;
+        (b[4] => z[27]) = 0;
+        (b[5] => z[27]) = 0;
+        (b[6] => z[27]) = 0;
+        (b[7] => z[27]) = 0;
+        (b[8] => z[27]) = 0;
+        (b[9] => z[27]) = 0;
+        (b[10] => z[27]) = 0;
+        (b[11] => z[27]) = 0;
+        (b[12] => z[27]) = 0;
+        (b[13] => z[27]) = 0;
+        (b[14] => z[27]) = 0;
+        (b[15] => z[27]) = 0;
+        (b[16] => z[27]) = 0;
+        (b[17] => z[27]) = 0;
+        (a[0] => z[28]) = 0;
+        (a[1] => z[28]) = 0;
+        (a[2] => z[28]) = 0;
+        (a[3] => z[28]) = 0;
+        (a[4] => z[28]) = 0;
+        (a[5] => z[28]) = 0;
+        (a[6] => z[28]) = 0;
+        (a[7] => z[28]) = 0;
+        (a[8] => z[28]) = 0;
+        (a[9] => z[28]) = 0;
+        (a[10] => z[28]) = 0;
+        (a[11] => z[28]) = 0;
+        (a[12] => z[28]) = 0;
+        (a[13] => z[28]) = 0;
+        (a[14] => z[28]) = 0;
+        (a[15] => z[28]) = 0;
+        (a[16] => z[28]) = 0;
+        (a[17] => z[28]) = 0;
+        (a[18] => z[28]) = 0;
+        (a[19] => z[28]) = 0;
+        (b[0] => z[28]) = 0;
+        (b[1] => z[28]) = 0;
+        (b[2] => z[28]) = 0;
+        (b[3] => z[28]) = 0;
+        (b[4] => z[28]) = 0;
+        (b[5] => z[28]) = 0;
+        (b[6] => z[28]) = 0;
+        (b[7] => z[28]) = 0;
+        (b[8] => z[28]) = 0;
+        (b[9] => z[28]) = 0;
+        (b[10] => z[28]) = 0;
+        (b[11] => z[28]) = 0;
+        (b[12] => z[28]) = 0;
+        (b[13] => z[28]) = 0;
+        (b[14] => z[28]) = 0;
+        (b[15] => z[28]) = 0;
+        (b[16] => z[28]) = 0;
+        (b[17] => z[28]) = 0;
+        (a[0] => z[29]) = 0;
+        (a[1] => z[29]) = 0;
+        (a[2] => z[29]) = 0;
+        (a[3] => z[29]) = 0;
+        (a[4] => z[29]) = 0;
+        (a[5] => z[29]) = 0;
+        (a[6] => z[29]) = 0;
+        (a[7] => z[29]) = 0;
+        (a[8] => z[29]) = 0;
+        (a[9] => z[29]) = 0;
+        (a[10] => z[29]) = 0;
+        (a[11] => z[29]) = 0;
+        (a[12] => z[29]) = 0;
+        (a[13] => z[29]) = 0;
+        (a[14] => z[29]) = 0;
+        (a[15] => z[29]) = 0;
+        (a[16] => z[29]) = 0;
+        (a[17] => z[29]) = 0;
+        (a[18] => z[29]) = 0;
+        (a[19] => z[29]) = 0;
+        (b[0] => z[29]) = 0;
+        (b[1] => z[29]) = 0;
+        (b[2] => z[29]) = 0;
+        (b[3] => z[29]) = 0;
+        (b[4] => z[29]) = 0;
+        (b[5] => z[29]) = 0;
+        (b[6] => z[29]) = 0;
+        (b[7] => z[29]) = 0;
+        (b[8] => z[29]) = 0;
+        (b[9] => z[29]) = 0;
+        (b[10] => z[29]) = 0;
+        (b[11] => z[29]) = 0;
+        (b[12] => z[29]) = 0;
+        (b[13] => z[29]) = 0;
+        (b[14] => z[29]) = 0;
+        (b[15] => z[29]) = 0;
+        (b[16] => z[29]) = 0;
+        (b[17] => z[29]) = 0;
+        (a[0] => z[30]) = 0;
+        (a[1] => z[30]) = 0;
+        (a[2] => z[30]) = 0;
+        (a[3] => z[30]) = 0;
+        (a[4] => z[30]) = 0;
+        (a[5] => z[30]) = 0;
+        (a[6] => z[30]) = 0;
+        (a[7] => z[30]) = 0;
+        (a[8] => z[30]) = 0;
+        (a[9] => z[30]) = 0;
+        (a[10] => z[30]) = 0;
+        (a[11] => z[30]) = 0;
+        (a[12] => z[30]) = 0;
+        (a[13] => z[30]) = 0;
+        (a[14] => z[30]) = 0;
+        (a[15] => z[30]) = 0;
+        (a[16] => z[30]) = 0;
+        (a[17] => z[30]) = 0;
+        (a[18] => z[30]) = 0;
+        (a[19] => z[30]) = 0;
+        (b[0] => z[30]) = 0;
+        (b[1] => z[30]) = 0;
+        (b[2] => z[30]) = 0;
+        (b[3] => z[30]) = 0;
+        (b[4] => z[30]) = 0;
+        (b[5] => z[30]) = 0;
+        (b[6] => z[30]) = 0;
+        (b[7] => z[30]) = 0;
+        (b[8] => z[30]) = 0;
+        (b[9] => z[30]) = 0;
+        (b[10] => z[30]) = 0;
+        (b[11] => z[30]) = 0;
+        (b[12] => z[30]) = 0;
+        (b[13] => z[30]) = 0;
+        (b[14] => z[30]) = 0;
+        (b[15] => z[30]) = 0;
+        (b[16] => z[30]) = 0;
+        (b[17] => z[30]) = 0;
+        (a[0] => z[31]) = 0;
+        (a[1] => z[31]) = 0;
+        (a[2] => z[31]) = 0;
+        (a[3] => z[31]) = 0;
+        (a[4] => z[31]) = 0;
+        (a[5] => z[31]) = 0;
+        (a[6] => z[31]) = 0;
+        (a[7] => z[31]) = 0;
+        (a[8] => z[31]) = 0;
+        (a[9] => z[31]) = 0;
+        (a[10] => z[31]) = 0;
+        (a[11] => z[31]) = 0;
+        (a[12] => z[31]) = 0;
+        (a[13] => z[31]) = 0;
+        (a[14] => z[31]) = 0;
+        (a[15] => z[31]) = 0;
+        (a[16] => z[31]) = 0;
+        (a[17] => z[31]) = 0;
+        (a[18] => z[31]) = 0;
+        (a[19] => z[31]) = 0;
+        (b[0] => z[31]) = 0;
+        (b[1] => z[31]) = 0;
+        (b[2] => z[31]) = 0;
+        (b[3] => z[31]) = 0;
+        (b[4] => z[31]) = 0;
+        (b[5] => z[31]) = 0;
+        (b[6] => z[31]) = 0;
+        (b[7] => z[31]) = 0;
+        (b[8] => z[31]) = 0;
+        (b[9] => z[31]) = 0;
+        (b[10] => z[31]) = 0;
+        (b[11] => z[31]) = 0;
+        (b[12] => z[31]) = 0;
+        (b[13] => z[31]) = 0;
+        (b[14] => z[31]) = 0;
+        (b[15] => z[31]) = 0;
+        (b[16] => z[31]) = 0;
+        (b[17] => z[31]) = 0;
+        (a[0] => z[32]) = 0;
+        (a[1] => z[32]) = 0;
+        (a[2] => z[32]) = 0;
+        (a[3] => z[32]) = 0;
+        (a[4] => z[32]) = 0;
+        (a[5] => z[32]) = 0;
+        (a[6] => z[32]) = 0;
+        (a[7] => z[32]) = 0;
+        (a[8] => z[32]) = 0;
+        (a[9] => z[32]) = 0;
+        (a[10] => z[32]) = 0;
+        (a[11] => z[32]) = 0;
+        (a[12] => z[32]) = 0;
+        (a[13] => z[32]) = 0;
+        (a[14] => z[32]) = 0;
+        (a[15] => z[32]) = 0;
+        (a[16] => z[32]) = 0;
+        (a[17] => z[32]) = 0;
+        (a[18] => z[32]) = 0;
+        (a[19] => z[32]) = 0;
+        (b[0] => z[32]) = 0;
+        (b[1] => z[32]) = 0;
+        (b[2] => z[32]) = 0;
+        (b[3] => z[32]) = 0;
+        (b[4] => z[32]) = 0;
+        (b[5] => z[32]) = 0;
+        (b[6] => z[32]) = 0;
+        (b[7] => z[32]) = 0;
+        (b[8] => z[32]) = 0;
+        (b[9] => z[32]) = 0;
+        (b[10] => z[32]) = 0;
+        (b[11] => z[32]) = 0;
+        (b[12] => z[32]) = 0;
+        (b[13] => z[32]) = 0;
+        (b[14] => z[32]) = 0;
+        (b[15] => z[32]) = 0;
+        (b[16] => z[32]) = 0;
+        (b[17] => z[32]) = 0;
+        (a[0] => z[33]) = 0;
+        (a[1] => z[33]) = 0;
+        (a[2] => z[33]) = 0;
+        (a[3] => z[33]) = 0;
+        (a[4] => z[33]) = 0;
+        (a[5] => z[33]) = 0;
+        (a[6] => z[33]) = 0;
+        (a[7] => z[33]) = 0;
+        (a[8] => z[33]) = 0;
+        (a[9] => z[33]) = 0;
+        (a[10] => z[33]) = 0;
+        (a[11] => z[33]) = 0;
+        (a[12] => z[33]) = 0;
+        (a[13] => z[33]) = 0;
+        (a[14] => z[33]) = 0;
+        (a[15] => z[33]) = 0;
+        (a[16] => z[33]) = 0;
+        (a[17] => z[33]) = 0;
+        (a[18] => z[33]) = 0;
+        (a[19] => z[33]) = 0;
+        (b[0] => z[33]) = 0;
+        (b[1] => z[33]) = 0;
+        (b[2] => z[33]) = 0;
+        (b[3] => z[33]) = 0;
+        (b[4] => z[33]) = 0;
+        (b[5] => z[33]) = 0;
+        (b[6] => z[33]) = 0;
+        (b[7] => z[33]) = 0;
+        (b[8] => z[33]) = 0;
+        (b[9] => z[33]) = 0;
+        (b[10] => z[33]) = 0;
+        (b[11] => z[33]) = 0;
+        (b[12] => z[33]) = 0;
+        (b[13] => z[33]) = 0;
+        (b[14] => z[33]) = 0;
+        (b[15] => z[33]) = 0;
+        (b[16] => z[33]) = 0;
+        (b[17] => z[33]) = 0;
+        (a[0] => z[34]) = 0;
+        (a[1] => z[34]) = 0;
+        (a[2] => z[34]) = 0;
+        (a[3] => z[34]) = 0;
+        (a[4] => z[34]) = 0;
+        (a[5] => z[34]) = 0;
+        (a[6] => z[34]) = 0;
+        (a[7] => z[34]) = 0;
+        (a[8] => z[34]) = 0;
+        (a[9] => z[34]) = 0;
+        (a[10] => z[34]) = 0;
+        (a[11] => z[34]) = 0;
+        (a[12] => z[34]) = 0;
+        (a[13] => z[34]) = 0;
+        (a[14] => z[34]) = 0;
+        (a[15] => z[34]) = 0;
+        (a[16] => z[34]) = 0;
+        (a[17] => z[34]) = 0;
+        (a[18] => z[34]) = 0;
+        (a[19] => z[34]) = 0;
+        (b[0] => z[34]) = 0;
+        (b[1] => z[34]) = 0;
+        (b[2] => z[34]) = 0;
+        (b[3] => z[34]) = 0;
+        (b[4] => z[34]) = 0;
+        (b[5] => z[34]) = 0;
+        (b[6] => z[34]) = 0;
+        (b[7] => z[34]) = 0;
+        (b[8] => z[34]) = 0;
+        (b[9] => z[34]) = 0;
+        (b[10] => z[34]) = 0;
+        (b[11] => z[34]) = 0;
+        (b[12] => z[34]) = 0;
+        (b[13] => z[34]) = 0;
+        (b[14] => z[34]) = 0;
+        (b[15] => z[34]) = 0;
+        (b[16] => z[34]) = 0;
+        (b[17] => z[34]) = 0;
+        (a[0] => z[35]) = 0;
+        (a[1] => z[35]) = 0;
+        (a[2] => z[35]) = 0;
+        (a[3] => z[35]) = 0;
+        (a[4] => z[35]) = 0;
+        (a[5] => z[35]) = 0;
+        (a[6] => z[35]) = 0;
+        (a[7] => z[35]) = 0;
+        (a[8] => z[35]) = 0;
+        (a[9] => z[35]) = 0;
+        (a[10] => z[35]) = 0;
+        (a[11] => z[35]) = 0;
+        (a[12] => z[35]) = 0;
+        (a[13] => z[35]) = 0;
+        (a[14] => z[35]) = 0;
+        (a[15] => z[35]) = 0;
+        (a[16] => z[35]) = 0;
+        (a[17] => z[35]) = 0;
+        (a[18] => z[35]) = 0;
+        (a[19] => z[35]) = 0;
+        (b[0] => z[35]) = 0;
+        (b[1] => z[35]) = 0;
+        (b[2] => z[35]) = 0;
+        (b[3] => z[35]) = 0;
+        (b[4] => z[35]) = 0;
+        (b[5] => z[35]) = 0;
+        (b[6] => z[35]) = 0;
+        (b[7] => z[35]) = 0;
+        (b[8] => z[35]) = 0;
+        (b[9] => z[35]) = 0;
+        (b[10] => z[35]) = 0;
+        (b[11] => z[35]) = 0;
+        (b[12] => z[35]) = 0;
+        (b[13] => z[35]) = 0;
+        (b[14] => z[35]) = 0;
+        (b[15] => z[35]) = 0;
+        (b[16] => z[35]) = 0;
+        (b[17] => z[35]) = 0;
+        (a[0] => z[36]) = 0;
+        (a[1] => z[36]) = 0;
+        (a[2] => z[36]) = 0;
+        (a[3] => z[36]) = 0;
+        (a[4] => z[36]) = 0;
+        (a[5] => z[36]) = 0;
+        (a[6] => z[36]) = 0;
+        (a[7] => z[36]) = 0;
+        (a[8] => z[36]) = 0;
+        (a[9] => z[36]) = 0;
+        (a[10] => z[36]) = 0;
+        (a[11] => z[36]) = 0;
+        (a[12] => z[36]) = 0;
+        (a[13] => z[36]) = 0;
+        (a[14] => z[36]) = 0;
+        (a[15] => z[36]) = 0;
+        (a[16] => z[36]) = 0;
+        (a[17] => z[36]) = 0;
+        (a[18] => z[36]) = 0;
+        (a[19] => z[36]) = 0;
+        (b[0] => z[36]) = 0;
+        (b[1] => z[36]) = 0;
+        (b[2] => z[36]) = 0;
+        (b[3] => z[36]) = 0;
+        (b[4] => z[36]) = 0;
+        (b[5] => z[36]) = 0;
+        (b[6] => z[36]) = 0;
+        (b[7] => z[36]) = 0;
+        (b[8] => z[36]) = 0;
+        (b[9] => z[36]) = 0;
+        (b[10] => z[36]) = 0;
+        (b[11] => z[36]) = 0;
+        (b[12] => z[36]) = 0;
+        (b[13] => z[36]) = 0;
+        (b[14] => z[36]) = 0;
+        (b[15] => z[36]) = 0;
+        (b[16] => z[36]) = 0;
+        (b[17] => z[36]) = 0;
+        (a[0] => z[37]) = 0;
+        (a[1] => z[37]) = 0;
+        (a[2] => z[37]) = 0;
+        (a[3] => z[37]) = 0;
+        (a[4] => z[37]) = 0;
+        (a[5] => z[37]) = 0;
+        (a[6] => z[37]) = 0;
+        (a[7] => z[37]) = 0;
+        (a[8] => z[37]) = 0;
+        (a[9] => z[37]) = 0;
+        (a[10] => z[37]) = 0;
+        (a[11] => z[37]) = 0;
+        (a[12] => z[37]) = 0;
+        (a[13] => z[37]) = 0;
+        (a[14] => z[37]) = 0;
+        (a[15] => z[37]) = 0;
+        (a[16] => z[37]) = 0;
+        (a[17] => z[37]) = 0;
+        (a[18] => z[37]) = 0;
+        (a[19] => z[37]) = 0;
+        (b[0] => z[37]) = 0;
+        (b[1] => z[37]) = 0;
+        (b[2] => z[37]) = 0;
+        (b[3] => z[37]) = 0;
+        (b[4] => z[37]) = 0;
+        (b[5] => z[37]) = 0;
+        (b[6] => z[37]) = 0;
+        (b[7] => z[37]) = 0;
+        (b[8] => z[37]) = 0;
+        (b[9] => z[37]) = 0;
+        (b[10] => z[37]) = 0;
+        (b[11] => z[37]) = 0;
+        (b[12] => z[37]) = 0;
+        (b[13] => z[37]) = 0;
+        (b[14] => z[37]) = 0;
+        (b[15] => z[37]) = 0;
+        (b[16] => z[37]) = 0;
+        (b[17] => z[37]) = 0;
+	endspecify
+`endif
+	
 endmodule
 
 module QL_DSP2_MULT_REGIN ( // TODO: Name subject to change
@@ -267,11 +1727,14 @@
     ) dsp (
         .a(a),
         .b(b),
+        .acc_fir(6'b0),
         .z(z),
+        .dly_b(),
 
         .f_mode(f_mode),
 
         .feedback(feedback),
+        .load_acc(1'b0),
 
         .unsigned_a(unsigned_a),
         .unsigned_b(unsigned_b),
@@ -280,8 +1743,23 @@
         .reset(reset),
 
         .output_select(output_select),      // unregistered output: a * b (0)
+        .saturate_enable(1'b0),
+        .shift_right(6'b0),
+        .round(1'b0),
+        .subtract(1'b0),
         .register_inputs(register_inputs)   // registered inputs
     );
+
+`ifdef SDF_SIM	
+	specify
+		(posedge clk => (z +: a)) = 0;
+		(posedge clk => (z +: b)) = 0;
+		$setuphold(posedge clk, a, 0, 0);
+		$setuphold(posedge clk, b, 0, 0);
+		$setuphold(posedge clk, feedback, 0, 0);
+	endspecify
+`endif
+
 endmodule
 
 module QL_DSP2_MULT_REGOUT ( // TODO: Name subject to change
@@ -313,11 +1791,14 @@
     ) dsp (
         .a(a),
         .b(b),
+        .acc_fir(6'b0),
         .z(z),
+        .dly_b(),
 
         .f_mode(f_mode),
 
         .feedback(feedback),
+        .load_acc(1'b0),
 
         .unsigned_a(unsigned_a),
         .unsigned_b(unsigned_b),
@@ -326,8 +1807,23 @@
         .reset(reset),
 
         .output_select(output_select),      // registered output: a * b (4)
+        .saturate_enable(1'b0),
+        .shift_right(6'b0),
+        .round(1'b0),
+        .subtract(1'b0),
         .register_inputs(register_inputs)   // unregistered inputs
     );
+
+`ifdef SDF_SIM
+	specify
+		(posedge clk => (z +: a)) = 0;
+		(posedge clk => (z +: b)) = 0;
+		$setuphold(posedge clk, a, 0, 0);
+		$setuphold(posedge clk, b, 0, 0);
+		$setuphold(posedge clk, feedback, 0, 0);
+	endspecify
+`endif
+	
 endmodule
 
 module QL_DSP2_MULT_REGIN_REGOUT ( // TODO: Name subject to change
@@ -359,11 +1855,14 @@
     ) dsp (
         .a(a),
         .b(b),
+        .acc_fir(6'b0),
         .z(z),
+        .dly_b(),
 
         .f_mode(f_mode),
 
         .feedback(feedback),
+        .load_acc(1'b0),
 
         .unsigned_a(unsigned_a),
         .unsigned_b(unsigned_b),
@@ -372,8 +1871,23 @@
         .reset(reset),
 
         .output_select(output_select),      // registered output: a * b (4)
+        .saturate_enable(1'b0),
+        .shift_right(6'b0),
+        .round(1'b0),
+        .subtract(1'b0),
         .register_inputs(register_inputs)   // registered inputs
     );
+
+`ifdef SDF_SIM	
+	specify
+		(posedge clk => (z +: a)) = 0;
+		(posedge clk => (z +: b)) = 0;
+		$setuphold(posedge clk, a, 0, 0);
+		$setuphold(posedge clk, b, 0, 0);
+		$setuphold(posedge clk, feedback, 0, 0);
+	endspecify
+`endif
+	
 endmodule
 
 module QL_DSP2_MULTADD (
@@ -410,6 +1924,7 @@
     ) dsp (
         .a(a),
         .b(b),
+        .dly_b(),
         .z(z),
 
         .f_mode(f_mode),
@@ -421,6 +1936,7 @@
         .unsigned_a(unsigned_a),
         .unsigned_b(unsigned_b),
 
+        //.clk(1'b0),
         .reset(reset),
 
         .output_select(output_select),      // unregistered output: ACCin (2, 3)
@@ -430,6 +1946,1722 @@
         .subtract(subtract),
         .register_inputs(register_inputs)   // unregistered inputs
     );
+
+`ifdef SDF_SIM	
+	specify
+        (a[0] => z[0]) = 0;
+        (a[1] => z[0]) = 0;
+        (a[2] => z[0]) = 0;
+        (a[3] => z[0]) = 0;
+        (a[4] => z[0]) = 0;
+        (a[5] => z[0]) = 0;
+        (a[6] => z[0]) = 0;
+        (a[7] => z[0]) = 0;
+        (a[8] => z[0]) = 0;
+        (a[9] => z[0]) = 0;
+        (a[10] => z[0]) = 0;
+        (a[11] => z[0]) = 0;
+        (a[12] => z[0]) = 0;
+        (a[13] => z[0]) = 0;
+        (a[14] => z[0]) = 0;
+        (a[15] => z[0]) = 0;
+        (a[16] => z[0]) = 0;
+        (a[17] => z[0]) = 0;
+        (a[18] => z[0]) = 0;
+        (a[19] => z[0]) = 0;
+        (b[0] => z[0]) = 0;
+        (b[1] => z[0]) = 0;
+        (b[2] => z[0]) = 0;
+        (b[3] => z[0]) = 0;
+        (b[4] => z[0]) = 0;
+        (b[5] => z[0]) = 0;
+        (b[6] => z[0]) = 0;
+        (b[7] => z[0]) = 0;
+        (b[8] => z[0]) = 0;
+        (b[9] => z[0]) = 0;
+        (b[10] => z[0]) = 0;
+        (b[11] => z[0]) = 0;
+        (b[12] => z[0]) = 0;
+        (b[13] => z[0]) = 0;
+        (b[14] => z[0]) = 0;
+        (b[15] => z[0]) = 0;
+        (b[16] => z[0]) = 0;
+        (b[17] => z[0]) = 0;
+        (a[0] => z[1]) = 0;
+        (a[1] => z[1]) = 0;
+        (a[2] => z[1]) = 0;
+        (a[3] => z[1]) = 0;
+        (a[4] => z[1]) = 0;
+        (a[5] => z[1]) = 0;
+        (a[6] => z[1]) = 0;
+        (a[7] => z[1]) = 0;
+        (a[8] => z[1]) = 0;
+        (a[9] => z[1]) = 0;
+        (a[10] => z[1]) = 0;
+        (a[11] => z[1]) = 0;
+        (a[12] => z[1]) = 0;
+        (a[13] => z[1]) = 0;
+        (a[14] => z[1]) = 0;
+        (a[15] => z[1]) = 0;
+        (a[16] => z[1]) = 0;
+        (a[17] => z[1]) = 0;
+        (a[18] => z[1]) = 0;
+        (a[19] => z[1]) = 0;
+        (b[0] => z[1]) = 0;
+        (b[1] => z[1]) = 0;
+        (b[2] => z[1]) = 0;
+        (b[3] => z[1]) = 0;
+        (b[4] => z[1]) = 0;
+        (b[5] => z[1]) = 0;
+        (b[6] => z[1]) = 0;
+        (b[7] => z[1]) = 0;
+        (b[8] => z[1]) = 0;
+        (b[9] => z[1]) = 0;
+        (b[10] => z[1]) = 0;
+        (b[11] => z[1]) = 0;
+        (b[12] => z[1]) = 0;
+        (b[13] => z[1]) = 0;
+        (b[14] => z[1]) = 0;
+        (b[15] => z[1]) = 0;
+        (b[16] => z[1]) = 0;
+        (b[17] => z[1]) = 0;
+        (a[0] => z[2]) = 0;
+        (a[1] => z[2]) = 0;
+        (a[2] => z[2]) = 0;
+        (a[3] => z[2]) = 0;
+        (a[4] => z[2]) = 0;
+        (a[5] => z[2]) = 0;
+        (a[6] => z[2]) = 0;
+        (a[7] => z[2]) = 0;
+        (a[8] => z[2]) = 0;
+        (a[9] => z[2]) = 0;
+        (a[10] => z[2]) = 0;
+        (a[11] => z[2]) = 0;
+        (a[12] => z[2]) = 0;
+        (a[13] => z[2]) = 0;
+        (a[14] => z[2]) = 0;
+        (a[15] => z[2]) = 0;
+        (a[16] => z[2]) = 0;
+        (a[17] => z[2]) = 0;
+        (a[18] => z[2]) = 0;
+        (a[19] => z[2]) = 0;
+        (b[0] => z[2]) = 0;
+        (b[1] => z[2]) = 0;
+        (b[2] => z[2]) = 0;
+        (b[3] => z[2]) = 0;
+        (b[4] => z[2]) = 0;
+        (b[5] => z[2]) = 0;
+        (b[6] => z[2]) = 0;
+        (b[7] => z[2]) = 0;
+        (b[8] => z[2]) = 0;
+        (b[9] => z[2]) = 0;
+        (b[10] => z[2]) = 0;
+        (b[11] => z[2]) = 0;
+        (b[12] => z[2]) = 0;
+        (b[13] => z[2]) = 0;
+        (b[14] => z[2]) = 0;
+        (b[15] => z[2]) = 0;
+        (b[16] => z[2]) = 0;
+        (b[17] => z[2]) = 0;
+        (a[0] => z[3]) = 0;
+        (a[1] => z[3]) = 0;
+        (a[2] => z[3]) = 0;
+        (a[3] => z[3]) = 0;
+        (a[4] => z[3]) = 0;
+        (a[5] => z[3]) = 0;
+        (a[6] => z[3]) = 0;
+        (a[7] => z[3]) = 0;
+        (a[8] => z[3]) = 0;
+        (a[9] => z[3]) = 0;
+        (a[10] => z[3]) = 0;
+        (a[11] => z[3]) = 0;
+        (a[12] => z[3]) = 0;
+        (a[13] => z[3]) = 0;
+        (a[14] => z[3]) = 0;
+        (a[15] => z[3]) = 0;
+        (a[16] => z[3]) = 0;
+        (a[17] => z[3]) = 0;
+        (a[18] => z[3]) = 0;
+        (a[19] => z[3]) = 0;
+        (b[0] => z[3]) = 0;
+        (b[1] => z[3]) = 0;
+        (b[2] => z[3]) = 0;
+        (b[3] => z[3]) = 0;
+        (b[4] => z[3]) = 0;
+        (b[5] => z[3]) = 0;
+        (b[6] => z[3]) = 0;
+        (b[7] => z[3]) = 0;
+        (b[8] => z[3]) = 0;
+        (b[9] => z[3]) = 0;
+        (b[10] => z[3]) = 0;
+        (b[11] => z[3]) = 0;
+        (b[12] => z[3]) = 0;
+        (b[13] => z[3]) = 0;
+        (b[14] => z[3]) = 0;
+        (b[15] => z[3]) = 0;
+        (b[16] => z[3]) = 0;
+        (b[17] => z[3]) = 0;
+        (a[0] => z[4]) = 0;
+        (a[1] => z[4]) = 0;
+        (a[2] => z[4]) = 0;
+        (a[3] => z[4]) = 0;
+        (a[4] => z[4]) = 0;
+        (a[5] => z[4]) = 0;
+        (a[6] => z[4]) = 0;
+        (a[7] => z[4]) = 0;
+        (a[8] => z[4]) = 0;
+        (a[9] => z[4]) = 0;
+        (a[10] => z[4]) = 0;
+        (a[11] => z[4]) = 0;
+        (a[12] => z[4]) = 0;
+        (a[13] => z[4]) = 0;
+        (a[14] => z[4]) = 0;
+        (a[15] => z[4]) = 0;
+        (a[16] => z[4]) = 0;
+        (a[17] => z[4]) = 0;
+        (a[18] => z[4]) = 0;
+        (a[19] => z[4]) = 0;
+        (b[0] => z[4]) = 0;
+        (b[1] => z[4]) = 0;
+        (b[2] => z[4]) = 0;
+        (b[3] => z[4]) = 0;
+        (b[4] => z[4]) = 0;
+        (b[5] => z[4]) = 0;
+        (b[6] => z[4]) = 0;
+        (b[7] => z[4]) = 0;
+        (b[8] => z[4]) = 0;
+        (b[9] => z[4]) = 0;
+        (b[10] => z[4]) = 0;
+        (b[11] => z[4]) = 0;
+        (b[12] => z[4]) = 0;
+        (b[13] => z[4]) = 0;
+        (b[14] => z[4]) = 0;
+        (b[15] => z[4]) = 0;
+        (b[16] => z[4]) = 0;
+        (b[17] => z[4]) = 0;
+        (a[0] => z[5]) = 0;
+        (a[1] => z[5]) = 0;
+        (a[2] => z[5]) = 0;
+        (a[3] => z[5]) = 0;
+        (a[4] => z[5]) = 0;
+        (a[5] => z[5]) = 0;
+        (a[6] => z[5]) = 0;
+        (a[7] => z[5]) = 0;
+        (a[8] => z[5]) = 0;
+        (a[9] => z[5]) = 0;
+        (a[10] => z[5]) = 0;
+        (a[11] => z[5]) = 0;
+        (a[12] => z[5]) = 0;
+        (a[13] => z[5]) = 0;
+        (a[14] => z[5]) = 0;
+        (a[15] => z[5]) = 0;
+        (a[16] => z[5]) = 0;
+        (a[17] => z[5]) = 0;
+        (a[18] => z[5]) = 0;
+        (a[19] => z[5]) = 0;
+        (b[0] => z[5]) = 0;
+        (b[1] => z[5]) = 0;
+        (b[2] => z[5]) = 0;
+        (b[3] => z[5]) = 0;
+        (b[4] => z[5]) = 0;
+        (b[5] => z[5]) = 0;
+        (b[6] => z[5]) = 0;
+        (b[7] => z[5]) = 0;
+        (b[8] => z[5]) = 0;
+        (b[9] => z[5]) = 0;
+        (b[10] => z[5]) = 0;
+        (b[11] => z[5]) = 0;
+        (b[12] => z[5]) = 0;
+        (b[13] => z[5]) = 0;
+        (b[14] => z[5]) = 0;
+        (b[15] => z[5]) = 0;
+        (b[16] => z[5]) = 0;
+        (b[17] => z[5]) = 0;
+        (a[0] => z[6]) = 0;
+        (a[1] => z[6]) = 0;
+        (a[2] => z[6]) = 0;
+        (a[3] => z[6]) = 0;
+        (a[4] => z[6]) = 0;
+        (a[5] => z[6]) = 0;
+        (a[6] => z[6]) = 0;
+        (a[7] => z[6]) = 0;
+        (a[8] => z[6]) = 0;
+        (a[9] => z[6]) = 0;
+        (a[10] => z[6]) = 0;
+        (a[11] => z[6]) = 0;
+        (a[12] => z[6]) = 0;
+        (a[13] => z[6]) = 0;
+        (a[14] => z[6]) = 0;
+        (a[15] => z[6]) = 0;
+        (a[16] => z[6]) = 0;
+        (a[17] => z[6]) = 0;
+        (a[18] => z[6]) = 0;
+        (a[19] => z[6]) = 0;
+        (b[0] => z[6]) = 0;
+        (b[1] => z[6]) = 0;
+        (b[2] => z[6]) = 0;
+        (b[3] => z[6]) = 0;
+        (b[4] => z[6]) = 0;
+        (b[5] => z[6]) = 0;
+        (b[6] => z[6]) = 0;
+        (b[7] => z[6]) = 0;
+        (b[8] => z[6]) = 0;
+        (b[9] => z[6]) = 0;
+        (b[10] => z[6]) = 0;
+        (b[11] => z[6]) = 0;
+        (b[12] => z[6]) = 0;
+        (b[13] => z[6]) = 0;
+        (b[14] => z[6]) = 0;
+        (b[15] => z[6]) = 0;
+        (b[16] => z[6]) = 0;
+        (b[17] => z[6]) = 0;
+        (a[0] => z[7]) = 0;
+        (a[1] => z[7]) = 0;
+        (a[2] => z[7]) = 0;
+        (a[3] => z[7]) = 0;
+        (a[4] => z[7]) = 0;
+        (a[5] => z[7]) = 0;
+        (a[6] => z[7]) = 0;
+        (a[7] => z[7]) = 0;
+        (a[8] => z[7]) = 0;
+        (a[9] => z[7]) = 0;
+        (a[10] => z[7]) = 0;
+        (a[11] => z[7]) = 0;
+        (a[12] => z[7]) = 0;
+        (a[13] => z[7]) = 0;
+        (a[14] => z[7]) = 0;
+        (a[15] => z[7]) = 0;
+        (a[16] => z[7]) = 0;
+        (a[17] => z[7]) = 0;
+        (a[18] => z[7]) = 0;
+        (a[19] => z[7]) = 0;
+        (b[0] => z[7]) = 0;
+        (b[1] => z[7]) = 0;
+        (b[2] => z[7]) = 0;
+        (b[3] => z[7]) = 0;
+        (b[4] => z[7]) = 0;
+        (b[5] => z[7]) = 0;
+        (b[6] => z[7]) = 0;
+        (b[7] => z[7]) = 0;
+        (b[8] => z[7]) = 0;
+        (b[9] => z[7]) = 0;
+        (b[10] => z[7]) = 0;
+        (b[11] => z[7]) = 0;
+        (b[12] => z[7]) = 0;
+        (b[13] => z[7]) = 0;
+        (b[14] => z[7]) = 0;
+        (b[15] => z[7]) = 0;
+        (b[16] => z[7]) = 0;
+        (b[17] => z[7]) = 0;
+        (a[0] => z[8]) = 0;
+        (a[1] => z[8]) = 0;
+        (a[2] => z[8]) = 0;
+        (a[3] => z[8]) = 0;
+        (a[4] => z[8]) = 0;
+        (a[5] => z[8]) = 0;
+        (a[6] => z[8]) = 0;
+        (a[7] => z[8]) = 0;
+        (a[8] => z[8]) = 0;
+        (a[9] => z[8]) = 0;
+        (a[10] => z[8]) = 0;
+        (a[11] => z[8]) = 0;
+        (a[12] => z[8]) = 0;
+        (a[13] => z[8]) = 0;
+        (a[14] => z[8]) = 0;
+        (a[15] => z[8]) = 0;
+        (a[16] => z[8]) = 0;
+        (a[17] => z[8]) = 0;
+        (a[18] => z[8]) = 0;
+        (a[19] => z[8]) = 0;
+        (b[0] => z[8]) = 0;
+        (b[1] => z[8]) = 0;
+        (b[2] => z[8]) = 0;
+        (b[3] => z[8]) = 0;
+        (b[4] => z[8]) = 0;
+        (b[5] => z[8]) = 0;
+        (b[6] => z[8]) = 0;
+        (b[7] => z[8]) = 0;
+        (b[8] => z[8]) = 0;
+        (b[9] => z[8]) = 0;
+        (b[10] => z[8]) = 0;
+        (b[11] => z[8]) = 0;
+        (b[12] => z[8]) = 0;
+        (b[13] => z[8]) = 0;
+        (b[14] => z[8]) = 0;
+        (b[15] => z[8]) = 0;
+        (b[16] => z[8]) = 0;
+        (b[17] => z[8]) = 0;
+        (a[0] => z[9]) = 0;
+        (a[1] => z[9]) = 0;
+        (a[2] => z[9]) = 0;
+        (a[3] => z[9]) = 0;
+        (a[4] => z[9]) = 0;
+        (a[5] => z[9]) = 0;
+        (a[6] => z[9]) = 0;
+        (a[7] => z[9]) = 0;
+        (a[8] => z[9]) = 0;
+        (a[9] => z[9]) = 0;
+        (a[10] => z[9]) = 0;
+        (a[11] => z[9]) = 0;
+        (a[12] => z[9]) = 0;
+        (a[13] => z[9]) = 0;
+        (a[14] => z[9]) = 0;
+        (a[15] => z[9]) = 0;
+        (a[16] => z[9]) = 0;
+        (a[17] => z[9]) = 0;
+        (a[18] => z[9]) = 0;
+        (a[19] => z[9]) = 0;
+        (b[0] => z[9]) = 0;
+        (b[1] => z[9]) = 0;
+        (b[2] => z[9]) = 0;
+        (b[3] => z[9]) = 0;
+        (b[4] => z[9]) = 0;
+        (b[5] => z[9]) = 0;
+        (b[6] => z[9]) = 0;
+        (b[7] => z[9]) = 0;
+        (b[8] => z[9]) = 0;
+        (b[9] => z[9]) = 0;
+        (b[10] => z[9]) = 0;
+        (b[11] => z[9]) = 0;
+        (b[12] => z[9]) = 0;
+        (b[13] => z[9]) = 0;
+        (b[14] => z[9]) = 0;
+        (b[15] => z[9]) = 0;
+        (b[16] => z[9]) = 0;
+        (b[17] => z[9]) = 0;
+        (a[0] => z[10]) = 0;
+        (a[1] => z[10]) = 0;
+        (a[2] => z[10]) = 0;
+        (a[3] => z[10]) = 0;
+        (a[4] => z[10]) = 0;
+        (a[5] => z[10]) = 0;
+        (a[6] => z[10]) = 0;
+        (a[7] => z[10]) = 0;
+        (a[8] => z[10]) = 0;
+        (a[9] => z[10]) = 0;
+        (a[10] => z[10]) = 0;
+        (a[11] => z[10]) = 0;
+        (a[12] => z[10]) = 0;
+        (a[13] => z[10]) = 0;
+        (a[14] => z[10]) = 0;
+        (a[15] => z[10]) = 0;
+        (a[16] => z[10]) = 0;
+        (a[17] => z[10]) = 0;
+        (a[18] => z[10]) = 0;
+        (a[19] => z[10]) = 0;
+        (b[0] => z[10]) = 0;
+        (b[1] => z[10]) = 0;
+        (b[2] => z[10]) = 0;
+        (b[3] => z[10]) = 0;
+        (b[4] => z[10]) = 0;
+        (b[5] => z[10]) = 0;
+        (b[6] => z[10]) = 0;
+        (b[7] => z[10]) = 0;
+        (b[8] => z[10]) = 0;
+        (b[9] => z[10]) = 0;
+        (b[10] => z[10]) = 0;
+        (b[11] => z[10]) = 0;
+        (b[12] => z[10]) = 0;
+        (b[13] => z[10]) = 0;
+        (b[14] => z[10]) = 0;
+        (b[15] => z[10]) = 0;
+        (b[16] => z[10]) = 0;
+        (b[17] => z[10]) = 0;
+        (a[0] => z[11]) = 0;
+        (a[1] => z[11]) = 0;
+        (a[2] => z[11]) = 0;
+        (a[3] => z[11]) = 0;
+        (a[4] => z[11]) = 0;
+        (a[5] => z[11]) = 0;
+        (a[6] => z[11]) = 0;
+        (a[7] => z[11]) = 0;
+        (a[8] => z[11]) = 0;
+        (a[9] => z[11]) = 0;
+        (a[10] => z[11]) = 0;
+        (a[11] => z[11]) = 0;
+        (a[12] => z[11]) = 0;
+        (a[13] => z[11]) = 0;
+        (a[14] => z[11]) = 0;
+        (a[15] => z[11]) = 0;
+        (a[16] => z[11]) = 0;
+        (a[17] => z[11]) = 0;
+        (a[18] => z[11]) = 0;
+        (a[19] => z[11]) = 0;
+        (b[0] => z[11]) = 0;
+        (b[1] => z[11]) = 0;
+        (b[2] => z[11]) = 0;
+        (b[3] => z[11]) = 0;
+        (b[4] => z[11]) = 0;
+        (b[5] => z[11]) = 0;
+        (b[6] => z[11]) = 0;
+        (b[7] => z[11]) = 0;
+        (b[8] => z[11]) = 0;
+        (b[9] => z[11]) = 0;
+        (b[10] => z[11]) = 0;
+        (b[11] => z[11]) = 0;
+        (b[12] => z[11]) = 0;
+        (b[13] => z[11]) = 0;
+        (b[14] => z[11]) = 0;
+        (b[15] => z[11]) = 0;
+        (b[16] => z[11]) = 0;
+        (b[17] => z[11]) = 0;
+        (a[0] => z[12]) = 0;
+        (a[1] => z[12]) = 0;
+        (a[2] => z[12]) = 0;
+        (a[3] => z[12]) = 0;
+        (a[4] => z[12]) = 0;
+        (a[5] => z[12]) = 0;
+        (a[6] => z[12]) = 0;
+        (a[7] => z[12]) = 0;
+        (a[8] => z[12]) = 0;
+        (a[9] => z[12]) = 0;
+        (a[10] => z[12]) = 0;
+        (a[11] => z[12]) = 0;
+        (a[12] => z[12]) = 0;
+        (a[13] => z[12]) = 0;
+        (a[14] => z[12]) = 0;
+        (a[15] => z[12]) = 0;
+        (a[16] => z[12]) = 0;
+        (a[17] => z[12]) = 0;
+        (a[18] => z[12]) = 0;
+        (a[19] => z[12]) = 0;
+        (b[0] => z[12]) = 0;
+        (b[1] => z[12]) = 0;
+        (b[2] => z[12]) = 0;
+        (b[3] => z[12]) = 0;
+        (b[4] => z[12]) = 0;
+        (b[5] => z[12]) = 0;
+        (b[6] => z[12]) = 0;
+        (b[7] => z[12]) = 0;
+        (b[8] => z[12]) = 0;
+        (b[9] => z[12]) = 0;
+        (b[10] => z[12]) = 0;
+        (b[11] => z[12]) = 0;
+        (b[12] => z[12]) = 0;
+        (b[13] => z[12]) = 0;
+        (b[14] => z[12]) = 0;
+        (b[15] => z[12]) = 0;
+        (b[16] => z[12]) = 0;
+        (b[17] => z[12]) = 0;
+        (a[0] => z[13]) = 0;
+        (a[1] => z[13]) = 0;
+        (a[2] => z[13]) = 0;
+        (a[3] => z[13]) = 0;
+        (a[4] => z[13]) = 0;
+        (a[5] => z[13]) = 0;
+        (a[6] => z[13]) = 0;
+        (a[7] => z[13]) = 0;
+        (a[8] => z[13]) = 0;
+        (a[9] => z[13]) = 0;
+        (a[10] => z[13]) = 0;
+        (a[11] => z[13]) = 0;
+        (a[12] => z[13]) = 0;
+        (a[13] => z[13]) = 0;
+        (a[14] => z[13]) = 0;
+        (a[15] => z[13]) = 0;
+        (a[16] => z[13]) = 0;
+        (a[17] => z[13]) = 0;
+        (a[18] => z[13]) = 0;
+        (a[19] => z[13]) = 0;
+        (b[0] => z[13]) = 0;
+        (b[1] => z[13]) = 0;
+        (b[2] => z[13]) = 0;
+        (b[3] => z[13]) = 0;
+        (b[4] => z[13]) = 0;
+        (b[5] => z[13]) = 0;
+        (b[6] => z[13]) = 0;
+        (b[7] => z[13]) = 0;
+        (b[8] => z[13]) = 0;
+        (b[9] => z[13]) = 0;
+        (b[10] => z[13]) = 0;
+        (b[11] => z[13]) = 0;
+        (b[12] => z[13]) = 0;
+        (b[13] => z[13]) = 0;
+        (b[14] => z[13]) = 0;
+        (b[15] => z[13]) = 0;
+        (b[16] => z[13]) = 0;
+        (b[17] => z[13]) = 0;
+        (a[0] => z[14]) = 0;
+        (a[1] => z[14]) = 0;
+        (a[2] => z[14]) = 0;
+        (a[3] => z[14]) = 0;
+        (a[4] => z[14]) = 0;
+        (a[5] => z[14]) = 0;
+        (a[6] => z[14]) = 0;
+        (a[7] => z[14]) = 0;
+        (a[8] => z[14]) = 0;
+        (a[9] => z[14]) = 0;
+        (a[10] => z[14]) = 0;
+        (a[11] => z[14]) = 0;
+        (a[12] => z[14]) = 0;
+        (a[13] => z[14]) = 0;
+        (a[14] => z[14]) = 0;
+        (a[15] => z[14]) = 0;
+        (a[16] => z[14]) = 0;
+        (a[17] => z[14]) = 0;
+        (a[18] => z[14]) = 0;
+        (a[19] => z[14]) = 0;
+        (b[0] => z[14]) = 0;
+        (b[1] => z[14]) = 0;
+        (b[2] => z[14]) = 0;
+        (b[3] => z[14]) = 0;
+        (b[4] => z[14]) = 0;
+        (b[5] => z[14]) = 0;
+        (b[6] => z[14]) = 0;
+        (b[7] => z[14]) = 0;
+        (b[8] => z[14]) = 0;
+        (b[9] => z[14]) = 0;
+        (b[10] => z[14]) = 0;
+        (b[11] => z[14]) = 0;
+        (b[12] => z[14]) = 0;
+        (b[13] => z[14]) = 0;
+        (b[14] => z[14]) = 0;
+        (b[15] => z[14]) = 0;
+        (b[16] => z[14]) = 0;
+        (b[17] => z[14]) = 0;
+        (a[0] => z[15]) = 0;
+        (a[1] => z[15]) = 0;
+        (a[2] => z[15]) = 0;
+        (a[3] => z[15]) = 0;
+        (a[4] => z[15]) = 0;
+        (a[5] => z[15]) = 0;
+        (a[6] => z[15]) = 0;
+        (a[7] => z[15]) = 0;
+        (a[8] => z[15]) = 0;
+        (a[9] => z[15]) = 0;
+        (a[10] => z[15]) = 0;
+        (a[11] => z[15]) = 0;
+        (a[12] => z[15]) = 0;
+        (a[13] => z[15]) = 0;
+        (a[14] => z[15]) = 0;
+        (a[15] => z[15]) = 0;
+        (a[16] => z[15]) = 0;
+        (a[17] => z[15]) = 0;
+        (a[18] => z[15]) = 0;
+        (a[19] => z[15]) = 0;
+        (b[0] => z[15]) = 0;
+        (b[1] => z[15]) = 0;
+        (b[2] => z[15]) = 0;
+        (b[3] => z[15]) = 0;
+        (b[4] => z[15]) = 0;
+        (b[5] => z[15]) = 0;
+        (b[6] => z[15]) = 0;
+        (b[7] => z[15]) = 0;
+        (b[8] => z[15]) = 0;
+        (b[9] => z[15]) = 0;
+        (b[10] => z[15]) = 0;
+        (b[11] => z[15]) = 0;
+        (b[12] => z[15]) = 0;
+        (b[13] => z[15]) = 0;
+        (b[14] => z[15]) = 0;
+        (b[15] => z[15]) = 0;
+        (b[16] => z[15]) = 0;
+        (b[17] => z[15]) = 0;
+        (a[0] => z[16]) = 0;
+        (a[1] => z[16]) = 0;
+        (a[2] => z[16]) = 0;
+        (a[3] => z[16]) = 0;
+        (a[4] => z[16]) = 0;
+        (a[5] => z[16]) = 0;
+        (a[6] => z[16]) = 0;
+        (a[7] => z[16]) = 0;
+        (a[8] => z[16]) = 0;
+        (a[9] => z[16]) = 0;
+        (a[10] => z[16]) = 0;
+        (a[11] => z[16]) = 0;
+        (a[12] => z[16]) = 0;
+        (a[13] => z[16]) = 0;
+        (a[14] => z[16]) = 0;
+        (a[15] => z[16]) = 0;
+        (a[16] => z[16]) = 0;
+        (a[17] => z[16]) = 0;
+        (a[18] => z[16]) = 0;
+        (a[19] => z[16]) = 0;
+        (b[0] => z[16]) = 0;
+        (b[1] => z[16]) = 0;
+        (b[2] => z[16]) = 0;
+        (b[3] => z[16]) = 0;
+        (b[4] => z[16]) = 0;
+        (b[5] => z[16]) = 0;
+        (b[6] => z[16]) = 0;
+        (b[7] => z[16]) = 0;
+        (b[8] => z[16]) = 0;
+        (b[9] => z[16]) = 0;
+        (b[10] => z[16]) = 0;
+        (b[11] => z[16]) = 0;
+        (b[12] => z[16]) = 0;
+        (b[13] => z[16]) = 0;
+        (b[14] => z[16]) = 0;
+        (b[15] => z[16]) = 0;
+        (b[16] => z[16]) = 0;
+        (b[17] => z[16]) = 0;
+        (a[0] => z[17]) = 0;
+        (a[1] => z[17]) = 0;
+        (a[2] => z[17]) = 0;
+        (a[3] => z[17]) = 0;
+        (a[4] => z[17]) = 0;
+        (a[5] => z[17]) = 0;
+        (a[6] => z[17]) = 0;
+        (a[7] => z[17]) = 0;
+        (a[8] => z[17]) = 0;
+        (a[9] => z[17]) = 0;
+        (a[10] => z[17]) = 0;
+        (a[11] => z[17]) = 0;
+        (a[12] => z[17]) = 0;
+        (a[13] => z[17]) = 0;
+        (a[14] => z[17]) = 0;
+        (a[15] => z[17]) = 0;
+        (a[16] => z[17]) = 0;
+        (a[17] => z[17]) = 0;
+        (a[18] => z[17]) = 0;
+        (a[19] => z[17]) = 0;
+        (b[0] => z[17]) = 0;
+        (b[1] => z[17]) = 0;
+        (b[2] => z[17]) = 0;
+        (b[3] => z[17]) = 0;
+        (b[4] => z[17]) = 0;
+        (b[5] => z[17]) = 0;
+        (b[6] => z[17]) = 0;
+        (b[7] => z[17]) = 0;
+        (b[8] => z[17]) = 0;
+        (b[9] => z[17]) = 0;
+        (b[10] => z[17]) = 0;
+        (b[11] => z[17]) = 0;
+        (b[12] => z[17]) = 0;
+        (b[13] => z[17]) = 0;
+        (b[14] => z[17]) = 0;
+        (b[15] => z[17]) = 0;
+        (b[16] => z[17]) = 0;
+        (b[17] => z[17]) = 0;
+        (a[0] => z[18]) = 0;
+        (a[1] => z[18]) = 0;
+        (a[2] => z[18]) = 0;
+        (a[3] => z[18]) = 0;
+        (a[4] => z[18]) = 0;
+        (a[5] => z[18]) = 0;
+        (a[6] => z[18]) = 0;
+        (a[7] => z[18]) = 0;
+        (a[8] => z[18]) = 0;
+        (a[9] => z[18]) = 0;
+        (a[10] => z[18]) = 0;
+        (a[11] => z[18]) = 0;
+        (a[12] => z[18]) = 0;
+        (a[13] => z[18]) = 0;
+        (a[14] => z[18]) = 0;
+        (a[15] => z[18]) = 0;
+        (a[16] => z[18]) = 0;
+        (a[17] => z[18]) = 0;
+        (a[18] => z[18]) = 0;
+        (a[19] => z[18]) = 0;
+        (b[0] => z[18]) = 0;
+        (b[1] => z[18]) = 0;
+        (b[2] => z[18]) = 0;
+        (b[3] => z[18]) = 0;
+        (b[4] => z[18]) = 0;
+        (b[5] => z[18]) = 0;
+        (b[6] => z[18]) = 0;
+        (b[7] => z[18]) = 0;
+        (b[8] => z[18]) = 0;
+        (b[9] => z[18]) = 0;
+        (b[10] => z[18]) = 0;
+        (b[11] => z[18]) = 0;
+        (b[12] => z[18]) = 0;
+        (b[13] => z[18]) = 0;
+        (b[14] => z[18]) = 0;
+        (b[15] => z[18]) = 0;
+        (b[16] => z[18]) = 0;
+        (b[17] => z[18]) = 0;
+        (a[0] => z[19]) = 0;
+        (a[1] => z[19]) = 0;
+        (a[2] => z[19]) = 0;
+        (a[3] => z[19]) = 0;
+        (a[4] => z[19]) = 0;
+        (a[5] => z[19]) = 0;
+        (a[6] => z[19]) = 0;
+        (a[7] => z[19]) = 0;
+        (a[8] => z[19]) = 0;
+        (a[9] => z[19]) = 0;
+        (a[10] => z[19]) = 0;
+        (a[11] => z[19]) = 0;
+        (a[12] => z[19]) = 0;
+        (a[13] => z[19]) = 0;
+        (a[14] => z[19]) = 0;
+        (a[15] => z[19]) = 0;
+        (a[16] => z[19]) = 0;
+        (a[17] => z[19]) = 0;
+        (a[18] => z[19]) = 0;
+        (a[19] => z[19]) = 0;
+        (b[0] => z[19]) = 0;
+        (b[1] => z[19]) = 0;
+        (b[2] => z[19]) = 0;
+        (b[3] => z[19]) = 0;
+        (b[4] => z[19]) = 0;
+        (b[5] => z[19]) = 0;
+        (b[6] => z[19]) = 0;
+        (b[7] => z[19]) = 0;
+        (b[8] => z[19]) = 0;
+        (b[9] => z[19]) = 0;
+        (b[10] => z[19]) = 0;
+        (b[11] => z[19]) = 0;
+        (b[12] => z[19]) = 0;
+        (b[13] => z[19]) = 0;
+        (b[14] => z[19]) = 0;
+        (b[15] => z[19]) = 0;
+        (b[16] => z[19]) = 0;
+        (b[17] => z[19]) = 0;
+        (a[0] => z[20]) = 0;
+        (a[1] => z[20]) = 0;
+        (a[2] => z[20]) = 0;
+        (a[3] => z[20]) = 0;
+        (a[4] => z[20]) = 0;
+        (a[5] => z[20]) = 0;
+        (a[6] => z[20]) = 0;
+        (a[7] => z[20]) = 0;
+        (a[8] => z[20]) = 0;
+        (a[9] => z[20]) = 0;
+        (a[10] => z[20]) = 0;
+        (a[11] => z[20]) = 0;
+        (a[12] => z[20]) = 0;
+        (a[13] => z[20]) = 0;
+        (a[14] => z[20]) = 0;
+        (a[15] => z[20]) = 0;
+        (a[16] => z[20]) = 0;
+        (a[17] => z[20]) = 0;
+        (a[18] => z[20]) = 0;
+        (a[19] => z[20]) = 0;
+        (b[0] => z[20]) = 0;
+        (b[1] => z[20]) = 0;
+        (b[2] => z[20]) = 0;
+        (b[3] => z[20]) = 0;
+        (b[4] => z[20]) = 0;
+        (b[5] => z[20]) = 0;
+        (b[6] => z[20]) = 0;
+        (b[7] => z[20]) = 0;
+        (b[8] => z[20]) = 0;
+        (b[9] => z[20]) = 0;
+        (b[10] => z[20]) = 0;
+        (b[11] => z[20]) = 0;
+        (b[12] => z[20]) = 0;
+        (b[13] => z[20]) = 0;
+        (b[14] => z[20]) = 0;
+        (b[15] => z[20]) = 0;
+        (b[16] => z[20]) = 0;
+        (b[17] => z[20]) = 0;
+        (a[0] => z[21]) = 0;
+        (a[1] => z[21]) = 0;
+        (a[2] => z[21]) = 0;
+        (a[3] => z[21]) = 0;
+        (a[4] => z[21]) = 0;
+        (a[5] => z[21]) = 0;
+        (a[6] => z[21]) = 0;
+        (a[7] => z[21]) = 0;
+        (a[8] => z[21]) = 0;
+        (a[9] => z[21]) = 0;
+        (a[10] => z[21]) = 0;
+        (a[11] => z[21]) = 0;
+        (a[12] => z[21]) = 0;
+        (a[13] => z[21]) = 0;
+        (a[14] => z[21]) = 0;
+        (a[15] => z[21]) = 0;
+        (a[16] => z[21]) = 0;
+        (a[17] => z[21]) = 0;
+        (a[18] => z[21]) = 0;
+        (a[19] => z[21]) = 0;
+        (b[0] => z[21]) = 0;
+        (b[1] => z[21]) = 0;
+        (b[2] => z[21]) = 0;
+        (b[3] => z[21]) = 0;
+        (b[4] => z[21]) = 0;
+        (b[5] => z[21]) = 0;
+        (b[6] => z[21]) = 0;
+        (b[7] => z[21]) = 0;
+        (b[8] => z[21]) = 0;
+        (b[9] => z[21]) = 0;
+        (b[10] => z[21]) = 0;
+        (b[11] => z[21]) = 0;
+        (b[12] => z[21]) = 0;
+        (b[13] => z[21]) = 0;
+        (b[14] => z[21]) = 0;
+        (b[15] => z[21]) = 0;
+        (b[16] => z[21]) = 0;
+        (b[17] => z[21]) = 0;
+        (a[0] => z[22]) = 0;
+        (a[1] => z[22]) = 0;
+        (a[2] => z[22]) = 0;
+        (a[3] => z[22]) = 0;
+        (a[4] => z[22]) = 0;
+        (a[5] => z[22]) = 0;
+        (a[6] => z[22]) = 0;
+        (a[7] => z[22]) = 0;
+        (a[8] => z[22]) = 0;
+        (a[9] => z[22]) = 0;
+        (a[10] => z[22]) = 0;
+        (a[11] => z[22]) = 0;
+        (a[12] => z[22]) = 0;
+        (a[13] => z[22]) = 0;
+        (a[14] => z[22]) = 0;
+        (a[15] => z[22]) = 0;
+        (a[16] => z[22]) = 0;
+        (a[17] => z[22]) = 0;
+        (a[18] => z[22]) = 0;
+        (a[19] => z[22]) = 0;
+        (b[0] => z[22]) = 0;
+        (b[1] => z[22]) = 0;
+        (b[2] => z[22]) = 0;
+        (b[3] => z[22]) = 0;
+        (b[4] => z[22]) = 0;
+        (b[5] => z[22]) = 0;
+        (b[6] => z[22]) = 0;
+        (b[7] => z[22]) = 0;
+        (b[8] => z[22]) = 0;
+        (b[9] => z[22]) = 0;
+        (b[10] => z[22]) = 0;
+        (b[11] => z[22]) = 0;
+        (b[12] => z[22]) = 0;
+        (b[13] => z[22]) = 0;
+        (b[14] => z[22]) = 0;
+        (b[15] => z[22]) = 0;
+        (b[16] => z[22]) = 0;
+        (b[17] => z[22]) = 0;
+        (a[0] => z[23]) = 0;
+        (a[1] => z[23]) = 0;
+        (a[2] => z[23]) = 0;
+        (a[3] => z[23]) = 0;
+        (a[4] => z[23]) = 0;
+        (a[5] => z[23]) = 0;
+        (a[6] => z[23]) = 0;
+        (a[7] => z[23]) = 0;
+        (a[8] => z[23]) = 0;
+        (a[9] => z[23]) = 0;
+        (a[10] => z[23]) = 0;
+        (a[11] => z[23]) = 0;
+        (a[12] => z[23]) = 0;
+        (a[13] => z[23]) = 0;
+        (a[14] => z[23]) = 0;
+        (a[15] => z[23]) = 0;
+        (a[16] => z[23]) = 0;
+        (a[17] => z[23]) = 0;
+        (a[18] => z[23]) = 0;
+        (a[19] => z[23]) = 0;
+        (b[0] => z[23]) = 0;
+        (b[1] => z[23]) = 0;
+        (b[2] => z[23]) = 0;
+        (b[3] => z[23]) = 0;
+        (b[4] => z[23]) = 0;
+        (b[5] => z[23]) = 0;
+        (b[6] => z[23]) = 0;
+        (b[7] => z[23]) = 0;
+        (b[8] => z[23]) = 0;
+        (b[9] => z[23]) = 0;
+        (b[10] => z[23]) = 0;
+        (b[11] => z[23]) = 0;
+        (b[12] => z[23]) = 0;
+        (b[13] => z[23]) = 0;
+        (b[14] => z[23]) = 0;
+        (b[15] => z[23]) = 0;
+        (b[16] => z[23]) = 0;
+        (b[17] => z[23]) = 0;
+        (a[0] => z[24]) = 0;
+        (a[1] => z[24]) = 0;
+        (a[2] => z[24]) = 0;
+        (a[3] => z[24]) = 0;
+        (a[4] => z[24]) = 0;
+        (a[5] => z[24]) = 0;
+        (a[6] => z[24]) = 0;
+        (a[7] => z[24]) = 0;
+        (a[8] => z[24]) = 0;
+        (a[9] => z[24]) = 0;
+        (a[10] => z[24]) = 0;
+        (a[11] => z[24]) = 0;
+        (a[12] => z[24]) = 0;
+        (a[13] => z[24]) = 0;
+        (a[14] => z[24]) = 0;
+        (a[15] => z[24]) = 0;
+        (a[16] => z[24]) = 0;
+        (a[17] => z[24]) = 0;
+        (a[18] => z[24]) = 0;
+        (a[19] => z[24]) = 0;
+        (b[0] => z[24]) = 0;
+        (b[1] => z[24]) = 0;
+        (b[2] => z[24]) = 0;
+        (b[3] => z[24]) = 0;
+        (b[4] => z[24]) = 0;
+        (b[5] => z[24]) = 0;
+        (b[6] => z[24]) = 0;
+        (b[7] => z[24]) = 0;
+        (b[8] => z[24]) = 0;
+        (b[9] => z[24]) = 0;
+        (b[10] => z[24]) = 0;
+        (b[11] => z[24]) = 0;
+        (b[12] => z[24]) = 0;
+        (b[13] => z[24]) = 0;
+        (b[14] => z[24]) = 0;
+        (b[15] => z[24]) = 0;
+        (b[16] => z[24]) = 0;
+        (b[17] => z[24]) = 0;
+        (a[0] => z[25]) = 0;
+        (a[1] => z[25]) = 0;
+        (a[2] => z[25]) = 0;
+        (a[3] => z[25]) = 0;
+        (a[4] => z[25]) = 0;
+        (a[5] => z[25]) = 0;
+        (a[6] => z[25]) = 0;
+        (a[7] => z[25]) = 0;
+        (a[8] => z[25]) = 0;
+        (a[9] => z[25]) = 0;
+        (a[10] => z[25]) = 0;
+        (a[11] => z[25]) = 0;
+        (a[12] => z[25]) = 0;
+        (a[13] => z[25]) = 0;
+        (a[14] => z[25]) = 0;
+        (a[15] => z[25]) = 0;
+        (a[16] => z[25]) = 0;
+        (a[17] => z[25]) = 0;
+        (a[18] => z[25]) = 0;
+        (a[19] => z[25]) = 0;
+        (b[0] => z[25]) = 0;
+        (b[1] => z[25]) = 0;
+        (b[2] => z[25]) = 0;
+        (b[3] => z[25]) = 0;
+        (b[4] => z[25]) = 0;
+        (b[5] => z[25]) = 0;
+        (b[6] => z[25]) = 0;
+        (b[7] => z[25]) = 0;
+        (b[8] => z[25]) = 0;
+        (b[9] => z[25]) = 0;
+        (b[10] => z[25]) = 0;
+        (b[11] => z[25]) = 0;
+        (b[12] => z[25]) = 0;
+        (b[13] => z[25]) = 0;
+        (b[14] => z[25]) = 0;
+        (b[15] => z[25]) = 0;
+        (b[16] => z[25]) = 0;
+        (b[17] => z[25]) = 0;
+        (a[0] => z[26]) = 0;
+        (a[1] => z[26]) = 0;
+        (a[2] => z[26]) = 0;
+        (a[3] => z[26]) = 0;
+        (a[4] => z[26]) = 0;
+        (a[5] => z[26]) = 0;
+        (a[6] => z[26]) = 0;
+        (a[7] => z[26]) = 0;
+        (a[8] => z[26]) = 0;
+        (a[9] => z[26]) = 0;
+        (a[10] => z[26]) = 0;
+        (a[11] => z[26]) = 0;
+        (a[12] => z[26]) = 0;
+        (a[13] => z[26]) = 0;
+        (a[14] => z[26]) = 0;
+        (a[15] => z[26]) = 0;
+        (a[16] => z[26]) = 0;
+        (a[17] => z[26]) = 0;
+        (a[18] => z[26]) = 0;
+        (a[19] => z[26]) = 0;
+        (b[0] => z[26]) = 0;
+        (b[1] => z[26]) = 0;
+        (b[2] => z[26]) = 0;
+        (b[3] => z[26]) = 0;
+        (b[4] => z[26]) = 0;
+        (b[5] => z[26]) = 0;
+        (b[6] => z[26]) = 0;
+        (b[7] => z[26]) = 0;
+        (b[8] => z[26]) = 0;
+        (b[9] => z[26]) = 0;
+        (b[10] => z[26]) = 0;
+        (b[11] => z[26]) = 0;
+        (b[12] => z[26]) = 0;
+        (b[13] => z[26]) = 0;
+        (b[14] => z[26]) = 0;
+        (b[15] => z[26]) = 0;
+        (b[16] => z[26]) = 0;
+        (b[17] => z[26]) = 0;
+        (a[0] => z[27]) = 0;
+        (a[1] => z[27]) = 0;
+        (a[2] => z[27]) = 0;
+        (a[3] => z[27]) = 0;
+        (a[4] => z[27]) = 0;
+        (a[5] => z[27]) = 0;
+        (a[6] => z[27]) = 0;
+        (a[7] => z[27]) = 0;
+        (a[8] => z[27]) = 0;
+        (a[9] => z[27]) = 0;
+        (a[10] => z[27]) = 0;
+        (a[11] => z[27]) = 0;
+        (a[12] => z[27]) = 0;
+        (a[13] => z[27]) = 0;
+        (a[14] => z[27]) = 0;
+        (a[15] => z[27]) = 0;
+        (a[16] => z[27]) = 0;
+        (a[17] => z[27]) = 0;
+        (a[18] => z[27]) = 0;
+        (a[19] => z[27]) = 0;
+        (b[0] => z[27]) = 0;
+        (b[1] => z[27]) = 0;
+        (b[2] => z[27]) = 0;
+        (b[3] => z[27]) = 0;
+        (b[4] => z[27]) = 0;
+        (b[5] => z[27]) = 0;
+        (b[6] => z[27]) = 0;
+        (b[7] => z[27]) = 0;
+        (b[8] => z[27]) = 0;
+        (b[9] => z[27]) = 0;
+        (b[10] => z[27]) = 0;
+        (b[11] => z[27]) = 0;
+        (b[12] => z[27]) = 0;
+        (b[13] => z[27]) = 0;
+        (b[14] => z[27]) = 0;
+        (b[15] => z[27]) = 0;
+        (b[16] => z[27]) = 0;
+        (b[17] => z[27]) = 0;
+        (a[0] => z[28]) = 0;
+        (a[1] => z[28]) = 0;
+        (a[2] => z[28]) = 0;
+        (a[3] => z[28]) = 0;
+        (a[4] => z[28]) = 0;
+        (a[5] => z[28]) = 0;
+        (a[6] => z[28]) = 0;
+        (a[7] => z[28]) = 0;
+        (a[8] => z[28]) = 0;
+        (a[9] => z[28]) = 0;
+        (a[10] => z[28]) = 0;
+        (a[11] => z[28]) = 0;
+        (a[12] => z[28]) = 0;
+        (a[13] => z[28]) = 0;
+        (a[14] => z[28]) = 0;
+        (a[15] => z[28]) = 0;
+        (a[16] => z[28]) = 0;
+        (a[17] => z[28]) = 0;
+        (a[18] => z[28]) = 0;
+        (a[19] => z[28]) = 0;
+        (b[0] => z[28]) = 0;
+        (b[1] => z[28]) = 0;
+        (b[2] => z[28]) = 0;
+        (b[3] => z[28]) = 0;
+        (b[4] => z[28]) = 0;
+        (b[5] => z[28]) = 0;
+        (b[6] => z[28]) = 0;
+        (b[7] => z[28]) = 0;
+        (b[8] => z[28]) = 0;
+        (b[9] => z[28]) = 0;
+        (b[10] => z[28]) = 0;
+        (b[11] => z[28]) = 0;
+        (b[12] => z[28]) = 0;
+        (b[13] => z[28]) = 0;
+        (b[14] => z[28]) = 0;
+        (b[15] => z[28]) = 0;
+        (b[16] => z[28]) = 0;
+        (b[17] => z[28]) = 0;
+        (a[0] => z[29]) = 0;
+        (a[1] => z[29]) = 0;
+        (a[2] => z[29]) = 0;
+        (a[3] => z[29]) = 0;
+        (a[4] => z[29]) = 0;
+        (a[5] => z[29]) = 0;
+        (a[6] => z[29]) = 0;
+        (a[7] => z[29]) = 0;
+        (a[8] => z[29]) = 0;
+        (a[9] => z[29]) = 0;
+        (a[10] => z[29]) = 0;
+        (a[11] => z[29]) = 0;
+        (a[12] => z[29]) = 0;
+        (a[13] => z[29]) = 0;
+        (a[14] => z[29]) = 0;
+        (a[15] => z[29]) = 0;
+        (a[16] => z[29]) = 0;
+        (a[17] => z[29]) = 0;
+        (a[18] => z[29]) = 0;
+        (a[19] => z[29]) = 0;
+        (b[0] => z[29]) = 0;
+        (b[1] => z[29]) = 0;
+        (b[2] => z[29]) = 0;
+        (b[3] => z[29]) = 0;
+        (b[4] => z[29]) = 0;
+        (b[5] => z[29]) = 0;
+        (b[6] => z[29]) = 0;
+        (b[7] => z[29]) = 0;
+        (b[8] => z[29]) = 0;
+        (b[9] => z[29]) = 0;
+        (b[10] => z[29]) = 0;
+        (b[11] => z[29]) = 0;
+        (b[12] => z[29]) = 0;
+        (b[13] => z[29]) = 0;
+        (b[14] => z[29]) = 0;
+        (b[15] => z[29]) = 0;
+        (b[16] => z[29]) = 0;
+        (b[17] => z[29]) = 0;
+        (a[0] => z[30]) = 0;
+        (a[1] => z[30]) = 0;
+        (a[2] => z[30]) = 0;
+        (a[3] => z[30]) = 0;
+        (a[4] => z[30]) = 0;
+        (a[5] => z[30]) = 0;
+        (a[6] => z[30]) = 0;
+        (a[7] => z[30]) = 0;
+        (a[8] => z[30]) = 0;
+        (a[9] => z[30]) = 0;
+        (a[10] => z[30]) = 0;
+        (a[11] => z[30]) = 0;
+        (a[12] => z[30]) = 0;
+        (a[13] => z[30]) = 0;
+        (a[14] => z[30]) = 0;
+        (a[15] => z[30]) = 0;
+        (a[16] => z[30]) = 0;
+        (a[17] => z[30]) = 0;
+        (a[18] => z[30]) = 0;
+        (a[19] => z[30]) = 0;
+        (b[0] => z[30]) = 0;
+        (b[1] => z[30]) = 0;
+        (b[2] => z[30]) = 0;
+        (b[3] => z[30]) = 0;
+        (b[4] => z[30]) = 0;
+        (b[5] => z[30]) = 0;
+        (b[6] => z[30]) = 0;
+        (b[7] => z[30]) = 0;
+        (b[8] => z[30]) = 0;
+        (b[9] => z[30]) = 0;
+        (b[10] => z[30]) = 0;
+        (b[11] => z[30]) = 0;
+        (b[12] => z[30]) = 0;
+        (b[13] => z[30]) = 0;
+        (b[14] => z[30]) = 0;
+        (b[15] => z[30]) = 0;
+        (b[16] => z[30]) = 0;
+        (b[17] => z[30]) = 0;
+        (a[0] => z[31]) = 0;
+        (a[1] => z[31]) = 0;
+        (a[2] => z[31]) = 0;
+        (a[3] => z[31]) = 0;
+        (a[4] => z[31]) = 0;
+        (a[5] => z[31]) = 0;
+        (a[6] => z[31]) = 0;
+        (a[7] => z[31]) = 0;
+        (a[8] => z[31]) = 0;
+        (a[9] => z[31]) = 0;
+        (a[10] => z[31]) = 0;
+        (a[11] => z[31]) = 0;
+        (a[12] => z[31]) = 0;
+        (a[13] => z[31]) = 0;
+        (a[14] => z[31]) = 0;
+        (a[15] => z[31]) = 0;
+        (a[16] => z[31]) = 0;
+        (a[17] => z[31]) = 0;
+        (a[18] => z[31]) = 0;
+        (a[19] => z[31]) = 0;
+        (b[0] => z[31]) = 0;
+        (b[1] => z[31]) = 0;
+        (b[2] => z[31]) = 0;
+        (b[3] => z[31]) = 0;
+        (b[4] => z[31]) = 0;
+        (b[5] => z[31]) = 0;
+        (b[6] => z[31]) = 0;
+        (b[7] => z[31]) = 0;
+        (b[8] => z[31]) = 0;
+        (b[9] => z[31]) = 0;
+        (b[10] => z[31]) = 0;
+        (b[11] => z[31]) = 0;
+        (b[12] => z[31]) = 0;
+        (b[13] => z[31]) = 0;
+        (b[14] => z[31]) = 0;
+        (b[15] => z[31]) = 0;
+        (b[16] => z[31]) = 0;
+        (b[17] => z[31]) = 0;
+        (a[0] => z[32]) = 0;
+        (a[1] => z[32]) = 0;
+        (a[2] => z[32]) = 0;
+        (a[3] => z[32]) = 0;
+        (a[4] => z[32]) = 0;
+        (a[5] => z[32]) = 0;
+        (a[6] => z[32]) = 0;
+        (a[7] => z[32]) = 0;
+        (a[8] => z[32]) = 0;
+        (a[9] => z[32]) = 0;
+        (a[10] => z[32]) = 0;
+        (a[11] => z[32]) = 0;
+        (a[12] => z[32]) = 0;
+        (a[13] => z[32]) = 0;
+        (a[14] => z[32]) = 0;
+        (a[15] => z[32]) = 0;
+        (a[16] => z[32]) = 0;
+        (a[17] => z[32]) = 0;
+        (a[18] => z[32]) = 0;
+        (a[19] => z[32]) = 0;
+        (b[0] => z[32]) = 0;
+        (b[1] => z[32]) = 0;
+        (b[2] => z[32]) = 0;
+        (b[3] => z[32]) = 0;
+        (b[4] => z[32]) = 0;
+        (b[5] => z[32]) = 0;
+        (b[6] => z[32]) = 0;
+        (b[7] => z[32]) = 0;
+        (b[8] => z[32]) = 0;
+        (b[9] => z[32]) = 0;
+        (b[10] => z[32]) = 0;
+        (b[11] => z[32]) = 0;
+        (b[12] => z[32]) = 0;
+        (b[13] => z[32]) = 0;
+        (b[14] => z[32]) = 0;
+        (b[15] => z[32]) = 0;
+        (b[16] => z[32]) = 0;
+        (b[17] => z[32]) = 0;
+        (a[0] => z[33]) = 0;
+        (a[1] => z[33]) = 0;
+        (a[2] => z[33]) = 0;
+        (a[3] => z[33]) = 0;
+        (a[4] => z[33]) = 0;
+        (a[5] => z[33]) = 0;
+        (a[6] => z[33]) = 0;
+        (a[7] => z[33]) = 0;
+        (a[8] => z[33]) = 0;
+        (a[9] => z[33]) = 0;
+        (a[10] => z[33]) = 0;
+        (a[11] => z[33]) = 0;
+        (a[12] => z[33]) = 0;
+        (a[13] => z[33]) = 0;
+        (a[14] => z[33]) = 0;
+        (a[15] => z[33]) = 0;
+        (a[16] => z[33]) = 0;
+        (a[17] => z[33]) = 0;
+        (a[18] => z[33]) = 0;
+        (a[19] => z[33]) = 0;
+        (b[0] => z[33]) = 0;
+        (b[1] => z[33]) = 0;
+        (b[2] => z[33]) = 0;
+        (b[3] => z[33]) = 0;
+        (b[4] => z[33]) = 0;
+        (b[5] => z[33]) = 0;
+        (b[6] => z[33]) = 0;
+        (b[7] => z[33]) = 0;
+        (b[8] => z[33]) = 0;
+        (b[9] => z[33]) = 0;
+        (b[10] => z[33]) = 0;
+        (b[11] => z[33]) = 0;
+        (b[12] => z[33]) = 0;
+        (b[13] => z[33]) = 0;
+        (b[14] => z[33]) = 0;
+        (b[15] => z[33]) = 0;
+        (b[16] => z[33]) = 0;
+        (b[17] => z[33]) = 0;
+        (a[0] => z[34]) = 0;
+        (a[1] => z[34]) = 0;
+        (a[2] => z[34]) = 0;
+        (a[3] => z[34]) = 0;
+        (a[4] => z[34]) = 0;
+        (a[5] => z[34]) = 0;
+        (a[6] => z[34]) = 0;
+        (a[7] => z[34]) = 0;
+        (a[8] => z[34]) = 0;
+        (a[9] => z[34]) = 0;
+        (a[10] => z[34]) = 0;
+        (a[11] => z[34]) = 0;
+        (a[12] => z[34]) = 0;
+        (a[13] => z[34]) = 0;
+        (a[14] => z[34]) = 0;
+        (a[15] => z[34]) = 0;
+        (a[16] => z[34]) = 0;
+        (a[17] => z[34]) = 0;
+        (a[18] => z[34]) = 0;
+        (a[19] => z[34]) = 0;
+        (b[0] => z[34]) = 0;
+        (b[1] => z[34]) = 0;
+        (b[2] => z[34]) = 0;
+        (b[3] => z[34]) = 0;
+        (b[4] => z[34]) = 0;
+        (b[5] => z[34]) = 0;
+        (b[6] => z[34]) = 0;
+        (b[7] => z[34]) = 0;
+        (b[8] => z[34]) = 0;
+        (b[9] => z[34]) = 0;
+        (b[10] => z[34]) = 0;
+        (b[11] => z[34]) = 0;
+        (b[12] => z[34]) = 0;
+        (b[13] => z[34]) = 0;
+        (b[14] => z[34]) = 0;
+        (b[15] => z[34]) = 0;
+        (b[16] => z[34]) = 0;
+        (b[17] => z[34]) = 0;
+        (a[0] => z[35]) = 0;
+        (a[1] => z[35]) = 0;
+        (a[2] => z[35]) = 0;
+        (a[3] => z[35]) = 0;
+        (a[4] => z[35]) = 0;
+        (a[5] => z[35]) = 0;
+        (a[6] => z[35]) = 0;
+        (a[7] => z[35]) = 0;
+        (a[8] => z[35]) = 0;
+        (a[9] => z[35]) = 0;
+        (a[10] => z[35]) = 0;
+        (a[11] => z[35]) = 0;
+        (a[12] => z[35]) = 0;
+        (a[13] => z[35]) = 0;
+        (a[14] => z[35]) = 0;
+        (a[15] => z[35]) = 0;
+        (a[16] => z[35]) = 0;
+        (a[17] => z[35]) = 0;
+        (a[18] => z[35]) = 0;
+        (a[19] => z[35]) = 0;
+        (b[0] => z[35]) = 0;
+        (b[1] => z[35]) = 0;
+        (b[2] => z[35]) = 0;
+        (b[3] => z[35]) = 0;
+        (b[4] => z[35]) = 0;
+        (b[5] => z[35]) = 0;
+        (b[6] => z[35]) = 0;
+        (b[7] => z[35]) = 0;
+        (b[8] => z[35]) = 0;
+        (b[9] => z[35]) = 0;
+        (b[10] => z[35]) = 0;
+        (b[11] => z[35]) = 0;
+        (b[12] => z[35]) = 0;
+        (b[13] => z[35]) = 0;
+        (b[14] => z[35]) = 0;
+        (b[15] => z[35]) = 0;
+        (b[16] => z[35]) = 0;
+        (b[17] => z[35]) = 0;
+        (a[0] => z[36]) = 0;
+        (a[1] => z[36]) = 0;
+        (a[2] => z[36]) = 0;
+        (a[3] => z[36]) = 0;
+        (a[4] => z[36]) = 0;
+        (a[5] => z[36]) = 0;
+        (a[6] => z[36]) = 0;
+        (a[7] => z[36]) = 0;
+        (a[8] => z[36]) = 0;
+        (a[9] => z[36]) = 0;
+        (a[10] => z[36]) = 0;
+        (a[11] => z[36]) = 0;
+        (a[12] => z[36]) = 0;
+        (a[13] => z[36]) = 0;
+        (a[14] => z[36]) = 0;
+        (a[15] => z[36]) = 0;
+        (a[16] => z[36]) = 0;
+        (a[17] => z[36]) = 0;
+        (a[18] => z[36]) = 0;
+        (a[19] => z[36]) = 0;
+        (b[0] => z[36]) = 0;
+        (b[1] => z[36]) = 0;
+        (b[2] => z[36]) = 0;
+        (b[3] => z[36]) = 0;
+        (b[4] => z[36]) = 0;
+        (b[5] => z[36]) = 0;
+        (b[6] => z[36]) = 0;
+        (b[7] => z[36]) = 0;
+        (b[8] => z[36]) = 0;
+        (b[9] => z[36]) = 0;
+        (b[10] => z[36]) = 0;
+        (b[11] => z[36]) = 0;
+        (b[12] => z[36]) = 0;
+        (b[13] => z[36]) = 0;
+        (b[14] => z[36]) = 0;
+        (b[15] => z[36]) = 0;
+        (b[16] => z[36]) = 0;
+        (b[17] => z[36]) = 0;
+        (a[0] => z[37]) = 0;
+        (a[1] => z[37]) = 0;
+        (a[2] => z[37]) = 0;
+        (a[3] => z[37]) = 0;
+        (a[4] => z[37]) = 0;
+        (a[5] => z[37]) = 0;
+        (a[6] => z[37]) = 0;
+        (a[7] => z[37]) = 0;
+        (a[8] => z[37]) = 0;
+        (a[9] => z[37]) = 0;
+        (a[10] => z[37]) = 0;
+        (a[11] => z[37]) = 0;
+        (a[12] => z[37]) = 0;
+        (a[13] => z[37]) = 0;
+        (a[14] => z[37]) = 0;
+        (a[15] => z[37]) = 0;
+        (a[16] => z[37]) = 0;
+        (a[17] => z[37]) = 0;
+        (a[18] => z[37]) = 0;
+        (a[19] => z[37]) = 0;
+        (b[0] => z[37]) = 0;
+        (b[1] => z[37]) = 0;
+        (b[2] => z[37]) = 0;
+        (b[3] => z[37]) = 0;
+        (b[4] => z[37]) = 0;
+        (b[5] => z[37]) = 0;
+        (b[6] => z[37]) = 0;
+        (b[7] => z[37]) = 0;
+        (b[8] => z[37]) = 0;
+        (b[9] => z[37]) = 0;
+        (b[10] => z[37]) = 0;
+        (b[11] => z[37]) = 0;
+        (b[12] => z[37]) = 0;
+        (b[13] => z[37]) = 0;
+        (b[14] => z[37]) = 0;
+        (b[15] => z[37]) = 0;
+        (b[16] => z[37]) = 0;
+        (b[17] => z[37]) = 0;
+		(subtract => z[0]) = 0;
+		(subtract => z[1]) = 0;
+		(subtract => z[2]) = 0;
+		(subtract => z[3]) = 0;
+		(subtract => z[4]) = 0;
+		(subtract => z[5]) = 0;
+		(subtract => z[6]) = 0;
+		(subtract => z[7]) = 0;
+		(subtract => z[8]) = 0;
+		(subtract => z[9]) = 0;
+		(subtract => z[10]) = 0;
+		(subtract => z[11]) = 0;
+		(subtract => z[12]) = 0;
+		(subtract => z[13]) = 0;
+		(subtract => z[14]) = 0;
+		(subtract => z[15]) = 0;
+		(subtract => z[16]) = 0;
+		(subtract => z[17]) = 0;
+		(subtract => z[18]) = 0;
+		(subtract => z[19]) = 0;
+		(subtract => z[20]) = 0;
+		(subtract => z[21]) = 0;
+		(subtract => z[22]) = 0;
+		(subtract => z[23]) = 0;
+		(subtract => z[24]) = 0;
+		(subtract => z[25]) = 0;
+		(subtract => z[26]) = 0;
+		(subtract => z[27]) = 0;
+		(subtract => z[28]) = 0;
+		(subtract => z[29]) = 0;
+		(subtract => z[30]) = 0;
+		(subtract => z[31]) = 0;
+		(subtract => z[32]) = 0;
+		(subtract => z[33]) = 0;
+		(subtract => z[34]) = 0;
+		(subtract => z[35]) = 0;
+		(subtract => z[36]) = 0;
+		(subtract => z[37]) = 0;
+		(acc_fir[0] => z[0]) = 0;
+        (acc_fir[1] => z[0]) = 0;
+        (acc_fir[2] => z[0]) = 0;
+        (acc_fir[3] => z[0]) = 0;
+        (acc_fir[4] => z[0]) = 0;
+		(acc_fir[5] => z[0]) = 0;
+		(acc_fir[0] => z[1]) = 0;
+        (acc_fir[1] => z[1]) = 0;
+        (acc_fir[2] => z[1]) = 0;
+        (acc_fir[3] => z[1]) = 0;
+        (acc_fir[4] => z[1]) = 0;
+		(acc_fir[5] => z[1]) = 0;
+		(acc_fir[0] => z[2]) = 0;
+        (acc_fir[1] => z[2]) = 0;
+        (acc_fir[2] => z[2]) = 0;
+        (acc_fir[3] => z[2]) = 0;
+        (acc_fir[4] => z[2]) = 0;
+		(acc_fir[5] => z[2]) = 0;
+		(acc_fir[0] => z[3]) = 0;
+        (acc_fir[1] => z[3]) = 0;
+        (acc_fir[2] => z[3]) = 0;
+        (acc_fir[3] => z[3]) = 0;
+        (acc_fir[4] => z[3]) = 0;
+		(acc_fir[5] => z[3]) = 0;
+		(acc_fir[0] => z[4]) = 0;
+        (acc_fir[1] => z[4]) = 0;
+        (acc_fir[2] => z[4]) = 0;
+        (acc_fir[3] => z[4]) = 0;
+        (acc_fir[4] => z[4]) = 0;
+		(acc_fir[5] => z[4]) = 0;
+		(acc_fir[0] => z[5]) = 0;
+        (acc_fir[1] => z[5]) = 0;
+        (acc_fir[2] => z[5]) = 0;
+        (acc_fir[3] => z[5]) = 0;
+        (acc_fir[4] => z[5]) = 0;
+		(acc_fir[5] => z[5]) = 0;
+		(acc_fir[0] => z[6]) = 0;
+        (acc_fir[1] => z[6]) = 0;
+        (acc_fir[2] => z[6]) = 0;
+        (acc_fir[3] => z[6]) = 0;
+        (acc_fir[4] => z[6]) = 0;
+		(acc_fir[5] => z[6]) = 0;
+		(acc_fir[0] => z[7]) = 0;
+        (acc_fir[1] => z[7]) = 0;
+        (acc_fir[2] => z[7]) = 0;
+        (acc_fir[3] => z[7]) = 0;
+        (acc_fir[4] => z[7]) = 0;
+		(acc_fir[5] => z[7]) = 0;
+		(acc_fir[0] => z[8]) = 0;
+        (acc_fir[1] => z[8]) = 0;
+        (acc_fir[2] => z[8]) = 0;
+        (acc_fir[3] => z[8]) = 0;
+        (acc_fir[4] => z[8]) = 0;
+		(acc_fir[5] => z[8]) = 0;
+		(acc_fir[0] => z[9]) = 0;
+        (acc_fir[1] => z[9]) = 0;
+        (acc_fir[2] => z[9]) = 0;
+        (acc_fir[3] => z[9]) = 0;
+        (acc_fir[4] => z[9]) = 0;
+		(acc_fir[5] => z[9]) = 0;
+		(acc_fir[0] => z[10]) = 0;
+        (acc_fir[1] => z[10]) = 0;
+        (acc_fir[2] => z[10]) = 0;
+        (acc_fir[3] => z[10]) = 0;
+        (acc_fir[4] => z[10]) = 0;
+		(acc_fir[5] => z[10]) = 0;
+		(acc_fir[0] => z[11]) = 0;
+        (acc_fir[1] => z[11]) = 0;
+        (acc_fir[2] => z[11]) = 0;
+        (acc_fir[3] => z[11]) = 0;
+        (acc_fir[4] => z[11]) = 0;
+		(acc_fir[5] => z[11]) = 0;
+		(acc_fir[0] => z[12]) = 0;
+        (acc_fir[1] => z[12]) = 0;
+        (acc_fir[2] => z[12]) = 0;
+        (acc_fir[3] => z[12]) = 0;
+        (acc_fir[4] => z[12]) = 0;
+		(acc_fir[5] => z[12]) = 0;
+		(acc_fir[0] => z[13]) = 0;
+        (acc_fir[1] => z[13]) = 0;
+        (acc_fir[2] => z[13]) = 0;
+        (acc_fir[3] => z[13]) = 0;
+        (acc_fir[4] => z[13]) = 0;
+		(acc_fir[5] => z[13]) = 0;
+		(acc_fir[0] => z[14]) = 0;
+        (acc_fir[1] => z[14]) = 0;
+        (acc_fir[2] => z[14]) = 0;
+        (acc_fir[3] => z[14]) = 0;
+        (acc_fir[4] => z[14]) = 0;
+		(acc_fir[5] => z[14]) = 0;
+		(acc_fir[0] => z[15]) = 0;
+        (acc_fir[1] => z[15]) = 0;
+        (acc_fir[2] => z[15]) = 0;
+        (acc_fir[3] => z[15]) = 0;
+        (acc_fir[4] => z[15]) = 0;
+		(acc_fir[5] => z[15]) = 0;
+		(acc_fir[0] => z[16]) = 0;
+        (acc_fir[1] => z[16]) = 0;
+        (acc_fir[2] => z[16]) = 0;
+        (acc_fir[3] => z[16]) = 0;
+        (acc_fir[4] => z[16]) = 0;
+		(acc_fir[5] => z[16]) = 0;
+		(acc_fir[0] => z[17]) = 0;
+        (acc_fir[1] => z[17]) = 0;
+        (acc_fir[2] => z[17]) = 0;
+        (acc_fir[3] => z[17]) = 0;
+        (acc_fir[4] => z[17]) = 0;
+		(acc_fir[5] => z[17]) = 0;
+		(acc_fir[0] => z[18]) = 0;
+        (acc_fir[1] => z[18]) = 0;
+        (acc_fir[2] => z[18]) = 0;
+        (acc_fir[3] => z[18]) = 0;
+        (acc_fir[4] => z[18]) = 0;
+		(acc_fir[5] => z[18]) = 0;
+		(acc_fir[0] => z[19]) = 0;
+        (acc_fir[1] => z[19]) = 0;
+        (acc_fir[2] => z[19]) = 0;
+        (acc_fir[3] => z[19]) = 0;
+        (acc_fir[4] => z[19]) = 0;
+		(acc_fir[5] => z[19]) = 0;
+		(acc_fir[0] => z[20]) = 0;
+        (acc_fir[1] => z[20]) = 0;
+        (acc_fir[2] => z[20]) = 0;
+        (acc_fir[3] => z[20]) = 0;
+        (acc_fir[4] => z[20]) = 0;
+		(acc_fir[5] => z[20]) = 0;
+		(acc_fir[0] => z[21]) = 0;
+        (acc_fir[1] => z[21]) = 0;
+        (acc_fir[2] => z[21]) = 0;
+        (acc_fir[3] => z[21]) = 0;
+        (acc_fir[4] => z[21]) = 0;
+		(acc_fir[5] => z[21]) = 0;
+		(acc_fir[0] => z[22]) = 0;
+        (acc_fir[1] => z[22]) = 0;
+        (acc_fir[2] => z[22]) = 0;
+        (acc_fir[3] => z[22]) = 0;
+        (acc_fir[4] => z[22]) = 0;
+		(acc_fir[5] => z[22]) = 0;
+		(acc_fir[0] => z[23]) = 0;
+        (acc_fir[1] => z[23]) = 0;
+        (acc_fir[2] => z[23]) = 0;
+        (acc_fir[3] => z[23]) = 0;
+        (acc_fir[4] => z[23]) = 0;
+		(acc_fir[5] => z[23]) = 0;
+		(acc_fir[0] => z[24]) = 0;
+        (acc_fir[1] => z[24]) = 0;
+        (acc_fir[2] => z[24]) = 0;
+        (acc_fir[3] => z[24]) = 0;
+        (acc_fir[4] => z[24]) = 0;
+		(acc_fir[5] => z[24]) = 0;
+		(acc_fir[0] => z[25]) = 0;
+        (acc_fir[1] => z[25]) = 0;
+        (acc_fir[2] => z[25]) = 0;
+        (acc_fir[3] => z[25]) = 0;
+        (acc_fir[4] => z[25]) = 0;
+		(acc_fir[5] => z[25]) = 0;
+		(acc_fir[0] => z[26]) = 0;
+        (acc_fir[1] => z[26]) = 0;
+        (acc_fir[2] => z[26]) = 0;
+        (acc_fir[3] => z[26]) = 0;
+        (acc_fir[4] => z[26]) = 0;
+		(acc_fir[5] => z[26]) = 0;
+		(acc_fir[0] => z[27]) = 0;
+        (acc_fir[1] => z[27]) = 0;
+        (acc_fir[2] => z[27]) = 0;
+        (acc_fir[3] => z[27]) = 0;
+        (acc_fir[4] => z[27]) = 0;
+		(acc_fir[5] => z[27]) = 0;
+		(acc_fir[0] => z[28]) = 0;
+        (acc_fir[1] => z[28]) = 0;
+        (acc_fir[2] => z[28]) = 0;
+        (acc_fir[3] => z[28]) = 0;
+        (acc_fir[4] => z[28]) = 0;
+		(acc_fir[5] => z[28]) = 0;
+		(acc_fir[0] => z[29]) = 0;
+        (acc_fir[1] => z[29]) = 0;
+        (acc_fir[2] => z[29]) = 0;
+        (acc_fir[3] => z[29]) = 0;
+        (acc_fir[4] => z[29]) = 0;
+		(acc_fir[5] => z[29]) = 0;
+		(acc_fir[0] => z[30]) = 0;
+        (acc_fir[1] => z[30]) = 0;
+        (acc_fir[2] => z[30]) = 0;
+        (acc_fir[3] => z[30]) = 0;
+        (acc_fir[4] => z[30]) = 0;
+		(acc_fir[5] => z[30]) = 0;
+		(acc_fir[0] => z[31]) = 0;
+        (acc_fir[1] => z[31]) = 0;
+        (acc_fir[2] => z[31]) = 0;
+        (acc_fir[3] => z[31]) = 0;
+        (acc_fir[4] => z[31]) = 0;
+		(acc_fir[5] => z[31]) = 0;
+		(acc_fir[0] => z[32]) = 0;
+        (acc_fir[1] => z[32]) = 0;
+        (acc_fir[2] => z[32]) = 0;
+        (acc_fir[3] => z[32]) = 0;
+        (acc_fir[4] => z[32]) = 0;
+		(acc_fir[5] => z[32]) = 0;
+		(acc_fir[0] => z[33]) = 0;
+        (acc_fir[1] => z[33]) = 0;
+        (acc_fir[2] => z[33]) = 0;
+        (acc_fir[3] => z[33]) = 0;
+        (acc_fir[4] => z[33]) = 0;
+		(acc_fir[5] => z[33]) = 0;
+		(acc_fir[0] => z[34]) = 0;
+        (acc_fir[1] => z[34]) = 0;
+        (acc_fir[2] => z[34]) = 0;
+        (acc_fir[3] => z[34]) = 0;
+        (acc_fir[4] => z[34]) = 0;
+		(acc_fir[5] => z[34]) = 0;
+		(acc_fir[0] => z[35]) = 0;
+        (acc_fir[1] => z[35]) = 0;
+        (acc_fir[2] => z[35]) = 0;
+        (acc_fir[3] => z[35]) = 0;
+        (acc_fir[4] => z[35]) = 0;
+		(acc_fir[5] => z[35]) = 0;
+		(acc_fir[0] => z[36]) = 0;
+        (acc_fir[1] => z[36]) = 0;
+        (acc_fir[2] => z[36]) = 0;
+        (acc_fir[3] => z[36]) = 0;
+        (acc_fir[4] => z[36]) = 0;
+		(acc_fir[5] => z[36]) = 0;
+		(acc_fir[0] => z[37]) = 0;
+        (acc_fir[1] => z[37]) = 0;
+        (acc_fir[2] => z[37]) = 0;
+        (acc_fir[3] => z[37]) = 0;
+        (acc_fir[4] => z[37]) = 0;
+		(acc_fir[5] => z[37]) = 0;
+	endspecify
+`endif
+	
 endmodule
 
 module QL_DSP2_MULTADD_REGIN (
@@ -468,6 +3700,7 @@
     ) dsp (
         .a(a),
         .b(b),
+        .dly_b(),
         .z(z),
 
         .f_mode(f_mode),
@@ -489,6 +3722,20 @@
         .subtract(subtract),
         .register_inputs(register_inputs)   // registered inputs
     );
+
+`ifdef SDF_SIM	
+	specify
+		(posedge clk => (z +: a)) = 0;
+		(posedge clk => (z +: b)) = 0;
+		$setuphold(posedge clk, a, 0, 0);
+		$setuphold(posedge clk, b, 0, 0);
+		$setuphold(posedge clk, feedback, 0, 0);
+		$setuphold(posedge clk, load_acc, 0, 0);
+		$setuphold(posedge clk, subtract, 0, 0);
+		$setuphold(posedge clk, acc_fir, 0, 0);
+	endspecify
+`endif
+	
 endmodule
 
 module QL_DSP2_MULTADD_REGOUT (
@@ -527,6 +3774,7 @@
     ) dsp (
         .a(a),
         .b(b),
+        .dly_b(),
         .z(z),
 
         .f_mode(f_mode),
@@ -548,6 +3796,20 @@
         .subtract(subtract),
         .register_inputs(register_inputs)   // unregistered inputs
     );
+
+`ifdef SDF_SIM	
+	specify
+		(posedge clk => (z +: a)) = 0;
+		(posedge clk => (z +: b)) = 0;
+		$setuphold(posedge clk, a, 0, 0);
+		$setuphold(posedge clk, b, 0, 0);
+		$setuphold(posedge clk, feedback, 0, 0);
+		$setuphold(posedge clk, load_acc, 0, 0);
+		$setuphold(posedge clk, subtract, 0, 0);
+		$setuphold(posedge clk, acc_fir, 0, 0);
+	endspecify
+`endif
+
 endmodule
 
 module QL_DSP2_MULTADD_REGIN_REGOUT (
@@ -586,6 +3848,7 @@
     ) dsp (
         .a(a),
         .b(b),
+        .dly_b(),
         .z(z),
 
         .f_mode(f_mode),
@@ -607,6 +3870,20 @@
         .subtract(subtract),
         .register_inputs(register_inputs)   // registered inputs
     );
+
+`ifdef SDF_SIM	
+	specify
+		(posedge clk => (z +: a)) = 0;
+		(posedge clk => (z +: b)) = 0;
+		$setuphold(posedge clk, a, 0, 0);
+		$setuphold(posedge clk, b, 0, 0);
+		$setuphold(posedge clk, feedback, 0, 0);
+		$setuphold(posedge clk, load_acc, 0, 0);
+		$setuphold(posedge clk, subtract, 0, 0);
+		$setuphold(posedge clk, acc_fir, 0, 0);
+	endspecify
+`endif
+
 endmodule
 
 module QL_DSP2_MULTACC (
@@ -644,7 +3921,9 @@
     ) dsp (
         .a(a),
         .b(b),
+        .acc_fir(6'b0),
         .z(z),
+        .dly_b(),
 
         .f_mode(f_mode),
 
@@ -664,6 +3943,19 @@
         .subtract(subtract),
         .register_inputs(register_inputs)   // unregistered inputs
     );
+
+`ifdef SDF_SIM	
+	specify
+		(posedge clk => (z +: a)) = 0;
+		(posedge clk => (z +: b)) = 0;
+		$setuphold(posedge clk, a, 0, 0);
+		$setuphold(posedge clk, b, 0, 0);
+		$setuphold(posedge clk, feedback, 0, 0);
+		$setuphold(posedge clk, load_acc, 0, 0);
+		$setuphold(posedge clk, subtract, 0, 0);
+	endspecify
+`endif
+	
 endmodule
 
 module QL_DSP2_MULTACC_REGIN (
@@ -701,7 +3993,9 @@
     ) dsp (
         .a(a),
         .b(b),
+        .acc_fir(6'b0),
         .z(z),
+        .dly_b(),
 
         .f_mode(f_mode),
 
@@ -721,6 +4015,19 @@
         .subtract(subtract),
         .register_inputs(register_inputs)   // registered inputs
     );
+
+`ifdef SDF_SIM	
+	specify
+		(posedge clk => (z +: a)) = 0;
+		(posedge clk => (z +: b)) = 0;
+		$setuphold(posedge clk, a, 0, 0);
+		$setuphold(posedge clk, b, 0, 0);
+		$setuphold(posedge clk, feedback, 0, 0);
+		$setuphold(posedge clk, load_acc, 0, 0);
+		$setuphold(posedge clk, subtract, 0, 0);
+	endspecify
+`endif
+	
 endmodule
 
 module QL_DSP2_MULTACC_REGOUT (
@@ -758,7 +4065,9 @@
     ) dsp (
         .a(a),
         .b(b),
+        .acc_fir(6'b0),
         .z(z),
+        .dly_b(),
 
         .f_mode(f_mode),
 
@@ -778,6 +4087,19 @@
         .subtract(subtract),
         .register_inputs(register_inputs)   // unregistered inputs
     );
+
+`ifdef SDF_SIM
+	specify
+		(posedge clk => (z +: a)) = 0;
+		(posedge clk => (z +: b)) = 0;
+		$setuphold(posedge clk, a, 0, 0);
+		$setuphold(posedge clk, b, 0, 0);
+		$setuphold(posedge clk, feedback, 0, 0);
+		$setuphold(posedge clk, load_acc, 0, 0);
+		$setuphold(posedge clk, subtract, 0, 0);
+	endspecify
+`endif
+	
 endmodule
 
 module QL_DSP2_MULTACC_REGIN_REGOUT (
@@ -815,7 +4137,9 @@
     ) dsp (
         .a(a),
         .b(b),
+        .acc_fir(6'b0),
         .z(z),
+        .dly_b(),
 
         .f_mode(f_mode),
 
@@ -835,6 +4159,19 @@
         .subtract(subtract),
         .register_inputs(register_inputs)   // registered inputs
     );
+
+`ifdef SDF_SIM	
+	specify
+		(posedge clk => (z +: a)) = 0;
+		(posedge clk => (z +: b)) = 0;
+		$setuphold(posedge clk, a, 0, 0);
+		$setuphold(posedge clk, b, 0, 0);
+		$setuphold(posedge clk, feedback, 0, 0);
+		$setuphold(posedge clk, load_acc, 0, 0);
+		$setuphold(posedge clk, subtract, 0, 0);
+	endspecify
+`endif
+	
 endmodule
 
 module dsp_t1_20x18x64_cfg_ports (
@@ -994,10 +4331,7 @@
 
 // FIXME: The version of Icarus Verilog from Conda seems not to recognize the
 // $error macro. Disable this sanity check for now because of that.
-`ifndef __ICARUS__
-    if (NBITS_ACC < NBITS_A + NBITS_B)
-        $error("NBITS_ACC must be > NBITS_A + NBITS_B");
-`endif
+
 
     // Input registers
     reg  [NBITS_A-1:0]  r_a;
@@ -2224,10 +5558,6 @@
 
 // FIXME: The version of Icarus Verilog from Conda seems not to recognize the
 // $error macro. Disable this sanity check for now because of that.
-`ifndef __ICARUS__
-    if (NBITS_ACC < NBITS_A + NBITS_B)
-        $error("NBITS_ACC must be > NBITS_A + NBITS_B");
-`endif
 
     // Input registers
     reg  [NBITS_A-1:0]  r_a;
diff --git a/ql-qlf-plugin/qlf_k6n10f/primitives_sim.v b/ql-qlf-plugin/qlf_k6n10f/primitives_sim.v
new file mode 100644
index 0000000..e8cc011
--- /dev/null
+++ b/ql-qlf-plugin/qlf_k6n10f/primitives_sim.v
@@ -0,0 +1,79 @@
+// Copyright 2020-2022 F4PGA Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
+`timescale 1ps/1ps
+
+`default_nettype none
+
+module fpga_interconnect(datain, dataout);
+    input  wire datain;
+    output wire dataout;
+
+    assign dataout = datain;
+
+    specify
+        (datain => dataout) = 0;
+    endspecify
+
+endmodule
+
+module LUT_K #(
+    //The Look-up Table size (number of inputs)
+    // supports 1<=K<=6
+    parameter K = 5, 
+
+    //The lut mask.  
+    //Left-most (MSB) bit corresponds to all inputs logic one. 
+    //Defaults to always false.
+    parameter LUT_MASK={2**K{1'b0}} 
+) (
+    //input  wire [K-1:0] in,
+    input  wire [5:0] in,
+    output wire out
+);
+
+    wire    [63:0]  LUT_MASK_full;
+    assign LUT_MASK_full =  (K == 6) ?  LUT_MASK[63:0] :
+                            (K == 5) ?  {32'b0, LUT_MASK[31:0]} :
+                            (K == 4) ?  {48'b0, LUT_MASK[15:0]} :
+                            (K == 3) ?  {56'b0, LUT_MASK[7:0]} :
+                            (K == 2) ?  {60'b0, LUT_MASK[3:0]} :
+                                        {62'b0, LUT_MASK[1:0]} ;
+    
+    reg     [5:0]   in_full;
+    always @(*)
+        case(K)
+            6:          in_full <= in[5:0];
+            5:          in_full <= {1'b0, in[4:0]};
+            4:          in_full <= {2'b0, in[3:0]};
+            3:          in_full <= {3'b0, in[2:0]};
+            2:          in_full <= {4'b0, in[1:0]};
+            1:          in_full <= {5'b0, in[0]};
+            default:    in_full <= in[5:0];
+        endcase
+
+    assign out = LUT_MASK_full[in_full];
+
+    specify
+        (in[0] => out) = 0;
+        (in[1] => out) = 0;
+        (in[2] => out) = 0;
+        (in[3] => out) = 0;
+        (in[4] => out) = 0;
+        (in[5] => out) = 0;
+    endspecify    
+
+endmodule
\ No newline at end of file
diff --git a/ql-qlf-plugin/synth_quicklogic.cc b/ql-qlf-plugin/synth_quicklogic.cc
index 2816daa..b6b475e 100644
--- a/ql-qlf-plugin/synth_quicklogic.cc
+++ b/ql-qlf-plugin/synth_quicklogic.cc
@@ -85,6 +85,9 @@
         log("        By default use Block RAM in output netlist.\n");
         log("        Specifying this switch turns it off.\n");
         log("\n");
+        log("    -bram_types\n");
+        log("        Emit specialized BRAM cells for particular address and data width configurations \n");
+        log("\n");
         log("    -no_ff_map\n");
         log("        By default ff techmap is turned on. Specifying this switch turns it off.\n");
         log("\n");
@@ -103,6 +106,7 @@
     bool nodsp;
     bool inferAdder;
     bool inferBram;
+    bool bramTypes;
     bool abcOpt;
     bool abc9;
     bool noffmap;
@@ -118,6 +122,7 @@
         family = "qlf_k4n8";
         inferAdder = true;
         inferBram = true;
+        bramTypes = false;
         abcOpt = true;
         abc9 = true;
         noffmap = false;
@@ -181,6 +186,10 @@
                 inferBram = false;
                 continue;
             }
+            if (args[argidx] == "-bram_types") {
+                bramTypes = true;
+                continue;
+            }
             if (args[argidx] == "-no_abc_opt") {
                 abcOpt = false;
                 continue;
@@ -237,8 +246,10 @@
 
             // Read simulation library
             readVelArgs = family_path + "/cells_sim.v";
-            if (family == "qlf_k6n10f")
+            if (family == "qlf_k6n10f") {
                 readVelArgs += family_path + "/dsp_sim.v";
+                readVelArgs += family_path + "/brams_sim.v";
+            }
 
             // Use -nomem2reg here to prevent Yosys from complaining about
             // some block ram cell models. After all the only part of the cells
@@ -368,6 +379,54 @@
             if (family == "qlf_k6n10f") {
                 run("techmap -map +/quicklogic/" + family + "/brams_final_map.v");
             }
+
+            // Data width to specialized cell type width map
+            const std::unordered_map<int, int> dataWidth36 = {{36, 36}, {32, 36}, {18, 18}, {16, 18}, {9, 9}, {8, 9}, {4, 4}, {2, 2}, {1, 1}};
+            const std::unordered_map<int, int> dataWidth18 = {{18, 18}, {16, 18}, {9, 9}, {8, 9}, {4, 4}, {2, 2}, {1, 1}};
+
+            // Perform a series of 'chtype' passess
+            if (bramTypes) {
+                for (const auto &ww : dataWidth18) {
+                    for (const auto &rw : dataWidth18) {
+                        auto cmd =
+                          stringf("chtype -set TDP36K_BRAM_WR_X%d_RD_X%d_split t:TDP36K a:is_inferred=1 %%i a:is_split=1 %%i a:wr_data_width=%d "
+                                  "%%i a:rd_data_width=%d %%i",
+                                  ww.second, rw.second, ww.first, rw.first);
+                        run(cmd);
+
+                        auto cmd1 = stringf("chtype -set TDP36K_FIFO_ASYNC_WR_X%d_RD_X%d_split t:TDP36K a:is_fifo=1 %%i a:sync_fifo=0 %%i "
+                                            "a:is_split=1 %%i a:wr_data_width=%d "
+                                            "%%i a:rd_data_width=%d %%i",
+                                            ww.second, rw.second, ww.first, rw.first);
+                        run(cmd1);
+
+                        auto cmd2 = stringf("chtype -set TDP36K_FIFO_SYNC_WR_X%d_RD_X%d_split t:TDP36K a:is_fifo=1 %%i a:sync_fifo=1 %%i "
+                                            "a:is_split=1 %%i a:wr_data_width=%d "
+                                            "%%i a:rd_data_width=%d %%i",
+                                            ww.second, rw.second, ww.first, rw.first);
+                        run(cmd2);
+                    }
+                }
+
+                for (const auto &ww : dataWidth36) {
+                    for (const auto &rw : dataWidth36) {
+                        auto cmd = stringf(
+                          "chtype -set TDP36K_BRAM_WR_X%d_RD_X%d_nonsplit t:TDP36K a:is_inferred=1 %%i a:wr_data_width=%d %%i a:rd_data_width=%d %%i",
+                          ww.second, rw.second, ww.first, rw.first);
+                        run(cmd);
+
+                        auto cmd1 = stringf("chtype -set TDP36K_FIFO_ASYNC_WR_X%d_RD_X%d_nonsplit t:TDP36K a:is_fifo=1 %%i a:sync_fifo=0 %%i "
+                                            "a:wr_data_width=%d %%i a:rd_data_width=%d %%i",
+                                            ww.second, rw.second, ww.first, rw.first);
+                        run(cmd1);
+
+                        auto cmd2 = stringf("chtype -set TDP36K_FIFO_SYNC_WR_X%d_RD_X%d_nonsplit t:TDP36K a:is_fifo=1 %%i a:sync_fifo=1 %%i "
+                                            "a:wr_data_width=%d %%i a:rd_data_width=%d %%i",
+                                            ww.second, rw.second, ww.first, rw.first);
+                        run(cmd2);
+                    }
+                }
+            }
         }
 
         if (check_label("map_ffram")) {
@@ -495,11 +554,7 @@
 
         if (check_label("blif")) {
             if (!blif_file.empty()) {
-                if (inferAdder) {
-                    run(stringf("write_blif -param %s", help_mode ? "<file-name>" : blif_file.c_str()));
-                } else {
-                    run(stringf("write_blif %s", help_mode ? "<file-name>" : blif_file.c_str()));
-                }
+                run(stringf("write_blif -param %s", help_mode ? "<file-name>" : blif_file.c_str()));
             }
         }
 
diff --git a/ql-qlf-plugin/tests/Makefile b/ql-qlf-plugin/tests/Makefile
index 661e92e..cd1c7e1 100644
--- a/ql-qlf-plugin/tests/Makefile
+++ b/ql-qlf-plugin/tests/Makefile
@@ -37,26 +37,39 @@
 #	qlf_k6n10_bram \
 
 SIM_TESTS = \
-    qlf_k6n10f/sim_dsp_mult_cfg_ports \
-    qlf_k6n10f/sim_dsp_mult_cfg_params \
-    qlf_k6n10f/sim_dsp_mult_r_cfg_ports \
-    qlf_k6n10f/sim_dsp_mult_r_cfg_params \
-    qlf_k6n10f/sim_dsp_fir_cfg_ports \
-    qlf_k6n10f/sim_dsp_fir_cfg_params \
-    qlf_k6n10f/sim_dsp_simd_cfg_ports \
-    qlf_k6n10f/sim_dsp_simd_cfg_params \
-    qlf_k6n10f/sim_tc36fifo
+     qlf_k6n10f/sim_dsp_mult_cfg_ports \
+     qlf_k6n10f/sim_dsp_mult_cfg_ports \
+     qlf_k6n10f/sim_dsp_mult_cfg_params \
+     qlf_k6n10f/sim_dsp_mult_r_cfg_ports \
+     qlf_k6n10f/sim_dsp_mult_r_cfg_params \
+     qlf_k6n10f/sim_dsp_fir_cfg_ports \
+     qlf_k6n10f/sim_dsp_fir_cfg_params \
+     qlf_k6n10f/sim_dsp_simd_cfg_ports \
+     qlf_k6n10f/sim_dsp_simd_cfg_params \
+     qlf_k6n10f/sim_tc36fifo
 
 # Those tests perform synthesis and simulation of synthesis results
 POST_SYNTH_SIM_TESTS = \
-    qlf_k6n10f/bram_tdp \
-    qlf_k6n10f/bram_sdp \
-    qlf_k6n10f/bram_tdp_split \
-    qlf_k6n10f/bram_sdp_split \
-    qlf_k6n10f/dsp_mult_post_synth_sim \
-    qlf_k6n10f/dsp_simd_post_synth_sim \
-    qlf_k6n10f/bram_asymmetric_wider_write \
-    qlf_k6n10f/bram_asymmetric_wider_read
+     qlf_k6n10f/asymmetric_bram36k_sfifo \
+     qlf_k6n10f/asymmetric_bram36k_afifo \
+     qlf_k6n10f/bram36k_sfifo \
+     qlf_k6n10f/bram36k_afifo \
+     qlf_k6n10f/bram18k_afifo \
+     qlf_k6n10f/bram18k_sfifo \
+     qlf_k6n10f/bram18k_tdp \
+     qlf_k6n10f/bram36k_tdp \
+     qlf_k6n10f/bram18k_sdp \
+     qlf_k6n10f/bram36k_sdp \
+     qlf_k6n10f/asymmetric_bram36k_sdp \
+     qlf_k6n10f/asymmetric_bram18k_sdp \
+     qlf_k6n10f/bram_tdp \
+     qlf_k6n10f/bram_sdp \
+     qlf_k6n10f/bram_tdp_split \
+     qlf_k6n10f/bram_sdp_split \
+     qlf_k6n10f/dsp_mult_post_synth_sim \
+     qlf_k6n10f/dsp_simd_post_synth_sim \
+     qlf_k6n10f/bram_asymmetric_wider_write \
+     qlf_k6n10f/bram_asymmetric_wider_read
 
 include $(shell pwd)/../../Makefile_test.common
 
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram18k_sdp/asymmetric_bram18k_sdp.tcl b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram18k_sdp/asymmetric_bram18k_sdp.tcl
new file mode 100644
index 0000000..0579462
--- /dev/null
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram18k_sdp/asymmetric_bram18k_sdp.tcl
@@ -0,0 +1,27 @@
+yosys -import
+
+if { [info procs ql-qlf-k6n10f] == {} } { plugin -i ql-qlf }
+yosys -import  ;
+
+read_verilog $::env(DESIGN_TOP).v
+design -save asymmetric_bram18k_sdp
+
+select spram_9x2048_18x1024
+select *
+synth_quicklogic -family qlf_k6n10f -top spram_9x2048_18x1024 -bram_types
+opt_expr -undriven
+opt_clean
+stat
+write_verilog sim/spram_9x2048_18x1024_post_synth.v
+select -assert-count 1 t:TDP36K_BRAM_WR_X9_RD_X18_split
+
+select -clear
+design -load asymmetric_bram18k_sdp
+select spram_18x1024_9x2048
+select *
+synth_quicklogic -family qlf_k6n10f -top spram_18x1024_9x2048 -bram_types
+opt_expr -undriven
+opt_clean
+stat
+write_verilog sim/spram_18x1024_9x2048_post_synth.v
+select -assert-count 1 t:TDP36K_BRAM_WR_X18_RD_X9_split
\ No newline at end of file
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram18k_sdp/asymmetric_bram18k_sdp.v b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram18k_sdp/asymmetric_bram18k_sdp.v
new file mode 100644
index 0000000..10fb3b3
--- /dev/null
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram18k_sdp/asymmetric_bram18k_sdp.v
@@ -0,0 +1,109 @@
+// Copyright 2020-2022 F4PGA Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
+module spram_9x2048_18x1024 (
+    WEN_i,
+    REN_i,
+    clock0,
+    clock1,
+    WR_ADDR_i,
+    RD_ADDR_i,
+    WDATA_i,
+    RDATA_o
+);
+
+parameter WR_ADDR_WIDTH = 11;
+parameter RD_ADDR_WIDTH = 10;
+parameter WR_DATA_WIDTH = 9;
+parameter RD_DATA_WIDTH = 18;
+parameter BE_WIDTH = 1;
+
+input wire WEN_i;
+input wire REN_i;
+input wire clock0;
+input wire clock1;
+input wire [WR_ADDR_WIDTH-1 :0] WR_ADDR_i;
+input wire [RD_ADDR_WIDTH-1 :0] RD_ADDR_i;
+input wire [WR_DATA_WIDTH-1 :0] WDATA_i;
+output wire [RD_DATA_WIDTH-1 :0] RDATA_o;
+
+RAM_18K_BLK #(
+              .WR_ADDR_WIDTH(WR_ADDR_WIDTH),
+              .RD_ADDR_WIDTH(RD_ADDR_WIDTH),
+              .WR_DATA_WIDTH(WR_DATA_WIDTH),
+              .RD_DATA_WIDTH(RD_DATA_WIDTH),
+              .BE_WIDTH(BE_WIDTH)
+              ) spram_x18_inst (
+              
+              .WEN_i(WEN_i),
+              .WR_BE_i(1'b1),
+              .REN_i(REN_i),              
+              .WR_CLK_i(clock0),
+              .RD_CLK_i(clock1),
+              .WR_ADDR_i(WR_ADDR_i),
+              .RD_ADDR_i(RD_ADDR_i),
+              .WDATA_i(WDATA_i),
+              .RDATA_o(RDATA_o)
+              );
+              
+endmodule    
+
+module spram_18x1024_9x2048 (
+    WEN_i,
+    REN_i,
+    clock0,
+    clock1,
+    WR_ADDR_i,
+    RD_ADDR_i,
+    WDATA_i,
+    RDATA_o
+);
+
+parameter WR_ADDR_WIDTH = 10;
+parameter RD_ADDR_WIDTH = 11;
+parameter WR_DATA_WIDTH = 18;
+parameter RD_DATA_WIDTH = 9;
+parameter BE_WIDTH = 2;
+
+input wire WEN_i;
+input wire REN_i;
+input wire clock0;
+input wire clock1;
+input wire [WR_ADDR_WIDTH-1 :0] WR_ADDR_i;
+input wire [RD_ADDR_WIDTH-1 :0] RD_ADDR_i;
+input wire [WR_DATA_WIDTH-1 :0] WDATA_i;
+output wire [RD_DATA_WIDTH-1 :0] RDATA_o;
+
+RAM_18K_BLK #(
+              .WR_ADDR_WIDTH(WR_ADDR_WIDTH),
+              .RD_ADDR_WIDTH(RD_ADDR_WIDTH),
+              .WR_DATA_WIDTH(WR_DATA_WIDTH),
+              .RD_DATA_WIDTH(RD_DATA_WIDTH),
+              .BE_WIDTH(BE_WIDTH)
+              ) spram_x18_inst (
+              
+              .WEN_i(WEN_i),
+              .WR_BE_i(2'b11),
+              .REN_i(REN_i),              
+              .WR_CLK_i(clock0),
+              .RD_CLK_i(clock1),
+              .WR_ADDR_i(WR_ADDR_i),
+              .RD_ADDR_i(RD_ADDR_i),
+              .WDATA_i(WDATA_i),
+              .RDATA_o(RDATA_o)
+              );
+              
+endmodule    
\ No newline at end of file
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram18k_sdp/sim/Makefile b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram18k_sdp/sim/Makefile
new file mode 100644
index 0000000..0cce75d
--- /dev/null
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram18k_sdp/sim/Makefile
@@ -0,0 +1,46 @@
+# Copyright 2020-2022 F4PGA Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+TESTBENCH = asymmetric_bram18k_sdp_tb.v
+POST_SYNTH = spram_9x2048_18x1024_post_synth spram_18x1024_9x2048_post_synth
+ADDR_WIDTH0 = 11 10
+DATA_WIDTH0 = 9 18
+ADDR_WIDTH1 = 10 11
+DATA_WIDTH1 = 18 9
+TOP = spram_9x2048_18x1024 spram_18x1024_9x2048
+ADDR0_DEFINES = $(foreach awidth0, $(ADDR_WIDTH0),-DADDR_WIDTH0="$(awidth0)")
+ADDR1_DEFINES = $(foreach awidth1, $(ADDR_WIDTH1),-DADDR_WIDTH1="$(awidth1)")
+DATA0_DEFINES = $(foreach dwidth0, $(DATA_WIDTH0),-DDATA_WIDTH0="$(dwidth0)")
+DATA1_DEFINES = $(foreach dwidth1, $(DATA_WIDTH1),-DDATA_WIDTH1="$(dwidth1)")
+TOP_DEFINES = $(foreach top, $(TOP),-DTOP="$(top)")
+VCD_DEFINES = $(foreach vcd, $(POST_SYNTH),-DVCD="$(vcd).vcd")
+
+SIM_LIBS = $(shell find ../../../../qlf_k6n10f -name "*.v" -not -name "*_map.v")
+
+define simulate_post_synth
+	@iverilog  -vvvv -g2005 $(word $(1),$(ADDR0_DEFINES)) $(word $(1),$(ADDR1_DEFINES)) $(word $(1),$(DATA0_DEFINES)) $(word $(1),$(DATA1_DEFINES)) $(word $(1),$(TOP_DEFINES)) $(word $(1),$(VCD_DEFINES)) -o $(word $(1),$(POST_SYNTH)).vvp $(word $(1),$(POST_SYNTH)).v $(SIM_LIBS) $(TESTBENCH) > $(word $(1),$(POST_SYNTH)).vvp.log 2>&1
+	@vvp -vvvv $(word $(1),$(POST_SYNTH)).vvp > $(word $(1),$(POST_SYNTH)).vcd.log 2>&1
+endef
+
+define clean_post_synth_sim
+	@rm -rf  $(word $(1),$(POST_SYNTH)).vcd $(word $(1),$(POST_SYNTH)).vvp $(word $(1),$(POST_SYNTH)).vvp.log $(word $(1),$(POST_SYNTH)).vcd.log
+endef
+
+sim:
+	$(call simulate_post_synth,1)
+	$(call clean_post_synth_sim,1)
+	$(call simulate_post_synth,2)
+	$(call clean_post_synth_sim,2)
\ No newline at end of file
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram18k_sdp/sim/asymmetric_bram18k_sdp_tb.v b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram18k_sdp/sim/asymmetric_bram18k_sdp_tb.v
new file mode 100644
index 0000000..e8ffaa5
--- /dev/null
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram18k_sdp/sim/asymmetric_bram18k_sdp_tb.v
@@ -0,0 +1,177 @@
+// Copyright 2020-2022 F4PGA Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//		 http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
+`timescale 1ns/1ps
+
+`define STRINGIFY(x) `"x`"
+
+module TB;
+	localparam PERIOD = 50;
+	localparam ADDR_INCR = 1;
+
+	reg clk_0;
+	reg clk_1;
+	reg rce;
+	reg [`ADDR_WIDTH1-1:0] ra;
+	wire [`DATA_WIDTH1-1:0] rq;
+	reg wce;
+	reg [`ADDR_WIDTH0-1:0] wa;
+	reg [`DATA_WIDTH0-1:0] wd;
+
+	initial clk_0 = 0;
+	initial clk_1 = 0;
+	initial ra = 0;
+	initial wa = 0;
+	initial wd = 0;
+	initial rce = 0;
+	initial wce = 0;
+	initial forever #(PERIOD / 2.0) clk_0 = ~clk_0;
+	initial begin
+		#(PERIOD / 4.0);
+		forever #(PERIOD / 2.0) clk_1 = ~clk_1;
+	end
+	initial begin
+		$dumpfile(`STRINGIFY(`VCD));
+		$dumpvars;
+	end
+
+	integer a;
+	integer b;
+
+	reg done_0;
+	initial done_0 = 1'b0;
+	wire done_sim = done_0;
+
+	reg [`DATA_WIDTH1-1:0] expected_0;
+
+	reg read_test_0;
+	initial read_test_0 = 0;
+
+
+	wire error_0 = (read_test_0) ? (rq !== expected_0) : 0;
+
+	integer error_0_cnt = 0;
+
+	always @ (posedge clk_1)
+	begin
+		if (error_0)
+			error_0_cnt <= error_0_cnt + 1'b1;
+	end
+
+	case (`STRINGIFY(`TOP))
+	"spram_9x2048_18x1024": begin
+		initial #(1) begin
+			// Write data
+			for (a = 0; a < (1<<`ADDR_WIDTH0) ; a = a + ADDR_INCR) begin
+				@(negedge clk_0) begin
+					wa = a[`ADDR_WIDTH0-1:0];
+					wd = a[9:1];
+					wce = 1;
+				end
+				@(posedge clk_0) begin
+					#(PERIOD/10) wce = 0;
+				end
+			end
+			// Read data
+			read_test_0 = 1;
+			for (a = 0; a < (1<<`ADDR_WIDTH1); a = a + ADDR_INCR) begin
+				@(negedge clk_1) begin
+					ra = a;
+					rce = 1;
+				end
+				@(posedge clk_1) begin
+					expected_0 <= {a[8],a[8],a[7:0],a[7:0]};				
+					#(PERIOD/10) rce = 0;
+					if ( rq !== expected_0) begin
+						$display("%d: PORT 0: FAIL: mismatch act=%x exp=%x at %x", $time, rq, expected_0, a);
+					end else begin
+						$display("%d: PORT 0: OK: act=%x exp=%x at %x", $time, rq, expected_0, a);
+					end
+				end
+			end
+			done_0 = 1'b1;
+			a = 0;		
+		end
+	end
+	"spram_18x1024_9x2048": begin
+		initial #(1) begin
+			// Write data
+			for (a = 0; a < (1<<`ADDR_WIDTH0) ; a = a + ADDR_INCR) begin
+				@(negedge clk_0) begin
+					wa = a[`ADDR_WIDTH0-1:0];
+					wd = {a[8],a[8],a[7:0],a[7:0]};
+					wce = 1;
+				end
+				@(posedge clk_0) begin
+					#(PERIOD/10) wce = 0;
+				end
+			end
+			// Read data
+			read_test_0 = 1;
+			for (a = 0; a < (1<<`ADDR_WIDTH1); a = a + ADDR_INCR) begin
+				@(negedge clk_1) begin
+					ra = a;
+					rce = 1;
+				end
+				@(posedge clk_1) begin				
+					expected_0 <= {a[9:1]};
+					#(PERIOD/10) rce = 0;
+					if ( rq !== expected_0) begin
+						$display("%d: PORT 0: FAIL: mismatch act=%x exp=%x at %x", $time, rq, expected_0, a);
+					end else begin
+						$display("%d: PORT 0: OK: act=%x exp=%x at %x", $time, rq, expected_0, a);
+					end
+				end
+			end
+			done_0 = 1'b1;
+			a = 0;		
+		end
+	end	 
+	endcase
+
+	// Scan for simulation finish
+	always @(posedge clk_1) begin
+		if (done_sim)
+			$finish_and_return( (error_0_cnt == 0) ? 0 : -1 );
+	end
+
+	case (`STRINGIFY(`TOP))
+		"spram_9x2048_18x1024": begin
+			spram_9x2048_18x1024 #() bram (
+				.clock0(clk_0),
+				.clock1(clk_1),			
+				.REN_i(rce),
+				.RD_ADDR_i(ra),
+				.RDATA_o(rq),
+				.WEN_i(wce),
+				.WR_ADDR_i(wa),
+				.WDATA_i(wd)
+			);
+		end
+		"spram_18x1024_9x2048": begin
+			spram_18x1024_9x2048 #() bram (
+				.clock0(clk_0),
+				.clock1(clk_1),			
+				.REN_i(rce),
+				.RD_ADDR_i(ra),
+				.RDATA_o(rq),
+				.WEN_i(wce),
+				.WR_ADDR_i(wa),
+				.WDATA_i(wd)
+			);
+		end
+	endcase
+endmodule
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_afifo/asymmetric_bram36k_afifo.tcl b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_afifo/asymmetric_bram36k_afifo.tcl
new file mode 100644
index 0000000..66e2686
--- /dev/null
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_afifo/asymmetric_bram36k_afifo.tcl
@@ -0,0 +1,49 @@
+yosys -import
+
+if { [info procs ql-qlf-k6n10f] == {} } { plugin -i ql-qlf }
+yosys -import  ;
+
+read_verilog $::env(DESIGN_TOP).v
+design -save asymmetric_bram36k_afifo
+
+select af4096x9_1024x36
+select *
+synth_quicklogic -family qlf_k6n10f -top af4096x9_1024x36 -bram_types
+opt_expr -undriven
+opt_clean
+stat
+write_verilog sim/af4096x9_1024x36_post_synth.v
+select -assert-count 1 t:TDP36K_FIFO_ASYNC_WR_X9_RD_X36_nonsplit
+
+select -clear
+design -load asymmetric_bram36k_afifo
+select af2048x18_1024x36
+select *
+synth_quicklogic -family qlf_k6n10f -top af2048x18_1024x36 -bram_types
+opt_expr -undriven
+opt_clean
+stat
+write_verilog sim/af2048x18_1024x36_post_synth.v
+select -assert-count 1 t:TDP36K_FIFO_ASYNC_WR_X18_RD_X36_nonsplit
+
+select -clear
+design -load asymmetric_bram36k_afifo
+select af2048x18_4098x9
+select *
+synth_quicklogic -family qlf_k6n10f -top af2048x18_4098x9 -bram_types
+opt_expr -undriven
+opt_clean
+stat
+write_verilog sim/af2048x18_4098x9_post_synth.v
+select -assert-count 1 t:TDP36K_FIFO_ASYNC_WR_X18_RD_X9_nonsplit
+
+select -clear
+design -load asymmetric_bram36k_afifo
+select af1024x36_4098x9
+select *
+synth_quicklogic -family qlf_k6n10f -top af1024x36_4098x9 -bram_types
+opt_expr -undriven
+opt_clean
+stat
+write_verilog sim/af1024x36_4098x9_post_synth.v
+select -assert-count 1 t:TDP36K_FIFO_ASYNC_WR_X36_RD_X9_nonsplit
\ No newline at end of file
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_afifo/asymmetric_bram36k_afifo.v b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_afifo/asymmetric_bram36k_afifo.v
new file mode 100644
index 0000000..6cef5f5
--- /dev/null
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_afifo/asymmetric_bram36k_afifo.v
@@ -0,0 +1,180 @@
+// Copyright 2020-2022 F4PGA Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
+module af4096x9_1024x36 (DIN,PUSH,POP,clock0,clock1,Async_Flush,Almost_Full,Almost_Empty,Full,Empty,Full_Watermark,Empty_Watermark,Overrun_Error,Underrun_Error,DOUT);
+
+parameter WR_DATA_WIDTH = 9;
+parameter RD_DATA_WIDTH = 36;
+parameter UPAE_DBITS = 12'd10;
+parameter UPAF_DBITS = 12'd10;
+
+input clock0,clock1;
+input PUSH,POP;
+input [WR_DATA_WIDTH-1:0] DIN;
+input Async_Flush;
+output [RD_DATA_WIDTH-1:0] DOUT;
+output Almost_Full,Almost_Empty;
+output Full, Empty;
+output Full_Watermark, Empty_Watermark;
+output Overrun_Error, Underrun_Error;
+
+
+AFIFO_36K_BLK  # (.WR_DATA_WIDTH(WR_DATA_WIDTH),.RD_DATA_WIDTH(RD_DATA_WIDTH),.UPAE_DBITS(UPAE_DBITS),.UPAF_DBITS(UPAF_DBITS)
+                 )
+  FIFO_INST    (
+                .DIN(DIN),
+                .PUSH(PUSH),
+                .POP(POP),
+                .Push_Clk(clock0),
+                .Pop_Clk(clock1),
+                .Async_Flush(Async_Flush),
+                
+                .Overrun_Error(Overrun_Error),
+                .Full_Watermark(Full_Watermark),
+                .Almost_Full(Almost_Full),
+                .Full(Full),
+                
+                .Underrun_Error(Underrun_Error),
+                .Empty_Watermark(Empty_Watermark),
+                .Almost_Empty(Almost_Empty),
+                .Empty(Empty),
+
+                .DOUT(DOUT)
+                );
+endmodule
+
+module af2048x18_1024x36 (DIN,PUSH,POP,clock0,clock1,Async_Flush,Almost_Full,Almost_Empty,Full,Empty,Full_Watermark,Empty_Watermark,Overrun_Error,Underrun_Error,DOUT);
+
+parameter WR_DATA_WIDTH = 18;
+parameter RD_DATA_WIDTH = 36;
+parameter UPAE_DBITS = 12'd10;
+parameter UPAF_DBITS = 12'd10;
+
+input clock0,clock1;
+input PUSH,POP;
+input [WR_DATA_WIDTH-1:0] DIN;
+input Async_Flush;
+output [RD_DATA_WIDTH-1:0] DOUT;
+output Almost_Full,Almost_Empty;
+output Full, Empty;
+output Full_Watermark, Empty_Watermark;
+output Overrun_Error, Underrun_Error;
+
+AFIFO_36K_BLK  # (.WR_DATA_WIDTH(WR_DATA_WIDTH),.RD_DATA_WIDTH(RD_DATA_WIDTH),.UPAE_DBITS(UPAE_DBITS),.UPAF_DBITS(UPAF_DBITS)
+                  )
+  FIFO_INST    (
+                .DIN(DIN),
+                .PUSH(PUSH),
+                .POP(POP),
+                .Push_Clk(clock0),
+                .Pop_Clk(clock1),
+                .Async_Flush(Async_Flush),
+                
+                .Overrun_Error(Overrun_Error),
+                .Full_Watermark(Full_Watermark),
+                .Almost_Full(Almost_Full),
+                .Full(Full),
+                
+                .Underrun_Error(Underrun_Error),
+                .Empty_Watermark(Empty_Watermark),
+                .Almost_Empty(Almost_Empty),
+                .Empty(Empty),
+
+                .DOUT(DOUT)
+                );
+endmodule
+
+module af2048x18_4098x9 (DIN,PUSH,POP,clock0,clock1,Async_Flush,Almost_Full,Almost_Empty,Full,Empty,Full_Watermark,Empty_Watermark,Overrun_Error,Underrun_Error,DOUT);
+
+parameter WR_DATA_WIDTH = 18;
+parameter RD_DATA_WIDTH = 9;
+parameter UPAE_DBITS = 12'd10;
+parameter UPAF_DBITS = 12'd10;
+
+input clock0,clock1;
+input PUSH,POP;
+input [WR_DATA_WIDTH-1:0] DIN;
+input Async_Flush;
+output [RD_DATA_WIDTH-1:0] DOUT;
+output Almost_Full,Almost_Empty;
+output Full, Empty;
+output Full_Watermark, Empty_Watermark;
+output Overrun_Error, Underrun_Error;
+
+AFIFO_36K_BLK  # (.WR_DATA_WIDTH(WR_DATA_WIDTH),.RD_DATA_WIDTH(RD_DATA_WIDTH),.UPAE_DBITS(UPAE_DBITS),.UPAF_DBITS(UPAF_DBITS)
+                  )
+  FIFO_INST    (
+                .DIN(DIN),
+                .PUSH(PUSH),
+                .POP(POP),
+                .Push_Clk(clock0),
+                .Pop_Clk(clock1),
+                .Async_Flush(Async_Flush),
+                
+                .Overrun_Error(Overrun_Error),
+                .Full_Watermark(Full_Watermark),
+                .Almost_Full(Almost_Full),
+                .Full(Full),
+                
+                .Underrun_Error(Underrun_Error),
+                .Empty_Watermark(Empty_Watermark),
+                .Almost_Empty(Almost_Empty),
+                .Empty(Empty),
+
+                .DOUT(DOUT)
+                );
+endmodule
+
+module af1024x36_4098x9 (DIN,PUSH,POP,clock0,clock1,Async_Flush,Almost_Full,Almost_Empty,Full,Empty,Full_Watermark,Empty_Watermark,Overrun_Error,Underrun_Error,DOUT);
+
+parameter WR_DATA_WIDTH = 36;
+parameter RD_DATA_WIDTH = 9;
+parameter UPAE_DBITS = 12'd10;
+parameter UPAF_DBITS = 12'd10;
+
+input clock0,clock1;
+input PUSH,POP;
+input [WR_DATA_WIDTH-1:0] DIN;
+input Async_Flush;
+output [RD_DATA_WIDTH-1:0] DOUT;
+output Almost_Full,Almost_Empty;
+output Full, Empty;
+output Full_Watermark, Empty_Watermark;
+output Overrun_Error, Underrun_Error;
+
+AFIFO_36K_BLK  # (.WR_DATA_WIDTH(WR_DATA_WIDTH),.RD_DATA_WIDTH(RD_DATA_WIDTH),.UPAE_DBITS(UPAE_DBITS),.UPAF_DBITS(UPAF_DBITS)
+                  )
+  FIFO_INST    (
+                .DIN(DIN),
+                .PUSH(PUSH),
+                .POP(POP),
+                .Push_Clk(clock0),
+                .Pop_Clk(clock1),
+                .Async_Flush(Async_Flush),
+                
+                .Overrun_Error(Overrun_Error),
+                .Full_Watermark(Full_Watermark),
+                .Almost_Full(Almost_Full),
+                .Full(Full),
+                
+                .Underrun_Error(Underrun_Error),
+                .Empty_Watermark(Empty_Watermark),
+                .Almost_Empty(Almost_Empty),
+                .Empty(Empty),
+
+                .DOUT(DOUT)
+                );
+endmodule
\ No newline at end of file
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_afifo/sim/Makefile b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_afifo/sim/Makefile
new file mode 100644
index 0000000..76bc1c7
--- /dev/null
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_afifo/sim/Makefile
@@ -0,0 +1,50 @@
+# Copyright 2020-2022 F4PGA Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+TESTBENCH = asymmetric_bram36k_afifo_tb.v
+POST_SYNTH = af4096x9_1024x36_post_synth af2048x18_1024x36_post_synth af2048x18_4098x9_post_synth af1024x36_4098x9_post_synth
+ADDR_WIDTH0 = 12 11 11 10
+DATA_WIDTH0 = 9 18 18 36
+ADDR_WIDTH1 = 10 10 12 12
+DATA_WIDTH1 = 36 36 9 9
+TOP = af4096x9_1024x36 af2048x18_1024x36 af2048x18_4098x9 af1024x36_4098x9
+ADDR0_DEFINES = $(foreach awidth0, $(ADDR_WIDTH0),-DADDR_WIDTH0="$(awidth0)")
+ADDR1_DEFINES = $(foreach awidth1, $(ADDR_WIDTH1),-DADDR_WIDTH1="$(awidth1)")
+DATA0_DEFINES = $(foreach dwidth0, $(DATA_WIDTH0),-DDATA_WIDTH0="$(dwidth0)")
+DATA1_DEFINES = $(foreach dwidth1, $(DATA_WIDTH1),-DDATA_WIDTH1="$(dwidth1)")
+TOP_DEFINES = $(foreach top, $(TOP),-DTOP="$(top)")
+VCD_DEFINES = $(foreach vcd, $(POST_SYNTH),-DVCD="$(vcd).vcd")
+
+SIM_LIBS = $(shell find ../../../../qlf_k6n10f -name "*.v" -not -name "*_map.v")
+
+define simulate_post_synth
+	@iverilog  -vvvv -g2005 $(word $(1),$(ADDR0_DEFINES)) $(word $(1),$(ADDR1_DEFINES)) $(word $(1),$(DATA0_DEFINES)) $(word $(1),$(DATA1_DEFINES)) $(word $(1),$(TOP_DEFINES)) $(word $(1),$(VCD_DEFINES)) -o $(word $(1),$(POST_SYNTH)).vvp $(word $(1),$(POST_SYNTH)).v $(SIM_LIBS) $(TESTBENCH) > $(word $(1),$(POST_SYNTH)).vvp.log 2>&1
+	@vvp -vvvv $(word $(1),$(POST_SYNTH)).vvp > $(word $(1),$(POST_SYNTH)).vcd.log 2>&1
+endef
+
+define clean_post_synth_sim
+	@rm -rf  $(word $(1),$(POST_SYNTH)).vcd $(word $(1),$(POST_SYNTH)).vvp $(word $(1),$(POST_SYNTH)).vvp.log $(word $(1),$(POST_SYNTH)).vcd.log
+endef
+
+sim:
+	$(call simulate_post_synth,1)
+	$(call clean_post_synth_sim,1)
+	$(call simulate_post_synth,2)
+	$(call clean_post_synth_sim,2)
+	$(call simulate_post_synth,3)
+	$(call clean_post_synth_sim,3)
+	$(call simulate_post_synth,4)
+	$(call clean_post_synth_sim,4)
\ No newline at end of file
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_afifo/sim/asymmetric_bram36k_afifo_tb.v b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_afifo/sim/asymmetric_bram36k_afifo_tb.v
new file mode 100644
index 0000000..dd40a5a
--- /dev/null
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_afifo/sim/asymmetric_bram36k_afifo_tb.v
@@ -0,0 +1,292 @@
+// Copyright 2020-2022 F4PGA Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//	http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
+`timescale 1ns/1ps
+
+`define STRINGIFY(x) `"x`"
+
+module TB;
+	localparam PERIOD = 30;
+	localparam ADDR_INCR = 1;
+
+	reg clk0;
+	reg clk1;
+	reg flush;
+	reg pop;
+	wire [`DATA_WIDTH1-1:0] dout;
+	reg push;
+	reg [`DATA_WIDTH0-1:0] din;	 
+	wire almost_full,almost_empty;
+	wire full, empty;
+	wire full_watermark, empty_watermark;
+	wire overrun_error, underrun_error;
+
+	initial 
+	begin
+		clk0 = 0;
+		clk1 = 0;
+		pop = 0;
+		push = 0;
+		flush = 1;
+		din = 0;
+		#40
+		flush = 0;
+	end
+	
+	initial forever #(PERIOD / 3.0) clk0 = ~clk0;
+	initial forever #(PERIOD / 2.0) clk1 = ~clk1;
+	
+	initial begin
+		$dumpfile(`STRINGIFY(`VCD));
+		$dumpvars;
+	end
+
+	integer a;
+
+	reg done;
+	initial done = 1'b0;
+	
+	reg read_test;
+	initial read_test = 0;
+
+	reg [`DATA_WIDTH1-1:0] expected;
+	initial expected = 0;
+
+	wire error = (read_test) ? dout !== expected : 0;
+
+	integer error_cnt = 0;
+	always @ (posedge clk1)
+	begin
+		if (error)
+			error_cnt <= error_cnt + 1'b1; 
+	end
+
+	case (`STRINGIFY(`TOP))
+	"af4096x9_1024x36": begin
+		initial #(50) begin
+			// Write data
+			for (a = 0; a < (1<<`ADDR_WIDTH0) ; a = a + ADDR_INCR) begin
+				@(negedge clk0) begin
+					din = a[10:2];
+					push = 1;
+				end
+				@(posedge clk0) begin
+					#(PERIOD/10) push = 0;
+				end
+			end
+			// Read data
+			read_test = 1;
+			for (a = 0; a < (1<<`ADDR_WIDTH1); a = a + ADDR_INCR) begin
+				@(posedge clk1) begin
+					expected <= {a[8],a[8],a[7:0],a[7:0],a[8],a[8],a[7:0],a[7:0]};
+					#(PERIOD/10) pop = 0;
+					if ( dout !== expected) begin
+						$display("%d: PORT 0: FAIL: mismatch act=%x exp=%x at %x", $time, dout, expected, a);
+					end else begin
+						$display("%d: PORT 0: OK: act=%x exp=%x at %x", $time, dout, expected, a);
+					end
+				end
+				@(negedge clk1) begin
+					pop = 1;
+				end
+			end
+			done = 1'b1;
+			a = 0;
+		end
+	end
+	"af2048x18_1024x36": begin
+		initial #(50) begin
+			// Write data
+			for (a = 0; a < (1<<`ADDR_WIDTH0) ; a = a + ADDR_INCR) begin
+				@(negedge clk0) begin
+					din = a[18:1];
+					push = 1;
+				end
+				@(posedge clk0) begin
+					#(PERIOD/10) push = 0;
+				end
+			end
+			// Read data
+			read_test = 1;
+			for (a = 0; a < (1<<`ADDR_WIDTH1); a = a + ADDR_INCR) begin
+				@(posedge clk1) begin
+					expected <= {a[17:0],a[17:0]};
+					#(PERIOD/10) pop = 0;
+					if ( dout !== expected) begin
+						$display("%d: PORT 0: FAIL: mismatch act=%x exp=%x at %x", $time, dout, expected, a);
+					end else begin
+						$display("%d: PORT 0: OK: act=%x exp=%x at %x", $time, dout, expected, a);
+					end
+				end
+				@(negedge clk1) begin
+					pop = 1;
+				end
+			end
+			done = 1'b1;
+			a = 0;
+		end
+	end	 
+	"af2048x18_4098x9": begin
+		initial #(50) begin
+			// Write data
+			for (a = 0; a < (1<<`ADDR_WIDTH0) ; a = a + ADDR_INCR) begin
+				@(negedge clk0) begin
+					din = {a[8],a[8],a[7:0],a[7:0]};
+					push = 1;
+				end
+				@(posedge clk0) begin
+					#(PERIOD/10) push = 0;
+				end
+			end
+			// Read data
+			read_test = 1;
+			for (a = 0; a < (1<<`ADDR_WIDTH1); a = a + ADDR_INCR) begin
+				@(posedge clk1) begin
+					expected <= {a[9:1]};
+					#(PERIOD/10) pop = 0;
+					if ( dout !== expected) begin
+						$display("%d: PORT 0: FAIL: mismatch act=%x exp=%x at %x", $time, dout, expected, a);
+					end else begin
+						$display("%d: PORT 0: OK: act=%x exp=%x at %x", $time, dout, expected, a);
+					end
+				end
+				@(negedge clk1) begin
+					pop = 1;
+				end
+			end
+			done = 1'b1;
+			a = 0;
+		end
+	end
+	"af1024x36_4098x9": begin
+		initial #(50) begin
+			// Write data
+			for (a = 0; a < (1<<`ADDR_WIDTH0) ; a = a + ADDR_INCR) begin
+				@(negedge clk0) begin
+					din = {a[8],a[8],a[7:0],a[7:0],a[8],a[8],a[7:0],a[7:0]};
+					push = 1;
+				end
+				@(posedge clk0) begin
+					#(PERIOD/10) push = 0;
+				end
+			end
+			// Read data
+			read_test = 1;
+			for (a = 0; a < (1<<`ADDR_WIDTH1); a = a + ADDR_INCR) begin
+				@(posedge clk1) begin
+					expected <= {a[10:2]};
+					#(PERIOD/10) pop = 0;
+					if ( dout !== expected) begin
+						$display("%d: PORT 0: FAIL: mismatch act=%x exp=%x at %x", $time, dout, expected, a);
+					end else begin
+						$display("%d: PORT 0: OK: act=%x exp=%x at %x", $time, dout, expected, a);
+					end
+				end
+				@(negedge clk1) begin
+					pop = 1;
+				end
+			end
+			done = 1'b1;
+			a = 0;
+		end
+	end
+	endcase
+
+	// Scan for simulation finish
+	always @(posedge clk1) begin
+		if (done)
+			$finish_and_return( (error_cnt == 0) ? 0 : -1 );
+	end
+
+	case (`STRINGIFY(`TOP))
+		"af4096x9_1024x36": begin
+			af4096x9_1024x36 #() afifo (
+				.DIN(din),
+				.PUSH(push),
+				.POP(pop),
+				.clock0(clk0),
+				.clock1(clk1),
+				.Async_Flush(flush),
+				.Almost_Full(almost_full),
+				.Almost_Empty(almost_empty),
+				.Full(full),
+				.Empty(empty),
+				.Full_Watermark(full_watermark),
+				.Empty_Watermark(empty_watermark),
+				.Overrun_Error(overrun_error),
+				.Underrun_Error(underrun_error),
+				.DOUT(dout)
+			);
+		end
+		"af2048x18_1024x36": begin
+			af2048x18_1024x36 #() afifo (
+				.DIN(din),
+				.PUSH(push),
+				.POP(pop),
+				.clock0(clk0),
+				.clock1(clk1),
+				.Async_Flush(flush),
+				.Almost_Full(almost_full),
+				.Almost_Empty(almost_empty),
+				.Full(full),
+				.Empty(empty),
+				.Full_Watermark(full_watermark),
+				.Empty_Watermark(empty_watermark),
+				.Overrun_Error(overrun_error),
+				.Underrun_Error(underrun_error),
+				.DOUT(dout)
+			);
+		end
+		"af2048x18_4098x9": begin
+			af2048x18_4098x9 #() afifo (
+				.DIN(din),
+				.PUSH(push),
+				.POP(pop),
+				.clock0(clk0),
+				.clock1(clk1),
+				.Async_Flush(flush),
+				.Almost_Full(almost_full),
+				.Almost_Empty(almost_empty),
+				.Full(full),
+				.Empty(empty),
+				.Full_Watermark(full_watermark),
+				.Empty_Watermark(empty_watermark),
+				.Overrun_Error(overrun_error),
+				.Underrun_Error(underrun_error),
+				.DOUT(dout)
+			);
+		end
+		"af1024x36_4098x9": begin
+			af1024x36_4098x9 #() afifo (
+				.DIN(din),
+				.PUSH(push),
+				.POP(pop),
+				.clock0(clk0),
+				.clock1(clk1),
+				.Async_Flush(flush),
+				.Almost_Full(almost_full),
+				.Almost_Empty(almost_empty),
+				.Full(full),
+				.Empty(empty),
+				.Full_Watermark(full_watermark),
+				.Empty_Watermark(empty_watermark),
+				.Overrun_Error(overrun_error),
+				.Underrun_Error(underrun_error),
+				.DOUT(dout)
+			);
+		end
+	endcase
+endmodule
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_sdp/asymmetric_bram36k_sdp.tcl b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_sdp/asymmetric_bram36k_sdp.tcl
new file mode 100644
index 0000000..827914a
--- /dev/null
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_sdp/asymmetric_bram36k_sdp.tcl
@@ -0,0 +1,49 @@
+yosys -import
+
+if { [info procs ql-qlf-k6n10f] == {} } { plugin -i ql-qlf }
+yosys -import  ;
+
+read_verilog $::env(DESIGN_TOP).v
+design -save asymmetric_bram36k_sdp
+
+select spram_9x4096_36x1024
+select *
+synth_quicklogic -family qlf_k6n10f -top spram_9x4096_36x1024 -bram_types
+opt_expr -undriven
+opt_clean
+stat
+write_verilog sim/spram_9x4096_36x1024_post_synth.v
+select -assert-count 1 t:TDP36K_BRAM_WR_X9_RD_X36_nonsplit
+
+select -clear
+design -load asymmetric_bram36k_sdp
+select spram_18x2048_36x1024
+select *
+synth_quicklogic -family qlf_k6n10f -top spram_18x2048_36x1024 -bram_types
+opt_expr -undriven
+opt_clean
+stat
+write_verilog sim/spram_18x2048_36x1024_post_synth.v
+select -assert-count 1 t:TDP36K_BRAM_WR_X18_RD_X36_nonsplit
+
+select -clear
+design -load asymmetric_bram36k_sdp
+select spram_18x2048_9x4096
+select *
+synth_quicklogic -family qlf_k6n10f -top spram_18x2048_9x4096 -bram_types
+opt_expr -undriven
+opt_clean
+stat
+write_verilog sim/spram_18x2048_9x4096_post_synth.v
+select -assert-count 1 t:TDP36K_BRAM_WR_X18_RD_X9_nonsplit
+
+select -clear
+design -load asymmetric_bram36k_sdp
+select spram_36x1024_18x2048
+select *
+synth_quicklogic -family qlf_k6n10f -top spram_36x1024_18x2048 -bram_types
+opt_expr -undriven
+opt_clean
+stat
+write_verilog sim/spram_36x1024_18x2048_post_synth.v
+select -assert-count 1 t:TDP36K_BRAM_WR_X36_RD_X18_nonsplit
\ No newline at end of file
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_sdp/asymmetric_bram36k_sdp.v b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_sdp/asymmetric_bram36k_sdp.v
new file mode 100644
index 0000000..1a274f5
--- /dev/null
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_sdp/asymmetric_bram36k_sdp.v
@@ -0,0 +1,203 @@
+// Copyright 2020-2022 F4PGA Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
+module spram_9x4096_36x1024 (
+    WEN_i,
+    REN_i,
+    clock0,
+    clock1,
+    WR_ADDR_i,
+    RD_ADDR_i,
+    WDATA_i,
+    RDATA_o
+);
+
+parameter WR_ADDR_WIDTH = 12;
+parameter RD_ADDR_WIDTH = 10;
+parameter WR_DATA_WIDTH = 9;
+parameter RD_DATA_WIDTH = 36;
+parameter BE_WIDTH = 1;
+
+input wire WEN_i;
+input wire REN_i;
+input wire clock0;
+input wire clock1;
+input wire [WR_ADDR_WIDTH-1 :0] WR_ADDR_i;
+input wire [RD_ADDR_WIDTH-1 :0] RD_ADDR_i;
+input wire [WR_DATA_WIDTH-1 :0] WDATA_i;
+output wire [RD_DATA_WIDTH-1 :0] RDATA_o;
+
+RAM_36K_BLK #(
+              .WR_ADDR_WIDTH(WR_ADDR_WIDTH),
+              .RD_ADDR_WIDTH(RD_ADDR_WIDTH),
+              .WR_DATA_WIDTH(WR_DATA_WIDTH),
+              .RD_DATA_WIDTH(RD_DATA_WIDTH),
+              .BE_WIDTH(BE_WIDTH)
+              ) spram_x36_inst (
+              
+              .WEN_i(WEN_i),
+              .WR_BE_i(1'b1),
+              .REN_i(REN_i),              
+              .WR_CLK_i(clock0),
+              .RD_CLK_i(clock1),
+              .WR_ADDR_i(WR_ADDR_i),
+              .RD_ADDR_i(RD_ADDR_i),
+              .WDATA_i(WDATA_i),
+              .RDATA_o(RDATA_o)
+              );
+              
+endmodule    
+
+module spram_18x2048_36x1024 (
+    WEN_i,
+    REN_i,
+    clock0,
+    clock1,
+    WR_ADDR_i,
+    RD_ADDR_i,
+    WDATA_i,
+    RDATA_o
+);
+
+parameter WR_ADDR_WIDTH = 11;
+parameter RD_ADDR_WIDTH = 10;
+parameter WR_DATA_WIDTH = 18;
+parameter RD_DATA_WIDTH = 36;
+parameter BE_WIDTH = 2;
+
+input wire WEN_i;
+input wire REN_i;
+input wire clock0;
+input wire clock1;
+input wire [WR_ADDR_WIDTH-1 :0] WR_ADDR_i;
+input wire [RD_ADDR_WIDTH-1 :0] RD_ADDR_i;
+input wire [WR_DATA_WIDTH-1 :0] WDATA_i;
+output wire [RD_DATA_WIDTH-1 :0] RDATA_o;
+
+RAM_36K_BLK #(
+              .WR_ADDR_WIDTH(WR_ADDR_WIDTH),
+              .RD_ADDR_WIDTH(RD_ADDR_WIDTH),
+              .WR_DATA_WIDTH(WR_DATA_WIDTH),
+              .RD_DATA_WIDTH(RD_DATA_WIDTH),
+              .BE_WIDTH(BE_WIDTH)
+              ) spram_x36_inst (
+              
+              .WEN_i(WEN_i),
+              .WR_BE_i(2'b11),
+              .REN_i(REN_i),              
+              .WR_CLK_i(clock0),
+              .RD_CLK_i(clock1),
+              .WR_ADDR_i(WR_ADDR_i),
+              .RD_ADDR_i(RD_ADDR_i),
+              .WDATA_i(WDATA_i),
+              .RDATA_o(RDATA_o)
+              );
+              
+endmodule   
+
+module spram_18x2048_9x4096 (
+    WEN_i,
+    REN_i,
+    clock0,
+    clock1,
+    WR_ADDR_i,
+    RD_ADDR_i,
+    WDATA_i,
+    RDATA_o
+);
+
+parameter WR_ADDR_WIDTH = 11;
+parameter RD_ADDR_WIDTH = 12;
+parameter WR_DATA_WIDTH = 18;
+parameter RD_DATA_WIDTH = 9;
+parameter BE_WIDTH = 2;
+
+input wire WEN_i;
+input wire REN_i;
+input wire clock0;
+input wire clock1;
+input wire [WR_ADDR_WIDTH-1 :0] WR_ADDR_i;
+input wire [RD_ADDR_WIDTH-1 :0] RD_ADDR_i;
+input wire [WR_DATA_WIDTH-1 :0] WDATA_i;
+output wire [RD_DATA_WIDTH-1 :0] RDATA_o;
+
+RAM_36K_BLK #(
+              .WR_ADDR_WIDTH(WR_ADDR_WIDTH),
+              .RD_ADDR_WIDTH(RD_ADDR_WIDTH),
+              .WR_DATA_WIDTH(WR_DATA_WIDTH),
+              .RD_DATA_WIDTH(RD_DATA_WIDTH),
+              .BE_WIDTH(BE_WIDTH)
+              ) spram_x36_inst (
+              
+              .WEN_i(WEN_i),
+              .WR_BE_i(2'b11),
+              .REN_i(REN_i),              
+              .WR_CLK_i(clock0),
+              .RD_CLK_i(clock1),
+              .WR_ADDR_i(WR_ADDR_i),
+              .RD_ADDR_i(RD_ADDR_i),
+              .WDATA_i(WDATA_i),
+              .RDATA_o(RDATA_o)
+              );
+              
+endmodule    
+
+module spram_36x1024_18x2048 (
+    WEN_i,
+    REN_i,
+    clock0,
+    clock1,
+    WR_ADDR_i,
+    RD_ADDR_i,
+    WDATA_i,
+    RDATA_o
+);
+
+parameter WR_ADDR_WIDTH = 10;
+parameter RD_ADDR_WIDTH = 11;
+parameter WR_DATA_WIDTH = 36;
+parameter RD_DATA_WIDTH = 18;
+parameter BE_WIDTH = 4;
+
+input wire WEN_i;
+input wire REN_i;
+input wire clock0;
+input wire clock1;
+input wire [WR_ADDR_WIDTH-1 :0] WR_ADDR_i;
+input wire [RD_ADDR_WIDTH-1 :0] RD_ADDR_i;
+input wire [WR_DATA_WIDTH-1 :0] WDATA_i;
+output wire [RD_DATA_WIDTH-1 :0] RDATA_o;
+
+RAM_36K_BLK #(
+              .WR_ADDR_WIDTH(WR_ADDR_WIDTH),
+              .RD_ADDR_WIDTH(RD_ADDR_WIDTH),
+              .WR_DATA_WIDTH(WR_DATA_WIDTH),
+              .RD_DATA_WIDTH(RD_DATA_WIDTH),
+              .BE_WIDTH(BE_WIDTH)
+              ) spram_x36_inst (
+              
+              .WEN_i(WEN_i),
+              .WR_BE_i(4'b1111),
+              .REN_i(REN_i),              
+              .WR_CLK_i(clock0),
+              .RD_CLK_i(clock1),
+              .WR_ADDR_i(WR_ADDR_i),
+              .RD_ADDR_i(RD_ADDR_i),
+              .WDATA_i(WDATA_i),
+              .RDATA_o(RDATA_o)
+              );
+              
+endmodule     
\ No newline at end of file
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_sdp/sim/Makefile b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_sdp/sim/Makefile
new file mode 100644
index 0000000..88ba3d5
--- /dev/null
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_sdp/sim/Makefile
@@ -0,0 +1,50 @@
+# Copyright 2020-2022 F4PGA Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+TESTBENCH = asymmetric_bram36k_sdp_tb.v
+POST_SYNTH = spram_9x4096_36x1024_post_synth spram_18x2048_36x1024_post_synth spram_18x2048_9x4096_post_synth spram_36x1024_18x2048_post_synth
+ADDR_WIDTH0 = 12 11 11 10
+DATA_WIDTH0 = 9 18 18 36
+ADDR_WIDTH1 = 10 10 12 11
+DATA_WIDTH1 = 36 36 9 18
+TOP = spram_9x4096_36x1024 spram_18x2048_36x1024 spram_18x2048_9x4096 spram_36x1024_18x2048
+ADDR0_DEFINES = $(foreach awidth0, $(ADDR_WIDTH0),-DADDR_WIDTH0="$(awidth0)")
+ADDR1_DEFINES = $(foreach awidth1, $(ADDR_WIDTH1),-DADDR_WIDTH1="$(awidth1)")
+DATA0_DEFINES = $(foreach dwidth0, $(DATA_WIDTH0),-DDATA_WIDTH0="$(dwidth0)")
+DATA1_DEFINES = $(foreach dwidth1, $(DATA_WIDTH1),-DDATA_WIDTH1="$(dwidth1)")
+TOP_DEFINES = $(foreach top, $(TOP),-DTOP="$(top)")
+VCD_DEFINES = $(foreach vcd, $(POST_SYNTH),-DVCD="$(vcd).vcd")
+
+SIM_LIBS = $(shell find ../../../../qlf_k6n10f -name "*.v" -not -name "*_map.v")
+
+define simulate_post_synth
+	@iverilog  -vvvv -g2005 $(word $(1),$(ADDR0_DEFINES)) $(word $(1),$(ADDR1_DEFINES)) $(word $(1),$(DATA0_DEFINES)) $(word $(1),$(DATA1_DEFINES)) $(word $(1),$(TOP_DEFINES)) $(word $(1),$(VCD_DEFINES)) -o $(word $(1),$(POST_SYNTH)).vvp $(word $(1),$(POST_SYNTH)).v $(SIM_LIBS) $(TESTBENCH) > $(word $(1),$(POST_SYNTH)).vvp.log 2>&1
+	@vvp -vvvv $(word $(1),$(POST_SYNTH)).vvp > $(word $(1),$(POST_SYNTH)).vcd.log 2>&1
+endef
+
+define clean_post_synth_sim
+	@rm -rf  $(word $(1),$(POST_SYNTH)).vcd $(word $(1),$(POST_SYNTH)).vvp $(word $(1),$(POST_SYNTH)).vvp.log $(word $(1),$(POST_SYNTH)).vcd.log
+endef
+
+sim:
+	$(call simulate_post_synth,1)
+	$(call clean_post_synth_sim,1)
+	$(call simulate_post_synth,2)
+	$(call clean_post_synth_sim,2)
+	$(call simulate_post_synth,3)
+	$(call clean_post_synth_sim,3)
+	$(call simulate_post_synth,4)
+	$(call clean_post_synth_sim,4)
\ No newline at end of file
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_sdp/sim/asymmetric_bram36k_sdp_tb.v b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_sdp/sim/asymmetric_bram36k_sdp_tb.v
new file mode 100644
index 0000000..38064a3
--- /dev/null
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_sdp/sim/asymmetric_bram36k_sdp_tb.v
@@ -0,0 +1,269 @@
+// Copyright 2020-2022 F4PGA Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//		 http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
+`timescale 1ns/1ps
+
+`define STRINGIFY(x) `"x`"
+
+module TB;
+	localparam PERIOD = 50;
+	localparam ADDR_INCR = 1;
+
+	reg clk_0;
+	reg clk_1;
+	reg rce;
+	reg [`ADDR_WIDTH1-1:0] ra;
+	wire [`DATA_WIDTH1-1:0] rq;
+	reg wce;
+	reg [`ADDR_WIDTH0-1:0] wa;
+	reg [`DATA_WIDTH0-1:0] wd;
+
+	initial clk_0 = 0;
+	initial clk_1 = 0;
+	initial ra = 0;
+	initial wa = 0;
+	initial wd = 0;
+	initial rce = 0;
+	initial wce = 0;
+	initial forever #(PERIOD / 2.0) clk_0 = ~clk_0;
+	initial begin
+		#(PERIOD / 4.0);
+		forever #(PERIOD / 2.0) clk_1 = ~clk_1;
+	end
+	initial begin
+		$dumpfile(`STRINGIFY(`VCD));
+		$dumpvars;
+	end
+
+	integer a;
+	integer b;
+
+	reg done_0;
+	initial done_0 = 1'b0;
+	wire done_sim = done_0;
+
+	reg [`DATA_WIDTH1-1:0] expected_0;
+
+	reg read_test_0;
+	initial read_test_0 = 0;
+
+
+	wire error_0 = (read_test_0) ? (rq !== expected_0) : 0;
+
+	integer error_0_cnt = 0;
+
+	always @ (posedge clk_1)
+	begin
+		if (error_0)
+			error_0_cnt <= error_0_cnt + 1'b1;
+	end
+
+	case (`STRINGIFY(`TOP))
+	"spram_9x4096_36x1024": begin
+		initial #(1) begin
+			// Write data
+			for (a = 0; a < (1<<`ADDR_WIDTH0) ; a = a + ADDR_INCR) begin
+				@(negedge clk_0) begin
+					wa = a[`ADDR_WIDTH0-1:0];
+					wd = a[10:2];
+					wce = 1;
+				end
+				@(posedge clk_0) begin
+					#(PERIOD/10) wce = 0;
+				end
+			end
+			// Read data
+			read_test_0 = 1;
+			for (a = 0; a < (1<<`ADDR_WIDTH1); a = a + ADDR_INCR) begin
+				@(negedge clk_1) begin
+					ra = a;
+					rce = 1;
+				end
+				@(posedge clk_1) begin
+					expected_0 <= {a[8],a[8],a[7:0],a[7:0],a[8],a[8],a[7:0],a[7:0]};
+					#(PERIOD/10) rce = 0;
+					if ( rq !== expected_0) begin
+						$display("%d: PORT 0: FAIL: mismatch act=%x exp=%x at %x", $time, rq, expected_0, a);
+					end else begin
+						$display("%d: PORT 0: OK: act=%x exp=%x at %x", $time, rq, expected_0, a);
+					end
+				end
+			end
+			done_0 = 1'b1;
+			a = 0;
+		end
+	end
+	"spram_18x2048_36x1024": begin
+		initial #(1) begin
+			// Write data
+			for (a = 0; a < (1<<`ADDR_WIDTH0) ; a = a + ADDR_INCR) begin
+				@(negedge clk_0) begin
+					wa = a[`ADDR_WIDTH0-1:0];
+					wd = a[18:1];
+					wce = 1;
+				end
+				@(posedge clk_0) begin
+					#(PERIOD/10) wce = 0;
+				end
+			end
+			// Read data
+			read_test_0 = 1;
+			for (a = 0; a < (1<<`ADDR_WIDTH1); a = a + ADDR_INCR) begin
+				@(negedge clk_1) begin
+					ra = a;
+					rce = 1;
+				end
+				@(posedge clk_1) begin
+					expected_0 <= {a[17:0],a[17:0]};
+					#(PERIOD/10) rce = 0;
+					if ( rq !== expected_0) begin
+						$display("%d: PORT 0: FAIL: mismatch act=%x exp=%x at %x", $time, rq, expected_0, a);
+					end else begin
+						$display("%d: PORT 0: OK: act=%x exp=%x at %x", $time, rq, expected_0, a);
+					end
+				end
+			end
+			done_0 = 1'b1;
+			a = 0;
+		end
+	end	 
+	"spram_18x2048_9x4096": begin
+		initial #(1) begin
+			// Write data
+			for (a = 0; a < (1<<`ADDR_WIDTH0) ; a = a + ADDR_INCR) begin
+				@(negedge clk_0) begin
+					wa = a[`ADDR_WIDTH0-1:0];
+					wd = {a[8],a[8],a[7:0],a[7:0]};
+					wce = 1;
+				end
+				@(posedge clk_0) begin
+					#(PERIOD/10) wce = 0;
+				end
+			end
+			// Read data
+			read_test_0 = 1;
+			for (a = 0; a < (1<<`ADDR_WIDTH1); a = a + ADDR_INCR) begin
+				@(negedge clk_1) begin
+					ra = a;
+					rce = 1;
+				end
+				@(posedge clk_1) begin
+					expected_0 <= {a[9:1]};
+					#(PERIOD/10) rce = 0;
+					if ( rq !== expected_0) begin
+						$display("%d: PORT 0: FAIL: mismatch act=%x exp=%x at %x", $time, rq, expected_0, a);
+					end else begin
+						$display("%d: PORT 0: OK: act=%x exp=%x at %x", $time, rq, expected_0, a);
+					end
+				end
+			end
+			done_0 = 1'b1;
+			a = 0;
+		end
+	end
+	"spram_36x1024_18x2048": begin
+		initial #(1) begin
+			// Write data
+			for (a = 0; a < (1<<`ADDR_WIDTH0) ; a = a + ADDR_INCR) begin
+				@(negedge clk_0) begin
+					wa = a[`ADDR_WIDTH0-1:0];
+					wd = {a[17:0],a[17:0]};
+					wce = 1;
+				end
+				@(posedge clk_0) begin
+					#(PERIOD/10) wce = 0;
+				end
+			end
+			// Read data
+			read_test_0 = 1;
+			for (a = 0; a < (1<<`ADDR_WIDTH1); a = a + ADDR_INCR) begin
+				@(negedge clk_1) begin
+					ra = a;
+					rce = 1;
+				end
+				@(posedge clk_1) begin
+					expected_0 <= {a[18:1]};
+					#(PERIOD/10) rce = 0;
+					if ( rq !== expected_0) begin
+						$display("%d: PORT 0: FAIL: mismatch act=%x exp=%x at %x", $time, rq, expected_0, a);
+					end else begin
+						$display("%d: PORT 0: OK: act=%x exp=%x at %x", $time, rq, expected_0, a);
+					end
+				end
+			end
+			done_0 = 1'b1;
+			a = 0;
+		end
+	end
+	endcase
+
+	// Scan for simulation finish
+	always @(posedge clk_1) begin
+		if (done_sim)
+			$finish_and_return( (error_0_cnt == 0) ? 0 : -1 );
+	end
+
+	case (`STRINGIFY(`TOP))
+		"spram_9x4096_36x1024": begin
+			spram_9x4096_36x1024 #() bram (
+				.clock0(clk_0),
+				.clock1(clk_1),				 
+				.REN_i(rce),
+				.RD_ADDR_i(ra),
+				.RDATA_o(rq),
+				.WEN_i(wce),
+				.WR_ADDR_i(wa),
+				.WDATA_i(wd)
+			);
+		end
+		"spram_18x2048_36x1024": begin
+			spram_18x2048_36x1024 #() bram (
+				.clock0(clk_0),
+				.clock1(clk_1),				 
+				.REN_i(rce),
+				.RD_ADDR_i(ra),
+				.RDATA_o(rq),
+				.WEN_i(wce),
+				.WR_ADDR_i(wa),
+				.WDATA_i(wd)
+			);
+		end
+		"spram_18x2048_9x4096": begin
+			spram_18x2048_9x4096 #() bram (
+				.clock0(clk_0),
+				.clock1(clk_1),				 
+				.REN_i(rce),
+				.RD_ADDR_i(ra),
+				.RDATA_o(rq),
+				.WEN_i(wce),
+				.WR_ADDR_i(wa),
+				.WDATA_i(wd)
+			);
+		end
+		"spram_36x1024_18x2048": begin
+			spram_36x1024_18x2048 #() bram (
+				.clock0(clk_0),
+				.clock1(clk_1),				 
+				.REN_i(rce),
+				.RD_ADDR_i(ra),
+				.RDATA_o(rq),
+				.WEN_i(wce),
+				.WR_ADDR_i(wa),
+				.WDATA_i(wd)
+			);
+		end
+	endcase
+endmodule
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_sfifo/asymmetric_bram36k_sfifo.tcl b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_sfifo/asymmetric_bram36k_sfifo.tcl
new file mode 100644
index 0000000..4b24470
--- /dev/null
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_sfifo/asymmetric_bram36k_sfifo.tcl
@@ -0,0 +1,49 @@
+yosys -import
+
+if { [info procs ql-qlf-k6n10f] == {} } { plugin -i ql-qlf }
+yosys -import  ;
+
+read_verilog $::env(DESIGN_TOP).v
+design -save asymmetric_bram36k_sfifo
+
+select f4096x9_1024x36
+select *
+synth_quicklogic -family qlf_k6n10f -top f4096x9_1024x36 -bram_types
+opt_expr -undriven
+opt_clean
+stat
+write_verilog sim/f4096x9_1024x36_post_synth.v
+select -assert-count 1 t:TDP36K_FIFO_SYNC_WR_X9_RD_X36_nonsplit
+
+select -clear
+design -load asymmetric_bram36k_sfifo
+select f2048x18_1024x36
+select *
+synth_quicklogic -family qlf_k6n10f -top f2048x18_1024x36 -bram_types
+opt_expr -undriven
+opt_clean
+stat
+write_verilog sim/f2048x18_1024x36_post_synth.v
+select -assert-count 1 t:TDP36K_FIFO_SYNC_WR_X18_RD_X36_nonsplit
+
+select -clear
+design -load asymmetric_bram36k_sfifo
+select f2048x18_4098x9
+select *
+synth_quicklogic -family qlf_k6n10f -top f2048x18_4098x9 -bram_types
+opt_expr -undriven
+opt_clean
+stat
+write_verilog sim/f2048x18_4098x9_post_synth.v
+select -assert-count 1 t:TDP36K_FIFO_SYNC_WR_X18_RD_X9_nonsplit
+
+select -clear
+design -load asymmetric_bram36k_sfifo
+select f1024x36_2048x18
+select *
+synth_quicklogic -family qlf_k6n10f -top f1024x36_2048x18 -bram_types
+opt_expr -undriven
+opt_clean
+stat
+write_verilog sim/f1024x36_2048x18_post_synth.v
+select -assert-count 1 t:TDP36K_FIFO_SYNC_WR_X36_RD_X18_nonsplit
\ No newline at end of file
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_sfifo/asymmetric_bram36k_sfifo.v b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_sfifo/asymmetric_bram36k_sfifo.v
new file mode 100644
index 0000000..c0b6507
--- /dev/null
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_sfifo/asymmetric_bram36k_sfifo.v
@@ -0,0 +1,175 @@
+// Copyright 2020-2022 F4PGA Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
+module f4096x9_1024x36 (DIN,PUSH,POP,clock0,Async_Flush,Almost_Full,Almost_Empty,Full,Empty,Full_Watermark,Empty_Watermark,Overrun_Error,Underrun_Error,DOUT);
+
+parameter WR_DATA_WIDTH = 9;
+parameter RD_DATA_WIDTH = 36;
+parameter UPAE_DBITS = 12'd10;
+parameter UPAF_DBITS = 12'd10;
+
+input clock0;
+input PUSH,POP;
+input [WR_DATA_WIDTH-1:0] DIN;
+input Async_Flush;
+output [RD_DATA_WIDTH-1:0] DOUT;
+output Almost_Full,Almost_Empty;
+output Full, Empty;
+output Full_Watermark, Empty_Watermark;
+output Overrun_Error, Underrun_Error;
+
+SFIFO_36K_BLK  # (.WR_DATA_WIDTH(WR_DATA_WIDTH),.RD_DATA_WIDTH(RD_DATA_WIDTH),.UPAE_DBITS(UPAE_DBITS),.UPAF_DBITS(UPAF_DBITS)
+                  )
+  FIFO_INST    (
+                .DIN(DIN),
+                .PUSH(PUSH),
+                .POP(POP),
+                .CLK(clock0),
+                .Async_Flush(Async_Flush),
+                
+                .Overrun_Error(Overrun_Error),
+                .Full_Watermark(Full_Watermark),
+                .Almost_Full(Almost_Full),
+                .Full(Full),
+                
+                .Underrun_Error(Underrun_Error),
+                .Empty_Watermark(Empty_Watermark),
+                .Almost_Empty(Almost_Empty),
+                .Empty(Empty),
+
+                .DOUT(DOUT)
+                );
+endmodule
+
+module f2048x18_1024x36 (DIN,PUSH,POP,clock0,Async_Flush,Almost_Full,Almost_Empty,Full,Empty,Full_Watermark,Empty_Watermark,Overrun_Error,Underrun_Error,DOUT);
+
+parameter WR_DATA_WIDTH = 18;
+parameter RD_DATA_WIDTH = 36;
+parameter UPAE_DBITS = 12'd10;
+parameter UPAF_DBITS = 12'd10;
+
+input clock0;
+input PUSH,POP;
+input [WR_DATA_WIDTH-1:0] DIN;
+input Async_Flush;
+output [RD_DATA_WIDTH-1:0] DOUT;
+output Almost_Full,Almost_Empty;
+output Full, Empty;
+output Full_Watermark, Empty_Watermark;
+output Overrun_Error, Underrun_Error;
+
+SFIFO_36K_BLK  # (.WR_DATA_WIDTH(WR_DATA_WIDTH),.RD_DATA_WIDTH(RD_DATA_WIDTH),.UPAE_DBITS(UPAE_DBITS),.UPAF_DBITS(UPAF_DBITS)
+                  )
+  FIFO_INST    (
+                .DIN(DIN),
+                .PUSH(PUSH),
+                .POP(POP),
+                .CLK(clock0),
+                .Async_Flush(Async_Flush),
+                
+                .Overrun_Error(Overrun_Error),
+                .Full_Watermark(Full_Watermark),
+                .Almost_Full(Almost_Full),
+                .Full(Full),
+                
+                .Underrun_Error(Underrun_Error),
+                .Empty_Watermark(Empty_Watermark),
+                .Almost_Empty(Almost_Empty),
+                .Empty(Empty),
+
+                .DOUT(DOUT)
+                );
+endmodule
+
+module f2048x18_4098x9 (DIN,PUSH,POP,clock0,Async_Flush,Almost_Full,Almost_Empty,Full,Empty,Full_Watermark,Empty_Watermark,Overrun_Error,Underrun_Error,DOUT);
+
+parameter WR_DATA_WIDTH = 18;
+parameter RD_DATA_WIDTH = 9;
+parameter UPAE_DBITS = 12'd10;
+parameter UPAF_DBITS = 12'd10;
+
+input clock0;
+input PUSH,POP;
+input [WR_DATA_WIDTH-1:0] DIN;
+input Async_Flush;
+output [RD_DATA_WIDTH-1:0] DOUT;
+output Almost_Full,Almost_Empty;
+output Full, Empty;
+output Full_Watermark, Empty_Watermark;
+output Overrun_Error, Underrun_Error;
+
+SFIFO_36K_BLK  # (.WR_DATA_WIDTH(WR_DATA_WIDTH),.RD_DATA_WIDTH(RD_DATA_WIDTH),.UPAE_DBITS(UPAE_DBITS),.UPAF_DBITS(UPAF_DBITS)
+                  )
+  FIFO_INST    (
+                .DIN(DIN),
+                .PUSH(PUSH),
+                .POP(POP),
+                .CLK(clock0),
+                .Async_Flush(Async_Flush),
+                
+                .Overrun_Error(Overrun_Error),
+                .Full_Watermark(Full_Watermark),
+                .Almost_Full(Almost_Full),
+                .Full(Full),
+                
+                .Underrun_Error(Underrun_Error),
+                .Empty_Watermark(Empty_Watermark),
+                .Almost_Empty(Almost_Empty),
+                .Empty(Empty),
+
+                .DOUT(DOUT)
+                );
+endmodule
+
+module f1024x36_2048x18 (DIN,PUSH,POP,clock0,Async_Flush,Almost_Full,Almost_Empty,Full,Empty,Full_Watermark,Empty_Watermark,Overrun_Error,Underrun_Error,DOUT);
+
+parameter WR_DATA_WIDTH = 36;
+parameter RD_DATA_WIDTH = 18;
+parameter UPAE_DBITS = 12'd10;
+parameter UPAF_DBITS = 12'd10;
+
+input clock0;
+input PUSH,POP;
+input [WR_DATA_WIDTH-1:0] DIN;
+input Async_Flush;
+output [RD_DATA_WIDTH-1:0] DOUT;
+output Almost_Full,Almost_Empty;
+output Full, Empty;
+output Full_Watermark, Empty_Watermark;
+output Overrun_Error, Underrun_Error;
+
+SFIFO_36K_BLK  # (.WR_DATA_WIDTH(WR_DATA_WIDTH),.RD_DATA_WIDTH(RD_DATA_WIDTH),.UPAE_DBITS(UPAE_DBITS),.UPAF_DBITS(UPAF_DBITS)
+                  )
+  FIFO_INST    (
+                .DIN(DIN),
+                .PUSH(PUSH),
+                .POP(POP),
+                .CLK(clock0),
+                .Async_Flush(Async_Flush),
+                
+                .Overrun_Error(Overrun_Error),
+                .Full_Watermark(Full_Watermark),
+                .Almost_Full(Almost_Full),
+                .Full(Full),
+                
+                .Underrun_Error(Underrun_Error),
+                .Empty_Watermark(Empty_Watermark),
+                .Almost_Empty(Almost_Empty),
+                .Empty(Empty),
+
+                .DOUT(DOUT)
+                );
+endmodule
\ No newline at end of file
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_sfifo/sim/Makefile b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_sfifo/sim/Makefile
new file mode 100644
index 0000000..e13baa3
--- /dev/null
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_sfifo/sim/Makefile
@@ -0,0 +1,50 @@
+# Copyright 2020-2022 F4PGA Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+TESTBENCH = asymmetric_bram36k_sfifo_tb.v
+POST_SYNTH = f4096x9_1024x36_post_synth f2048x18_1024x36_post_synth f2048x18_4098x9_post_synth f1024x36_2048x18_post_synth
+ADDR_WIDTH0 = 12 11 11 10
+DATA_WIDTH0 = 9 18 18 36
+ADDR_WIDTH1 = 10 10 12 11
+DATA_WIDTH1 = 36 36 9 18
+TOP = f4096x9_1024x36 f2048x18_1024x36 f2048x18_4098x9 f1024x36_2048x18
+ADDR0_DEFINES = $(foreach awidth0, $(ADDR_WIDTH0),-DADDR_WIDTH0="$(awidth0)")
+ADDR1_DEFINES = $(foreach awidth1, $(ADDR_WIDTH1),-DADDR_WIDTH1="$(awidth1)")
+DATA0_DEFINES = $(foreach dwidth0, $(DATA_WIDTH0),-DDATA_WIDTH0="$(dwidth0)")
+DATA1_DEFINES = $(foreach dwidth1, $(DATA_WIDTH1),-DDATA_WIDTH1="$(dwidth1)")
+TOP_DEFINES = $(foreach top, $(TOP),-DTOP="$(top)")
+VCD_DEFINES = $(foreach vcd, $(POST_SYNTH),-DVCD="$(vcd).vcd")
+
+SIM_LIBS = $(shell find ../../../../qlf_k6n10f -name "*.v" -not -name "*_map.v")
+
+define simulate_post_synth
+	@iverilog  -vvvv -g2005 $(word $(1),$(ADDR0_DEFINES)) $(word $(1),$(ADDR1_DEFINES)) $(word $(1),$(DATA0_DEFINES)) $(word $(1),$(DATA1_DEFINES)) $(word $(1),$(TOP_DEFINES)) $(word $(1),$(VCD_DEFINES)) -o $(word $(1),$(POST_SYNTH)).vvp $(word $(1),$(POST_SYNTH)).v $(SIM_LIBS) $(TESTBENCH) > $(word $(1),$(POST_SYNTH)).vvp.log 2>&1
+	@vvp -vvvv $(word $(1),$(POST_SYNTH)).vvp > $(word $(1),$(POST_SYNTH)).vcd.log 2>&1
+endef
+
+define clean_post_synth_sim
+	@rm -rf  $(word $(1),$(POST_SYNTH)).vcd $(word $(1),$(POST_SYNTH)).vvp $(word $(1),$(POST_SYNTH)).vvp.log $(word $(1),$(POST_SYNTH)).vcd.log
+endef
+
+sim:
+	$(call simulate_post_synth,1)
+	$(call clean_post_synth_sim,1)
+	$(call simulate_post_synth,2)
+	$(call clean_post_synth_sim,2)
+	$(call simulate_post_synth,3)
+	$(call clean_post_synth_sim,3)
+	$(call simulate_post_synth,4)
+	$(call clean_post_synth_sim,4)
\ No newline at end of file
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_sfifo/sim/asymmetric_bram36k_sfifo_tb.v b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_sfifo/sim/asymmetric_bram36k_sfifo_tb.v
new file mode 100644
index 0000000..b1c753c
--- /dev/null
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_sfifo/sim/asymmetric_bram36k_sfifo_tb.v
@@ -0,0 +1,285 @@
+// Copyright 2020-2022 F4PGA Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//		 http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
+`timescale 1ns/1ps
+
+`define STRINGIFY(x) `"x`"
+
+module TB;
+	localparam PERIOD = 30;
+	localparam ADDR_INCR = 1;
+
+	reg clk0;
+	reg flush;
+	reg pop;
+	wire [`DATA_WIDTH1-1:0] dout;
+	reg push;
+	reg [`DATA_WIDTH0-1:0] din;
+	wire almost_full,almost_empty;
+	wire full, empty;
+	wire full_watermark, empty_watermark;
+	wire overrun_error, underrun_error;
+
+	initial 
+	begin
+		clk0 = 0;
+		pop = 0;
+		push = 0;
+		flush = 1;
+		din = 0;
+		#40
+		flush = 0;
+	end
+	
+	initial forever #(PERIOD / 3.0) clk0 = ~clk0;
+	
+	initial begin
+		$dumpfile(`STRINGIFY(`VCD));
+		$dumpvars;
+	end
+
+	integer a;
+
+	reg done;
+	initial done = 1'b0;
+	
+	reg read_test;
+	initial read_test = 0;
+
+	reg [`DATA_WIDTH1-1:0] expected;
+	initial expected = 0;
+
+	wire error = (read_test) ? dout !== expected : 0;
+
+	integer error_cnt = 0;
+	always @ (posedge clk0)
+	begin
+		if (error)
+			error_cnt <= error_cnt + 1'b1; 
+	end
+
+	case (`STRINGIFY(`TOP))
+	"f4096x9_1024x36": begin
+		initial #(50) begin
+			// Write data
+			for (a = 0; a < (1<<`ADDR_WIDTH0) ; a = a + ADDR_INCR) begin
+				@(negedge clk0) begin
+					din = a[10:2];
+					push = 1;
+				end
+				@(posedge clk0) begin
+					#(PERIOD/10) push = 0;
+				end
+			end
+			// Read data
+			read_test = 1;
+			for (a = 0; a < (1<<`ADDR_WIDTH1); a = a + ADDR_INCR) begin
+				@(posedge clk0) begin
+					expected <= {a[8],a[8],a[7:0],a[7:0],a[8],a[8],a[7:0],a[7:0]};
+					#(PERIOD/10) pop = 0;
+					if ( dout !== expected) begin
+						$display("%d: PORT 0: FAIL: mismatch act=%x exp=%x at %x", $time, dout, expected, a);
+					end else begin
+						$display("%d: PORT 0: OK: act=%x exp=%x at %x", $time, dout, expected, a);
+					end
+				end
+				@(negedge clk0) begin
+					pop = 1;
+				end
+			end
+			done = 1'b1;
+			a = 0;
+		end
+	end
+	"f2048x18_1024x36": begin
+		initial #(50) begin
+			// Write data
+			for (a = 0; a < (1<<`ADDR_WIDTH0) ; a = a + ADDR_INCR) begin
+				@(negedge clk0) begin
+					din = a[18:1];
+					push = 1;
+				end
+				@(posedge clk0) begin
+					#(PERIOD/10) push = 0;
+				end
+			end
+			// Read data
+			read_test = 1;
+			for (a = 0; a < (1<<`ADDR_WIDTH1); a = a + ADDR_INCR) begin
+				@(posedge clk0) begin
+					expected <= {a[17:0],a[17:0]};
+					#(PERIOD/10) pop = 0;
+					if ( dout !== expected) begin
+						$display("%d: PORT 0: FAIL: mismatch act=%x exp=%x at %x", $time, dout, expected, a);
+					end else begin
+						$display("%d: PORT 0: OK: act=%x exp=%x at %x", $time, dout, expected, a);
+					end
+				end
+				@(negedge clk0) begin
+					pop = 1;
+				end
+			end
+			done = 1'b1;
+			a = 0;
+		end
+	end	 
+	"f2048x18_4098x9": begin
+		initial #(50) begin
+			// Write data
+			for (a = 0; a < (1<<`ADDR_WIDTH0) ; a = a + ADDR_INCR) begin
+				@(negedge clk0) begin
+					din = {a[8],a[8],a[7:0],a[7:0]};
+					push = 1;
+				end
+				@(posedge clk0) begin
+					#(PERIOD/10) push = 0;
+				end
+			end
+			// Read data
+			read_test = 1;
+			for (a = 0; a < (1<<`ADDR_WIDTH1); a = a + ADDR_INCR) begin
+				@(posedge clk0) begin
+					expected <= {a[9:1]};
+					#(PERIOD/10) pop = 0;
+					if ( dout !== expected) begin
+						$display("%d: PORT 0: FAIL: mismatch act=%x exp=%x at %x", $time, dout, expected, a);
+					end else begin
+						$display("%d: PORT 0: OK: act=%x exp=%x at %x", $time, dout, expected, a);
+					end
+				end
+				@(negedge clk0) begin
+					pop = 1;
+				end
+			end
+			done = 1'b1;
+			a = 0;
+		end
+	end
+	"f1024x36_2048x18": begin
+		initial #(50) begin
+			// Write data
+			for (a = 0; a < (1<<`ADDR_WIDTH0) ; a = a + ADDR_INCR) begin
+				@(negedge clk0) begin
+					din = {a[17:0],a[17:0]};
+					push = 1;
+				end
+				@(posedge clk0) begin
+					#(PERIOD/10) push = 0;
+				end
+			end
+			// Read data
+			read_test = 1;
+			for (a = 0; a < (1<<`ADDR_WIDTH1); a = a + ADDR_INCR) begin
+				@(posedge clk0) begin
+					expected <= {a[18:1]};
+					#(PERIOD/10) pop = 0;
+					if ( dout !== expected) begin
+						$display("%d: PORT 0: FAIL: mismatch act=%x exp=%x at %x", $time, dout, expected, a);
+					end else begin
+						$display("%d: PORT 0: OK: act=%x exp=%x at %x", $time, dout, expected, a);
+					end
+				end
+				@(negedge clk0) begin
+					pop = 1;
+				end
+			end
+			done = 1'b1;
+			a = 0;
+		end
+	end
+	endcase
+
+	// Scan for simulation finish
+	always @(posedge clk0) begin
+		if (done)
+			$finish_and_return( (error_cnt == 0) ? 0 : -1 );
+	end
+
+	case (`STRINGIFY(`TOP))
+		"f4096x9_1024x36": begin
+			f4096x9_1024x36 #() afifo (
+				.DIN(din),
+				.PUSH(push),
+				.POP(pop),
+				.clock0(clk0),
+				.Async_Flush(flush),
+				.Almost_Full(almost_full),
+				.Almost_Empty(almost_empty),
+				.Full(full),
+				.Empty(empty),
+				.Full_Watermark(full_watermark),
+				.Empty_Watermark(empty_watermark),
+				.Overrun_Error(overrun_error),
+				.Underrun_Error(underrun_error),
+				.DOUT(dout)
+			);
+		end
+		"f2048x18_1024x36": begin
+			f2048x18_1024x36 #() afifo (
+				.DIN(din),
+				.PUSH(push),
+				.POP(pop),
+				.clock0(clk0),
+				.Async_Flush(flush),
+				.Almost_Full(almost_full),
+				.Almost_Empty(almost_empty),
+				.Full(full),
+				.Empty(empty),
+				.Full_Watermark(full_watermark),
+				.Empty_Watermark(empty_watermark),
+				.Overrun_Error(overrun_error),
+				.Underrun_Error(underrun_error),
+				.DOUT(dout)
+			);
+		end
+		"f2048x18_4098x9": begin
+			f2048x18_4098x9 #() afifo (
+				.DIN(din),
+				.PUSH(push),
+				.POP(pop),
+				.clock0(clk0),
+				.Async_Flush(flush),
+				.Almost_Full(almost_full),
+				.Almost_Empty(almost_empty),
+				.Full(full),
+				.Empty(empty),
+				.Full_Watermark(full_watermark),
+				.Empty_Watermark(empty_watermark),
+				.Overrun_Error(overrun_error),
+				.Underrun_Error(underrun_error),
+				.DOUT(dout)
+			);
+		end
+		"f1024x36_2048x18": begin
+			f1024x36_2048x18 #() afifo (
+				.DIN(din),
+				.PUSH(push),
+				.POP(pop),
+				.clock0(clk0),
+				.Async_Flush(flush),
+				.Almost_Full(almost_full),
+				.Almost_Empty(almost_empty),
+				.Full(full),
+				.Empty(empty),
+				.Full_Watermark(full_watermark),
+				.Empty_Watermark(empty_watermark),
+				.Overrun_Error(overrun_error),
+				.Underrun_Error(underrun_error),
+				.DOUT(dout)
+			);
+		end
+	endcase
+endmodule
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_afifo/bram18k_afifo.tcl b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_afifo/bram18k_afifo.tcl
new file mode 100644
index 0000000..99c7405
--- /dev/null
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_afifo/bram18k_afifo.tcl
@@ -0,0 +1,49 @@
+yosys -import
+
+if { [info procs ql-qlf-k6n10f] == {} } { plugin -i ql-qlf }
+yosys -import  ;
+
+read_verilog $::env(DESIGN_TOP).v
+design -save bram18k_afifo
+
+select af1024x18_1024x18
+select *
+synth_quicklogic -family qlf_k6n10f -top af1024x18_1024x18 -bram_types
+opt_expr -undriven
+opt_clean
+stat
+write_verilog sim/af1024x18_1024x18_post_synth.v
+select -assert-count 1 t:TDP36K_FIFO_ASYNC_WR_X18_RD_X18_split
+
+select -clear
+design -load bram18k_afifo
+select af1024x16_1024x16
+select *
+synth_quicklogic -family qlf_k6n10f -top af1024x16_1024x16 -bram_types
+opt_expr -undriven
+opt_clean
+stat
+write_verilog sim/af1024x16_1024x16_post_synth.v
+select -assert-count 1 t:TDP36K_FIFO_ASYNC_WR_X18_RD_X18_split
+
+select -clear
+design -load bram18k_afifo
+select af2048x9_2048x9
+select *
+synth_quicklogic -family qlf_k6n10f -top af2048x9_2048x9 -bram_types
+opt_expr -undriven
+opt_clean
+stat
+write_verilog sim/af2048x9_2048x9_post_synth.v
+select -assert-count 1 t:TDP36K_FIFO_ASYNC_WR_X9_RD_X9_split
+
+select -clear
+design -load bram18k_afifo
+select af2048x8_2048x8
+select *
+synth_quicklogic -family qlf_k6n10f -top af2048x8_2048x8 -bram_types
+opt_expr -undriven
+opt_clean
+stat
+write_verilog sim/af2048x8_2048x8_post_synth.v
+select -assert-count 1 t:TDP36K_FIFO_ASYNC_WR_X9_RD_X9_split
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_afifo/bram18k_afifo.v b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_afifo/bram18k_afifo.v
new file mode 100644
index 0000000..bd1fa13
--- /dev/null
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_afifo/bram18k_afifo.v
@@ -0,0 +1,179 @@
+// Copyright 2020-2022 F4PGA Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
+module af1024x18_1024x18 (DIN,PUSH,POP,clock0,clock1,Async_Flush,Almost_Full,Almost_Empty,Full,Empty,Full_Watermark,Empty_Watermark,Overrun_Error,Underrun_Error,DOUT);
+
+parameter WR_DATA_WIDTH = 18;
+parameter RD_DATA_WIDTH = 18;
+parameter UPAE_DBITS = 11'd10;
+parameter UPAF_DBITS = 11'd10;
+
+input clock0,clock1;
+input PUSH,POP;
+input [WR_DATA_WIDTH-1:0] DIN;
+input Async_Flush;
+output [RD_DATA_WIDTH-1:0] DOUT;
+output Almost_Full,Almost_Empty;
+output Full, Empty;
+output Full_Watermark, Empty_Watermark;
+output Overrun_Error, Underrun_Error;
+
+AFIFO_18K_BLK  # (.WR_DATA_WIDTH(WR_DATA_WIDTH),.RD_DATA_WIDTH(RD_DATA_WIDTH),.UPAE_DBITS(UPAE_DBITS),.UPAF_DBITS(UPAF_DBITS)
+                  )
+  FIFO_INST    (
+                .DIN(DIN),
+                .PUSH(PUSH),
+                .POP(POP),
+                .Push_Clk(clock0),
+                .Pop_Clk(clock1),
+                .Async_Flush(Async_Flush),
+                
+                .Overrun_Error(Overrun_Error),
+                .Full_Watermark(Full_Watermark),
+                .Almost_Full(Almost_Full),
+                .Full(Full),
+                
+                .Underrun_Error(Underrun_Error),
+                .Empty_Watermark(Empty_Watermark),
+                .Almost_Empty(Almost_Empty),
+                .Empty(Empty),
+
+                .DOUT(DOUT)
+                );
+endmodule
+
+module af1024x16_1024x16 (DIN,PUSH,POP,clock0,clock1,Async_Flush,Almost_Full,Almost_Empty,Full,Empty,Full_Watermark,Empty_Watermark,Overrun_Error,Underrun_Error,DOUT);
+
+parameter WR_DATA_WIDTH = 16;
+parameter RD_DATA_WIDTH = 16;
+parameter UPAE_DBITS = 11'd10;
+parameter UPAF_DBITS = 11'd10;
+
+input clock0,clock1;
+input PUSH,POP;
+input [WR_DATA_WIDTH-1:0] DIN;
+input Async_Flush;
+output [RD_DATA_WIDTH-1:0] DOUT;
+output Almost_Full,Almost_Empty;
+output Full, Empty;
+output Full_Watermark, Empty_Watermark;
+output Overrun_Error, Underrun_Error;
+
+AFIFO_18K_BLK  # (.WR_DATA_WIDTH(WR_DATA_WIDTH),.RD_DATA_WIDTH(RD_DATA_WIDTH),.UPAE_DBITS(UPAE_DBITS),.UPAF_DBITS(UPAF_DBITS)
+                  )
+  FIFO_INST    (
+                .DIN(DIN),
+                .PUSH(PUSH),
+                .POP(POP),
+                .Push_Clk(clock0),
+                .Pop_Clk(clock1),
+                .Async_Flush(Async_Flush),
+                
+                .Overrun_Error(Overrun_Error),
+                .Full_Watermark(Full_Watermark),
+                .Almost_Full(Almost_Full),
+                .Full(Full),
+                
+                .Underrun_Error(Underrun_Error),
+                .Empty_Watermark(Empty_Watermark),
+                .Almost_Empty(Almost_Empty),
+                .Empty(Empty),
+
+                .DOUT(DOUT)
+                );
+endmodule
+
+module af2048x9_2048x9 (DIN,PUSH,POP,clock0,clock1,Async_Flush,Almost_Full,Almost_Empty,Full,Empty,Full_Watermark,Empty_Watermark,Overrun_Error,Underrun_Error,DOUT);
+
+parameter WR_DATA_WIDTH = 9;
+parameter RD_DATA_WIDTH = 9;
+parameter UPAE_DBITS = 11'd10;
+parameter UPAF_DBITS = 11'd10;
+
+input clock0,clock1;
+input PUSH,POP;
+input [WR_DATA_WIDTH-1:0] DIN;
+input Async_Flush;
+output [RD_DATA_WIDTH-1:0] DOUT;
+output Almost_Full,Almost_Empty;
+output Full, Empty;
+output Full_Watermark, Empty_Watermark;
+output Overrun_Error, Underrun_Error;
+
+AFIFO_18K_BLK  # (.WR_DATA_WIDTH(WR_DATA_WIDTH),.RD_DATA_WIDTH(RD_DATA_WIDTH),.UPAE_DBITS(UPAE_DBITS),.UPAF_DBITS(UPAF_DBITS)
+                  )
+  FIFO_INST    (
+                .DIN(DIN),
+                .PUSH(PUSH),
+                .POP(POP),
+                .Push_Clk(clock0),
+                .Pop_Clk(clock1),
+                .Async_Flush(Async_Flush),
+                
+                .Overrun_Error(Overrun_Error),
+                .Full_Watermark(Full_Watermark),
+                .Almost_Full(Almost_Full),
+                .Full(Full),
+                
+                .Underrun_Error(Underrun_Error),
+                .Empty_Watermark(Empty_Watermark),
+                .Almost_Empty(Almost_Empty),
+                .Empty(Empty),
+
+                .DOUT(DOUT)
+                );
+endmodule
+
+module af2048x8_2048x8 (DIN,PUSH,POP,clock0,clock1,Async_Flush,Almost_Full,Almost_Empty,Full,Empty,Full_Watermark,Empty_Watermark,Overrun_Error,Underrun_Error,DOUT);
+
+parameter WR_DATA_WIDTH = 8;
+parameter RD_DATA_WIDTH = 8;
+parameter UPAE_DBITS = 11'd10;
+parameter UPAF_DBITS = 11'd10;
+
+input clock0,clock1;
+input PUSH,POP;
+input [WR_DATA_WIDTH-1:0] DIN;
+input Async_Flush;
+output [RD_DATA_WIDTH-1:0] DOUT;
+output Almost_Full,Almost_Empty;
+output Full, Empty;
+output Full_Watermark, Empty_Watermark;
+output Overrun_Error, Underrun_Error;
+
+AFIFO_18K_BLK  # (.WR_DATA_WIDTH(WR_DATA_WIDTH),.RD_DATA_WIDTH(RD_DATA_WIDTH),.UPAE_DBITS(UPAE_DBITS),.UPAF_DBITS(UPAF_DBITS)
+                  )
+  FIFO_INST    (
+                .DIN(DIN),
+                .PUSH(PUSH),
+                .POP(POP),
+                .Push_Clk(clock0),
+                .Pop_Clk(clock1),
+                .Async_Flush(Async_Flush),
+                
+                .Overrun_Error(Overrun_Error),
+                .Full_Watermark(Full_Watermark),
+                .Almost_Full(Almost_Full),
+                .Full(Full),
+                
+                .Underrun_Error(Underrun_Error),
+                .Empty_Watermark(Empty_Watermark),
+                .Almost_Empty(Almost_Empty),
+                .Empty(Empty),
+
+                .DOUT(DOUT)
+                );
+endmodule
\ No newline at end of file
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_afifo/sim/Makefile b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_afifo/sim/Makefile
new file mode 100644
index 0000000..3c2bce7
--- /dev/null
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_afifo/sim/Makefile
@@ -0,0 +1,50 @@
+# Copyright 2020-2022 F4PGA Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+TESTBENCH = bram18k_afifo_tb.v
+POST_SYNTH = af1024x18_1024x18_post_synth af1024x16_1024x16_post_synth af2048x9_2048x9_post_synth af2048x8_2048x8_post_synth
+ADDR_WIDTH0 = 10 10 11 11
+DATA_WIDTH0 = 18 16 9 8
+ADDR_WIDTH1 = 10 10 11 11
+DATA_WIDTH1 = 18 16 9 8
+TOP = af1024x18_1024x18 af1024x16_1024x16 af2048x9_2048x9 af2048x8_2048x8
+ADDR0_DEFINES = $(foreach awidth0, $(ADDR_WIDTH0),-DADDR_WIDTH0="$(awidth0)")
+ADDR1_DEFINES = $(foreach awidth1, $(ADDR_WIDTH1),-DADDR_WIDTH1="$(awidth1)")
+DATA0_DEFINES = $(foreach dwidth0, $(DATA_WIDTH0),-DDATA_WIDTH0="$(dwidth0)")
+DATA1_DEFINES = $(foreach dwidth1, $(DATA_WIDTH1),-DDATA_WIDTH1="$(dwidth1)")
+TOP_DEFINES = $(foreach top, $(TOP),-DTOP="$(top)")
+VCD_DEFINES = $(foreach vcd, $(POST_SYNTH),-DVCD="$(vcd).vcd")
+
+SIM_LIBS = $(shell find ../../../../qlf_k6n10f -name "*.v" -not -name "*_map.v")
+
+define simulate_post_synth
+	@iverilog  -vvvv -g2005 $(word $(1),$(ADDR0_DEFINES)) $(word $(1),$(ADDR1_DEFINES)) $(word $(1),$(DATA0_DEFINES)) $(word $(1),$(DATA1_DEFINES)) $(word $(1),$(TOP_DEFINES)) $(word $(1),$(VCD_DEFINES)) -o $(word $(1),$(POST_SYNTH)).vvp $(word $(1),$(POST_SYNTH)).v $(SIM_LIBS) $(TESTBENCH) > $(word $(1),$(POST_SYNTH)).vvp.log 2>&1
+	@vvp -vvvv $(word $(1),$(POST_SYNTH)).vvp > $(word $(1),$(POST_SYNTH)).vcd.log 2>&1
+endef
+
+define clean_post_synth_sim
+	@rm -rf  $(word $(1),$(POST_SYNTH)).vcd $(word $(1),$(POST_SYNTH)).vvp $(word $(1),$(POST_SYNTH)).vvp.log $(word $(1),$(POST_SYNTH)).vcd.log
+endef
+
+sim:
+	$(call simulate_post_synth,1)
+	$(call clean_post_synth_sim,1)
+	$(call simulate_post_synth,2)
+	$(call clean_post_synth_sim,2)
+	$(call simulate_post_synth,3)
+	$(call clean_post_synth_sim,3)
+	$(call simulate_post_synth,4)
+	$(call clean_post_synth_sim,4)
\ No newline at end of file
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_afifo/sim/bram18k_afifo_tb.v b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_afifo/sim/bram18k_afifo_tb.v
new file mode 100644
index 0000000..1795312
--- /dev/null
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_afifo/sim/bram18k_afifo_tb.v
@@ -0,0 +1,195 @@
+// Copyright 2020-2022 F4PGA Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//		 http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
+`timescale 1ns/1ps
+
+`define STRINGIFY(x) `"x`"
+
+module TB;
+	localparam PERIOD = 30;
+	localparam ADDR_INCR = 1;
+
+	reg clk0;
+	reg clk1;
+	reg flush;
+	reg pop;
+	wire [`DATA_WIDTH1-1:0] dout;
+	reg push;
+	reg [`DATA_WIDTH0-1:0] din;
+	wire almost_full,almost_empty;
+	wire full, empty;
+	wire full_watermark, empty_watermark;
+	wire overrun_error, underrun_error;
+
+	initial 
+	begin
+		clk0 = 0;
+		clk1 = 0;
+		pop = 0;
+		push = 0;
+		flush = 1;
+		din = 0;
+		#40
+		flush = 0;
+	end
+	
+	initial forever #(PERIOD / 3.0) clk0 = ~clk0;
+	initial forever #(PERIOD / 2.0) clk1 = ~clk1;
+	
+	initial begin
+		$dumpfile(`STRINGIFY(`VCD));
+		$dumpvars;
+	end
+
+	integer a;
+
+	reg done;
+	initial done = 1'b0;
+ 
+	reg read_test;
+	initial read_test = 0;
+
+	reg [`DATA_WIDTH1-1:0] expected;
+	initial expected = 0;
+
+	always @(posedge clk1) begin
+		expected <= (a | (a << 20) | 20'h55000) & {`DATA_WIDTH1{1'b1}};
+	end
+
+	wire error = ((a != 0) && read_test) ? dout !== expected : 0;
+
+	integer error_cnt = 0;
+	always @ (posedge clk1)
+	begin
+		if (error)
+			error_cnt <= error_cnt + 1'b1; 
+	end
+
+	initial #(50) begin
+		@(posedge clk0)
+		// Write data
+		for (a = 0; a < (1<<`ADDR_WIDTH0); a = a + ADDR_INCR) begin
+			@(negedge clk0) begin
+				din = a | (a << 20) | 20'h55000;
+				push = 1;
+			end
+			@(posedge clk0) begin
+				#(PERIOD/10) push = 0;
+			end
+		end
+		// Read data
+		read_test = 1;
+		for (a = 0; a < (1<<`ADDR_WIDTH1); a = a + ADDR_INCR) begin
+			@(posedge clk1) begin
+				#(PERIOD/10) pop = 0;
+				if ( dout !== expected) begin
+					$display("%d: FAIL: mismatch act=%x exp=%x at %x", $time, dout, expected, a);
+				end else begin
+					$display("%d: OK: act=%x exp=%x at %x", $time, dout, expected, a);
+				end
+			end
+			@(negedge clk1) begin
+				pop = 1;
+			end
+		end
+		done = 1'b1;
+	end
+
+	// Scan for simulation finish
+	always @(posedge clk1) begin
+		if (done)
+			$finish_and_return( (error_cnt == 0) ? 0 : -1 );
+	end
+
+	case (`STRINGIFY(`TOP))
+		"af1024x18_1024x18": begin
+			af1024x18_1024x18 #() afifo (
+				.DIN(din),
+				.PUSH(push),
+				.POP(pop),
+				.clock0(clk0),
+				.clock1(clk1),
+				.Async_Flush(flush),
+				.Almost_Full(almost_full),
+				.Almost_Empty(almost_empty),
+				.Full(full),
+				.Empty(empty),
+				.Full_Watermark(full_watermark),
+				.Empty_Watermark(empty_watermark),
+				.Overrun_Error(overrun_error),
+				.Underrun_Error(underrun_error),
+				.DOUT(dout)
+			);
+		end
+		"af1024x16_1024x16": begin
+			af1024x16_1024x16 #() afifo (
+				.DIN(din),
+				.PUSH(push),
+				.POP(pop),
+				.clock0(clk0),
+				.clock1(clk1),
+				.Async_Flush(flush),
+				.Almost_Full(almost_full),
+				.Almost_Empty(almost_empty),
+				.Full(full),
+				.Empty(empty),
+				.Full_Watermark(full_watermark),
+				.Empty_Watermark(empty_watermark),
+				.Overrun_Error(overrun_error),
+				.Underrun_Error(underrun_error),
+				.DOUT(dout)
+			);
+		end
+		"af2048x9_2048x9": begin
+			af2048x9_2048x9 #() afifo (
+				.DIN(din),
+				.PUSH(push),
+				.POP(pop),
+				.clock0(clk0),
+				.clock1(clk1),
+				.Async_Flush(flush),
+				.Almost_Full(almost_full),
+				.Almost_Empty(almost_empty),
+				.Full(full),
+				.Empty(empty),
+				.Full_Watermark(full_watermark),
+				.Empty_Watermark(empty_watermark),
+				.Overrun_Error(overrun_error),
+				.Underrun_Error(underrun_error),
+				.DOUT(dout)
+			);
+		end		
+		"af2048x8_2048x8": begin
+			af2048x8_2048x8 #() afifo (
+				.DIN(din),
+				.PUSH(push),
+				.POP(pop),
+				.clock0(clk0),
+				.clock1(clk1),
+				.Async_Flush(flush),
+				.Almost_Full(almost_full),
+				.Almost_Empty(almost_empty),
+				.Full(full),
+				.Empty(empty),
+				.Full_Watermark(full_watermark),
+				.Empty_Watermark(empty_watermark),
+				.Overrun_Error(overrun_error),
+				.Underrun_Error(underrun_error),
+				.DOUT(dout)
+			);
+		end	
+	endcase
+endmodule
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_sdp/bram18k_sdp.tcl b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_sdp/bram18k_sdp.tcl
new file mode 100644
index 0000000..092d4c2
--- /dev/null
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_sdp/bram18k_sdp.tcl
@@ -0,0 +1,39 @@
+yosys -import
+
+if { [info procs ql-qlf-k6n10f] == {} } { plugin -i ql-qlf }
+yosys -import  ;
+
+read_verilog $::env(DESIGN_TOP).v
+design -save bram18k_sdp
+
+select spram_18x1024_2x
+select *
+synth_quicklogic -family qlf_k6n10f -top spram_18x1024_2x -bram_types
+opt_expr -undriven
+opt_clean
+stat
+write_verilog sim/spram_18x1024_2x_post_synth.v
+select -assert-count 2 t:TDP36K_BRAM_WR_X18_RD_X18_split
+
+select -clear
+design -load bram18k_sdp
+select spram_9x2048_x2
+select *
+synth_quicklogic -family qlf_k6n10f -top spram_9x2048_x2 -bram_types
+opt_expr -undriven
+opt_clean
+stat
+write_verilog sim/spram_9x2048_x2_post_synth.v
+select -assert-count 2 t:TDP36K_BRAM_WR_X9_RD_X9_split
+
+select -clear
+design -load bram18k_sdp
+select spram_9x2048_18x1024
+select *
+synth_quicklogic -family qlf_k6n10f -top spram_9x2048_18x1024 -bram_types
+opt_expr -undriven
+opt_clean
+stat
+write_verilog sim/spram_9x2048_18x1024_post_synth.v
+select -assert-count 1 t:TDP36K_BRAM_WR_X9_RD_X9_split
+select -assert-count 1 t:TDP36K_BRAM_WR_X18_RD_X18_split
\ No newline at end of file
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_sdp/bram18k_sdp.v b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_sdp/bram18k_sdp.v
new file mode 100644
index 0000000..a8ea0a2
--- /dev/null
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_sdp/bram18k_sdp.v
@@ -0,0 +1,276 @@
+// Copyright 2020-2022 F4PGA Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
+module spram_18x1024_2x (   
+    WEN0_i,
+    REN0_i,
+    clock0,
+    WR_ADDR0_i,
+    RD_ADDR0_i,
+    WDATA0_i,
+    RDATA0_o,
+    
+    WEN1_i,
+    REN1_i,
+    clock1,
+    WR_ADDR1_i,
+    RD_ADDR1_i,
+    WDATA1_i,
+    RDATA1_o
+);
+
+parameter WR_ADDR_WIDTH0 = 10;
+parameter RD_ADDR_WIDTH0 = 10;
+parameter WR_DATA_WIDTH0 = 18;
+parameter RD_DATA_WIDTH0 = 18;
+parameter BE_WIDTH0 = 2;
+
+parameter WR_ADDR_WIDTH1 = 10;
+parameter RD_ADDR_WIDTH1 = 10;
+parameter WR_DATA_WIDTH1 = 18;
+parameter RD_DATA_WIDTH1 = 18;
+parameter BE_WIDTH1 = 2;
+
+input wire WEN0_i;
+input wire REN0_i;
+input wire clock0;
+input wire [WR_ADDR_WIDTH0-1 :0] WR_ADDR0_i;
+input wire [RD_ADDR_WIDTH0-1 :0] RD_ADDR0_i;
+input wire [WR_DATA_WIDTH0-1 :0] WDATA0_i;
+output wire [RD_DATA_WIDTH0-1 :0] RDATA0_o;
+
+input wire WEN1_i;
+input wire REN1_i;
+input wire clock1;
+input wire [WR_ADDR_WIDTH0-1 :0] WR_ADDR1_i;
+input wire [RD_ADDR_WIDTH0-1 :0] RD_ADDR1_i;
+input wire [WR_DATA_WIDTH0-1 :0] WDATA1_i;
+output wire [RD_DATA_WIDTH0-1 :0] RDATA1_o;
+
+
+RAM_18K_BLK #(
+              .WR_ADDR_WIDTH(WR_ADDR_WIDTH0),
+              .RD_ADDR_WIDTH(RD_ADDR_WIDTH0),
+              .WR_DATA_WIDTH(WR_DATA_WIDTH0),
+              .RD_DATA_WIDTH(RD_DATA_WIDTH0),
+              .BE_WIDTH(BE_WIDTH0)
+              ) spram_x18_inst1 (
+              
+              .WEN_i(WEN0_i),
+              .WR_BE_i(2'b11),
+              .REN_i(REN0_i),              
+              .WR_CLK_i(clock0),
+              .RD_CLK_i(clock0),
+              .WR_ADDR_i(WR_ADDR0_i),
+              .RD_ADDR_i(RD_ADDR0_i),
+              .WDATA_i(WDATA0_i),
+              .RDATA_o(RDATA0_o)
+              );
+              
+RAM_18K_BLK #(
+              .WR_ADDR_WIDTH(WR_ADDR_WIDTH1),
+              .RD_ADDR_WIDTH(RD_ADDR_WIDTH1),
+              .WR_DATA_WIDTH(WR_DATA_WIDTH1),
+              .RD_DATA_WIDTH(RD_DATA_WIDTH1),
+              .BE_WIDTH(BE_WIDTH1)
+              ) spram_x18_inst2 (
+              
+              .WEN_i(WEN1_i),
+              .WR_BE_i(2'b11),
+              .REN_i(REN1_i),              
+              .WR_CLK_i(clock1),
+              .RD_CLK_i(clock1),
+              .WR_ADDR_i(WR_ADDR1_i),
+              .RD_ADDR_i(RD_ADDR1_i),
+              .WDATA_i(WDATA1_i),
+              .RDATA_o(RDATA1_o)
+              );
+              
+endmodule    
+
+module spram_9x2048_x2 (
+    WEN0_i,
+    REN0_i,
+    clock0,
+    WR_ADDR0_i,
+    RD_ADDR0_i,
+    WDATA0_i,
+    RDATA0_o,
+    
+    WEN1_i,
+    REN1_i,
+    clock1,
+    WR_ADDR1_i,
+    RD_ADDR1_i,
+    WDATA1_i,
+    RDATA1_o
+);
+
+parameter WR_ADDR_WIDTH0 = 11;
+parameter RD_ADDR_WIDTH0 = 11;
+parameter WR_DATA_WIDTH0 = 9;
+parameter RD_DATA_WIDTH0 = 9;
+parameter BE_WIDTH0 = 1;
+
+parameter WR_ADDR_WIDTH1 = 11;
+parameter RD_ADDR_WIDTH1 = 11;
+parameter WR_DATA_WIDTH1 = 9;
+parameter RD_DATA_WIDTH1 = 9;
+parameter BE_WIDTH1 = 1;
+
+input wire WEN0_i;
+input wire REN0_i;
+input wire clock0;
+input wire [WR_ADDR_WIDTH0-1 :0] WR_ADDR0_i;
+input wire [RD_ADDR_WIDTH0-1 :0] RD_ADDR0_i;
+input wire [WR_DATA_WIDTH0-1 :0] WDATA0_i;
+output wire [RD_DATA_WIDTH0-1 :0] RDATA0_o;
+
+input wire WEN1_i;
+input wire REN1_i;
+input wire clock1;
+input wire [WR_ADDR_WIDTH1-1 :0] WR_ADDR1_i;
+input wire [RD_ADDR_WIDTH1-1 :0] RD_ADDR1_i;
+input wire [WR_DATA_WIDTH1-1 :0] WDATA1_i;
+output wire [RD_DATA_WIDTH1-1 :0] RDATA1_o;
+
+
+RAM_18K_BLK #(
+              .WR_ADDR_WIDTH(WR_ADDR_WIDTH0),
+              .RD_ADDR_WIDTH(RD_ADDR_WIDTH0),
+              .WR_DATA_WIDTH(WR_DATA_WIDTH0),
+              .RD_DATA_WIDTH(RD_DATA_WIDTH0),
+              .BE_WIDTH(BE_WIDTH0)
+              ) spram_x18_inst1 (
+              
+              .WEN_i(WEN0_i),
+              .WR_BE_i(2'b11),
+              .REN_i(REN0_i),              
+              .WR_CLK_i(clock0),
+              .RD_CLK_i(clock0),
+              .WR_ADDR_i(WR_ADDR0_i),
+              .RD_ADDR_i(RD_ADDR0_i),
+              .WDATA_i(WDATA0_i),
+              .RDATA_o(RDATA0_o)
+              );
+              
+RAM_18K_BLK #(
+              .WR_ADDR_WIDTH(WR_ADDR_WIDTH1),
+              .RD_ADDR_WIDTH(RD_ADDR_WIDTH1),
+              .WR_DATA_WIDTH(WR_DATA_WIDTH1),
+              .RD_DATA_WIDTH(RD_DATA_WIDTH1),
+              .BE_WIDTH(BE_WIDTH1)
+              ) spram_x18_inst2 (
+              
+              .WEN_i(WEN1_i),
+              .WR_BE_i(2'b11),
+              .REN_i(REN1_i),              
+              .WR_CLK_i(clock1),
+              .RD_CLK_i(clock1),
+              .WR_ADDR_i(WR_ADDR1_i),
+              .RD_ADDR_i(RD_ADDR1_i),
+              .WDATA_i(WDATA1_i),
+              .RDATA_o(RDATA1_o)
+              );
+              
+endmodule    
+
+module spram_9x2048_18x1024 (
+    WEN0_i,
+    REN0_i,
+    clock0,
+    WR_ADDR0_i,
+    RD_ADDR0_i,
+    WDATA0_i,
+    RDATA0_o,
+    
+    WEN1_i,
+    REN1_i,
+    clock1,
+    WR_ADDR1_i,
+    RD_ADDR1_i,
+    WDATA1_i,
+    RDATA1_o
+);
+
+parameter WR_ADDR_WIDTH0 = 11;
+parameter RD_ADDR_WIDTH0 = 11;
+parameter WR_DATA_WIDTH0 = 9;
+parameter RD_DATA_WIDTH0 = 9;
+parameter BE_WIDTH0 = 1;
+
+parameter WR_ADDR_WIDTH1 = 10;
+parameter RD_ADDR_WIDTH1 = 10;
+parameter WR_DATA_WIDTH1 = 18;
+parameter RD_DATA_WIDTH1 = 18;
+parameter BE_WIDTH1 = 2;
+
+input wire WEN0_i;
+input wire REN0_i;
+input wire clock0;
+input wire [WR_ADDR_WIDTH0-1 :0] WR_ADDR0_i;
+input wire [RD_ADDR_WIDTH0-1 :0] RD_ADDR0_i;
+input wire [WR_DATA_WIDTH0-1 :0] WDATA0_i;
+output wire [RD_DATA_WIDTH0-1 :0] RDATA0_o;
+
+input wire WEN1_i;
+input wire REN1_i;
+input wire clock1;
+input wire [WR_ADDR_WIDTH1-1 :0] WR_ADDR1_i;
+input wire [RD_ADDR_WIDTH1-1 :0] RD_ADDR1_i;
+input wire [WR_DATA_WIDTH1-1 :0] WDATA1_i;
+output wire [RD_DATA_WIDTH1-1 :0] RDATA1_o;
+
+
+RAM_18K_BLK #(
+              .WR_ADDR_WIDTH(WR_ADDR_WIDTH0),
+              .RD_ADDR_WIDTH(RD_ADDR_WIDTH0),
+              .WR_DATA_WIDTH(WR_DATA_WIDTH0),
+              .RD_DATA_WIDTH(RD_DATA_WIDTH0),
+              .BE_WIDTH(BE_WIDTH0)
+              ) spram_x18_inst1 (
+              
+              .WEN_i(WEN0_i),
+              .WR_BE_i(1'b1),
+              .REN_i(REN0_i),              
+              .WR_CLK_i(clock0),
+              .RD_CLK_i(clock0),
+              .WR_ADDR_i(WR_ADDR0_i),
+              .RD_ADDR_i(RD_ADDR0_i),
+              .WDATA_i(WDATA0_i),
+              .RDATA_o(RDATA0_o)
+              );
+              
+RAM_18K_BLK #(
+              .WR_ADDR_WIDTH(WR_ADDR_WIDTH1),
+              .RD_ADDR_WIDTH(RD_ADDR_WIDTH1),
+              .WR_DATA_WIDTH(WR_DATA_WIDTH1),
+              .RD_DATA_WIDTH(RD_DATA_WIDTH1),
+              .BE_WIDTH(BE_WIDTH1)
+              ) spram_x18_inst2 (
+              
+              .WEN_i(WEN1_i),
+              .WR_BE_i(2'b11),
+              .REN_i(REN1_i),              
+              .WR_CLK_i(clock1),
+              .RD_CLK_i(clock1),
+              .WR_ADDR_i(WR_ADDR1_i),
+              .RD_ADDR_i(RD_ADDR1_i),
+              .WDATA_i(WDATA1_i),
+              .RDATA_o(RDATA1_o)
+              );
+              
+endmodule    
\ No newline at end of file
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_sdp/sim/Makefile b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_sdp/sim/Makefile
new file mode 100644
index 0000000..aeb9aec
--- /dev/null
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_sdp/sim/Makefile
@@ -0,0 +1,48 @@
+# Copyright 2020-2022 F4PGA Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+TESTBENCH = bram18k_sdp_tb.v
+POST_SYNTH = spram_18x1024_2x_post_synth spram_9x2048_x2_post_synth spram_9x2048_18x1024_post_synth
+ADDR_WIDTH0 = 10 11 11
+DATA_WIDTH0 = 18 9 9
+ADDR_WIDTH1 = 10 11 10
+DATA_WIDTH1 = 18 9 18
+TOP = spram_18x1024_2x spram_9x2048_x2 spram_9x2048_18x1024
+ADDR0_DEFINES = $(foreach awidth0, $(ADDR_WIDTH0),-DADDR_WIDTH0="$(awidth0)")
+ADDR1_DEFINES = $(foreach awidth1, $(ADDR_WIDTH1),-DADDR_WIDTH1="$(awidth1)")
+DATA0_DEFINES = $(foreach dwidth0, $(DATA_WIDTH0),-DDATA_WIDTH0="$(dwidth0)")
+DATA1_DEFINES = $(foreach dwidth1, $(DATA_WIDTH1),-DDATA_WIDTH1="$(dwidth1)")
+TOP_DEFINES = $(foreach top, $(TOP),-DTOP="$(top)")
+VCD_DEFINES = $(foreach vcd, $(POST_SYNTH),-DVCD="$(vcd).vcd")
+
+SIM_LIBS = $(shell find ../../../../qlf_k6n10f -name "*.v" -not -name "*_map.v")
+
+define simulate_post_synth
+	@iverilog  -vvvv -g2005 $(word $(1),$(ADDR0_DEFINES)) $(word $(1),$(ADDR1_DEFINES)) $(word $(1),$(DATA0_DEFINES)) $(word $(1),$(DATA1_DEFINES)) $(word $(1),$(TOP_DEFINES)) $(word $(1),$(VCD_DEFINES)) -o $(word $(1),$(POST_SYNTH)).vvp $(word $(1),$(POST_SYNTH)).v $(SIM_LIBS) $(TESTBENCH) > $(word $(1),$(POST_SYNTH)).vvp.log 2>&1
+	@vvp -vvvv $(word $(1),$(POST_SYNTH)).vvp > $(word $(1),$(POST_SYNTH)).vcd.log 2>&1
+endef
+
+define clean_post_synth_sim
+	@rm -rf  $(word $(1),$(POST_SYNTH)).vcd $(word $(1),$(POST_SYNTH)).vvp $(word $(1),$(POST_SYNTH)).vvp.log $(word $(1),$(POST_SYNTH)).vcd.log
+endef
+
+sim:
+	$(call simulate_post_synth,1)
+	$(call clean_post_synth_sim,1)
+	$(call simulate_post_synth,2)
+	$(call clean_post_synth_sim,2)
+	$(call simulate_post_synth,3)
+	$(call clean_post_synth_sim,3)
\ No newline at end of file
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_sdp/sim/bram18k_sdp_tb.v b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_sdp/sim/bram18k_sdp_tb.v
new file mode 100644
index 0000000..8d91922
--- /dev/null
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_sdp/sim/bram18k_sdp_tb.v
@@ -0,0 +1,230 @@
+// Copyright 2020-2022 F4PGA Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//		 http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
+`timescale 1ns/1ps
+
+`define STRINGIFY(x) `"x`"
+
+module TB;
+	localparam PERIOD = 50;
+	localparam ADDR_INCR = 1;
+
+	reg clk_0;
+	reg rce_0;
+	reg [`ADDR_WIDTH0-1:0] ra_0;
+	wire [`DATA_WIDTH0-1:0] rq_0;
+	reg wce_0;
+	reg [`ADDR_WIDTH0-1:0] wa_0;
+	reg [`DATA_WIDTH0-1:0] wd_0;
+
+	reg clk_1;
+	reg rce_1;
+	reg [`ADDR_WIDTH1-1:0] ra_1;
+	wire [`DATA_WIDTH1-1:0] rq_1;
+	reg wce_1;
+	reg [`ADDR_WIDTH1-1:0] wa_1;
+	reg [`DATA_WIDTH1-1:0] wd_1;
+
+
+	initial clk_0 = 0;
+	initial clk_1 = 0;
+	initial ra_0 = 0;
+	initial ra_1 = 0;
+	initial rce_0 = 0;
+	initial rce_1 = 0;
+	initial forever #(PERIOD / 2.0) clk_0 = ~clk_0;
+	initial begin
+		#(PERIOD / 4.0);
+		forever #(PERIOD / 2.0) clk_1 = ~clk_1;
+	end
+	initial begin
+		$dumpfile(`STRINGIFY(`VCD));
+		$dumpvars;
+	end
+
+	integer a;
+	integer b;
+
+	reg done_0;
+	reg done_1;
+	initial done_0 = 1'b0;
+	initial done_1 = 1'b0;
+	wire done_sim = done_0 & done_1;
+
+	reg [`DATA_WIDTH0-1:0] expected_0;
+	reg [`DATA_WIDTH1-1:0] expected_1;
+
+	reg read_test_0;
+	reg read_test_1;
+	initial read_test_0 = 0;
+	initial read_test_1 = 0;
+
+	always @(posedge clk_0) begin
+		expected_0 <= (a | (a << 20) | 20'h55000) & {`DATA_WIDTH0{1'b1}};
+	end
+	always @(posedge clk_1) begin
+		expected_1 <= ((b+1) | ((b+1) << 20) | 20'h55000) & {`DATA_WIDTH1{1'b1}};
+	end
+
+	wire error_0 = ((a != 0) && read_test_0) ? (rq_0 !== expected_0) : 0;
+	wire error_1 = ((b != (1<<`ADDR_WIDTH1) / 2) && read_test_1) ? (rq_1 !== expected_1) : 0;
+
+	integer error_0_cnt = 0;
+	integer error_1_cnt = 0;
+
+	always @ (posedge clk_0)
+	begin
+		if (error_0)
+			error_0_cnt <= error_0_cnt + 1'b1;
+	end
+	always @ (posedge clk_1)
+	begin
+		if (error_1)
+			error_1_cnt <= error_1_cnt + 1'b1;
+	end
+
+	// PART 0
+	initial #(1) begin
+		// Write data
+		for (a = 0; a < (1<<`ADDR_WIDTH0) / 2; a = a + ADDR_INCR) begin
+			@(negedge clk_0) begin
+				wa_0 = a;
+				wd_0 = a | (a << 20) | 20'h55000;
+				wce_0 = 1;
+			end
+			@(posedge clk_0) begin
+				#(PERIOD/10) wce_0 = 0;
+			end
+		end
+		// Read data
+		read_test_0 = 1;
+		for (a = 0; a < (1<<`ADDR_WIDTH0) / 2; a = a + ADDR_INCR) begin
+			@(negedge clk_0) begin
+				ra_0 = a;
+				rce_0 = 1;
+			end
+			@(posedge clk_0) begin
+				#(PERIOD/10) rce_0 = 0;
+				if ( rq_0 !== expected_0) begin
+					$display("%d: PORT 0: FAIL: mismatch act=%x exp=%x at %x", $time, rq_0, expected_0, a);
+				end else begin
+					$display("%d: PORT 0: OK: act=%x exp=%x at %x", $time, rq_0, expected_0, a);
+				end
+			end
+		end
+		done_0 = 1'b1;
+		a = 0;
+	end
+
+	// PART 1
+	initial #(1) begin
+		// Write data
+		for (b = (1<<`ADDR_WIDTH1) / 2; b < (1<<`ADDR_WIDTH1); b = b + ADDR_INCR) begin
+			@(negedge clk_1) begin
+				wa_1 = b;
+				wd_1 = (b+1) | ((b+1) << 20) | 20'h55000;
+				wce_1 = 1;
+			end
+			@(posedge clk_1) begin
+				#(PERIOD/10) wce_1 = 0;
+			end
+		end
+		// Read data
+		read_test_1 = 1;
+		for (b = (1<<`ADDR_WIDTH1) / 2; b < (1<<`ADDR_WIDTH1); b = b + ADDR_INCR) begin
+			@(negedge clk_1) begin
+				ra_1 = b;
+				rce_1 = 1;
+			end
+			@(posedge clk_1) begin
+				#(PERIOD/10) rce_1 = 0;
+				if ( rq_1 !== expected_1) begin
+					$display("%d: PORT 1: FAIL: mismatch act=%x exp=%x at %x", $time, rq_1, expected_1, b);
+				end else begin
+					$display("%d: PORT 1: OK: act=%x exp=%x at %x", $time, rq_1, expected_1, b);
+				end
+			end
+		end
+		done_1 = 1'b1;
+		b = (1<<`ADDR_WIDTH1) / 2;
+	end
+
+	// Scan for simulation finish
+	always @(posedge clk_0, posedge clk_1) begin
+		if (done_sim)
+			$finish_and_return( (error_0_cnt == 0 & error_1_cnt == 0) ? 0 : -1 );
+	end
+
+	case (`STRINGIFY(`TOP))
+		"spram_18x1024_2x": begin
+			spram_18x1024_2x #() bram (
+				.clock0(clk_0),
+				.REN0_i(rce_0),
+				.RD_ADDR0_i(ra_0),
+				.RDATA0_o(rq_0),
+				.WEN0_i(wce_0),
+				.WR_ADDR0_i(wa_0),
+				.WDATA0_i(wd_0),
+
+				.clock1(clk_1),
+				.REN1_i(rce_1),
+				.RD_ADDR1_i(ra_1),
+				.RDATA1_o(rq_1),
+				.WEN1_i(wce_1),
+				.WR_ADDR1_i(wa_1),
+				.WDATA1_i(wd_1)
+			);
+		end
+		"spram_9x2048_x2": begin
+			spram_9x2048_x2 #() bram (
+				.clock0(clk_0),
+				.REN0_i(rce_0),
+				.RD_ADDR0_i(ra_0),
+				.RDATA0_o(rq_0),
+				.WEN0_i(wce_0),
+				.WR_ADDR0_i(wa_0),
+				.WDATA0_i(wd_0),
+
+				.clock1(clk_1),
+				.REN1_i(rce_1),
+				.RD_ADDR1_i(ra_1),
+				.RDATA1_o(rq_1),
+				.WEN1_i(wce_1),
+				.WR_ADDR1_i(wa_1),
+				.WDATA1_i(wd_1)
+			);
+		end
+		"spram_9x2048_18x1024": begin
+			spram_9x2048_18x1024 #() bram (
+				.clock0(clk_0),
+				.REN0_i(rce_0),
+				.RD_ADDR0_i(ra_0),
+				.RDATA0_o(rq_0),
+				.WEN0_i(wce_0),
+				.WR_ADDR0_i(wa_0),
+				.WDATA0_i(wd_0),
+
+				.clock1(clk_1),
+				.REN1_i(rce_1),
+				.RD_ADDR1_i(ra_1),
+				.RDATA1_o(rq_1),
+				.WEN1_i(wce_1),
+				.WR_ADDR1_i(wa_1),
+				.WDATA1_i(wd_1)
+			);
+		end
+	endcase
+endmodule
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_sfifo/bram18k_sfifo.tcl b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_sfifo/bram18k_sfifo.tcl
new file mode 100644
index 0000000..a5ff276
--- /dev/null
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_sfifo/bram18k_sfifo.tcl
@@ -0,0 +1,49 @@
+yosys -import
+
+if { [info procs ql-qlf-k6n10f] == {} } { plugin -i ql-qlf }
+yosys -import  ;
+
+read_verilog $::env(DESIGN_TOP).v
+design -save bram18k_sfifo
+
+select f1024x18_1024x18
+select *
+synth_quicklogic -family qlf_k6n10f -top f1024x18_1024x18 -bram_types
+opt_expr -undriven
+opt_clean
+stat
+write_verilog sim/f1024x18_1024x18_post_synth.v
+select -assert-count 1 t:TDP36K_FIFO_SYNC_WR_X18_RD_X18_split
+
+select -clear
+design -load bram18k_sfifo
+select f1024x16_1024x16
+select *
+synth_quicklogic -family qlf_k6n10f -top f1024x16_1024x16 -bram_types
+opt_expr -undriven
+opt_clean
+stat
+write_verilog sim/f1024x16_1024x16_post_synth.v
+select -assert-count 1 t:TDP36K_FIFO_SYNC_WR_X18_RD_X18_split
+
+select -clear
+design -load bram18k_sfifo
+select f2048x9_2048x9
+select *
+synth_quicklogic -family qlf_k6n10f -top f2048x9_2048x9 -bram_types
+opt_expr -undriven
+opt_clean
+stat
+write_verilog sim/f2048x9_2048x9_post_synth.v
+select -assert-count 1 t:TDP36K_FIFO_SYNC_WR_X9_RD_X9_split
+
+select -clear
+design -load bram18k_sfifo
+select f2048x8_2048x8
+select *
+synth_quicklogic -family qlf_k6n10f -top f2048x8_2048x8 -bram_types
+opt_expr -undriven
+opt_clean
+stat
+write_verilog sim/f2048x8_2048x8_post_synth.v
+select -assert-count 1 t:TDP36K_FIFO_SYNC_WR_X9_RD_X9_split
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_sfifo/bram18k_sfifo.v b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_sfifo/bram18k_sfifo.v
new file mode 100644
index 0000000..c559134
--- /dev/null
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_sfifo/bram18k_sfifo.v
@@ -0,0 +1,175 @@
+// Copyright 2020-2022 F4PGA Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
+module f1024x18_1024x18 (DIN,PUSH,POP,clock0,Async_Flush,Almost_Full,Almost_Empty,Full,Empty,Full_Watermark,Empty_Watermark,Overrun_Error,Underrun_Error,DOUT);
+
+parameter WR_DATA_WIDTH = 18;
+parameter RD_DATA_WIDTH = 18;
+parameter UPAE_DBITS = 11'd10;
+parameter UPAF_DBITS = 11'd10;
+
+input clock0;
+input PUSH,POP;
+input [WR_DATA_WIDTH-1:0] DIN;
+input Async_Flush;
+output [RD_DATA_WIDTH-1:0] DOUT;
+output Almost_Full,Almost_Empty;
+output Full, Empty;
+output Full_Watermark, Empty_Watermark;
+output Overrun_Error, Underrun_Error;
+
+SFIFO_18K_BLK  # (.WR_DATA_WIDTH(WR_DATA_WIDTH),.RD_DATA_WIDTH(RD_DATA_WIDTH),.UPAE_DBITS(UPAE_DBITS),.UPAF_DBITS(UPAF_DBITS)
+                  )
+  FIFO_INST    (
+                .DIN(DIN),
+                .PUSH(PUSH),
+                .POP(POP),
+                .CLK(clock0),
+                .Async_Flush(Async_Flush),
+                
+                .Overrun_Error(Overrun_Error),
+                .Full_Watermark(Full_Watermark),
+                .Almost_Full(Almost_Full),
+                .Full(Full),
+                
+                .Underrun_Error(Underrun_Error),
+                .Empty_Watermark(Empty_Watermark),
+                .Almost_Empty(Almost_Empty),
+                .Empty(Empty),
+
+                .DOUT(DOUT)
+                );
+endmodule
+
+module f1024x16_1024x16 (DIN,PUSH,POP,clock0,Async_Flush,Almost_Full,Almost_Empty,Full,Empty,Full_Watermark,Empty_Watermark,Overrun_Error,Underrun_Error,DOUT);
+
+parameter WR_DATA_WIDTH = 16;
+parameter RD_DATA_WIDTH = 16;
+parameter UPAE_DBITS = 11'd10;
+parameter UPAF_DBITS = 11'd10;
+
+input clock0;
+input PUSH,POP;
+input [WR_DATA_WIDTH-1:0] DIN;
+input Async_Flush;
+output [RD_DATA_WIDTH-1:0] DOUT;
+output Almost_Full,Almost_Empty;
+output Full, Empty;
+output Full_Watermark, Empty_Watermark;
+output Overrun_Error, Underrun_Error;
+
+SFIFO_18K_BLK  # (.WR_DATA_WIDTH(WR_DATA_WIDTH),.RD_DATA_WIDTH(RD_DATA_WIDTH),.UPAE_DBITS(UPAE_DBITS),.UPAF_DBITS(UPAF_DBITS)
+                  )
+  FIFO_INST    (
+                .DIN(DIN),
+                .PUSH(PUSH),
+                .POP(POP),
+                .CLK(clock0),
+                .Async_Flush(Async_Flush),
+                
+                .Overrun_Error(Overrun_Error),
+                .Full_Watermark(Full_Watermark),
+                .Almost_Full(Almost_Full),
+                .Full(Full),
+                
+                .Underrun_Error(Underrun_Error),
+                .Empty_Watermark(Empty_Watermark),
+                .Almost_Empty(Almost_Empty),
+                .Empty(Empty),
+
+                .DOUT(DOUT)
+                );
+endmodule
+
+module f2048x9_2048x9 (DIN,PUSH,POP,clock0,Async_Flush,Almost_Full,Almost_Empty,Full,Empty,Full_Watermark,Empty_Watermark,Overrun_Error,Underrun_Error,DOUT);
+
+parameter WR_DATA_WIDTH = 9;
+parameter RD_DATA_WIDTH = 9;
+parameter UPAE_DBITS = 11'd10;
+parameter UPAF_DBITS = 11'd10;
+
+input clock0;
+input PUSH,POP;
+input [WR_DATA_WIDTH-1:0] DIN;
+input Async_Flush;
+output [RD_DATA_WIDTH-1:0] DOUT;
+output Almost_Full,Almost_Empty;
+output Full, Empty;
+output Full_Watermark, Empty_Watermark;
+output Overrun_Error, Underrun_Error;
+
+SFIFO_18K_BLK  # (.WR_DATA_WIDTH(WR_DATA_WIDTH),.RD_DATA_WIDTH(RD_DATA_WIDTH),.UPAE_DBITS(UPAE_DBITS),.UPAF_DBITS(UPAF_DBITS)
+                  )
+  FIFO_INST    (
+                .DIN(DIN),
+                .PUSH(PUSH),
+                .POP(POP),
+                .CLK(clock0),
+                .Async_Flush(Async_Flush),
+                
+                .Overrun_Error(Overrun_Error),
+                .Full_Watermark(Full_Watermark),
+                .Almost_Full(Almost_Full),
+                .Full(Full),
+                
+                .Underrun_Error(Underrun_Error),
+                .Empty_Watermark(Empty_Watermark),
+                .Almost_Empty(Almost_Empty),
+                .Empty(Empty),
+
+                .DOUT(DOUT)
+                );
+endmodule
+
+module f2048x8_2048x8 (DIN,PUSH,POP,clock0,Async_Flush,Almost_Full,Almost_Empty,Full,Empty,Full_Watermark,Empty_Watermark,Overrun_Error,Underrun_Error,DOUT);
+
+parameter WR_DATA_WIDTH = 8;
+parameter RD_DATA_WIDTH = 8;
+parameter UPAE_DBITS = 11'd10;
+parameter UPAF_DBITS = 11'd10;
+
+input clock0;
+input PUSH,POP;
+input [WR_DATA_WIDTH-1:0] DIN;
+input Async_Flush;
+output [RD_DATA_WIDTH-1:0] DOUT;
+output Almost_Full,Almost_Empty;
+output Full, Empty;
+output Full_Watermark, Empty_Watermark;
+output Overrun_Error, Underrun_Error;
+
+SFIFO_18K_BLK  # (.WR_DATA_WIDTH(WR_DATA_WIDTH),.RD_DATA_WIDTH(RD_DATA_WIDTH),.UPAE_DBITS(UPAE_DBITS),.UPAF_DBITS(UPAF_DBITS)
+                  )
+  FIFO_INST    (
+                .DIN(DIN),
+                .PUSH(PUSH),
+                .POP(POP),
+                .CLK(clock0),
+                .Async_Flush(Async_Flush),
+                
+                .Overrun_Error(Overrun_Error),
+                .Full_Watermark(Full_Watermark),
+                .Almost_Full(Almost_Full),
+                .Full(Full),
+                
+                .Underrun_Error(Underrun_Error),
+                .Empty_Watermark(Empty_Watermark),
+                .Almost_Empty(Almost_Empty),
+                .Empty(Empty),
+
+                .DOUT(DOUT)
+                );
+endmodule
\ No newline at end of file
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_sfifo/sim/Makefile b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_sfifo/sim/Makefile
new file mode 100644
index 0000000..86a1b10
--- /dev/null
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_sfifo/sim/Makefile
@@ -0,0 +1,50 @@
+# Copyright 2020-2022 F4PGA Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+TESTBENCH = bram18k_sfifo_tb.v
+POST_SYNTH = f1024x18_1024x18_post_synth f1024x16_1024x16_post_synth f2048x9_2048x9_post_synth f2048x8_2048x8_post_synth
+ADDR_WIDTH0 = 10 10 11 11
+DATA_WIDTH0 = 18 16 9 8
+ADDR_WIDTH1 = 10 10 11 11
+DATA_WIDTH1 = 18 16 9 8
+TOP = f1024x18_1024x18 f1024x16_1024x16 f2048x9_2048x9 f2048x8_2048x8
+ADDR0_DEFINES = $(foreach awidth0, $(ADDR_WIDTH0),-DADDR_WIDTH0="$(awidth0)")
+ADDR1_DEFINES = $(foreach awidth1, $(ADDR_WIDTH1),-DADDR_WIDTH1="$(awidth1)")
+DATA0_DEFINES = $(foreach dwidth0, $(DATA_WIDTH0),-DDATA_WIDTH0="$(dwidth0)")
+DATA1_DEFINES = $(foreach dwidth1, $(DATA_WIDTH1),-DDATA_WIDTH1="$(dwidth1)")
+TOP_DEFINES = $(foreach top, $(TOP),-DTOP="$(top)")
+VCD_DEFINES = $(foreach vcd, $(POST_SYNTH),-DVCD="$(vcd).vcd")
+
+SIM_LIBS = $(shell find ../../../../qlf_k6n10f -name "*.v" -not -name "*_map.v")
+
+define simulate_post_synth
+	@iverilog  -vvvv -g2005 $(word $(1),$(ADDR0_DEFINES)) $(word $(1),$(ADDR1_DEFINES)) $(word $(1),$(DATA0_DEFINES)) $(word $(1),$(DATA1_DEFINES)) $(word $(1),$(TOP_DEFINES)) $(word $(1),$(VCD_DEFINES)) -o $(word $(1),$(POST_SYNTH)).vvp $(word $(1),$(POST_SYNTH)).v $(SIM_LIBS) $(TESTBENCH) > $(word $(1),$(POST_SYNTH)).vvp.log 2>&1
+	@vvp -vvvv $(word $(1),$(POST_SYNTH)).vvp > $(word $(1),$(POST_SYNTH)).vcd.log 2>&1
+endef
+
+define clean_post_synth_sim
+	@rm -rf  $(word $(1),$(POST_SYNTH)).vcd $(word $(1),$(POST_SYNTH)).vvp $(word $(1),$(POST_SYNTH)).vvp.log $(word $(1),$(POST_SYNTH)).vcd.log
+endef
+
+sim:
+	$(call simulate_post_synth,1)
+	$(call clean_post_synth_sim,1)
+	$(call simulate_post_synth,2)
+	$(call clean_post_synth_sim,2)
+	$(call simulate_post_synth,3)
+	$(call clean_post_synth_sim,3)
+	$(call simulate_post_synth,4)
+	$(call clean_post_synth_sim,4)
\ No newline at end of file
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_sfifo/sim/bram18k_sfifo_tb.v b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_sfifo/sim/bram18k_sfifo_tb.v
new file mode 100644
index 0000000..579d881
--- /dev/null
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_sfifo/sim/bram18k_sfifo_tb.v
@@ -0,0 +1,188 @@
+// Copyright 2020-2022 F4PGA Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//		 http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
+`timescale 1ns/1ps
+
+`define STRINGIFY(x) `"x`"
+
+module TB;
+	localparam PERIOD = 30;
+	localparam ADDR_INCR = 1;
+
+	reg clk;
+	reg flush;
+	reg pop;
+	wire [`DATA_WIDTH1-1:0] dout;
+	reg push;
+	reg [`DATA_WIDTH0-1:0] din;
+	wire almost_full,almost_empty;
+	wire full, empty;
+	wire full_watermark, empty_watermark;
+	wire overrun_error, underrun_error;
+
+	initial 
+	begin
+		clk = 0;
+		pop = 0;
+		push = 0;
+		flush = 1;
+		din = 0;
+		#40
+		flush = 0;
+	end
+	
+	initial forever #(PERIOD / 3.0) clk = ~clk;
+	
+	initial begin
+		$dumpfile(`STRINGIFY(`VCD));
+		$dumpvars;
+	end
+
+	integer a;
+
+	reg done;
+	initial done = 1'b0;
+	
+	reg read_test;
+	initial read_test = 0;
+
+	reg [`DATA_WIDTH1-1:0] expected;
+	initial expected = 0;
+
+	always @(posedge clk) begin
+		expected <= (a | (a << 20) | 20'h55000) & {`DATA_WIDTH1{1'b1}};
+	end
+
+	wire error = ((a != 0) && read_test) ? dout !== expected : 0;
+
+	integer error_cnt = 0;
+	always @ (posedge clk)
+	begin
+		if (error)
+			error_cnt <= error_cnt + 1'b1; 
+	end
+
+	initial #(50) begin
+		@(posedge clk)
+		// Write data
+		for (a = 0; a < (1<<`ADDR_WIDTH0); a = a + ADDR_INCR) begin
+			@(negedge clk) begin
+				din = a | (a << 20) | 20'h55000;
+				push = 1;
+			end
+			@(posedge clk) begin
+				#(PERIOD/10) push = 0;
+			end
+		end
+		// Read data
+		read_test = 1;
+		for (a = 0; a < (1<<`ADDR_WIDTH1); a = a + ADDR_INCR) begin
+			@(posedge clk) begin
+				#(PERIOD/10) pop = 0;
+				if ( dout !== expected) begin
+					$display("%d: FAIL: mismatch act=%x exp=%x at %x", $time, dout, expected, a);
+				end else begin
+					$display("%d: OK: act=%x exp=%x at %x", $time, dout, expected, a);
+				end
+			end
+			@(negedge clk) begin
+				pop = 1;
+			end
+		end
+		done = 1'b1;
+	end
+
+	// Scan for simulation finish
+	always @(posedge clk) begin
+		if (done)
+			$finish_and_return( (error_cnt == 0) ? 0 : -1 );
+	end
+
+	case (`STRINGIFY(`TOP))
+		"f1024x18_1024x18": begin
+			f1024x18_1024x18 #() afifo (
+				.DIN(din),
+				.PUSH(push),
+				.POP(pop),
+				.clock0(clk),
+				.Async_Flush(flush),
+				.Almost_Full(almost_full),
+				.Almost_Empty(almost_empty),
+				.Full(full),
+				.Empty(empty),
+				.Full_Watermark(full_watermark),
+				.Empty_Watermark(empty_watermark),
+				.Overrun_Error(overrun_error),
+				.Underrun_Error(underrun_error),
+				.DOUT(dout)
+			);
+		end
+		"f1024x16_1024x16": begin
+			f1024x16_1024x16 #() afifo (
+				.DIN(din),
+				.PUSH(push),
+				.POP(pop),
+				.clock0(clk),
+				.Async_Flush(flush),
+				.Almost_Full(almost_full),
+				.Almost_Empty(almost_empty),
+				.Full(full),
+				.Empty(empty),
+				.Full_Watermark(full_watermark),
+				.Empty_Watermark(empty_watermark),
+				.Overrun_Error(overrun_error),
+				.Underrun_Error(underrun_error),
+				.DOUT(dout)
+			);
+		end
+		"f2048x9_2048x9": begin
+			f2048x9_2048x9 #() afifo (
+				.DIN(din),
+				.PUSH(push),
+				.POP(pop),
+				.clock0(clk),
+				.Async_Flush(flush),
+				.Almost_Full(almost_full),
+				.Almost_Empty(almost_empty),
+				.Full(full),
+				.Empty(empty),
+				.Full_Watermark(full_watermark),
+				.Empty_Watermark(empty_watermark),
+				.Overrun_Error(overrun_error),
+				.Underrun_Error(underrun_error),
+				.DOUT(dout)
+			);
+		end	
+		"f2048x8_2048x8": begin
+			f2048x8_2048x8 #() afifo (
+				.DIN(din),
+				.PUSH(push),
+				.POP(pop),
+				.clock0(clk),
+				.Async_Flush(flush),
+				.Almost_Full(almost_full),
+				.Almost_Empty(almost_empty),
+				.Full(full),
+				.Empty(empty),
+				.Full_Watermark(full_watermark),
+				.Empty_Watermark(empty_watermark),
+				.Overrun_Error(overrun_error),
+				.Underrun_Error(underrun_error),
+				.DOUT(dout)
+			);
+		end			
+	endcase
+endmodule
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_tdp/bram18k_tdp.tcl b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_tdp/bram18k_tdp.tcl
new file mode 100644
index 0000000..e42cd16
--- /dev/null
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_tdp/bram18k_tdp.tcl
@@ -0,0 +1,39 @@
+yosys -import
+
+if { [info procs ql-qlf-k6n10f] == {} } { plugin -i ql-qlf }
+yosys -import  ;
+
+read_verilog $::env(DESIGN_TOP).v
+design -save bram18k_tdp
+
+select dpram_18x1024_x2
+select *
+synth_quicklogic -family qlf_k6n10f -top dpram_18x1024_x2 -bram_types
+opt_expr -undriven
+opt_clean
+stat
+write_verilog sim/dpram_18x1024_x2_post_synth.v
+select -assert-count 2 t:TDP36K_BRAM_WR_X18_RD_X18_split
+
+select -clear
+design -load bram18k_tdp
+select dpram_9x2048_x2
+select *
+synth_quicklogic -family qlf_k6n10f -top dpram_9x2048_x2 -bram_types
+opt_expr -undriven
+opt_clean
+stat
+write_verilog sim/dpram_9x2048_x2_post_synth.v
+select -assert-count 2 t:TDP36K_BRAM_WR_X9_RD_X9_split
+
+select -clear
+design -load bram18k_tdp
+select dpram_18x1024_9x2048
+select *
+synth_quicklogic -family qlf_k6n10f -top dpram_18x1024_9x2048 -bram_types
+opt_expr -undriven
+opt_clean
+stat
+write_verilog sim/dpram_18x1024_9x2048_post_synth.v
+select -assert-count 1 t:TDP36K_BRAM_WR_X18_RD_X18_split
+select -assert-count 1 t:TDP36K_BRAM_WR_X9_RD_X9_split
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_tdp/bram18k_tdp.v b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_tdp/bram18k_tdp.v
new file mode 100644
index 0000000..5151eeb
--- /dev/null
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_tdp/bram18k_tdp.v
@@ -0,0 +1,396 @@
+// Copyright 2020-2022 F4PGA Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
+module dpram_18x1024_x2 (   
+    clk_a_0,
+    WEN_a_0,
+    REN_a_0,
+    WR_ADDR_a_0,
+    RD_ADDR_a_0,
+    WDATA_a_0,
+    RDATA_a_0,
+    
+    clk_b_0,
+    WEN_b_0,
+    REN_b_0,
+    WR_ADDR_b_0,
+    RD_ADDR_b_0,
+    WDATA_b_0,
+    RDATA_b_0,
+    
+    clk_a_1,
+    WEN_a_1,
+    REN_a_1,
+    WR_ADDR_a_1,
+    RD_ADDR_a_1,
+    WDATA_a_1,
+    RDATA_a_1,
+    
+    clk_b_1,
+    WEN_b_1,
+    REN_b_1,
+    WR_ADDR_b_1,
+    RD_ADDR_b_1,
+    WDATA_b_1,
+    RDATA_b_1
+);
+
+parameter ADDR_WIDTH0 = 10;
+parameter DATA_WIDTH0 = 18;
+parameter BE1_WIDTH0 = 2;
+parameter BE2_WIDTH0 = 2;
+
+parameter ADDR_WIDTH1 = 10;
+parameter DATA_WIDTH1 = 18;
+parameter BE1_WIDTH1 = 2;
+parameter BE2_WIDTH1 = 2;
+
+input wire clk_a_0;
+input wire WEN_a_0;
+input wire REN_a_0;
+input wire [ADDR_WIDTH0-1 :0] WR_ADDR_a_0;
+input wire [ADDR_WIDTH0-1 :0] RD_ADDR_a_0;
+input wire [DATA_WIDTH0-1 :0] WDATA_a_0;
+output wire [DATA_WIDTH0-1 :0] RDATA_a_0;
+
+input wire clk_b_0;
+input wire WEN_b_0;
+input wire REN_b_0;
+input wire [ADDR_WIDTH0-1 :0] WR_ADDR_b_0;
+input wire [ADDR_WIDTH0-1 :0] RD_ADDR_b_0;
+input wire [DATA_WIDTH0-1 :0] WDATA_b_0;
+output wire [DATA_WIDTH0-1 :0] RDATA_b_0;
+
+input wire clk_a_1;
+input wire WEN_a_1;
+input wire REN_a_1;
+input wire [ADDR_WIDTH1-1 :0] WR_ADDR_a_1;
+input wire [ADDR_WIDTH1-1 :0] RD_ADDR_a_1;
+input wire [DATA_WIDTH1-1 :0] WDATA_a_1;
+output wire [DATA_WIDTH1-1 :0] RDATA_a_1;
+
+input wire clk_b_1;
+input wire WEN_b_1;
+input wire REN_b_1;
+input wire [ADDR_WIDTH1-1 :0] WR_ADDR_b_1;
+input wire [ADDR_WIDTH1-1 :0] RD_ADDR_b_1;
+input wire [DATA_WIDTH1-1 :0] WDATA_b_1;
+output wire [DATA_WIDTH1-1 :0] RDATA_b_1;
+ 
+DPRAM_18K_BLK #(
+              .ADDR_WIDTH(ADDR_WIDTH0),
+              .DATA_WIDTH(DATA_WIDTH0),
+              .BE1_WIDTH(BE1_WIDTH0),
+              .BE2_WIDTH(BE2_WIDTH0)
+              ) dpram_x18_inst0 ( 
+              
+              .CLK1_i(clk_a_0),
+              .WEN1_i(WEN_a_0),
+              .REN1_i(REN_a_0),
+              .WR1_ADDR_i(WR_ADDR_a_0),
+              .RD1_ADDR_i(RD_ADDR_a_0),
+              .WDATA1_i(WDATA_a_0),
+              .RDATA1_o(RDATA_a_0),
+              
+              .CLK2_i(clk_b_0),
+              .WEN2_i(WEN_b_0),
+              .REN2_i(REN_b_0),
+              .WR2_ADDR_i(WR_ADDR_b_0),
+              .RD2_ADDR_i(RD_ADDR_b_0),
+              .WDATA2_i(WDATA_b_0),
+              .RDATA2_o(RDATA_b_0)
+              );
+              
+ 
+DPRAM_18K_BLK #(
+              .ADDR_WIDTH(ADDR_WIDTH1),
+              .DATA_WIDTH(DATA_WIDTH1),
+              .BE1_WIDTH(BE1_WIDTH1),
+              .BE2_WIDTH(BE2_WIDTH1)
+              ) dpram_x18_inst1 ( 
+              
+              .CLK1_i(clk_a_1),
+              .WEN1_i(WEN_a_1),
+              .REN1_i(REN_a_1),
+              .WR1_ADDR_i(WR_ADDR_a_1),
+              .RD1_ADDR_i(RD_ADDR_a_1),
+              .WDATA1_i(WDATA_a_1),
+              .RDATA1_o(RDATA_a_1),
+              
+              .CLK2_i(clk_b_1),
+              .WEN2_i(WEN_b_1),
+              .REN2_i(REN_b_1),
+              .WR2_ADDR_i(WR_ADDR_b_1),
+              .RD2_ADDR_i(RD_ADDR_b_1),
+              .WDATA2_i(WDATA_b_1),
+              .RDATA2_o(RDATA_b_1)
+              );
+              
+endmodule    
+
+module dpram_9x2048_x2 (   
+    clk_a_0,
+    WEN_a_0,
+    REN_a_0,
+    WR_ADDR_a_0,
+    RD_ADDR_a_0,
+    WDATA_a_0,
+    RDATA_a_0,
+    
+    clk_b_0,
+    WEN_b_0,
+    REN_b_0,
+    WR_ADDR_b_0,
+    RD_ADDR_b_0,
+    WDATA_b_0,
+    RDATA_b_0,
+    
+    clk_a_1,
+    WEN_a_1,
+    REN_a_1,
+    WR_ADDR_a_1,
+    RD_ADDR_a_1,
+    WDATA_a_1,
+    RDATA_a_1,
+    
+    clk_b_1,
+    WEN_b_1,
+    REN_b_1,
+    WR_ADDR_b_1,
+    RD_ADDR_b_1,
+    WDATA_b_1,
+    RDATA_b_1
+);
+
+parameter ADDR_WIDTH0 = 11;
+parameter DATA_WIDTH0 = 9;
+parameter BE1_WIDTH0 = 1;
+parameter BE2_WIDTH0 = 1;
+
+parameter ADDR_WIDTH1 = 11;
+parameter DATA_WIDTH1 = 9;
+parameter BE1_WIDTH1 = 1;
+parameter BE2_WIDTH1 = 1;
+
+input wire clk_a_0;
+input wire WEN_a_0;
+input wire REN_a_0;
+input wire [ADDR_WIDTH0-1 :0] WR_ADDR_a_0;
+input wire [ADDR_WIDTH0-1 :0] RD_ADDR_a_0;
+input wire [DATA_WIDTH0-1 :0] WDATA_a_0;
+output wire [DATA_WIDTH0-1 :0] RDATA_a_0;
+
+input wire clk_b_0;
+input wire WEN_b_0;
+input wire REN_b_0;
+input wire [ADDR_WIDTH0-1 :0] WR_ADDR_b_0;
+input wire [ADDR_WIDTH0-1 :0] RD_ADDR_b_0;
+input wire [DATA_WIDTH0-1 :0] WDATA_b_0;
+output wire [DATA_WIDTH0-1 :0] RDATA_b_0;
+
+input wire clk_a_1;
+input wire WEN_a_1;
+input wire REN_a_1;
+input wire [ADDR_WIDTH1-1 :0] WR_ADDR_a_1;
+input wire [ADDR_WIDTH1-1 :0] RD_ADDR_a_1;
+input wire [DATA_WIDTH1-1 :0] WDATA_a_1;
+output wire [DATA_WIDTH1-1 :0] RDATA_a_1;
+
+input wire clk_b_1;
+input wire WEN_b_1;
+input wire REN_b_1;
+input wire [ADDR_WIDTH1-1 :0] WR_ADDR_b_1;
+input wire [ADDR_WIDTH1-1 :0] RD_ADDR_b_1;
+input wire [DATA_WIDTH1-1 :0] WDATA_b_1;
+output wire [DATA_WIDTH1-1 :0] RDATA_b_1;
+ 
+DPRAM_18K_BLK #(
+              .ADDR_WIDTH(ADDR_WIDTH0),
+              .DATA_WIDTH(DATA_WIDTH0),
+              .BE1_WIDTH(BE1_WIDTH0),
+              .BE2_WIDTH(BE2_WIDTH0)
+              ) dpram_x18_inst0 ( 
+              
+              .CLK1_i(clk_a_0),
+              .WEN1_i(WEN_a_0),
+              .REN1_i(REN_a_0),
+              .WR1_ADDR_i(WR_ADDR_a_0),
+              .RD1_ADDR_i(RD_ADDR_a_0),
+              .WDATA1_i(WDATA_a_0),
+              .RDATA1_o(RDATA_a_0),
+              
+              .CLK2_i(clk_b_0),
+              .WEN2_i(WEN_b_0),
+              .REN2_i(REN_b_0),
+              .WR2_ADDR_i(WR_ADDR_b_0),
+              .RD2_ADDR_i(RD_ADDR_b_0),
+              .WDATA2_i(WDATA_b_0),
+              .RDATA2_o(RDATA_b_0)
+              );
+              
+ 
+DPRAM_18K_BLK #(
+              .ADDR_WIDTH(ADDR_WIDTH1),
+              .DATA_WIDTH(DATA_WIDTH1),
+              .BE1_WIDTH(BE1_WIDTH1),
+              .BE2_WIDTH(BE2_WIDTH1)
+              ) dpram_x18_inst1 ( 
+              
+              .CLK1_i(clk_a_1),
+              .WEN1_i(WEN_a_1),
+              .REN1_i(REN_a_1),
+              .WR1_ADDR_i(WR_ADDR_a_1),
+              .RD1_ADDR_i(RD_ADDR_a_1),
+              .WDATA1_i(WDATA_a_1),
+              .RDATA1_o(RDATA_a_1),
+              
+              .CLK2_i(clk_b_1),
+              .WEN2_i(WEN_b_1),
+              .REN2_i(REN_b_1),
+              .WR2_ADDR_i(WR_ADDR_b_1),
+              .RD2_ADDR_i(RD_ADDR_b_1),
+              .WDATA2_i(WDATA_b_1),
+              .RDATA2_o(RDATA_b_1)
+              );
+              
+endmodule    
+
+module dpram_18x1024_9x2048 (   
+    clk_a_0,
+    WEN_a_0,
+    REN_a_0,
+    WR_ADDR_a_0,
+    RD_ADDR_a_0,
+    WDATA_a_0,
+    RDATA_a_0,
+    
+    clk_b_0,
+    WEN_b_0,
+    REN_b_0,
+    WR_ADDR_b_0,
+    RD_ADDR_b_0,
+    WDATA_b_0,
+    RDATA_b_0,
+    
+    clk_a_1,
+    WEN_a_1,
+    REN_a_1,
+    WR_ADDR_a_1,
+    RD_ADDR_a_1,
+    WDATA_a_1,
+    RDATA_a_1,
+    
+    clk_b_1,
+    WEN_b_1,
+    REN_b_1,
+    WR_ADDR_b_1,
+    RD_ADDR_b_1,
+    WDATA_b_1,
+    RDATA_b_1
+);
+
+parameter ADDR_WIDTH0 = 10;
+parameter DATA_WIDTH0 = 18;
+parameter BE1_WIDTH0 = 2;
+parameter BE2_WIDTH0 = 2;
+
+parameter ADDR_WIDTH1 = 11;
+parameter DATA_WIDTH1 = 9;
+parameter BE1_WIDTH1 = 1;
+parameter BE2_WIDTH1 = 1;
+
+input wire clk_a_0;
+input wire WEN_a_0;
+input wire REN_a_0;
+input wire [ADDR_WIDTH0-1 :0] WR_ADDR_a_0;
+input wire [ADDR_WIDTH0-1 :0] RD_ADDR_a_0;
+input wire [DATA_WIDTH0-1 :0] WDATA_a_0;
+output wire [DATA_WIDTH0-1 :0] RDATA_a_0;
+
+input wire clk_b_0;
+input wire WEN_b_0;
+input wire REN_b_0;
+input wire [ADDR_WIDTH0-1 :0] WR_ADDR_b_0;
+input wire [ADDR_WIDTH0-1 :0] RD_ADDR_b_0;
+input wire [DATA_WIDTH0-1 :0] WDATA_b_0;
+output wire [DATA_WIDTH0-1 :0] RDATA_b_0;
+
+input wire clk_a_1;
+input wire WEN_a_1;
+input wire REN_a_1;
+input wire [ADDR_WIDTH1-1 :0] WR_ADDR_a_1;
+input wire [ADDR_WIDTH1-1 :0] RD_ADDR_a_1;
+input wire [DATA_WIDTH1-1 :0] WDATA_a_1;
+output wire [DATA_WIDTH1-1 :0] RDATA_a_1;
+
+input wire clk_b_1;
+input wire WEN_b_1;
+input wire REN_b_1;
+input wire [ADDR_WIDTH1-1 :0] WR_ADDR_b_1;
+input wire [ADDR_WIDTH1-1 :0] RD_ADDR_b_1;
+input wire [DATA_WIDTH1-1 :0] WDATA_b_1;
+output wire [DATA_WIDTH1-1 :0] RDATA_b_1;
+ 
+DPRAM_18K_BLK #(
+              .ADDR_WIDTH(ADDR_WIDTH0),
+              .DATA_WIDTH(DATA_WIDTH0),
+              .BE1_WIDTH(BE1_WIDTH0),
+              .BE2_WIDTH(BE2_WIDTH0)
+              ) dpram_x18_inst0 ( 
+              
+              .CLK1_i(clk_a_0),
+              .WEN1_i(WEN_a_0),
+              .REN1_i(REN_a_0),
+              .WR1_ADDR_i(WR_ADDR_a_0),
+              .RD1_ADDR_i(RD_ADDR_a_0),
+              .WDATA1_i(WDATA_a_0),
+              .RDATA1_o(RDATA_a_0),
+              
+              .CLK2_i(clk_b_0),
+              .WEN2_i(WEN_b_0),
+              .REN2_i(REN_b_0),
+              .WR2_ADDR_i(WR_ADDR_b_0),
+              .RD2_ADDR_i(RD_ADDR_b_0),
+              .WDATA2_i(WDATA_b_0),
+              .RDATA2_o(RDATA_b_0)
+              );
+              
+ 
+DPRAM_18K_BLK #(
+              .ADDR_WIDTH(ADDR_WIDTH1),
+              .DATA_WIDTH(DATA_WIDTH1),
+              .BE1_WIDTH(BE1_WIDTH1),
+              .BE2_WIDTH(BE2_WIDTH1)
+              ) dpram_x18_inst1 ( 
+              
+              .CLK1_i(clk_a_1),
+              .WEN1_i(WEN_a_1),
+              .REN1_i(REN_a_1),
+              .WR1_ADDR_i(WR_ADDR_a_1),
+              .RD1_ADDR_i(RD_ADDR_a_1),
+              .WDATA1_i(WDATA_a_1),
+              .RDATA1_o(RDATA_a_1),
+              
+              .CLK2_i(clk_b_1),
+              .WEN2_i(WEN_b_1),
+              .REN2_i(REN_b_1),
+              .WR2_ADDR_i(WR_ADDR_b_1),
+              .RD2_ADDR_i(RD_ADDR_b_1),
+              .WDATA2_i(WDATA_b_1),
+              .RDATA2_o(RDATA_b_1)
+              );
+              
+endmodule    
\ No newline at end of file
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_tdp/sim/Makefile b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_tdp/sim/Makefile
new file mode 100644
index 0000000..b9883eb
--- /dev/null
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_tdp/sim/Makefile
@@ -0,0 +1,48 @@
+# Copyright 2020-2022 F4PGA Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+TESTBENCH = bram18k_tdp_tb.v
+POST_SYNTH = dpram_18x1024_9x2048_post_synth dpram_9x2048_x2_post_synth dpram_18x1024_x2_post_synth   
+ADDR_WIDTH0 = 10 11 10
+DATA_WIDTH0 = 18 9 18
+ADDR_WIDTH1 = 11 11 10
+DATA_WIDTH1 = 9 9 18
+TOP = dpram_18x1024_9x2048 dpram_9x2048_x2 dpram_18x1024_x2
+ADDR_DEFINES0 = $(foreach awidth0, $(ADDR_WIDTH0),-DADDR_WIDTH0="$(awidth0)")
+ADDR_DEFINES1 = $(foreach awidth1, $(ADDR_WIDTH1),-DADDR_WIDTH1="$(awidth1)")
+DATA_DEFINES0 = $(foreach dwidth0, $(DATA_WIDTH0),-DDATA_WIDTH0="$(dwidth0)")
+DATA_DEFINES1 = $(foreach dwidth1, $(DATA_WIDTH1),-DDATA_WIDTH1="$(dwidth1)")
+TOP_DEFINES = $(foreach top, $(TOP),-DTOP="$(top)")
+VCD_DEFINES = $(foreach vcd, $(POST_SYNTH),-DVCD="$(vcd).vcd")
+
+SIM_LIBS = $(shell find ../../../../qlf_k6n10f -name "*.v" -not -name "*_map.v")
+
+define simulate_post_synth
+	@iverilog  -vvvv -g2005 $(word $(1),$(ADDR_DEFINES0)) $(word $(1),$(ADDR_DEFINES1)) $(word $(1),$(DATA_DEFINES0)) $(word $(1),$(DATA_DEFINES1)) $(word $(1),$(TOP_DEFINES)) $(word $(1),$(VCD_DEFINES)) -o $(word $(1),$(POST_SYNTH)).vvp $(word $(1),$(POST_SYNTH)).v $(SIM_LIBS) $(TESTBENCH) > $(word $(1),$(POST_SYNTH)).vvp.log 2>&1
+	@vvp -vvvv $(word $(1),$(POST_SYNTH)).vvp > $(word $(1),$(POST_SYNTH)).vcd.log 2>&1
+endef
+
+define clean_post_synth_sim
+	@rm -rf  $(word $(1),$(POST_SYNTH)).vcd $(word $(1),$(POST_SYNTH)).vvp $(word $(1),$(POST_SYNTH)).vvp.log $(word $(1),$(POST_SYNTH)).vcd.log
+endef
+
+sim:
+	$(call simulate_post_synth,1)
+	$(call clean_post_synth_sim,1)
+	$(call simulate_post_synth,2)
+	$(call clean_post_synth_sim,2)
+	$(call simulate_post_synth,3)
+	$(call clean_post_synth_sim,3)
\ No newline at end of file
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_tdp/sim/bram18k_tdp_tb.v b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_tdp/sim/bram18k_tdp_tb.v
new file mode 100644
index 0000000..004f32c
--- /dev/null
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_tdp/sim/bram18k_tdp_tb.v
@@ -0,0 +1,364 @@
+// Copyright 2020-2022 F4PGA Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//		 http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
+`timescale 1ns/1ps
+
+`define STRINGIFY(x) `"x`"
+
+module TB;
+	localparam PERIOD = 50;
+	localparam ADDR_INCR = 1;
+
+	reg clk_a;
+	reg rce_a_0;
+	reg rce_a_1;
+	reg [`ADDR_WIDTH0-1:0] ra_a_0;
+	reg [`ADDR_WIDTH1-1:0] ra_a_1;
+	wire [`DATA_WIDTH0-1:0] rq_a_0;
+	wire [`DATA_WIDTH1-1:0] rq_a_1;
+	reg wce_a_0;
+	reg wce_a_1;
+	reg [`ADDR_WIDTH0-1:0] wa_a_0;
+	reg [`ADDR_WIDTH1-1:0] wa_a_1;
+	reg [`DATA_WIDTH0-1:0] wd_a_0;
+	reg [`DATA_WIDTH1-1:0] wd_a_1;
+
+	reg clk_b;
+	reg rce_b_0;
+	reg rce_b_1;
+	reg [`ADDR_WIDTH0-1:0] ra_b_0;
+	reg [`ADDR_WIDTH1-1:0] ra_b_1;
+	wire [`DATA_WIDTH0-1:0] rq_b_0;
+	wire [`DATA_WIDTH1-1:0] rq_b_1;
+	reg wce_b_0;
+	reg wce_b_1;
+	reg [`ADDR_WIDTH0-1:0] wa_b_0;
+	reg [`ADDR_WIDTH1-1:0] wa_b_1;
+	reg [`DATA_WIDTH0-1:0] wd_b_0;
+	reg [`DATA_WIDTH1-1:0] wd_b_1;
+
+
+	initial clk_a = 0;
+	initial clk_b = 0;
+	initial ra_a_0 = 0;
+	initial ra_a_1 = 0;
+	initial ra_b_0 = 0;
+	initial ra_b_1 = 0;
+	initial rce_a_0 = 0;
+	initial rce_a_1 = 0;
+	initial rce_b_0 = 0;
+	initial rce_b_1 = 0;
+	initial wce_a_0 = 0;
+	initial wce_a_1 = 0;
+	initial wce_b_0 = 0;
+	initial wce_b_1 = 0;
+	initial forever #(PERIOD / 2.0) clk_a = ~clk_a;
+	initial begin
+		#(PERIOD / 4.0);
+		forever #(PERIOD / 2.0) clk_b = ~clk_b;
+	end	 
+	initial begin
+		$dumpfile(`STRINGIFY(`VCD));
+		$dumpvars;
+	end
+
+	integer a0;
+	integer b0;
+	integer a1;
+	integer b1;
+
+	reg done_a0;
+	reg done_b0;
+	reg done_a1;
+	reg done_b1;
+	initial done_a0 = 1'b0;
+	initial done_b0 = 1'b0;
+	initial done_a1 = 1'b0;
+	initial done_b1 = 1'b0;
+	wire done_sim = done_a0 & done_b0 & done_a1 & done_b1;
+
+	reg [`DATA_WIDTH0-1:0] expected_a_0;
+	reg [`DATA_WIDTH1-1:0] expected_a_1;
+	reg [`DATA_WIDTH0-1:0] expected_b_0;
+	reg [`DATA_WIDTH1-1:0] expected_b_1;
+
+	always @(posedge clk_a) begin
+			expected_a_0 <= (a0 | (a0 << 20) | 20'h55000) & {`DATA_WIDTH0{1'b1}};
+			expected_a_1 <= ((a1+1) | ((a1+1) << 20) | 20'h55000) & {`DATA_WIDTH1{1'b1}};
+	end
+	always @(posedge clk_b) begin
+			expected_b_0 <= ((b0+2) | ((b0+2) << 20) | 20'h55000) & {`DATA_WIDTH0{1'b1}};
+			expected_b_1 <= ((b1+3) | ((b1+3) << 20) | 20'h55000) & {`DATA_WIDTH1{1'b1}};
+	end
+
+	wire error_a_0 = a0 != 0 ? (rq_a_0 !== expected_a_0) : 0;
+	wire error_a_1 = a1 != 0 ? (rq_a_1 !== expected_a_1) : 0;
+	wire error_b_0 = b0 != (1<<`ADDR_WIDTH0) / 2 ? (rq_b_0 !== expected_b_0) : 0;
+	wire error_b_1 = b1 != (1<<`ADDR_WIDTH1) / 2 ? (rq_b_1 !== expected_b_1) : 0;
+
+	integer error_a_0_cnt = 0;
+	integer error_a_1_cnt = 0;
+	integer error_b_0_cnt = 0;
+	integer error_b_1_cnt = 0;
+
+	always @ (posedge clk_a)
+	begin
+		if (error_a_0)
+			error_a_0_cnt <= error_a_0_cnt + 1'b1;
+		if (error_a_1)
+			error_a_1_cnt <= error_a_1_cnt + 1'b1;
+	end
+	always @ (posedge clk_b)
+	begin
+		if (error_b_0)
+			error_b_0_cnt <= error_b_0_cnt + 1'b1;
+		if (error_b_1)
+			error_b_1_cnt <= error_b_1_cnt + 1'b1;
+	end
+
+	// PORTs A0
+	initial #(1) begin
+		// Write data
+		for (a0 = 0; a0 < (1<<`ADDR_WIDTH0) / 2; a0 = a0 + ADDR_INCR) begin
+			@(negedge clk_a) begin
+				wa_a_0 = a0;
+				wd_a_0 = a0 | (a0 << 20) | 20'h55000;
+				wce_a_0 = 1;
+			end
+			@(posedge clk_a) begin
+				#(PERIOD/10) wce_a_0 = 0;
+			end
+		end
+		// Read data
+		for (a0 = 0; a0 < (1<<`ADDR_WIDTH0) / 2; a0 = a0 + ADDR_INCR) begin
+			@(negedge clk_a) begin
+				ra_a_0 = a0;
+				rce_a_0 = 1;
+			end
+			@(posedge clk_a) begin
+				#(PERIOD/10) rce_a_0 = 0;
+				if ( rq_a_0 !== expected_a_0) begin
+					$display("%d: PORT A0: FAIL: mismatch act=%x exp=%x at %x", $time, rq_a_0, expected_a_0, a0);
+				end else begin
+					$display("%d: PORT A0: OK: act=%x exp=%x at %x", $time, rq_a_0, expected_a_0, a0);
+				end
+			end
+		end
+		done_a0 = 1'b1;
+		a0 = 0;
+		// PORTs B0
+		@(posedge clk_b)
+		#2;
+		// Write data
+		for (b0 = (1<<`ADDR_WIDTH0) / 2; b0 < (1<<`ADDR_WIDTH0); b0 = b0 + ADDR_INCR) begin
+			@(negedge clk_b) begin
+				wa_b_0 = b0;
+				wd_b_0 = (b0+2) | ((b0+2) << 20) | 20'h55000;
+				wce_b_0 = 1;
+			end
+			@(posedge clk_b) begin
+				#(PERIOD/10) wce_b_0 = 0;
+			end
+		end
+		// Read data
+		for (b0 = (1<<`ADDR_WIDTH0) / 2; b0 < (1<<`ADDR_WIDTH0); b0 = b0 + ADDR_INCR) begin
+			@(negedge clk_b) begin
+				ra_b_0 = b0;
+				rce_b_0 = 1;
+			end
+			@(posedge clk_b) begin
+				#(PERIOD/10) rce_b_0 = 0;
+				if ( rq_b_0 !== expected_b_0) begin
+					$display("%d: PORT B0: FAIL: mismatch act=%x exp=%x at %x", $time, rq_b_0, expected_b_0, b0);
+				end else begin
+					$display("%d: PORT B0: OK: act=%x exp=%x at %x", $time, rq_b_0, expected_b_0, b0);
+				end
+			end
+		end
+		done_b0 = 1'b1;
+		b0 = (1<<`ADDR_WIDTH0) / 2;
+		// PORTs A1
+		@(posedge clk_a)
+		#2;
+		// Write data
+		for (a1 = 0; a1 < (1<<`ADDR_WIDTH1) / 2; a1 = a1 + ADDR_INCR) begin
+			@(negedge clk_a) begin
+				wa_a_1 = a1;
+				wd_a_1 = (a1+1) | ((a1+1) << 20) | 20'h55000;
+				wce_a_1 = 1;
+			end
+			@(posedge clk_a) begin
+				#(PERIOD/10) wce_a_1 = 0;
+			end
+		end
+		// Read data
+		for (a1 = 0; a1 < (1<<`ADDR_WIDTH1) / 2; a1 = a1 + ADDR_INCR) begin
+			@(negedge clk_a) begin
+				ra_a_1 = a1;
+				rce_a_1 = 1;
+			end
+			@(posedge clk_a) begin
+				#(PERIOD/10) rce_a_1 = 0;
+				if ( rq_a_1 !== expected_a_1) begin
+					$display("%d: PORT A1: FAIL: mismatch act=%x exp=%x at %x", $time, rq_a_1, expected_a_1, a1);
+				end else begin
+					$display("%d: PORT A1: OK: act=%x exp=%x at %x", $time, rq_a_1, expected_a_1, a1);
+				end
+			end
+		end
+		done_a1 = 1'b1;
+		a1 = 0;
+		// PORTs B1
+		@(posedge clk_b)
+		#2;
+		// Write data
+		for (b1 = (1<<`ADDR_WIDTH1) / 2; b1 < (1<<`ADDR_WIDTH1); b1 = b1 + ADDR_INCR) begin
+			@(negedge clk_b) begin
+				wa_b_1 = b1;
+				wd_b_1 = (b1+3) | ((b1+3) << 20) | 20'h55000;
+				wce_b_1 = 1;
+			end
+			@(posedge clk_b) begin
+				#(PERIOD/10) wce_b_1 = 0;
+			end
+		end
+		// Read data
+		for (b1 = (1<<`ADDR_WIDTH1) / 2; b1 < (1<<`ADDR_WIDTH1); b1 = b1 + ADDR_INCR) begin
+			@(negedge clk_b) begin
+				ra_b_1 = b1;
+				rce_b_1 = 1;
+			end
+			@(posedge clk_b) begin
+				#(PERIOD/10) rce_b_1 = 0;
+				if ( rq_b_1 !== expected_b_1) begin
+					$display("%d: PORT B1: FAIL: mismatch act=%x exp=%x at %x", $time, rq_b_1, expected_b_1, b1);
+				end else begin
+					$display("%d: PORT B1: OK: act=%x exp=%x at %x", $time, rq_b_1, expected_b_1, b1);
+				end
+			end
+		end
+		done_b1 = 1'b1;
+		b1 = (1<<`ADDR_WIDTH1) / 2;
+	end
+
+	// Scan for simulation finish
+	always @(posedge clk_a, posedge clk_b) begin
+		if (done_sim)
+			$finish_and_return( (error_a_0_cnt == 0 & error_b_0_cnt == 0 & error_a_1_cnt == 0 & error_b_1_cnt == 0) ? 0 : -1 );
+	end
+	
+	case (`STRINGIFY(`TOP))
+		"dpram_18x1024_9x2048": begin
+			dpram_18x1024_9x2048 #() bram (
+				.clk_a_0(clk_a),
+				.REN_a_0(rce_a_0),
+				.RD_ADDR_a_0(ra_a_0),
+				.RDATA_a_0(rq_a_0),
+				.WEN_a_0(wce_a_0),
+				.WR_ADDR_a_0(wa_a_0),
+				.WDATA_a_0(wd_a_0),
+				.clk_b_0(clk_b),
+				.REN_b_0(rce_b_0),
+				.RD_ADDR_b_0(ra_b_0),
+				.RDATA_b_0(rq_b_0),
+				.WEN_b_0(wce_b_0),
+				.WR_ADDR_b_0(wa_b_0),
+				.WDATA_b_0(wd_b_0),
+
+				.clk_a_1(clk_a),
+				.REN_a_1(rce_a_1),
+				.RD_ADDR_a_1(ra_a_1),
+				.RDATA_a_1(rq_a_1),
+				.WEN_a_1(wce_a_1),
+				.WR_ADDR_a_1(wa_a_1),
+				.WDATA_a_1(wd_a_1),
+				.clk_b_1(clk_b),
+				.REN_b_1(rce_b_1),
+				.RD_ADDR_b_1(ra_b_1),
+				.RDATA_b_1(rq_b_1),
+				.WEN_b_1(wce_b_1),
+				.WR_ADDR_b_1(wa_b_1),
+				.WDATA_b_1(wd_b_1)
+			);
+		end
+		"dpram_9x2048_x2": begin
+			dpram_9x2048_x2 #() bram (
+				.clk_a_0(clk_a),
+				.REN_a_0(rce_a_0),
+				.RD_ADDR_a_0(ra_a_0),
+				.RDATA_a_0(rq_a_0),
+				.WEN_a_0(wce_a_0),
+				.WR_ADDR_a_0(wa_a_0),
+				.WDATA_a_0(wd_a_0),
+				.clk_b_0(clk_b),
+				.REN_b_0(rce_b_0),
+				.RD_ADDR_b_0(ra_b_0),
+				.RDATA_b_0(rq_b_0),
+				.WEN_b_0(wce_b_0),
+				.WR_ADDR_b_0(wa_b_0),
+				.WDATA_b_0(wd_b_0),
+
+				.clk_a_1(clk_a),
+				.REN_a_1(rce_a_1),
+				.RD_ADDR_a_1(ra_a_1),
+				.RDATA_a_1(rq_a_1),
+				.WEN_a_1(wce_a_1),
+				.WR_ADDR_a_1(wa_a_1),
+				.WDATA_a_1(wd_a_1),
+				.clk_b_1(clk_b),
+				.REN_b_1(rce_b_1),
+				.RD_ADDR_b_1(ra_b_1),
+				.RDATA_b_1(rq_b_1),
+				.WEN_b_1(wce_b_1),
+				.WR_ADDR_b_1(wa_b_1),
+				.WDATA_b_1(wd_b_1)
+			);
+		end
+		"dpram_18x1024_x2": begin
+			dpram_18x1024_x2 #() bram (
+				.clk_a_0(clk_a),
+				.REN_a_0(rce_a_0),
+				.RD_ADDR_a_0(ra_a_0),
+				.RDATA_a_0(rq_a_0),
+				.WEN_a_0(wce_a_0),
+				.WR_ADDR_a_0(wa_a_0),
+				.WDATA_a_0(wd_a_0),
+				.clk_b_0(clk_b),
+				.REN_b_0(rce_b_0),
+				.RD_ADDR_b_0(ra_b_0),
+				.RDATA_b_0(rq_b_0),
+				.WEN_b_0(wce_b_0),
+				.WR_ADDR_b_0(wa_b_0),
+				.WDATA_b_0(wd_b_0),
+
+				.clk_a_1(clk_a),
+				.REN_a_1(rce_a_1),
+				.RD_ADDR_a_1(ra_a_1),
+				.RDATA_a_1(rq_a_1),
+				.WEN_a_1(wce_a_1),
+				.WR_ADDR_a_1(wa_a_1),
+				.WDATA_a_1(wd_a_1),
+				.clk_b_1(clk_b),
+				.REN_b_1(rce_b_1),
+				.RD_ADDR_b_1(ra_b_1),
+				.RDATA_b_1(rq_b_1),
+				.WEN_b_1(wce_b_1),
+				.WR_ADDR_b_1(wa_b_1),
+				.WDATA_b_1(wd_b_1)
+			);
+		end
+	endcase
+endmodule
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_afifo/bram36k_afifo.tcl b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_afifo/bram36k_afifo.tcl
new file mode 100644
index 0000000..dacbe77
--- /dev/null
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_afifo/bram36k_afifo.tcl
@@ -0,0 +1,38 @@
+yosys -import
+
+if { [info procs ql-qlf-k6n10f] == {} } { plugin -i ql-qlf }
+yosys -import  ;
+
+read_verilog $::env(DESIGN_TOP).v
+design -save bram36k_afifo
+
+select af1024x36_1024x36
+select *
+synth_quicklogic -family qlf_k6n10f -top af1024x36_1024x36 -bram_types
+opt_expr -undriven
+opt_clean
+stat
+write_verilog sim/af1024x36_1024x36_post_synth.v
+select -assert-count 1 t:TDP36K_FIFO_ASYNC_WR_X36_RD_X36_nonsplit
+
+select -clear
+design -load bram36k_afifo
+select af2048x18_2048x18
+select *
+synth_quicklogic -family qlf_k6n10f -top af2048x18_2048x18 -bram_types
+opt_expr -undriven
+opt_clean
+stat
+write_verilog sim/af2048x18_2048x18_post_synth.v
+select -assert-count 1 t:TDP36K_FIFO_ASYNC_WR_X18_RD_X18_nonsplit
+
+select -clear
+design -load bram36k_afifo
+select af4096x9_4096x9
+select *
+synth_quicklogic -family qlf_k6n10f -top af4096x9_4096x9 -bram_types
+opt_expr -undriven
+opt_clean
+stat
+write_verilog sim/af4096x9_4096x9_post_synth.v
+select -assert-count 1 t:TDP36K_FIFO_ASYNC_WR_X9_RD_X9_nonsplit
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_afifo/bram36k_afifo.v b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_afifo/bram36k_afifo.v
new file mode 100644
index 0000000..2fc55ee
--- /dev/null
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_afifo/bram36k_afifo.v
@@ -0,0 +1,138 @@
+// Copyright 2020-2022 F4PGA Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
+module af1024x36_1024x36 (DIN,PUSH,POP,clock0,clock1,Async_Flush,Almost_Full,Almost_Empty,Full,Empty,Full_Watermark,Empty_Watermark,Overrun_Error,Underrun_Error,DOUT);
+
+parameter WR_DATA_WIDTH = 36;
+parameter RD_DATA_WIDTH = 36;
+parameter UPAE_DBITS = 12'd10;
+parameter UPAF_DBITS = 12'd10;
+
+input clock0,clock1;
+input PUSH,POP;
+input [WR_DATA_WIDTH-1:0] DIN;
+input Async_Flush;
+output [RD_DATA_WIDTH-1:0] DOUT;
+output Almost_Full,Almost_Empty;
+output Full, Empty;
+output Full_Watermark, Empty_Watermark;
+output Overrun_Error, Underrun_Error;
+
+AFIFO_36K_BLK  # (.WR_DATA_WIDTH(WR_DATA_WIDTH),.RD_DATA_WIDTH(RD_DATA_WIDTH),.UPAE_DBITS(UPAE_DBITS),.UPAF_DBITS(UPAF_DBITS)
+                  )
+  FIFO_INST    (
+                .DIN(DIN),
+                .PUSH(PUSH),
+                .POP(POP),
+                .Push_Clk(clock0),
+                .Pop_Clk(clock1),
+                .Async_Flush(Async_Flush),
+                
+                .Overrun_Error(Overrun_Error),
+                .Full_Watermark(Full_Watermark),
+                .Almost_Full(Almost_Full),
+                .Full(Full),
+                
+                .Underrun_Error(Underrun_Error),
+                .Empty_Watermark(Empty_Watermark),
+                .Almost_Empty(Almost_Empty),
+                .Empty(Empty),
+
+                .DOUT(DOUT)
+                );
+endmodule
+
+module af2048x18_2048x18 (DIN,PUSH,POP,clock0,clock1,Async_Flush,Almost_Full,Almost_Empty,Full,Empty,Full_Watermark,Empty_Watermark,Overrun_Error,Underrun_Error,DOUT);
+
+parameter WR_DATA_WIDTH = 18;
+parameter RD_DATA_WIDTH = 18;
+parameter UPAE_DBITS = 12'd10;
+parameter UPAF_DBITS = 12'd10;
+
+input clock0,clock1;
+input PUSH,POP;
+input [WR_DATA_WIDTH-1:0] DIN;
+input Async_Flush;
+output [RD_DATA_WIDTH-1:0] DOUT;
+output Almost_Full,Almost_Empty;
+output Full, Empty;
+output Full_Watermark, Empty_Watermark;
+output Overrun_Error, Underrun_Error;
+
+AFIFO_36K_BLK  # (.WR_DATA_WIDTH(WR_DATA_WIDTH),.RD_DATA_WIDTH(RD_DATA_WIDTH),.UPAE_DBITS(UPAE_DBITS),.UPAF_DBITS(UPAF_DBITS)
+                  )
+  FIFO_INST    (
+                .DIN(DIN),
+                .PUSH(PUSH),
+                .POP(POP),
+                .Push_Clk(clock0),
+                .Pop_Clk(clock1),
+                .Async_Flush(Async_Flush),
+                
+                .Overrun_Error(Overrun_Error),
+                .Full_Watermark(Full_Watermark),
+                .Almost_Full(Almost_Full),
+                .Full(Full),
+                
+                .Underrun_Error(Underrun_Error),
+                .Empty_Watermark(Empty_Watermark),
+                .Almost_Empty(Almost_Empty),
+                .Empty(Empty),
+
+                .DOUT(DOUT)
+                );
+endmodule
+
+module af4096x9_4096x9 (DIN,PUSH,POP,clock0,clock1,Async_Flush,Almost_Full,Almost_Empty,Full,Empty,Full_Watermark,Empty_Watermark,Overrun_Error,Underrun_Error,DOUT);
+
+parameter WR_DATA_WIDTH = 9;
+parameter RD_DATA_WIDTH = 9;
+parameter UPAE_DBITS = 12'd10;
+parameter UPAF_DBITS = 12'd10;
+
+input clock0,clock1;
+input PUSH,POP;
+input [WR_DATA_WIDTH-1:0] DIN;
+input Async_Flush;
+output [RD_DATA_WIDTH-1:0] DOUT;
+output Almost_Full,Almost_Empty;
+output Full, Empty;
+output Full_Watermark, Empty_Watermark;
+output Overrun_Error, Underrun_Error;
+
+AFIFO_36K_BLK  # (.WR_DATA_WIDTH(WR_DATA_WIDTH),.RD_DATA_WIDTH(RD_DATA_WIDTH),.UPAE_DBITS(UPAE_DBITS),.UPAF_DBITS(UPAF_DBITS)
+                  )
+  FIFO_INST    (
+                .DIN(DIN),
+                .PUSH(PUSH),
+                .POP(POP),
+                .Push_Clk(clock0),
+                .Pop_Clk(clock1),
+                .Async_Flush(Async_Flush),
+                
+                .Overrun_Error(Overrun_Error),
+                .Full_Watermark(Full_Watermark),
+                .Almost_Full(Almost_Full),
+                .Full(Full),
+                
+                .Underrun_Error(Underrun_Error),
+                .Empty_Watermark(Empty_Watermark),
+                .Almost_Empty(Almost_Empty),
+                .Empty(Empty),
+
+                .DOUT(DOUT)
+                );
+endmodule
\ No newline at end of file
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_afifo/sim/Makefile b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_afifo/sim/Makefile
new file mode 100644
index 0000000..7c93214
--- /dev/null
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_afifo/sim/Makefile
@@ -0,0 +1,48 @@
+# Copyright 2020-2022 F4PGA Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+TESTBENCH = bram36k_afifo_tb.v
+POST_SYNTH = af1024x36_1024x36_post_synth af2048x18_2048x18_post_synth af4096x9_4096x9_post_synth
+ADDR_WIDTH0 = 10 11 12
+DATA_WIDTH0 = 36 18 9
+ADDR_WIDTH1 = 10 11 12
+DATA_WIDTH1 = 36 18 9
+TOP = af1024x36_1024x36 af2048x18_2048x18 af4096x9_4096x9
+ADDR0_DEFINES = $(foreach awidth0, $(ADDR_WIDTH0),-DADDR_WIDTH0="$(awidth0)")
+ADDR1_DEFINES = $(foreach awidth1, $(ADDR_WIDTH1),-DADDR_WIDTH1="$(awidth1)")
+DATA0_DEFINES = $(foreach dwidth0, $(DATA_WIDTH0),-DDATA_WIDTH0="$(dwidth0)")
+DATA1_DEFINES = $(foreach dwidth1, $(DATA_WIDTH1),-DDATA_WIDTH1="$(dwidth1)")
+TOP_DEFINES = $(foreach top, $(TOP),-DTOP="$(top)")
+VCD_DEFINES = $(foreach vcd, $(POST_SYNTH),-DVCD="$(vcd).vcd")
+
+SIM_LIBS = $(shell find ../../../../qlf_k6n10f -name "*.v" -not -name "*_map.v")
+
+define simulate_post_synth
+	@iverilog  -vvvv -g2005 $(word $(1),$(ADDR0_DEFINES)) $(word $(1),$(ADDR1_DEFINES)) $(word $(1),$(DATA0_DEFINES)) $(word $(1),$(DATA1_DEFINES)) $(word $(1),$(TOP_DEFINES)) $(word $(1),$(VCD_DEFINES)) -o $(word $(1),$(POST_SYNTH)).vvp $(word $(1),$(POST_SYNTH)).v $(SIM_LIBS) $(TESTBENCH) > $(word $(1),$(POST_SYNTH)).vvp.log 2>&1
+	@vvp -vvvv $(word $(1),$(POST_SYNTH)).vvp > $(word $(1),$(POST_SYNTH)).vcd.log 2>&1
+endef
+
+define clean_post_synth_sim
+	@rm -rf  $(word $(1),$(POST_SYNTH)).vcd $(word $(1),$(POST_SYNTH)).vvp $(word $(1),$(POST_SYNTH)).vvp.log $(word $(1),$(POST_SYNTH)).vcd.log
+endef
+
+sim:
+	$(call simulate_post_synth,1)
+	$(call clean_post_synth_sim,1)
+	$(call simulate_post_synth,2)
+	$(call clean_post_synth_sim,2)
+	$(call simulate_post_synth,3)
+	$(call clean_post_synth_sim,3)
\ No newline at end of file
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_afifo/sim/bram36k_afifo_tb.v b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_afifo/sim/bram36k_afifo_tb.v
new file mode 100644
index 0000000..48424fc
--- /dev/null
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_afifo/sim/bram36k_afifo_tb.v
@@ -0,0 +1,177 @@
+// Copyright 2020-2022 F4PGA Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//		 http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
+`timescale 1ns/1ps
+
+`define STRINGIFY(x) `"x`"
+
+module TB;
+	localparam PERIOD = 30;
+	localparam ADDR_INCR = 1;
+
+	reg clk0;
+	reg clk1;
+	reg flush;
+	reg pop;
+	wire [`DATA_WIDTH1-1:0] dout;
+	reg push;
+	reg [`DATA_WIDTH0-1:0] din;
+	wire almost_full,almost_empty;
+	wire full, empty;
+	wire full_watermark, empty_watermark;
+	wire overrun_error, underrun_error;
+
+	initial 
+	begin
+		clk0 = 0;
+		clk1 = 0;
+		pop = 0;
+		push = 0;
+		flush = 1;
+		din = 0;
+		#40
+		flush = 0;
+	end
+	
+	initial forever #(PERIOD / 3.0) clk0 = ~clk0;
+	initial forever #(PERIOD / 2.0) clk1 = ~clk1;
+	
+	initial begin
+		$dumpfile(`STRINGIFY(`VCD));
+		$dumpvars;
+	end
+
+	integer a;
+
+	reg done;
+	initial done = 1'b0;
+	
+	reg read_test;
+	initial read_test = 0;
+
+	reg [`DATA_WIDTH1-1:0] expected;
+	initial expected = 0;
+
+	always @(posedge clk1) begin
+		expected <= (a | (a << 20) | 20'h55000) & {`DATA_WIDTH1{1'b1}};
+	end
+
+	wire error = ((a != 0) && read_test) ? dout !== expected : 0;
+
+	integer error_cnt = 0;
+	always @ (posedge clk1)
+	begin
+		if (error)
+			error_cnt <= error_cnt + 1'b1; 
+	end
+
+
+	initial #(50) begin
+		@(posedge clk0)
+		// Write data
+		for (a = 0; a < (1<<`ADDR_WIDTH0); a = a + ADDR_INCR) begin
+			@(negedge clk0) begin
+				din = a | (a << 20) | 20'h55000;
+				push = 1;
+			end
+			@(posedge clk0) begin
+				#(PERIOD/10) push = 0;
+			end
+		end
+		// Read data
+		read_test = 1;
+		for (a = 0; a < (1<<`ADDR_WIDTH1); a = a + ADDR_INCR) begin
+			@(posedge clk1) begin
+				#(PERIOD/10) pop = 0;
+				if ( dout !== expected) begin
+					$display("%d: FAIL: mismatch act=%x exp=%x at %x", $time, dout, expected, a);
+				end else begin
+					$display("%d: OK: act=%x exp=%x at %x", $time, dout, expected, a);
+				end
+			end
+			@(negedge clk1) begin
+				pop = 1;
+			end
+		end
+		done = 1'b1;
+	end
+
+	// Scan for simulation finish
+	always @(posedge clk1) begin
+		if (done)
+			$finish_and_return( (error_cnt == 0) ? 0 : -1 );
+	end
+
+	case (`STRINGIFY(`TOP))
+		"af1024x36_1024x36": begin
+			af1024x36_1024x36 #() afifo (
+				.DIN(din),
+				.PUSH(push),
+				.POP(pop),
+				.clock0(clk0),
+				.clock1(clk1),
+				.Async_Flush(flush),
+				.Almost_Full(almost_full),
+				.Almost_Empty(almost_empty),
+				.Full(full),
+				.Empty(empty),
+				.Full_Watermark(full_watermark),
+				.Empty_Watermark(empty_watermark),
+				.Overrun_Error(overrun_error),
+				.Underrun_Error(underrun_error),
+				.DOUT(dout)
+			);
+		end
+		"af2048x18_2048x18": begin
+			af2048x18_2048x18 #() afifo (
+				.DIN(din),
+				.PUSH(push),
+				.POP(pop),
+				.clock0(clk0),
+				.clock1(clk1),
+				.Async_Flush(flush),
+				.Almost_Full(almost_full),
+				.Almost_Empty(almost_empty),
+				.Full(full),
+				.Empty(empty),
+				.Full_Watermark(full_watermark),
+				.Empty_Watermark(empty_watermark),
+				.Overrun_Error(overrun_error),
+				.Underrun_Error(underrun_error),
+				.DOUT(dout)
+			);
+		end
+		"af4096x9_4096x9": begin
+			af4096x9_4096x9 #() afifo (
+				.DIN(din),
+				.PUSH(push),
+				.POP(pop),
+				.clock0(clk0),
+				.clock1(clk1),
+				.Async_Flush(flush),
+				.Almost_Full(almost_full),
+				.Almost_Empty(almost_empty),
+				.Full(full),
+				.Empty(empty),
+				.Full_Watermark(full_watermark),
+				.Empty_Watermark(empty_watermark),
+				.Overrun_Error(overrun_error),
+				.Underrun_Error(underrun_error),
+				.DOUT(dout)
+			);
+		end		
+	endcase
+endmodule
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_sdp/bram36k_sdp.tcl b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_sdp/bram36k_sdp.tcl
new file mode 100644
index 0000000..b5d38b0
--- /dev/null
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_sdp/bram36k_sdp.tcl
@@ -0,0 +1,71 @@
+yosys -import
+
+if { [info procs ql-qlf-k6n10f] == {} } { plugin -i ql-qlf }
+yosys -import  ;
+
+read_verilog $::env(DESIGN_TOP).v
+design -save bram36_sdp
+
+select spram_36x1024
+select *
+synth_quicklogic -family qlf_k6n10f -top spram_36x1024 -bram_types
+opt_expr -undriven
+opt_clean
+stat
+write_verilog sim/spram_36x1024_post_synth.v
+select -assert-count 1 t:TDP36K_BRAM_WR_X36_RD_X36_nonsplit
+
+select -clear
+design -load bram36_sdp
+select spram_32x1024
+select *
+synth_quicklogic -family qlf_k6n10f -top spram_32x1024 -bram_types
+opt_expr -undriven
+opt_clean
+stat
+write_verilog sim/spram_32x1024_post_synth.v
+select -assert-count 1 t:TDP36K_BRAM_WR_X36_RD_X36_nonsplit
+
+select -clear
+design -load bram36_sdp
+select spram_18x2048
+select *
+synth_quicklogic -family qlf_k6n10f -top spram_18x2048 -bram_types
+opt_expr -undriven
+opt_clean
+stat
+write_verilog sim/spram_18x2048_post_synth.v
+select -assert-count 1 t:TDP36K_BRAM_WR_X18_RD_X18_nonsplit
+
+select -clear
+design -load bram36_sdp
+select spram_16x2048
+select *
+synth_quicklogic -family qlf_k6n10f -top spram_16x2048 -bram_types
+opt_expr -undriven
+opt_clean
+stat
+write_verilog sim/spram_16x2048_post_synth.v
+select -assert-count 1 t:TDP36K_BRAM_WR_X18_RD_X18_nonsplit
+
+select -clear
+design -load bram36_sdp
+select spram_9x4096
+select *
+synth_quicklogic -family qlf_k6n10f -top spram_9x4096 -bram_types
+opt_expr -undriven
+opt_clean
+stat
+write_verilog sim/spram_9x4096_post_synth.v
+select -assert-count 1 t:TDP36K_BRAM_WR_X9_RD_X9_nonsplit
+
+select -clear
+design -load bram36_sdp
+select spram_8x4096
+select *
+synth_quicklogic -family qlf_k6n10f -top spram_8x4096 -bram_types
+opt_expr -undriven
+opt_clean
+stat
+write_verilog sim/spram_8x4096_post_synth.v
+select -assert-count 1 t:TDP36K_BRAM_WR_X9_RD_X9_nonsplit
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_sdp/bram36k_sdp.v b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_sdp/bram36k_sdp.v
new file mode 100644
index 0000000..783bc36
--- /dev/null
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_sdp/bram36k_sdp.v
@@ -0,0 +1,297 @@
+// Copyright 2020-2022 F4PGA Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
+module spram_36x1024 (
+    WEN_i,
+    REN_i,
+    clock0,
+    clock1,
+    WR_ADDR_i,
+    RD_ADDR_i,
+    WDATA_i,
+    RDATA_o
+);
+
+parameter WR_ADDR_WIDTH = 10;
+parameter RD_ADDR_WIDTH = 10;
+parameter WR_DATA_WIDTH = 36;
+parameter RD_DATA_WIDTH = 36;
+parameter BE_WIDTH = 4;
+
+input wire WEN_i;
+input wire REN_i;
+input wire clock0;
+input wire clock1;
+input wire [WR_ADDR_WIDTH-1 :0] WR_ADDR_i;
+input wire [RD_ADDR_WIDTH-1 :0] RD_ADDR_i;
+input wire [WR_DATA_WIDTH-1 :0] WDATA_i;
+output wire [RD_DATA_WIDTH-1 :0] RDATA_o;
+
+RAM_36K_BLK #(
+              .WR_ADDR_WIDTH(WR_ADDR_WIDTH),
+              .RD_ADDR_WIDTH(RD_ADDR_WIDTH),
+              .WR_DATA_WIDTH(WR_DATA_WIDTH),
+              .RD_DATA_WIDTH(RD_DATA_WIDTH),
+              .BE_WIDTH(BE_WIDTH)
+              ) spram_x36_inst (
+              
+              .WEN_i(WEN_i),
+              .WR_BE_i(4'b1111),
+              .REN_i(REN_i),              
+              .WR_CLK_i(clock0),
+              .RD_CLK_i(clock1),
+              .WR_ADDR_i(WR_ADDR_i),
+              .RD_ADDR_i(RD_ADDR_i),
+              .WDATA_i(WDATA_i),
+              .RDATA_o(RDATA_o)
+              );
+              
+endmodule    
+
+module spram_32x1024 (
+    WEN_i,
+    REN_i,
+    clock0,
+    clock1,
+    WR_ADDR_i,
+    RD_ADDR_i,
+    WDATA_i,
+    RDATA_o
+);
+
+parameter WR_ADDR_WIDTH = 10;
+parameter RD_ADDR_WIDTH = 10;
+parameter WR_DATA_WIDTH = 32;
+parameter RD_DATA_WIDTH = 32;
+parameter BE_WIDTH = 4;
+
+input wire WEN_i;
+input wire REN_i;
+input wire clock0;
+input wire clock1;
+input wire [WR_ADDR_WIDTH-1 :0] WR_ADDR_i;
+input wire [RD_ADDR_WIDTH-1 :0] RD_ADDR_i;
+input wire [WR_DATA_WIDTH-1 :0] WDATA_i;
+output wire [RD_DATA_WIDTH-1 :0] RDATA_o;
+
+RAM_36K_BLK #(
+              .WR_ADDR_WIDTH(WR_ADDR_WIDTH),
+              .RD_ADDR_WIDTH(RD_ADDR_WIDTH),
+              .WR_DATA_WIDTH(WR_DATA_WIDTH),
+              .RD_DATA_WIDTH(RD_DATA_WIDTH),
+              .BE_WIDTH(BE_WIDTH)
+              ) spram_x36_inst (
+              
+              .WEN_i(WEN_i),
+              .WR_BE_i(4'b1111),
+              .REN_i(REN_i),              
+              .WR_CLK_i(clock0),
+              .RD_CLK_i(clock1),
+              .WR_ADDR_i(WR_ADDR_i),
+              .RD_ADDR_i(RD_ADDR_i),
+              .WDATA_i(WDATA_i),
+              .RDATA_o(RDATA_o)
+              );
+              
+endmodule   
+
+module spram_18x2048 (
+    WEN_i,
+    REN_i,
+    clock0,
+    clock1,
+    WR_ADDR_i,
+    RD_ADDR_i,
+    WDATA_i,
+    RDATA_o
+);
+
+parameter WR_ADDR_WIDTH = 11;
+parameter RD_ADDR_WIDTH = 11;
+parameter WR_DATA_WIDTH = 18;
+parameter RD_DATA_WIDTH = 18;
+parameter BE_WIDTH = 2;
+
+input wire WEN_i;
+input wire REN_i;
+input wire clock0;
+input wire clock1;
+input wire [WR_ADDR_WIDTH-1 :0] WR_ADDR_i;
+input wire [RD_ADDR_WIDTH-1 :0] RD_ADDR_i;
+input wire [WR_DATA_WIDTH-1 :0] WDATA_i;
+output wire [RD_DATA_WIDTH-1 :0] RDATA_o;
+
+RAM_36K_BLK #(
+              .WR_ADDR_WIDTH(WR_ADDR_WIDTH),
+              .RD_ADDR_WIDTH(RD_ADDR_WIDTH),
+              .WR_DATA_WIDTH(WR_DATA_WIDTH),
+              .RD_DATA_WIDTH(RD_DATA_WIDTH),
+              .BE_WIDTH(BE_WIDTH)
+              ) spram_x36_inst (
+              
+              .WEN_i(WEN_i),
+              .WR_BE_i(2'b11),
+              .REN_i(REN_i),              
+              .WR_CLK_i(clock0),
+              .RD_CLK_i(clock1),
+              .WR_ADDR_i(WR_ADDR_i),
+              .RD_ADDR_i(RD_ADDR_i),
+              .WDATA_i(WDATA_i),
+              .RDATA_o(RDATA_o)
+              );
+              
+endmodule    
+
+module spram_16x2048 (
+    WEN_i,
+    REN_i,
+    clock0,
+    clock1,
+    WR_ADDR_i,
+    RD_ADDR_i,
+    WDATA_i,
+    RDATA_o
+);
+
+parameter WR_ADDR_WIDTH = 11;
+parameter RD_ADDR_WIDTH = 11;
+parameter WR_DATA_WIDTH = 16;
+parameter RD_DATA_WIDTH = 16;
+parameter BE_WIDTH = 2;
+
+input wire WEN_i;
+input wire REN_i;
+input wire clock0;
+input wire clock1;
+input wire [WR_ADDR_WIDTH-1 :0] WR_ADDR_i;
+input wire [RD_ADDR_WIDTH-1 :0] RD_ADDR_i;
+input wire [WR_DATA_WIDTH-1 :0] WDATA_i;
+output wire [RD_DATA_WIDTH-1 :0] RDATA_o;
+
+RAM_36K_BLK #(
+              .WR_ADDR_WIDTH(WR_ADDR_WIDTH),
+              .RD_ADDR_WIDTH(RD_ADDR_WIDTH),
+              .WR_DATA_WIDTH(WR_DATA_WIDTH),
+              .RD_DATA_WIDTH(RD_DATA_WIDTH),
+              .BE_WIDTH(BE_WIDTH)
+              ) spram_x36_inst (
+              
+              .WEN_i(WEN_i),
+              .WR_BE_i(2'b11),
+              .REN_i(REN_i),              
+              .WR_CLK_i(clock0),
+              .RD_CLK_i(clock1),
+              .WR_ADDR_i(WR_ADDR_i),
+              .RD_ADDR_i(RD_ADDR_i),
+              .WDATA_i(WDATA_i),
+              .RDATA_o(RDATA_o)
+              );
+              
+endmodule    
+
+module spram_9x4096 (
+    WEN_i,
+    REN_i,
+    clock0,
+    clock1,
+    WR_ADDR_i,
+    RD_ADDR_i,
+    WDATA_i,
+    RDATA_o
+);
+
+parameter WR_ADDR_WIDTH = 12;
+parameter RD_ADDR_WIDTH = 12;
+parameter WR_DATA_WIDTH = 9;
+parameter RD_DATA_WIDTH = 9;
+parameter BE_WIDTH = 1;
+
+input wire WEN_i;
+input wire REN_i;
+input wire clock0;
+input wire clock1;
+input wire [WR_ADDR_WIDTH-1 :0] WR_ADDR_i;
+input wire [RD_ADDR_WIDTH-1 :0] RD_ADDR_i;
+input wire [WR_DATA_WIDTH-1 :0] WDATA_i;
+output wire [RD_DATA_WIDTH-1 :0] RDATA_o;
+
+RAM_36K_BLK #(
+              .WR_ADDR_WIDTH(WR_ADDR_WIDTH),
+              .RD_ADDR_WIDTH(RD_ADDR_WIDTH),
+              .WR_DATA_WIDTH(WR_DATA_WIDTH),
+              .RD_DATA_WIDTH(RD_DATA_WIDTH),
+              .BE_WIDTH(BE_WIDTH)
+              ) spram_x36_inst (
+              
+              .WEN_i(WEN_i),
+              .WR_BE_i(1'b1),
+              .REN_i(REN_i),              
+              .WR_CLK_i(clock0),
+              .RD_CLK_i(clock1),
+              .WR_ADDR_i(WR_ADDR_i),
+              .RD_ADDR_i(RD_ADDR_i),
+              .WDATA_i(WDATA_i),
+              .RDATA_o(RDATA_o)
+              );
+              
+endmodule    
+
+module spram_8x4096 (
+    WEN_i,
+    REN_i,
+    clock0,
+    clock1,
+    WR_ADDR_i,
+    RD_ADDR_i,
+    WDATA_i,
+    RDATA_o
+);
+
+parameter WR_ADDR_WIDTH = 12;
+parameter RD_ADDR_WIDTH = 12;
+parameter WR_DATA_WIDTH = 8;
+parameter RD_DATA_WIDTH = 8;
+parameter BE_WIDTH = 1;
+
+input wire WEN_i;
+input wire REN_i;
+input wire clock0;
+input wire clock1;
+input wire [WR_ADDR_WIDTH-1 :0] WR_ADDR_i;
+input wire [RD_ADDR_WIDTH-1 :0] RD_ADDR_i;
+input wire [WR_DATA_WIDTH-1 :0] WDATA_i;
+output wire [RD_DATA_WIDTH-1 :0] RDATA_o;
+
+RAM_36K_BLK #(
+              .WR_ADDR_WIDTH(WR_ADDR_WIDTH),
+              .RD_ADDR_WIDTH(RD_ADDR_WIDTH),
+              .WR_DATA_WIDTH(WR_DATA_WIDTH),
+              .RD_DATA_WIDTH(RD_DATA_WIDTH),
+              .BE_WIDTH(BE_WIDTH)
+              ) spram_x36_inst (
+              
+              .WEN_i(WEN_i),
+              .WR_BE_i(1'b1),
+              .REN_i(REN_i),              
+              .WR_CLK_i(clock0),
+              .RD_CLK_i(clock1),
+              .WR_ADDR_i(WR_ADDR_i),
+              .RD_ADDR_i(RD_ADDR_i),
+              .WDATA_i(WDATA_i),
+              .RDATA_o(RDATA_o)
+              );
+              
+endmodule    
\ No newline at end of file
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_sdp/sim/Makefile b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_sdp/sim/Makefile
new file mode 100644
index 0000000..05b231f
--- /dev/null
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_sdp/sim/Makefile
@@ -0,0 +1,50 @@
+# Copyright 2020-2022 F4PGA Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+TESTBENCH = bram36k_sdp_tb.v
+POST_SYNTH = spram_36x1024_post_synth spram_32x1024_post_synth spram_18x2048_post_synth spram_16x2048_post_synth spram_9x4096_post_synth spram_8x4096_post_synth
+ADDR_WIDTH = 10 10 11 11 12 12
+DATA_WIDTH = 36 32 18 16 9 8
+TOP = spram_36x1024 spram_32x1024 spram_18x2048 spram_16x2048 spram_9x4096 spram_8x4096
+ADDR_DEFINES = $(foreach awidth, $(ADDR_WIDTH),-DADDR_WIDTH="$(awidth)")
+DATA_DEFINES = $(foreach dwidth, $(DATA_WIDTH),-DDATA_WIDTH="$(dwidth)")
+TOP_DEFINES = $(foreach top, $(TOP),-DTOP="$(top)")
+VCD_DEFINES = $(foreach vcd, $(POST_SYNTH),-DVCD="$(vcd).vcd")
+
+SIM_LIBS = $(shell find ../../../../qlf_k6n10f -name "*.v" -not -name "*_map.v")
+
+define simulate_post_synth
+	@iverilog  -vvvv -g2005 $(word $(1),$(ADDR_DEFINES)) $(word $(1),$(DATA_DEFINES)) $(word $(1),$(TOP_DEFINES)) $(word $(1),$(VCD_DEFINES)) -o $(word $(1),$(POST_SYNTH)).vvp $(word $(1),$(POST_SYNTH)).v $(SIM_LIBS) $(TESTBENCH) > $(word $(1),$(POST_SYNTH)).vvp.log 2>&1
+	@vvp -vvvv $(word $(1),$(POST_SYNTH)).vvp > $(word $(1),$(POST_SYNTH)).vcd.log 2>&1
+endef
+
+define clean_post_synth_sim
+	@rm -rf  $(word $(1),$(POST_SYNTH)).vcd $(word $(1),$(POST_SYNTH)).vvp $(word $(1),$(POST_SYNTH)).vvp.log $(word $(1),$(POST_SYNTH)).vcd.log
+endef
+
+sim:
+	$(call simulate_post_synth,1)
+	$(call clean_post_synth_sim,1)
+	$(call simulate_post_synth,2)
+	$(call clean_post_synth_sim,2)
+	$(call simulate_post_synth,3)
+	$(call clean_post_synth_sim,3)
+	$(call simulate_post_synth,4)
+	$(call clean_post_synth_sim,4)
+	$(call simulate_post_synth,5)
+	$(call clean_post_synth_sim,5)
+	$(call simulate_post_synth,6)
+	$(call clean_post_synth_sim,6)
\ No newline at end of file
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_sdp/sim/bram36k_sdp_tb.v b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_sdp/sim/bram36k_sdp_tb.v
new file mode 100644
index 0000000..c47b873
--- /dev/null
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_sdp/sim/bram36k_sdp_tb.v
@@ -0,0 +1,176 @@
+// Copyright 2020-2022 F4PGA Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//		 http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
+`timescale 1ns/1ps
+
+`define STRINGIFY(x) `"x`"
+
+module TB;
+	localparam PERIOD = 50;
+	localparam ADDR_INCR = 1;
+
+	reg clk;
+	reg rce;
+	reg [`ADDR_WIDTH-1:0] ra;
+	wire [`DATA_WIDTH-1:0] rq;
+	reg wce;
+	reg [`ADDR_WIDTH-1:0] wa;
+	reg [`DATA_WIDTH-1:0] wd;
+
+	initial clk = 0;
+	initial ra = 0;
+	initial rce = 0;
+	initial forever #(PERIOD / 2.0) clk = ~clk;
+	initial begin
+		$dumpfile(`STRINGIFY(`VCD));
+		$dumpvars;
+	end
+
+	integer a;
+
+	reg done;
+	initial done = 1'b0;
+
+	reg [`DATA_WIDTH-1:0] expected;
+
+	always @(posedge clk) begin
+		expected <= (a | (a << 20) | 20'h55000) & {`DATA_WIDTH{1'b1}};
+	end
+
+	wire error = ((a != 0) && read_test) ? rq !== expected : 0;
+
+	integer error_cnt = 0;
+	always @ (posedge clk)
+	begin
+		if (error)
+			error_cnt <= error_cnt + 1'b1;
+	end
+
+	reg read_test;
+	initial read_test = 0;
+
+	initial #(1) begin
+		// Write data
+		for (a = 0; a < (1<<`ADDR_WIDTH); a = a + ADDR_INCR) begin
+			@(negedge clk) begin
+				wa = a;
+				wd = a | (a << 20) | 20'h55000;
+				wce = 1;
+			end
+			@(posedge clk) begin
+				#(PERIOD/10) wce = 0;
+			end
+		end
+		// Read data
+		read_test = 1;
+		for (a = 0; a < (1<<`ADDR_WIDTH); a = a + ADDR_INCR) begin
+			@(negedge clk) begin
+				ra = a;
+				rce = 1;
+			end
+			@(posedge clk) begin
+				#(PERIOD/10) rce = 0;
+				if ( rq !== expected) begin
+					$display("%d: FAIL: mismatch act=%x exp=%x at %x", $time, rq, expected, a);
+				end else begin
+					$display("%d: OK: act=%x exp=%x at %x", $time, rq, expected, a);
+				end
+			end
+		end
+		done = 1'b1;
+	end
+
+	// Scan for simulation finish
+	always @(posedge clk) begin
+		if (done)
+			$finish_and_return( (error_cnt == 0) ? 0 : -1 );
+	end
+
+	case (`STRINGIFY(`TOP))
+		"spram_36x1024": begin
+			spram_36x1024 #() bram (
+				.clock0(clk),
+				.clock1(clk),				 
+				.REN_i(rce),
+				.RD_ADDR_i(ra),
+				.RDATA_o(rq),
+				.WEN_i(wce),
+				.WR_ADDR_i(wa),
+				.WDATA_i(wd)
+			);
+		end
+		"spram_32x1024": begin
+			spram_32x1024 #() bram (
+				.clock0(clk),
+				.clock1(clk),				 
+				.REN_i(rce),
+				.RD_ADDR_i(ra),
+				.RDATA_o(rq),
+				.WEN_i(wce),
+				.WR_ADDR_i(wa),
+				.WDATA_i(wd)
+			);
+		end
+		"spram_18x2048": begin
+			spram_18x2048 #() bram (
+				.clock0(clk),
+				.clock1(clk),				 
+				.REN_i(rce),
+				.RD_ADDR_i(ra),
+				.RDATA_o(rq),
+				.WEN_i(wce),
+				.WR_ADDR_i(wa),
+				.WDATA_i(wd)
+			);
+		end
+		"spram_16x2048": begin
+			spram_16x2048 #() bram (
+				.clock0(clk),
+				.clock1(clk),				 
+				.REN_i(rce),
+				.RD_ADDR_i(ra),
+				.RDATA_o(rq),
+				.WEN_i(wce),
+				.WR_ADDR_i(wa),
+				.WDATA_i(wd)
+			);
+		end
+		"spram_9x4096": begin
+			spram_9x4096 #() bram (
+				.clock0(clk),
+				.clock1(clk),				 
+				.REN_i(rce),
+				.RD_ADDR_i(ra),
+				.RDATA_o(rq),
+				.WEN_i(wce),
+				.WR_ADDR_i(wa),
+				.WDATA_i(wd)
+			);
+		end
+		"spram_8x4096": begin
+			spram_8x4096 #() bram (
+				.clock0(clk),
+				.clock1(clk),				 
+				.REN_i(rce),
+				.RD_ADDR_i(ra),
+				.RDATA_o(rq),
+				.WEN_i(wce),
+				.WR_ADDR_i(wa),
+				.WDATA_i(wd)
+			);
+		end
+	endcase
+endmodule
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_sfifo/bram36k_sfifo.tcl b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_sfifo/bram36k_sfifo.tcl
new file mode 100644
index 0000000..8ffd95f
--- /dev/null
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_sfifo/bram36k_sfifo.tcl
@@ -0,0 +1,38 @@
+yosys -import
+
+if { [info procs ql-qlf-k6n10f] == {} } { plugin -i ql-qlf }
+yosys -import  ;
+
+read_verilog $::env(DESIGN_TOP).v
+design -save bram36k_sfifo
+
+select f1024x36_1024x36
+select *
+synth_quicklogic -family qlf_k6n10f -top f1024x36_1024x36 -bram_types
+opt_expr -undriven
+opt_clean
+stat
+write_verilog sim/f1024x36_1024x36_post_synth.v
+select -assert-count 1 t:TDP36K_FIFO_SYNC_WR_X36_RD_X36_nonsplit
+
+select -clear
+design -load bram36k_sfifo
+select f2048x18_2048x18
+select *
+synth_quicklogic -family qlf_k6n10f -top f2048x18_2048x18 -bram_types
+opt_expr -undriven
+opt_clean
+stat
+write_verilog sim/f2048x18_2048x18_post_synth.v
+select -assert-count 1 t:TDP36K_FIFO_SYNC_WR_X18_RD_X18_nonsplit
+
+select -clear
+design -load bram36k_sfifo
+select f4096x9_4096x9
+select *
+synth_quicklogic -family qlf_k6n10f -top f4096x9_4096x9 -bram_types
+opt_expr -undriven
+opt_clean
+stat
+write_verilog sim/f4096x9_4096x9_post_synth.v
+select -assert-count 1 t:TDP36K_FIFO_SYNC_WR_X9_RD_X9_nonsplit
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_sfifo/bram36k_sfifo.v b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_sfifo/bram36k_sfifo.v
new file mode 100644
index 0000000..d3bf2d6
--- /dev/null
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_sfifo/bram36k_sfifo.v
@@ -0,0 +1,135 @@
+// Copyright 2020-2022 F4PGA Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
+module f1024x36_1024x36 (DIN,PUSH,POP,clock0,Async_Flush,Almost_Full,Almost_Empty,Full,Empty,Full_Watermark,Empty_Watermark,Overrun_Error,Underrun_Error,DOUT);
+
+parameter WR_DATA_WIDTH = 36;
+parameter RD_DATA_WIDTH = 36;
+parameter UPAE_DBITS = 12'd10;
+parameter UPAF_DBITS = 12'd10;
+
+input clock0;
+input PUSH,POP;
+input [WR_DATA_WIDTH-1:0] DIN;
+input Async_Flush;
+output [RD_DATA_WIDTH-1:0] DOUT;
+output Almost_Full,Almost_Empty;
+output Full, Empty;
+output Full_Watermark, Empty_Watermark;
+output Overrun_Error, Underrun_Error;
+
+SFIFO_36K_BLK  # (.WR_DATA_WIDTH(WR_DATA_WIDTH),.RD_DATA_WIDTH(RD_DATA_WIDTH),.UPAE_DBITS(UPAE_DBITS),.UPAF_DBITS(UPAF_DBITS)
+                  )
+  FIFO_INST    (
+                .DIN(DIN),
+                .PUSH(PUSH),
+                .POP(POP),
+                .CLK(clock0),
+                .Async_Flush(Async_Flush),
+                
+                .Overrun_Error(Overrun_Error),
+                .Full_Watermark(Full_Watermark),
+                .Almost_Full(Almost_Full),
+                .Full(Full),
+                
+                .Underrun_Error(Underrun_Error),
+                .Empty_Watermark(Empty_Watermark),
+                .Almost_Empty(Almost_Empty),
+                .Empty(Empty),
+
+                .DOUT(DOUT)
+                );
+endmodule
+
+module f2048x18_2048x18 (DIN,PUSH,POP,clock0,Async_Flush,Almost_Full,Almost_Empty,Full,Empty,Full_Watermark,Empty_Watermark,Overrun_Error,Underrun_Error,DOUT);
+
+parameter WR_DATA_WIDTH = 18;
+parameter RD_DATA_WIDTH = 18;
+parameter UPAE_DBITS = 12'd10;
+parameter UPAF_DBITS = 12'd10;
+
+input clock0;
+input PUSH,POP;
+input [WR_DATA_WIDTH-1:0] DIN;
+input Async_Flush;
+output [RD_DATA_WIDTH-1:0] DOUT;
+output Almost_Full,Almost_Empty;
+output Full, Empty;
+output Full_Watermark, Empty_Watermark;
+output Overrun_Error, Underrun_Error;
+
+SFIFO_36K_BLK  # (.WR_DATA_WIDTH(WR_DATA_WIDTH),.RD_DATA_WIDTH(RD_DATA_WIDTH),.UPAE_DBITS(UPAE_DBITS),.UPAF_DBITS(UPAF_DBITS)
+                  )
+  FIFO_INST    (
+                .DIN(DIN),
+                .PUSH(PUSH),
+                .POP(POP),
+                .CLK(clock0),
+                .Async_Flush(Async_Flush),
+                
+                .Overrun_Error(Overrun_Error),
+                .Full_Watermark(Full_Watermark),
+                .Almost_Full(Almost_Full),
+                .Full(Full),
+                
+                .Underrun_Error(Underrun_Error),
+                .Empty_Watermark(Empty_Watermark),
+                .Almost_Empty(Almost_Empty),
+                .Empty(Empty),
+
+                .DOUT(DOUT)
+                );
+endmodule
+
+module f4096x9_4096x9 (DIN,PUSH,POP,clock0,Async_Flush,Almost_Full,Almost_Empty,Full,Empty,Full_Watermark,Empty_Watermark,Overrun_Error,Underrun_Error,DOUT);
+
+parameter WR_DATA_WIDTH = 9;
+parameter RD_DATA_WIDTH = 9;
+parameter UPAE_DBITS = 12'd10;
+parameter UPAF_DBITS = 12'd10;
+
+input clock0;
+input PUSH,POP;
+input [WR_DATA_WIDTH-1:0] DIN;
+input Async_Flush;
+output [RD_DATA_WIDTH-1:0] DOUT;
+output Almost_Full,Almost_Empty;
+output Full, Empty;
+output Full_Watermark, Empty_Watermark;
+output Overrun_Error, Underrun_Error;
+
+SFIFO_36K_BLK  # (.WR_DATA_WIDTH(WR_DATA_WIDTH),.RD_DATA_WIDTH(RD_DATA_WIDTH),.UPAE_DBITS(UPAE_DBITS),.UPAF_DBITS(UPAF_DBITS)
+                  )
+  FIFO_INST    (
+                .DIN(DIN),
+                .PUSH(PUSH),
+                .POP(POP),
+                .CLK(clock0),
+                .Async_Flush(Async_Flush),
+                
+                .Overrun_Error(Overrun_Error),
+                .Full_Watermark(Full_Watermark),
+                .Almost_Full(Almost_Full),
+                .Full(Full),
+                
+                .Underrun_Error(Underrun_Error),
+                .Empty_Watermark(Empty_Watermark),
+                .Almost_Empty(Almost_Empty),
+                .Empty(Empty),
+
+                .DOUT(DOUT)
+                );
+endmodule
\ No newline at end of file
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_sfifo/sim/Makefile b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_sfifo/sim/Makefile
new file mode 100644
index 0000000..e31e1d0
--- /dev/null
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_sfifo/sim/Makefile
@@ -0,0 +1,48 @@
+# Copyright 2020-2022 F4PGA Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+TESTBENCH = bram36k_sfifo_tb.v
+POST_SYNTH = f1024x36_1024x36_post_synth f2048x18_2048x18_post_synth f4096x9_4096x9_post_synth
+ADDR_WIDTH0 = 10 11 12
+DATA_WIDTH0 = 36 18 9
+ADDR_WIDTH1 = 10 11 12
+DATA_WIDTH1 = 36 18 9
+TOP = f1024x36_1024x36 f2048x18_2048x18 f4096x9_4096x9
+ADDR0_DEFINES = $(foreach awidth0, $(ADDR_WIDTH0),-DADDR_WIDTH0="$(awidth0)")
+ADDR1_DEFINES = $(foreach awidth1, $(ADDR_WIDTH1),-DADDR_WIDTH1="$(awidth1)")
+DATA0_DEFINES = $(foreach dwidth0, $(DATA_WIDTH0),-DDATA_WIDTH0="$(dwidth0)")
+DATA1_DEFINES = $(foreach dwidth1, $(DATA_WIDTH1),-DDATA_WIDTH1="$(dwidth1)")
+TOP_DEFINES = $(foreach top, $(TOP),-DTOP="$(top)")
+VCD_DEFINES = $(foreach vcd, $(POST_SYNTH),-DVCD="$(vcd).vcd")
+
+SIM_LIBS = $(shell find ../../../../qlf_k6n10f -name "*.v" -not -name "*_map.v")
+
+define simulate_post_synth
+	@iverilog  -vvvv -g2005 $(word $(1),$(ADDR0_DEFINES)) $(word $(1),$(ADDR1_DEFINES)) $(word $(1),$(DATA0_DEFINES)) $(word $(1),$(DATA1_DEFINES)) $(word $(1),$(TOP_DEFINES)) $(word $(1),$(VCD_DEFINES)) -o $(word $(1),$(POST_SYNTH)).vvp $(word $(1),$(POST_SYNTH)).v $(SIM_LIBS) $(TESTBENCH) > $(word $(1),$(POST_SYNTH)).vvp.log 2>&1
+	@vvp -vvvv $(word $(1),$(POST_SYNTH)).vvp > $(word $(1),$(POST_SYNTH)).vcd.log 2>&1
+endef
+
+define clean_post_synth_sim
+	@rm -rf  $(word $(1),$(POST_SYNTH)).vcd $(word $(1),$(POST_SYNTH)).vvp $(word $(1),$(POST_SYNTH)).vvp.log $(word $(1),$(POST_SYNTH)).vcd.log
+endef
+
+sim:
+	$(call simulate_post_synth,1)
+	$(call clean_post_synth_sim,1)
+	$(call simulate_post_synth,2)
+	$(call clean_post_synth_sim,2)
+	$(call simulate_post_synth,3)
+	$(call clean_post_synth_sim,3)
\ No newline at end of file
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_sfifo/sim/bram36k_sfifo_tb.v b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_sfifo/sim/bram36k_sfifo_tb.v
new file mode 100644
index 0000000..76be519
--- /dev/null
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_sfifo/sim/bram36k_sfifo_tb.v
@@ -0,0 +1,170 @@
+// Copyright 2020-2022 F4PGA Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//		 http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
+`timescale 1ns/1ps
+
+`define STRINGIFY(x) `"x`"
+
+module TB;
+	localparam PERIOD = 30;
+	localparam ADDR_INCR = 1;
+
+	reg clk;
+	reg flush;
+	reg pop;
+	wire [`DATA_WIDTH1-1:0] dout;
+	reg push;
+	reg [`DATA_WIDTH0-1:0] din;
+	wire almost_full,almost_empty;
+	wire full, empty;
+	wire full_watermark, empty_watermark;
+	wire overrun_error, underrun_error;
+
+	initial 
+	begin
+		clk = 0;
+		pop = 0;
+		push = 0;
+		flush = 1;
+		din = 0;
+		#40
+		flush = 0;
+	end
+	
+	initial forever #(PERIOD / 3.0) clk = ~clk;
+	
+	initial begin
+		$dumpfile(`STRINGIFY(`VCD));
+		$dumpvars;
+	end
+
+	integer a;
+
+	reg done;
+	initial done = 1'b0;
+	
+	reg read_test;
+	initial read_test = 0;
+
+	reg [`DATA_WIDTH1-1:0] expected;
+	initial expected = 0;
+
+	always @(posedge clk) begin
+		expected <= (a | (a << 20) | 20'h55000) & {`DATA_WIDTH1{1'b1}};
+	end
+
+	wire error = ((a != 0) && read_test) ? dout !== expected : 0;
+
+	integer error_cnt = 0;
+	always @ (posedge clk)
+	begin
+		if (error)
+			error_cnt <= error_cnt + 1'b1; 
+	end
+
+	initial #(50) begin
+		@(posedge clk)
+		// Write data
+		for (a = 0; a < (1<<`ADDR_WIDTH0); a = a + ADDR_INCR) begin
+			@(negedge clk) begin
+				din = a | (a << 20) | 20'h55000;
+				push = 1;
+			end
+			@(posedge clk) begin
+				#(PERIOD/10) push = 0;
+			end
+		end
+		// Read data
+		read_test = 1;
+		for (a = 0; a < (1<<`ADDR_WIDTH1); a = a + ADDR_INCR) begin
+			@(posedge clk) begin
+				#(PERIOD/10) pop = 0;
+				if ( dout !== expected) begin
+					$display("%d: FAIL: mismatch act=%x exp=%x at %x", $time, dout, expected, a);
+				end else begin
+					$display("%d: OK: act=%x exp=%x at %x", $time, dout, expected, a);
+				end
+			end
+			@(negedge clk) begin
+				pop = 1;
+			end
+		end
+		done = 1'b1;
+	end
+
+	// Scan for simulation finish
+	always @(posedge clk) begin
+		if (done)
+			$finish_and_return( (error_cnt == 0) ? 0 : -1 );
+	end
+
+	case (`STRINGIFY(`TOP))
+		"f1024x36_1024x36": begin
+			f1024x36_1024x36 #() afifo (
+				.DIN(din),
+				.PUSH(push),
+				.POP(pop),
+				.clock0(clk),
+				.Async_Flush(flush),
+				.Almost_Full(almost_full),
+				.Almost_Empty(almost_empty),
+				.Full(full),
+				.Empty(empty),
+				.Full_Watermark(full_watermark),
+				.Empty_Watermark(empty_watermark),
+				.Overrun_Error(overrun_error),
+				.Underrun_Error(underrun_error),
+				.DOUT(dout)
+			);
+		end
+		"f2048x18_2048x18": begin
+			f2048x18_2048x18 #() afifo (
+				.DIN(din),
+				.PUSH(push),
+				.POP(pop),
+				.clock0(clk),
+				.Async_Flush(flush),
+				.Almost_Full(almost_full),
+				.Almost_Empty(almost_empty),
+				.Full(full),
+				.Empty(empty),
+				.Full_Watermark(full_watermark),
+				.Empty_Watermark(empty_watermark),
+				.Overrun_Error(overrun_error),
+				.Underrun_Error(underrun_error),
+				.DOUT(dout)
+			);
+		end
+		"f4096x9_4096x9": begin
+			f4096x9_4096x9 #() afifo (
+				.DIN(din),
+				.PUSH(push),
+				.POP(pop),
+				.clock0(clk),
+				.Async_Flush(flush),
+				.Almost_Full(almost_full),
+				.Almost_Empty(almost_empty),
+				.Full(full),
+				.Empty(empty),
+				.Full_Watermark(full_watermark),
+				.Empty_Watermark(empty_watermark),
+				.Overrun_Error(overrun_error),
+				.Underrun_Error(underrun_error),
+				.DOUT(dout)
+			);
+		end		
+	endcase
+endmodule
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_tdp/bram36k_tdp.tcl b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_tdp/bram36k_tdp.tcl
new file mode 100644
index 0000000..df4591e
--- /dev/null
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_tdp/bram36k_tdp.tcl
@@ -0,0 +1,38 @@
+yosys -import
+
+if { [info procs ql-qlf-k6n10f] == {} } { plugin -i ql-qlf }
+yosys -import  ;
+
+read_verilog $::env(DESIGN_TOP).v
+design -save bram36k_tdp
+
+select dpram_36x1024
+select *
+synth_quicklogic -family qlf_k6n10f -top dpram_36x1024 -bram_types
+opt_expr -undriven
+opt_clean
+stat
+write_verilog sim/dpram_36x1024_post_synth.v
+select -assert-count 1 t:TDP36K_BRAM_WR_X36_RD_X36_nonsplit
+
+select -clear
+design -load bram36k_tdp
+select dpram_18x2048
+select *
+synth_quicklogic -family qlf_k6n10f -top dpram_18x2048 -bram_types
+opt_expr -undriven
+opt_clean
+stat
+write_verilog sim/dpram_18x2048_post_synth.v
+select -assert-count 1 t:TDP36K_BRAM_WR_X18_RD_X18_nonsplit
+
+select -clear
+design -load bram36k_tdp
+select dpram_9x4096
+select *
+synth_quicklogic -family qlf_k6n10f -top dpram_9x4096 -bram_types
+opt_expr -undriven
+opt_clean
+stat
+write_verilog sim/dpram_9x4096_post_synth.v
+select -assert-count 1 t:TDP36K_BRAM_WR_X9_RD_X9_nonsplit
\ No newline at end of file
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_tdp/bram36k_tdp.v b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_tdp/bram36k_tdp.v
new file mode 100644
index 0000000..89fdbec
--- /dev/null
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_tdp/bram36k_tdp.v
@@ -0,0 +1,213 @@
+// Copyright 2020-2022 F4PGA Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
+module dpram_36x1024 (
+    clock0,
+    WEN1_i,
+    REN1_i,
+    WR1_ADDR_i,
+    RD1_ADDR_i,
+    WDATA1_i,
+    RDATA1_o,
+    
+    clock1,
+    WEN2_i,
+    REN2_i,
+    WR2_ADDR_i,
+    RD2_ADDR_i,
+    WDATA2_i,
+    RDATA2_o
+);
+
+parameter ADDR_WIDTH = 10;
+parameter DATA_WIDTH = 36;
+parameter BE1_WIDTH = 4;
+parameter BE2_WIDTH = 4;
+
+input wire clock0;
+input wire WEN1_i;
+input wire REN1_i;
+input wire [ADDR_WIDTH-1 :0] WR1_ADDR_i;
+input wire [ADDR_WIDTH-1 :0] RD1_ADDR_i;
+input wire [DATA_WIDTH-1 :0] WDATA1_i;
+output wire [DATA_WIDTH-1 :0] RDATA1_o;
+
+input wire clock1;
+input wire WEN2_i;
+input wire REN2_i;
+input wire [ADDR_WIDTH-1 :0] WR2_ADDR_i;
+input wire [ADDR_WIDTH-1 :0] RD2_ADDR_i;
+input wire [DATA_WIDTH-1 :0] WDATA2_i;
+output wire [DATA_WIDTH-1 :0] RDATA2_o;
+
+DPRAM_36K_BLK #(
+              .ADDR_WIDTH(ADDR_WIDTH),
+              .DATA_WIDTH(DATA_WIDTH),
+              .BE1_WIDTH(BE1_WIDTH),
+              .BE2_WIDTH(BE2_WIDTH)
+              ) dpram_x36_inst (             
+              .CLK1_i(clock0),
+              .WEN1_i(WEN1_i),
+              .WR1_BE_i(4'b1111),
+              .REN1_i(REN1_i),
+              .WR1_ADDR_i(WR1_ADDR_i),
+              .RD1_ADDR_i(RD1_ADDR_i),
+              .WDATA1_i(WDATA1_i),
+              .RDATA1_o(RDATA1_o),
+              
+              .CLK2_i(clock1),
+              .WEN2_i(WEN2_i),
+              .WR2_BE_i(4'b1111),
+              .REN2_i(REN2_i),
+              .WR2_ADDR_i(WR2_ADDR_i),
+              .RD2_ADDR_i(RD2_ADDR_i),
+              .WDATA2_i(WDATA2_i),
+              .RDATA2_o(RDATA2_o)
+              );
+
+endmodule
+
+module dpram_18x2048 (
+    clock0,
+    WEN1_i,
+    REN1_i,
+    WR1_ADDR_i,
+    RD1_ADDR_i,
+    WDATA1_i,
+    RDATA1_o,
+    
+    clock1,
+    WEN2_i,
+    REN2_i,
+    WR2_ADDR_i,
+    RD2_ADDR_i,
+    WDATA2_i,
+    RDATA2_o
+);
+
+parameter ADDR_WIDTH = 11;
+parameter DATA_WIDTH = 18;
+parameter BE1_WIDTH = 2;
+parameter BE2_WIDTH = 2;
+
+input wire clock0;
+input wire WEN1_i;
+input wire REN1_i;
+input wire [ADDR_WIDTH-1 :0] WR1_ADDR_i;
+input wire [ADDR_WIDTH-1 :0] RD1_ADDR_i;
+input wire [DATA_WIDTH-1 :0] WDATA1_i;
+output wire [DATA_WIDTH-1 :0] RDATA1_o;
+
+input wire clock1;
+input wire WEN2_i;
+input wire REN2_i;
+input wire [ADDR_WIDTH-1 :0] WR2_ADDR_i;
+input wire [ADDR_WIDTH-1 :0] RD2_ADDR_i;
+input wire [DATA_WIDTH-1 :0] WDATA2_i;
+output wire [DATA_WIDTH-1 :0] RDATA2_o;
+
+DPRAM_36K_BLK #(
+              .ADDR_WIDTH(ADDR_WIDTH),
+              .DATA_WIDTH(DATA_WIDTH),
+              .BE1_WIDTH(BE1_WIDTH),
+              .BE2_WIDTH(BE2_WIDTH)
+              ) dpram_x36_inst (             
+              .CLK1_i(clock0),
+              .WEN1_i(WEN1_i),
+              .WR1_BE_i(2'b11),
+              .REN1_i(REN1_i),
+              .WR1_ADDR_i(WR1_ADDR_i),
+              .RD1_ADDR_i(RD1_ADDR_i),
+              .WDATA1_i(WDATA1_i),
+              .RDATA1_o(RDATA1_o),
+              
+              .CLK2_i(clock1),
+              .WEN2_i(WEN2_i),
+              .WR2_BE_i(2'b11),
+              .REN2_i(REN2_i),
+              .WR2_ADDR_i(WR2_ADDR_i),
+              .RD2_ADDR_i(RD2_ADDR_i),
+              .WDATA2_i(WDATA2_i),
+              .RDATA2_o(RDATA2_o)
+              );
+
+endmodule
+
+module dpram_9x4096 (
+    clock0,
+    WEN1_i,
+    REN1_i,
+    WR1_ADDR_i,
+    RD1_ADDR_i,
+    WDATA1_i,
+    RDATA1_o,
+    
+    clock1,
+    WEN2_i,
+    REN2_i,
+    WR2_ADDR_i,
+    RD2_ADDR_i,
+    WDATA2_i,
+    RDATA2_o
+);
+
+parameter ADDR_WIDTH = 12;
+parameter DATA_WIDTH = 9;
+parameter BE1_WIDTH = 1;
+parameter BE2_WIDTH = 1;
+
+input wire clock0;
+input wire WEN1_i;
+input wire REN1_i;
+input wire [ADDR_WIDTH-1 :0] WR1_ADDR_i;
+input wire [ADDR_WIDTH-1 :0] RD1_ADDR_i;
+input wire [DATA_WIDTH-1 :0] WDATA1_i;
+output wire [DATA_WIDTH-1 :0] RDATA1_o;
+
+input wire clock1;
+input wire WEN2_i;
+input wire REN2_i;
+input wire [ADDR_WIDTH-1 :0] WR2_ADDR_i;
+input wire [ADDR_WIDTH-1 :0] RD2_ADDR_i;
+input wire [DATA_WIDTH-1 :0] WDATA2_i;
+output wire [DATA_WIDTH-1 :0] RDATA2_o;
+
+DPRAM_36K_BLK #(
+              .ADDR_WIDTH(ADDR_WIDTH),
+              .DATA_WIDTH(DATA_WIDTH),
+              .BE1_WIDTH(BE1_WIDTH),
+              .BE2_WIDTH(BE2_WIDTH)
+              ) dpram_x36_inst (             
+              .CLK1_i(clock0),
+              .WEN1_i(WEN1_i),
+              .WR1_BE_i(1'b1),
+              .REN1_i(REN1_i),
+              .WR1_ADDR_i(WR1_ADDR_i),
+              .RD1_ADDR_i(RD1_ADDR_i),
+              .WDATA1_i(WDATA1_i),
+              .RDATA1_o(RDATA1_o),
+              
+              .CLK2_i(clock1),
+              .WEN2_i(WEN2_i),
+              .WR2_BE_i(1'b1),
+              .REN2_i(REN2_i),
+              .WR2_ADDR_i(WR2_ADDR_i),
+              .RD2_ADDR_i(RD2_ADDR_i),
+              .WDATA2_i(WDATA2_i),
+              .RDATA2_o(RDATA2_o)
+              );
+
+endmodule
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_tdp/sim/Makefile b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_tdp/sim/Makefile
new file mode 100644
index 0000000..6ce8344
--- /dev/null
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_tdp/sim/Makefile
@@ -0,0 +1,44 @@
+# Copyright 2020-2022 F4PGA Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+TESTBENCH = bram36k_tdp_tb.v
+POST_SYNTH = dpram_36x1024_post_synth dpram_18x2048_post_synth dpram_9x4096_post_synth
+ADDR_WIDTH = 10 11 12
+DATA_WIDTH = 36 18 9
+TOP = dpram_36x1024 dpram_18x2048 dpram_9x4096
+ADDR_DEFINES = $(foreach awidth, $(ADDR_WIDTH),-DADDR_WIDTH="$(awidth)")
+DATA_DEFINES = $(foreach dwidth, $(DATA_WIDTH),-DDATA_WIDTH="$(dwidth)")
+TOP_DEFINES = $(foreach top, $(TOP),-DTOP="$(top)")
+VCD_DEFINES = $(foreach vcd, $(POST_SYNTH),-DVCD="$(vcd).vcd")
+
+SIM_LIBS = $(shell find ../../../../qlf_k6n10f -name "*.v" -not -name "*_map.v")
+
+define simulate_post_synth
+	@iverilog  -vvvv -g2005 $(word $(1),$(ADDR_DEFINES)) $(word $(1),$(DATA_DEFINES)) $(word $(1),$(TOP_DEFINES)) $(word $(1),$(VCD_DEFINES)) -o $(word $(1),$(POST_SYNTH)).vvp $(word $(1),$(POST_SYNTH)).v $(SIM_LIBS) $(TESTBENCH) > $(word $(1),$(POST_SYNTH)).vvp.log 2>&1
+	@vvp -vvvv $(word $(1),$(POST_SYNTH)).vvp > $(word $(1),$(POST_SYNTH)).vcd.log 2>&1
+endef
+
+define clean_post_synth_sim
+	@rm -rf  $(word $(1),$(POST_SYNTH)).vcd $(word $(1),$(POST_SYNTH)).vvp $(word $(1),$(POST_SYNTH)).vvp.log $(word $(1),$(POST_SYNTH)).vcd.log
+endef
+
+sim:
+	$(call simulate_post_synth,1)
+	$(call clean_post_synth_sim,1)
+	$(call simulate_post_synth,2)
+	$(call clean_post_synth_sim,2)
+	$(call simulate_post_synth,3)
+	$(call clean_post_synth_sim,3)
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_tdp/sim/bram36k_tdp_tb.v b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_tdp/sim/bram36k_tdp_tb.v
new file mode 100644
index 0000000..646561a
--- /dev/null
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_tdp/sim/bram36k_tdp_tb.v
@@ -0,0 +1,220 @@
+// Copyright 2020-2022 F4PGA Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//		 http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
+`timescale 1ns/1ps
+
+`define STRINGIFY(x) `"x`"
+
+module TB;
+	localparam PERIOD = 50;
+	localparam ADDR_INCR = 1;
+
+	reg clk_a;
+	reg rce_a;
+	reg [`ADDR_WIDTH-1:0] ra_a;
+	wire [`DATA_WIDTH-1:0] rq_a;
+	reg wce_a;
+	reg [`ADDR_WIDTH-1:0] wa_a;
+	reg [`DATA_WIDTH-1:0] wd_a;
+
+	reg clk_b;
+	reg rce_b;
+	reg [`ADDR_WIDTH-1:0] ra_b;
+	wire [`DATA_WIDTH-1:0] rq_b;
+	reg wce_b;
+	reg [`ADDR_WIDTH-1:0] wa_b;
+	reg [`DATA_WIDTH-1:0] wd_b;
+
+
+	initial clk_a = 0;
+	initial clk_b = 0;
+	initial ra_a = 0;
+	initial ra_b = 0;
+	initial rce_a = 0;
+	initial rce_b = 0;
+	initial forever #(PERIOD / 2.0) clk_a = ~clk_a;
+	initial begin
+		#(PERIOD / 4.0);
+		forever #(PERIOD / 2.0) clk_b = ~clk_b;
+	end
+	initial begin
+		$dumpfile(`STRINGIFY(`VCD));
+		$dumpvars;
+	end
+
+	integer a;
+	integer b;
+
+	reg done_a;
+	reg done_b;
+	initial done_a = 1'b0;
+	initial done_b = 1'b0;
+	wire done_sim = done_a & done_b;
+
+	reg [`DATA_WIDTH-1:0] expected_a;
+	reg [`DATA_WIDTH-1:0] expected_b;
+
+	always @(posedge clk_a) begin
+		expected_a <= (a | (a << 20) | 20'h55000) & {`DATA_WIDTH{1'b1}};
+	end
+	always @(posedge clk_b) begin
+		expected_b <= (b | (b << 20) | 20'h55000) & {`DATA_WIDTH{1'b1}};
+	end
+
+	wire error_a = a != 0 ? rq_a !== expected_a : 0;
+	wire error_b = b != (1<<`ADDR_WIDTH) / 2 ? rq_b !== expected_b : 0;
+
+	integer error_a_cnt = 0;
+	integer error_b_cnt = 0;
+
+	always @ (posedge clk_a)
+	begin
+		if (error_a)
+			error_a_cnt <= error_a_cnt + 1'b1;
+	end
+	always @ (posedge clk_b)
+	begin
+		if (error_b)
+			error_b_cnt <= error_b_cnt + 1'b1;
+	end
+	// PORT A
+	initial #(1) begin
+		// Write data
+		for (a = 0; a < (1<<`ADDR_WIDTH) / 2; a = a + ADDR_INCR) begin
+			@(negedge clk_a) begin
+				wa_a = a;
+				wd_a = a | (a << 20) | 20'h55000;
+				wce_a = 1;
+			end
+			@(posedge clk_a) begin
+				#(PERIOD/10) wce_a = 0;
+			end
+		end
+		// Read data
+		for (a = 0; a < (1<<`ADDR_WIDTH) / 2; a = a + ADDR_INCR) begin
+			@(negedge clk_a) begin
+				ra_a = a;
+				rce_a = 1;
+			end
+			@(posedge clk_a) begin
+				#(PERIOD/10) rce_a = 0;
+				if ( rq_a !== expected_a) begin
+					$display("%d: PORT A: FAIL: mismatch act=%x exp=%x at %x", $time, rq_a, expected_a, a);
+				end else begin
+					$display("%d: PORT A: OK: act=%x exp=%x at %x", $time, rq_a, expected_a, a);
+				end
+			end
+		end
+		done_a = 1'b1;
+	end
+
+	// PORT B
+	initial #(1) begin
+		// Write data
+		for (b = (1<<`ADDR_WIDTH) / 2; b < (1<<`ADDR_WIDTH); b = b + ADDR_INCR) begin
+			@(negedge clk_b) begin
+				wa_b = b;
+				wd_b = b | (b << 20) | 20'h55000;
+				wce_b = 1;
+			end
+			@(posedge clk_b) begin
+				#(PERIOD/10) wce_b = 0;
+			end
+		end
+		// Read data
+		for (b = (1<<`ADDR_WIDTH) / 2; b < (1<<`ADDR_WIDTH); b = b + ADDR_INCR) begin
+			@(negedge clk_b) begin
+				ra_b = b;
+				rce_b = 1;
+			end
+			@(posedge clk_b) begin
+				#(PERIOD/10) rce_b = 0;
+				if ( rq_b !== expected_b) begin
+					$display("%d: PORT B: FAIL: mismatch act=%x exp=%x at %x", $time, rq_b, expected_b, b);
+				end else begin
+					$display("%d: PORT B: OK: act=%x exp=%x at %x", $time, rq_b, expected_b, b);
+				end
+			end
+		end
+		done_b = 1'b1;
+	end
+
+	// Scan for simulation finish
+	always @(posedge clk_a, posedge clk_b) begin
+		if (done_sim)
+			$finish_and_return( (error_a_cnt == 0 & error_b_cnt == 0) ? 0 : -1 );
+	end
+	
+	case (`STRINGIFY(`TOP))
+		"dpram_36x1024": begin
+			dpram_36x1024 #() bram (
+				.clock0(clk_a),
+				.REN1_i(rce_a),
+				.RD1_ADDR_i(ra_a),
+				.RDATA1_o(rq_a),
+				.WEN1_i(wce_a),
+				.WR1_ADDR_i(wa_a),
+				.WDATA1_i(wd_a),
+				
+				.clock1(clk_b),
+				.REN2_i(rce_b),
+				.RD2_ADDR_i(ra_b),
+				.RDATA2_o(rq_b),
+				.WEN2_i(wce_b),
+				.WR2_ADDR_i(wa_b),
+				.WDATA2_i(wd_b)
+			);
+		end
+		"dpram_18x2048": begin
+			dpram_18x2048 #() bram (
+				.clock0(clk_a),
+				.REN1_i(rce_a),
+				.RD1_ADDR_i(ra_a),
+				.RDATA1_o(rq_a),
+				.WEN1_i(wce_a),
+				.WR1_ADDR_i(wa_a),
+				.WDATA1_i(wd_a),
+				
+				.clock1(clk_b),
+				.REN2_i(rce_b),
+				.RD2_ADDR_i(ra_b),
+				.RDATA2_o(rq_b),
+				.WEN2_i(wce_b),
+				.WR2_ADDR_i(wa_b),
+				.WDATA2_i(wd_b)
+			);
+		end
+		"dpram_9x4096": begin
+			dpram_9x4096 #() bram (
+				.clock0(clk_a),
+				.REN1_i(rce_a),
+				.RD1_ADDR_i(ra_a),
+				.RDATA1_o(rq_a),
+				.WEN1_i(wce_a),
+				.WR1_ADDR_i(wa_a),
+				.WDATA1_i(wd_a),
+				
+				.clock1(clk_b),
+				.REN2_i(rce_b),
+				.RD2_ADDR_i(ra_b),
+				.RDATA2_o(rq_b),
+				.WEN2_i(wce_b),
+				.WR2_ADDR_i(wa_b),
+				.WDATA2_i(wd_b)
+			);
+		end
+	endcase
+endmodule
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram_asymmetric_wider_read/bram_asymmetric_wider_read.tcl b/ql-qlf-plugin/tests/qlf_k6n10f/bram_asymmetric_wider_read/bram_asymmetric_wider_read.tcl
index b413b43..1ae531a 100644
--- a/ql-qlf-plugin/tests/qlf_k6n10f/bram_asymmetric_wider_read/bram_asymmetric_wider_read.tcl
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram_asymmetric_wider_read/bram_asymmetric_wider_read.tcl
@@ -8,46 +8,46 @@
 
 select spram_16x2048_32x1024
 select *
-synth_quicklogic -family qlf_k6n10f -top spram_16x2048_32x1024
+synth_quicklogic -family qlf_k6n10f -top spram_16x2048_32x1024 -bram_types
 opt_expr -undriven
 opt_clean
 stat
 write_verilog sim/spram_16x2048_32x1024_post_synth.v
-select -assert-count 1 t:TDP36K
+select -assert-count 1 t:TDP36K_BRAM_WR_X18_RD_X36_nonsplit
 select -assert-count 1 t:*
 
 select -clear
 design -load bram_tdp
 select spram_8x4096_16x2048
 select *
-synth_quicklogic -family qlf_k6n10f -top spram_8x4096_16x2048
+synth_quicklogic -family qlf_k6n10f -top spram_8x4096_16x2048 -bram_types
 opt_expr -undriven
 opt_clean
 stat
 write_verilog sim/spram_8x4096_16x2048_post_synth.v
-select -assert-count 1 t:TDP36K
+select -assert-count 1 t:TDP36K_BRAM_WR_X9_RD_X18_nonsplit
 select -assert-count 1 t:*
 
 select -clear
 design -load bram_tdp
 select spram_8x2048_16x1024
 select *
-synth_quicklogic -family qlf_k6n10f -top spram_8x2048_16x1024
+synth_quicklogic -family qlf_k6n10f -top spram_8x2048_16x1024 -bram_types
 opt_expr -undriven
 opt_clean
 stat
 write_verilog sim/spram_8x2048_16x1024_post_synth.v
-select -assert-count 1 t:TDP36K
+select -assert-count 1 t:TDP36K_BRAM_WR_X9_RD_X18_nonsplit
 select -assert-count 1 t:*
 
 select -clear
 design -load bram_tdp
 select spram_8x4096_32x1024
 select *
-synth_quicklogic -family qlf_k6n10f -top spram_8x4096_32x1024
+synth_quicklogic -family qlf_k6n10f -top spram_8x4096_32x1024 -bram_types
 opt_expr -undriven
 opt_clean
 stat
 write_verilog sim/spram_8x4096_32x1024_post_synth.v
-select -assert-count 1 t:TDP36K
+select -assert-count 1 t:TDP36K_BRAM_WR_X9_RD_X36_nonsplit
 select -assert-count 1 t:*
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram_asymmetric_wider_write/bram_asymmetric_wider_write.tcl b/ql-qlf-plugin/tests/qlf_k6n10f/bram_asymmetric_wider_write/bram_asymmetric_wider_write.tcl
index 9d086bb..254c2ea 100644
--- a/ql-qlf-plugin/tests/qlf_k6n10f/bram_asymmetric_wider_write/bram_asymmetric_wider_write.tcl
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram_asymmetric_wider_write/bram_asymmetric_wider_write.tcl
@@ -8,46 +8,46 @@
 
 select spram_16x1024_8x2048
 select *
-synth_quicklogic -family qlf_k6n10f -top spram_16x1024_8x2048
+synth_quicklogic -family qlf_k6n10f -top spram_16x1024_8x2048 -bram_types
 opt_expr -undriven
 opt_clean
 stat
 write_verilog sim/spram_16x1024_8x2048_post_synth.v
-select -assert-count 1 t:TDP36K
+select -assert-count 1 t:TDP36K_BRAM_WR_X18_RD_X9_nonsplit
 select -assert-count 1 t:*
 
 select -clear
 design -load bram_tdp
 select spram_16x2048_8x4096
 select *
-synth_quicklogic -family qlf_k6n10f -top spram_16x2048_8x4096
+synth_quicklogic -family qlf_k6n10f -top spram_16x2048_8x4096 -bram_types
 opt_expr -undriven
 opt_clean
 stat
 write_verilog sim/spram_16x2048_8x4096_post_synth.v
-select -assert-count 1 t:TDP36K
+select -assert-count 1 t:TDP36K_BRAM_WR_X18_RD_X9_nonsplit
 select -assert-count 1 t:*
 
 select -clear
 design -load bram_tdp
 select spram_32x1024_16x2048
 select *
-synth_quicklogic -family qlf_k6n10f -top spram_32x1024_16x2048
+synth_quicklogic -family qlf_k6n10f -top spram_32x1024_16x2048 -bram_types
 opt_expr -undriven
 opt_clean
 stat
 write_verilog sim/spram_32x1024_16x2048_post_synth.v
-select -assert-count 1 t:TDP36K
+select -assert-count 1 t:TDP36K_BRAM_WR_X36_RD_X18_nonsplit
 select -assert-count 1 t:*
 
 select -clear
 design -load bram_tdp
 select spram_32x1024_8x4096
 select *
-synth_quicklogic -family qlf_k6n10f -top spram_32x1024_8x4096
+synth_quicklogic -family qlf_k6n10f -top spram_32x1024_8x4096 -bram_types
 opt_expr -undriven
 opt_clean
 stat
 write_verilog sim/spram_32x1024_8x4096_post_synth.v
-select -assert-count 1 t:TDP36K
+select -assert-count 1 t:TDP36K_BRAM_WR_X36_RD_X9_nonsplit
 select -assert-count 1 t:*
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram_sdp/bram_sdp.tcl b/ql-qlf-plugin/tests/qlf_k6n10f/bram_sdp/bram_sdp.tcl
index f8567ce..4e98585 100644
--- a/ql-qlf-plugin/tests/qlf_k6n10f/bram_sdp/bram_sdp.tcl
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram_sdp/bram_sdp.tcl
@@ -8,98 +8,98 @@
 
 select BRAM_SDP_36x1024
 select *
-synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_36x1024
+synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_36x1024 -bram_types
 opt_expr -undriven
 opt_clean
 stat
 write_verilog sim/bram_sdp_36x1024_post_synth.v
-select -assert-count 1 t:TDP36K
+select -assert-count 1 t:TDP36K_BRAM_WR_X36_RD_X36_nonsplit
 
 select -clear
 design -load bram_sdp
 select BRAM_SDP_32x1024
 select *
-synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_32x1024
+synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_32x1024 -bram_types
 opt_expr -undriven
 opt_clean
 stat
 write_verilog sim/bram_sdp_32x1024_post_synth.v
-select -assert-count 1 t:TDP36K
+select -assert-count 1 t:TDP36K_BRAM_WR_X36_RD_X36_nonsplit
 
 select -clear
 design -load bram_sdp
 select BRAM_SDP_18x2048
 select *
-synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_18x2048
+synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_18x2048 -bram_types
 opt_expr -undriven
 opt_clean
 stat
 write_verilog sim/bram_sdp_18x2048_post_synth.v
-select -assert-count 1 t:TDP36K
+select -assert-count 1 t:TDP36K_BRAM_WR_X18_RD_X18_nonsplit
 
 select -clear
 design -load bram_sdp
 select BRAM_SDP_16x2048
 select *
-synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_16x2048
+synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_16x2048 -bram_types
 opt_expr -undriven
 opt_clean
 stat
 write_verilog sim/bram_sdp_16x2048_post_synth.v
-select -assert-count 1 t:TDP36K
+select -assert-count 1 t:TDP36K_BRAM_WR_X18_RD_X18_nonsplit
 
 select -clear
 design -load bram_sdp
 select BRAM_SDP_9x4096
 select *
-synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_9x4096
+synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_9x4096 -bram_types
 opt_expr -undriven
 opt_clean
 stat
 write_verilog sim/bram_sdp_9x4096_post_synth.v
-select -assert-count 1 t:TDP36K
+select -assert-count 1 t:TDP36K_BRAM_WR_X9_RD_X9_nonsplit
 
 select -clear
 design -load bram_sdp
 select BRAM_SDP_8x4096
 select *
-synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_8x4096
+synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_8x4096 -bram_types
 opt_expr -undriven
 opt_clean
 stat
 write_verilog sim/bram_sdp_8x4096_post_synth.v
-select -assert-count 1 t:TDP36K
+select -assert-count 1 t:TDP36K_BRAM_WR_X9_RD_X9_nonsplit
 
 select -clear
 design -load bram_sdp
 select BRAM_SDP_4x8192
 select *
-synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_4x8192
+synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_4x8192 -bram_types
 opt_expr -undriven
 opt_clean
 stat
 write_verilog sim/bram_sdp_4x8192_post_synth.v
-select -assert-count 1 t:TDP36K
+select -assert-count 1 t:TDP36K_BRAM_WR_X4_RD_X4_nonsplit
 
 select -clear
 design -load bram_sdp
 select BRAM_SDP_2x16384
 select *
-synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_2x16384
+synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_2x16384 -bram_types
 opt_expr -undriven
 opt_clean
 stat
 write_verilog sim/bram_sdp_2x16384_post_synth.v
-select -assert-count 1 t:TDP36K
+select -assert-count 1 t:TDP36K_BRAM_WR_X2_RD_X2_nonsplit
 
 select -clear
 design -load bram_sdp
 select BRAM_SDP_1x32768
 select *
-synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_1x32768
+synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_1x32768 -bram_types
 opt_expr -undriven
 opt_clean
 stat
 write_verilog sim/bram_sdp_1x32768_post_synth.v
-select -assert-count 1 t:TDP36K
+select -assert-count 1 t:TDP36K_BRAM_WR_X1_RD_X1_nonsplit
 
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram_sdp_split/bram_sdp_split.tcl b/ql-qlf-plugin/tests/qlf_k6n10f/bram_sdp_split/bram_sdp_split.tcl
index a296d8c..fcf9acd 100644
--- a/ql-qlf-plugin/tests/qlf_k6n10f/bram_sdp_split/bram_sdp_split.tcl
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram_sdp_split/bram_sdp_split.tcl
@@ -8,76 +8,76 @@
 
 select BRAM_SDP_SPLIT_2x18x1024
 select *
-synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_SPLIT_2x18x1024
+synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_SPLIT_2x18x1024 -bram_types
 opt_expr -undriven
 opt_clean
 stat
 write_verilog sim/bram_sdp_split_2x18x1024_post_synth.v
-select -assert-count 1 t:TDP36K
+select -assert-count 1 t:TDP36K_BRAM_WR_X18_RD_X18_split
 
 select -clear
 design -load bram_sdp_split
 select BRAM_SDP_SPLIT_2x16x1024
 select *
-synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_SPLIT_2x16x1024
+synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_SPLIT_2x16x1024 -bram_types
 opt_expr -undriven
 opt_clean
 stat
 write_verilog sim/bram_sdp_split_2x16x1024_post_synth.v
-select -assert-count 1 t:TDP36K
+select -assert-count 1 t:TDP36K_BRAM_WR_X18_RD_X18_split
 
 select -clear
 design -load bram_sdp_split
 select BRAM_SDP_SPLIT_2x9x2048
 select *
-synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_SPLIT_2x9x2048
+synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_SPLIT_2x9x2048 -bram_types
 opt_expr -undriven
 opt_clean
 stat
 write_verilog sim/bram_sdp_split_2x9x2048_post_synth.v
-select -assert-count 1 t:TDP36K
+select -assert-count 1 t:TDP36K_BRAM_WR_X9_RD_X9_split
 
 select -clear
 design -load bram_sdp_split
 select BRAM_SDP_SPLIT_2x8x2048
 select *
-synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_SPLIT_2x8x2048
+synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_SPLIT_2x8x2048 -bram_types
 opt_expr -undriven
 opt_clean
 stat
 write_verilog sim/bram_sdp_split_2x8x2048_post_synth.v
-select -assert-count 1 t:TDP36K
+select -assert-count 1 t:TDP36K_BRAM_WR_X9_RD_X9_split
 
 select -clear
 design -load bram_sdp_split
 select BRAM_SDP_SPLIT_2x4x4096
 select *
-synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_SPLIT_2x4x4096
+synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_SPLIT_2x4x4096 -bram_types
 opt_expr -undriven
 opt_clean
 stat
 write_verilog sim/bram_sdp_split_2x4x4096_post_synth.v
-select -assert-count 1 t:TDP36K
+select -assert-count 1 t:TDP36K_BRAM_WR_X4_RD_X4_split
 
 select -clear
 design -load bram_sdp_split
 select BRAM_SDP_SPLIT_2x2x8192
 select *
-synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_SPLIT_2x2x8192
+synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_SPLIT_2x2x8192 -bram_types
 opt_expr -undriven
 opt_clean
 stat
 write_verilog sim/bram_sdp_split_2x2x8192_post_synth.v
-select -assert-count 1 t:TDP36K
+select -assert-count 1 t:TDP36K_BRAM_WR_X2_RD_X2_split
 
 select -clear
 design -load bram_sdp_split
 select BRAM_SDP_SPLIT_2x1x16384
 select *
-synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_SPLIT_2x1x16384
+synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_SPLIT_2x1x16384 -bram_types
 opt_expr -undriven
 opt_clean
 stat
 write_verilog sim/bram_sdp_split_2x1x16384_post_synth.v
-select -assert-count 1 t:TDP36K
+select -assert-count 1 t:TDP36K_BRAM_WR_X1_RD_X1_split
 
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram_tdp/bram_tdp.tcl b/ql-qlf-plugin/tests/qlf_k6n10f/bram_tdp/bram_tdp.tcl
index 8ef0e9d..ea5ae8e 100644
--- a/ql-qlf-plugin/tests/qlf_k6n10f/bram_tdp/bram_tdp.tcl
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram_tdp/bram_tdp.tcl
@@ -8,98 +8,98 @@
 
 select BRAM_TDP_36x1024
 select *
-synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_36x1024
+synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_36x1024 -bram_types
 opt_expr -undriven
 opt_clean
 stat
 write_verilog sim/bram_tdp_36x1024_post_synth.v
-select -assert-count 1 t:TDP36K
+select -assert-count 1 t:TDP36K_BRAM_WR_X36_RD_X36_nonsplit
 
 select -clear
 design -load bram_tdp
 select BRAM_TDP_32x1024
 select *
-synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_32x1024
+synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_32x1024 -bram_types
 opt_expr -undriven
 opt_clean
 stat
 write_verilog sim/bram_tdp_32x1024_post_synth.v
-select -assert-count 1 t:TDP36K
+select -assert-count 1 t:TDP36K_BRAM_WR_X36_RD_X36_nonsplit
 
 select -clear
 design -load bram_tdp
 select BRAM_TDP_18x2048
 select *
-synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_18x2048
+synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_18x2048 -bram_types
 opt_expr -undriven
 opt_clean
 stat
 write_verilog sim/bram_tdp_18x2048_post_synth.v
-select -assert-count 1 t:TDP36K
+select -assert-count 1 t:TDP36K_BRAM_WR_X18_RD_X18_nonsplit
 
 select -clear
 design -load bram_tdp
 select BRAM_TDP_16x2048
 select *
-synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_16x2048
+synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_16x2048 -bram_types
 opt_expr -undriven
 opt_clean
 stat
 write_verilog sim/bram_tdp_16x2048_post_synth.v
-select -assert-count 1 t:TDP36K
+select -assert-count 1 t:TDP36K_BRAM_WR_X18_RD_X18_nonsplit
 
 select -clear
 design -load bram_tdp
 select BRAM_TDP_9x4096
 select *
-synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_9x4096
+synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_9x4096 -bram_types
 opt_expr -undriven
 opt_clean
 stat
 write_verilog sim/bram_tdp_9x4096_post_synth.v
-select -assert-count 1 t:TDP36K
+select -assert-count 1 t:TDP36K_BRAM_WR_X9_RD_X9_nonsplit
 
 select -clear
 design -load bram_tdp
 select BRAM_TDP_8x4096
 select *
-synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_8x4096
+synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_8x4096 -bram_types
 opt_expr -undriven
 opt_clean
 stat
 write_verilog sim/bram_tdp_8x4096_post_synth.v
-select -assert-count 1 t:TDP36K
+select -assert-count 1 t:TDP36K_BRAM_WR_X9_RD_X9_nonsplit
 
 select -clear
 design -load bram_tdp
 select BRAM_TDP_4x8192
 select *
-synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_4x8192
+synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_4x8192 -bram_types
 opt_expr -undriven
 opt_clean
 stat
 write_verilog sim/bram_tdp_4x8192_post_synth.v
-select -assert-count 1 t:TDP36K
+select -assert-count 1 t:TDP36K_BRAM_WR_X4_RD_X4_nonsplit
 
 select -clear
 design -load bram_tdp
 select BRAM_TDP_2x16384
 select *
-synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_2x16384
+synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_2x16384 -bram_types
 opt_expr -undriven
 opt_clean
 stat
 write_verilog sim/bram_tdp_2x16384_post_synth.v
-select -assert-count 1 t:TDP36K
+select -assert-count 1 t:TDP36K_BRAM_WR_X2_RD_X2_nonsplit
 
 select -clear
 design -load bram_tdp
 select BRAM_TDP_1x32768
 select *
-synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_1x32768
+synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_1x32768 -bram_types
 opt_expr -undriven
 opt_clean
 stat
 write_verilog sim/bram_tdp_1x32768_post_synth.v
-select -assert-count 1 t:TDP36K
+select -assert-count 1 t:TDP36K_BRAM_WR_X1_RD_X1_nonsplit
 
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram_tdp_split/bram_tdp_split.tcl b/ql-qlf-plugin/tests/qlf_k6n10f/bram_tdp_split/bram_tdp_split.tcl
index 9a8921e..7b56e8d 100644
--- a/ql-qlf-plugin/tests/qlf_k6n10f/bram_tdp_split/bram_tdp_split.tcl
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram_tdp_split/bram_tdp_split.tcl
@@ -8,76 +8,76 @@
 
 select BRAM_TDP_SPLIT_2x18x1024
 select *
-synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_SPLIT_2x18x1024
+synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_SPLIT_2x18x1024 -bram_types
 opt_expr -undriven
 opt_clean
 stat
 write_verilog sim/bram_tdp_split_2x18x1024_post_synth.v
-select -assert-count 1 t:TDP36K
+select -assert-count 1 t:TDP36K_BRAM_WR_X18_RD_X18_split
 
 select -clear
 design -load bram_tdp_split
 select BRAM_TDP_SPLIT_2x16x1024
 select *
-synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_SPLIT_2x16x1024
+synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_SPLIT_2x16x1024 -bram_types
 opt_expr -undriven
 opt_clean
 stat
 write_verilog sim/bram_tdp_split_2x16x1024_post_synth.v
-select -assert-count 1 t:TDP36K
+select -assert-count 1 t:TDP36K_BRAM_WR_X18_RD_X18_split
 
 select -clear
 design -load bram_tdp_split
 select BRAM_TDP_SPLIT_2x9x2048
 select *
-synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_SPLIT_2x9x2048
+synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_SPLIT_2x9x2048 -bram_types
 opt_expr -undriven
 opt_clean
 stat
 write_verilog sim/bram_tdp_split_2x9x2048_post_synth.v
-select -assert-count 1 t:TDP36K
+select -assert-count 1 t:TDP36K_BRAM_WR_X9_RD_X9_split
 
 select -clear
 design -load bram_tdp_split
 select BRAM_TDP_SPLIT_2x8x2048
 select *
-synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_SPLIT_2x8x2048
+synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_SPLIT_2x8x2048 -bram_types
 opt_expr -undriven
 opt_clean
 stat
 write_verilog sim/bram_tdp_split_2x8x2048_post_synth.v
-select -assert-count 1 t:TDP36K
+select -assert-count 1 t:TDP36K_BRAM_WR_X9_RD_X9_split
 
 select -clear
 design -load bram_tdp_split
 select BRAM_TDP_SPLIT_2x4x4096
 select *
-synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_SPLIT_2x4x4096
+synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_SPLIT_2x4x4096 -bram_types
 opt_expr -undriven
 opt_clean
 stat
 write_verilog sim/bram_tdp_split_2x4x4096_post_synth.v
-select -assert-count 1 t:TDP36K
+select -assert-count 1 t:TDP36K_BRAM_WR_X4_RD_X4_split
 
 select -clear
 design -load bram_tdp_split
 select BRAM_TDP_SPLIT_2x2x8192
 select *
-synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_SPLIT_2x2x8192
+synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_SPLIT_2x2x8192 -bram_types
 opt_expr -undriven
 opt_clean
 stat
 write_verilog sim/bram_tdp_split_2x2x8192_post_synth.v
-select -assert-count 1 t:TDP36K
+select -assert-count 1 t:TDP36K_BRAM_WR_X2_RD_X2_split
 
 select -clear
 design -load bram_tdp_split
 select BRAM_TDP_SPLIT_2x1x16384
 select *
-synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_SPLIT_2x1x16384
+synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_SPLIT_2x1x16384 -bram_types
 opt_expr -undriven
 opt_clean
 stat
 write_verilog sim/bram_tdp_split_2x1x16384_post_synth.v
-select -assert-count 1 t:TDP36K
+select -assert-count 1 t:TDP36K_BRAM_WR_X1_RD_X1_split
 
diff --git a/sdc-plugin/Makefile b/sdc-plugin/Makefile
index 3ae63e0..871c9bc 100644
--- a/sdc-plugin/Makefile
+++ b/sdc-plugin/Makefile
@@ -14,6 +14,8 @@
 #
 # SPDX-License-Identifier: Apache-2.0
 
+PLUGIN_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
+
 NAME = sdc
 SOURCES = buffers.cc \
           clocks.cc \
diff --git a/systemverilog-plugin/Makefile b/systemverilog-plugin/Makefile
index 1b162be..af5320d 100644
--- a/systemverilog-plugin/Makefile
+++ b/systemverilog-plugin/Makefile
@@ -14,24 +14,44 @@
 #
 # SPDX-License-Identifier: Apache-2.0
 
+PLUGIN_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
+
 NAME = systemverilog
 SOURCES = UhdmAst.cc \
-	  uhdmastfrontend.cc \
-	  uhdmcommonfrontend.cc \
-	  uhdmsurelogastfrontend.cc \
-	  uhdmastreport.cc
+          uhdmastfrontend.cc \
+          uhdmcommonfrontend.cc \
+          uhdmsurelogastfrontend.cc \
+          uhdmastreport.cc \
+          third_party/yosys/const2ast.cc
 
 # Directory to search for Surelog and UHDM libraries
 UHDM_INSTALL_DIR ?= /usr/local
 
 include ../Makefile_plugin.common
 
-CPPFLAGS += -std=c++17 -Wall -W -Wextra \
-              -Wno-deprecated-declarations \
-              -Wno-unused-parameter \
-              -I${UHDM_INSTALL_DIR}/include \
-	      -I${UHDM_INSTALL_DIR}/include/Surelog
+CXXFLAGS += -std=c++17 -Wall -W -Wextra \
+            -Wno-deprecated-declarations \
+            -Wno-unused-parameter \
+            -I${UHDM_INSTALL_DIR}/include \
+            -I${UHDM_INSTALL_DIR}/include/Surelog
 
-CXXFLAGS += -Wno-unused-parameter
-LDFLAGS += -L${UHDM_INSTALL_DIR}/lib/uhdm -L${UHDM_INSTALL_DIR}/lib/surelog -L${UHDM_INSTALL_DIR}/lib -L${UHDM_INSTALL_DIR}/lib64/uhdm -L${UHDM_INSTALL_DIR}/lib64/surelog -L${UHDM_INSTALL_DIR}/lib64
-LDLIBS += -Wl,--whole-archive -luhdm -Wl,--no-whole-archive -lsurelog -lantlr4-runtime -lflatbuffers -lcapnp -lkj -ldl -lutil -lm -lrt -lpthread
+LDFLAGS += -L${UHDM_INSTALL_DIR}/lib/uhdm \
+           -L${UHDM_INSTALL_DIR}/lib/surelog \
+           -L${UHDM_INSTALL_DIR}/lib \
+           -L${UHDM_INSTALL_DIR}/lib64/uhdm \
+           -L${UHDM_INSTALL_DIR}/lib64/surelog \
+           -L${UHDM_INSTALL_DIR}/lib64
+
+LDLIBS += -Wl,--whole-archive \
+          -luhdm \
+          -Wl,--no-whole-archive \
+          -lsurelog \
+          -lantlr4-runtime \
+          -lflatbuffers \
+          -lcapnp \
+          -lkj \
+          -ldl \
+          -lutil \
+          -lm \
+          -lrt \
+          -lpthread
diff --git a/systemverilog-plugin/UhdmAst.cc b/systemverilog-plugin/UhdmAst.cc
index 6580d0d..3936d03 100644
--- a/systemverilog-plugin/UhdmAst.cc
+++ b/systemverilog-plugin/UhdmAst.cc
@@ -1,6 +1,7 @@
 #include <algorithm>
 #include <cstring>
 #include <functional>
+#include <limits>
 #include <regex>
 #include <string>
 #include <vector>
@@ -13,7 +14,33 @@
 #include <uhdm/uhdm.h>
 #include <uhdm/vpi_user.h>
 
+#include "third_party/yosys/const2ast.h"
+
 YOSYS_NAMESPACE_BEGIN
+namespace VERILOG_FRONTEND
+{
+extern bool sv_mode;
+}
+YOSYS_NAMESPACE_END
+
+namespace systemverilog_plugin
+{
+
+using namespace ::Yosys;
+
+namespace AST
+{
+using namespace ::Yosys::AST;
+
+namespace Extended
+{
+enum AstNodeTypeExtended {
+    AST_DOT = ::Yosys::AST::AST_BIND + 1, // here we always want to point to the last element of yosys' AstNodeType
+    AST_BREAK,
+    AST_CONTINUE
+};
+}
+} // namespace AST
 
 /*static*/ const IdString &UhdmAst::partial()
 {
@@ -40,6 +67,11 @@
     static const IdString id("\\is_imported");
     return id;
 }
+/*static*/ const IdString &UhdmAst::is_simplified_wire()
+{
+    static const IdString id("\\is_simplified_wire");
+    return id;
+}
 
 static void sanitize_symbol_name(std::string &name)
 {
@@ -93,6 +125,13 @@
     return objectName;
 }
 
+static AST::AstNode *mkconst_real(double d)
+{
+    AST::AstNode *node = new AST::AstNode(AST::AST_REALVALUE);
+    node->realvalue = d;
+    return node;
+}
+
 static AST::AstNode *make_range(int left, int right, bool is_signed = false)
 {
     // generate a pre-validated range node for a fixed signal range.
@@ -124,8 +163,6 @@
     }
 }
 
-#include "UhdmAstUpstream.cc"
-
 static int get_max_offset_struct(AST::AstNode *node)
 {
     // get the width from the MS member in the struct
@@ -303,7 +340,7 @@
     log_assert(AST_INTERNAL::current_scope.count(wiretype_node->str));
     wiretype_ast = AST_INTERNAL::current_scope[wiretype_node->str];
     // we need to setup current top ast as this simplify
-    // needs to have access to all already definied ids
+    // needs to have access to all already defined ids
     while (wire_node->simplify(true, false, false, 1, -1, false, false)) {
     }
     if (wiretype_ast->children[0]->type == AST::AST_STRUCT && wire_node->type == AST::AST_WIRE) {
@@ -413,11 +450,27 @@
     size_t packed_size = 1;
     size_t unpacked_size = 1;
     std::vector<AST::AstNode *> ranges;
-    bool convert_node = packed_ranges.size() > 1 || unpacked_ranges.size() > 1 || wire_node->attributes.count(ID::wiretype) ||
-                        wire_node->type == AST::AST_PARAMETER || wire_node->type == AST::AST_LOCALPARAM ||
-                        ((wire_node->is_input || wire_node->is_output) && ((packed_ranges.size() > 0 || unpacked_ranges.size() > 0))) ||
-                        (wire_node->attributes.count(UhdmAst::force_convert()) && wire_node->attributes[UhdmAst::force_convert()]->integer == 1);
-    // Convert only when atleast 1 of the ranges has more then 1 range
+
+    // Convert only when node is not a memory and at least 1 of the ranges has more than 1 range
+    const bool convert_node = [&]() {
+        if (wire_node->type == AST::AST_MEMORY)
+            return false;
+        if (packed_ranges.size() > 1)
+            return true;
+        if (unpacked_ranges.size() > 1)
+            return true;
+        if (wire_node->attributes.count(ID::wiretype))
+            return true;
+        if (wire_node->type == AST::AST_PARAMETER)
+            return true;
+        if (wire_node->type == AST::AST_LOCALPARAM)
+            return true;
+        if ((wire_node->is_input || wire_node->is_output) && (packed_ranges.size() > 0 || unpacked_ranges.size() > 0))
+            return true;
+        if (wire_node->attributes.count(UhdmAst::force_convert()) && wire_node->attributes[UhdmAst::force_convert()]->integer == 1)
+            return true;
+        return false;
+    }();
     if (convert_node) {
         if (wire_node->multirange_dimensions.empty()) {
             packed_size = add_multirange_attribute(wire_node, packed_ranges);
@@ -437,6 +490,7 @@
         if (wire_node->type == AST::AST_WIRE && packed_ranges.size() == 1 && unpacked_ranges.size() == 1 && !wire_node->is_input &&
             !wire_node->is_output) {
             wire_node->type = AST::AST_MEMORY;
+            wire_node->is_logic = true;
         }
     }
 
@@ -470,10 +524,13 @@
         // we get left range for first children, and right range for last children
         left = AST::AstNode::mkconst_int(current_struct_elem->children.front()->range_left, true);
         right = AST::AstNode::mkconst_int(current_struct_elem->children.back()->range_right, true);
+    } else if (current_struct_elem->type == AST::AST_UNION) {
+        left = AST::AstNode::mkconst_int(current_struct_elem->range_left, true);
+        right = AST::AstNode::mkconst_int(current_struct_elem->range_right, true);
     } else {
-        // Structs currently can only have AST_STRUCT or AST_STRUCT_ITEM
-        // so, it should never happen
-        log_error("Found %s elem in struct that is currently unsupported!\n", type2str(current_struct_elem->type).c_str());
+        // Structs currently can only have AST_STRUCT, AST_STRUCT_ITEM, or AST_UNION.
+        log_file_error(current_struct_elem->filename, current_struct_elem->location.first_line,
+                       "Accessing struct member of type %s is unsupported.\n", type2str(current_struct_elem->type).c_str());
     }
 
     auto elem_size =
@@ -482,7 +539,7 @@
     AST::AstNode *struct_range = nullptr;
 
     for (auto c : search_node->children) {
-        if (c->type == static_cast<int>(AST::AST_DOT)) {
+        if (c->type == static_cast<int>(AST::Extended::AST_DOT)) {
             // There should be only 1 AST_DOT node children
             log_assert(!sub_dot);
             sub_dot = expand_dot(current_struct_elem, c);
@@ -549,7 +606,8 @@
                 log_error("Unhandled range select (AST_STRUCT) in AST_DOT!\n");
             }
         } else {
-            log_error("Found %s elem in struct that is currently unsupported!\n", type2str(current_struct_elem->type).c_str());
+            log_file_error(current_struct_elem->filename, current_struct_elem->location.first_line,
+                           "Accessing member of a slice of type %s is unsupported.\n", type2str(current_struct_elem->type).c_str());
         }
     }
     // Return range from the begining of *current* struct
@@ -561,11 +619,13 @@
 static AST::AstNode *convert_dot(AST::AstNode *wire_node, AST::AstNode *node, AST::AstNode *dot)
 {
     AST::AstNode *struct_node = nullptr;
-    if (wire_node->type == AST::AST_STRUCT) {
+    if (wire_node->type == AST::AST_STRUCT || wire_node->type == AST::AST_UNION) {
         struct_node = wire_node;
     } else if (wire_node->attributes.count(ID::wiretype)) {
         log_assert(wire_node->attributes[ID::wiretype]->id2ast);
         struct_node = wire_node->attributes[ID::wiretype]->id2ast;
+    } else {
+        log_file_error(wire_node->filename, wire_node->location.first_line, "Unsupported node type: %s\n", type2str(wire_node->type).c_str());
     }
     log_assert(struct_node);
     auto expanded = expand_dot(struct_node, dot);
@@ -844,8 +904,8 @@
 
 static void simplify(AST::AstNode *current_node, AST::AstNode *parent_node)
 {
-    auto dot_it =
-      std::find_if(current_node->children.begin(), current_node->children.end(), [](auto c) { return c->type == static_cast<int>(AST::AST_DOT); });
+    auto dot_it = std::find_if(current_node->children.begin(), current_node->children.end(),
+                               [](auto c) { return c->type == static_cast<int>(AST::Extended::AST_DOT); });
     AST::AstNode *dot = (dot_it != current_node->children.end()) ? *dot_it : nullptr;
 
     AST::AstNode *expanded = nullptr;
@@ -868,8 +928,8 @@
                     break;
                 } else {
                     current_node->str += "." + dot->str.substr(1);
-                    dot_it =
-                      std::find_if(dot->children.begin(), dot->children.end(), [](auto c) { return c->type == static_cast<int>(AST::AST_DOT); });
+                    dot_it = std::find_if(dot->children.begin(), dot->children.end(),
+                                          [](auto c) { return c->type == static_cast<int>(AST::Extended::AST_DOT); });
                     parent_node = dot;
                     dot = (dot_it != dot->children.end()) ? *dot_it : nullptr;
                 }
@@ -906,6 +966,8 @@
         AST_INTERNAL::current_scope[current_node->str] = current_node;
         break;
     case AST::AST_WIRE:
+        current_node->attributes[UhdmAst::is_simplified_wire()] = AST::AstNode::mkconst_int(1, true);
+        [[fallthrough]];
     case AST::AST_PARAMETER:
     case AST::AST_LOCALPARAM:
         AST_INTERNAL::current_scope[current_node->str] = current_node;
@@ -918,7 +980,11 @@
                 break;
             }
             AST::AstNode *wire_node = AST_INTERNAL::current_scope[current_node->str];
-            simplify(wire_node, nullptr);
+
+            // if a wire is simplified multiple times, its ranges may be added multiple times and be redundant as a result
+            if (!wire_node->attributes.count(UhdmAst::is_simplified_wire())) {
+                simplify(wire_node, nullptr);
+            }
             const std::vector<AST::AstNode *> packed_ranges = wire_node->attributes.count(UhdmAst::packed_ranges())
                                                                 ? wire_node->attributes[UhdmAst::packed_ranges()]->children
                                                                 : std::vector<AST::AstNode *>();
@@ -1064,33 +1130,54 @@
 {
     s_vpi_value val;
     vpi_get_value(obj_h, &val);
-    std::string strValType;
+    std::string strValType = "'";
+    bool is_signed = false;
+    if (vpiHandle typespec_h = vpi_handle(vpiTypespec, obj_h)) {
+        is_signed = vpi_get(vpiSigned, typespec_h);
+        if (is_signed) {
+            strValType += "s";
+        }
+    }
     if (val.format) { // Needed to handle parameter nodes without typespecs and constants
         switch (val.format) {
         case vpiScalarVal:
             return AST::AstNode::mkconst_int(val.value.scalar, false, 1);
         case vpiBinStrVal: {
-            strValType = "'b";
+            strValType += "b";
             break;
         }
         case vpiDecStrVal: {
-            strValType = "'d";
+            strValType += "d";
             break;
         }
         case vpiHexStrVal: {
-            strValType = "'h";
+            strValType += "h";
             break;
         }
         case vpiOctStrVal: {
-            strValType = "'o";
+            strValType += "o";
             break;
         }
         // Surelog reports constant integers as a unsigned, but by default int is signed
         // so we are treating here UInt in the same way as if they would be Int
         case vpiUIntVal:
+            if (val.value.uint > std::numeric_limits<std::uint32_t>::max()) {
+                // an integer is by default signed, so use 'sd despite the variant vpiUIntVal
+                strValType = "'sd";
+                string str_value = std::to_string(val.value.uint);
+                val.value.str = strdup(str_value.c_str());
+                break;
+            }
+            [[fallthrough]];
         case vpiIntVal: {
+            if (val.value.integer > std::numeric_limits<std::int32_t>::max()) {
+                strValType = "'sd";
+                string str_value = std::to_string(val.value.integer);
+                val.value.str = strdup(str_value.c_str());
+                break;
+            }
+
             int size = -1;
-            bool is_signed = false;
             // Surelog sometimes report size as part of vpiTypespec (e.g. int_typespec)
             // if it is the case, we need to set size to the left_range of first packed range
             visit_one_to_one({vpiTypespec}, obj_h, [&](AST::AstNode *node) {
@@ -1110,7 +1197,7 @@
                 size = 32;
                 is_signed = true;
             }
-            auto c = AST::AstNode::mkconst_int(val.value.integer, is_signed, size > 0 ? size : 32);
+            auto c = AST::AstNode::mkconst_int(val.format == vpiUIntVal ? val.value.uint : val.value.integer, is_signed, size > 0 ? size : 32);
             if (size == 0 || size == -1)
                 c->is_unsized = true;
             return c;
@@ -1122,12 +1209,13 @@
         default: {
             const uhdm_handle *const handle = (const uhdm_handle *)obj_h;
             const UHDM::BaseClass *const object = (const UHDM::BaseClass *)handle->object;
-            report_error("%s:%d: Encountered unhandled constant format %d\n", object->VpiFile().c_str(), object->VpiLineNo(), val.format);
+            report_error("%.*s:%d: Encountered unhandled constant format %d\n", (int)object->VpiFile().length(), object->VpiFile().data(),
+                         object->VpiLineNo(), val.format);
         }
         }
         // handle vpiBinStrVal, vpiDecStrVal and vpiHexStrVal
         if (std::strchr(val.value.str, '\'')) {
-            return VERILOG_FRONTEND::const2ast(val.value.str, 0, false);
+            return ::systemverilog_plugin::const2ast(val.value.str, 0, false);
         } else {
             auto size = vpi_get(vpiSize, obj_h);
             if (size == 0) {
@@ -1135,7 +1223,7 @@
                 c->is_unsized = true;
                 return c;
             } else {
-                return VERILOG_FRONTEND::const2ast(std::to_string(size) + strValType + val.value.str, 0, false);
+                return ::systemverilog_plugin::const2ast(std::to_string(size) + strValType + val.value.str, 0, false);
             }
         }
     }
@@ -1205,15 +1293,15 @@
                 }
                 break;
             }
-            case AST::AST_BREAK:
-            case AST::AST_CONTINUE: {
+            case AST::Extended::AST_BREAK:
+            case AST::Extended::AST_CONTINUE: {
                 std::for_each(it, block->children.end(), [](auto *node) { delete node; });
                 block->children.erase(it, block->children.end());
                 if (!continue_wire)
                     continue_wire = make_cond_var("$continue");
                 auto *continue_id = make_identifier(continue_wire->str);
                 block->children.push_back(make_ast_node(AST::AST_ASSIGN_EQ, {continue_id, AST::AstNode::mkconst_int(1, false)}));
-                if (type == AST::AST_BREAK) {
+                if (type == AST::Extended::AST_BREAK) {
                     if (!break_wire)
                         break_wire = make_cond_var("$break");
                     auto *break_id = make_identifier(break_wire->str);
@@ -1271,8 +1359,21 @@
     if (auto filename = vpi_get_str(vpiFile, obj_h)) {
         node->filename = filename;
     }
-    if (unsigned int line = vpi_get(vpiLineNo, obj_h)) {
-        node->location.first_line = node->location.last_line = line;
+    if (unsigned int first_line = vpi_get(vpiLineNo, obj_h)) {
+        node->location.first_line = first_line;
+    }
+    if (unsigned int last_line = vpi_get(vpiEndLineNo, obj_h)) {
+        node->location.last_line = last_line;
+    } else {
+        node->location.last_line = node->location.first_line;
+    }
+    if (unsigned int first_col = vpi_get(vpiColumnNo, obj_h)) {
+        node->location.first_column = first_col;
+    }
+    if (unsigned int last_col = vpi_get(vpiEndColumnNo, obj_h)) {
+        node->location.last_column = last_col;
+    } else {
+        node->location.last_column = node->location.first_column;
     }
     node->children = children;
     return node;
@@ -1325,6 +1426,7 @@
                 if (child->type == AST::AST_MEMORY)
                     child->type = AST::AST_WIRE;
             }
+            child->is_signed = child->is_signed || (*it)->is_signed;
             if (!(*it)->children.empty() && child->children.empty()) {
                 // This is a bit ugly, but if the child we're replacing has children and
                 // our node doesn't, we copy its children to not lose any information
@@ -1508,17 +1610,20 @@
 void UhdmAst::process_design()
 {
     current_node = make_ast_node(AST::AST_DESIGN);
-    visit_one_to_many({UHDM::uhdmallInterfaces, UHDM::uhdmallPackages, UHDM::uhdmtopPackages, UHDM::uhdmallModules, UHDM::uhdmtopModules}, obj_h,
-                      [&](AST::AstNode *node) {
-                          if (node) {
-                              shared.top_nodes[node->str] = node;
-                          }
-                      });
+    visit_one_to_many(
+      {UHDM::uhdmallInterfaces, UHDM::uhdmallPackages, UHDM::uhdmtopPackages, UHDM::uhdmallModules, UHDM::uhdmtopModules, vpiTaskFunc}, obj_h,
+      [&](AST::AstNode *node) {
+          if (node) {
+              shared.top_nodes[node->str] = node;
+          }
+      });
     visit_one_to_many({vpiParameter, vpiParamAssign}, obj_h, [&](AST::AstNode *node) {});
     visit_one_to_many({vpiTypedef}, obj_h, [&](AST::AstNode *node) {
         if (node)
             move_type_to_new_typedef(current_node, node);
     });
+    // Add top level typedefs and params to scope
+    setup_current_scope(shared.top_nodes, current_node);
     for (auto pair : shared.top_nodes) {
         if (!pair.second)
             continue;
@@ -1529,6 +1634,7 @@
             clear_current_scope();
         }
     }
+    setup_current_scope(shared.top_nodes, current_node);
     // Once we walked everything, unroll that as children of this node
     for (auto &pair : shared.top_nodes) {
         if (!pair.second)
@@ -1551,6 +1657,17 @@
             pair.second = nullptr;
         }
     }
+    if (!shared.debug_flag) {
+        // Ranges were already converted, erase obsolete attributes
+        visitEachDescendant(current_node, [&](AST::AstNode *node) {
+            node->attributes.erase(UhdmAst::packed_ranges());
+            node->attributes.erase(UhdmAst::unpacked_ranges());
+            if (node->attributes.count(UhdmAst::is_simplified_wire())) {
+                delete node->attributes[UhdmAst::is_simplified_wire()];
+                node->attributes.erase(UhdmAst::is_simplified_wire());
+            }
+        });
+    }
 }
 
 void UhdmAst::simplify_parameter(AST::AstNode *parameter, AST::AstNode *module_node)
@@ -1559,8 +1676,6 @@
     visitEachDescendant(shared.current_top_node, [&](AST::AstNode *current_scope_node) {
         if (current_scope_node->type == AST::AST_TYPEDEF || current_scope_node->type == AST::AST_PARAMETER ||
             current_scope_node->type == AST::AST_LOCALPARAM) {
-            if (current_scope_node->type == AST::AST_TYPEDEF)
-                simplify(current_scope_node, nullptr);
             AST_INTERNAL::current_scope[current_scope_node->str] = current_scope_node;
         }
     });
@@ -1629,7 +1744,7 @@
                 }
             });
             visit_one_to_many({vpiModule, vpiInterface, vpiTaskFunc, vpiParameter, vpiParamAssign, vpiPort, vpiNet, vpiArrayNet, vpiGenScopeArray,
-                               vpiContAssign, vpiProcess, vpiClockingBlock, vpiAssertion},
+                               vpiProcess, vpiClockingBlock, vpiAssertion},
                               obj_h, [&](AST::AstNode *node) {
                                   if (node) {
                                       if (node->type == AST::AST_ASSIGN && node->children.size() < 2)
@@ -1754,7 +1869,7 @@
                 add_or_replace_child(module_node, node);
             }
         });
-        visit_one_to_many({vpiInterface, vpiModule, vpiPort, vpiGenScopeArray}, obj_h, [&](AST::AstNode *node) {
+        visit_one_to_many({vpiInterface, vpiModule, vpiPort, vpiGenScopeArray, vpiContAssign}, obj_h, [&](AST::AstNode *node) {
             if (node) {
                 add_or_replace_child(module_node, node);
             }
@@ -1821,6 +1936,10 @@
             delete node;
         }
     });
+    if (auto elemtypespec_h = vpi_handle(vpiElemTypespec, obj_h)) {
+        visit_one_to_many({vpiRange}, elemtypespec_h, [&](AST::AstNode *node) { packed_ranges.push_back(node); });
+        vpi_release_handle(elemtypespec_h);
+    }
     visit_one_to_many({vpiRange}, obj_h, [&](AST::AstNode *node) { unpacked_ranges.push_back(node); });
     add_multirange_wire(current_node, packed_ranges, unpacked_ranges);
 }
@@ -1844,27 +1963,27 @@
         break;
     }
     case vpiByteTypespec: {
-        current_node->is_signed = true;
+        current_node->is_signed = vpi_get(vpiSigned, typespec_h);
         packed_ranges.push_back(make_range(7, 0));
         shared.report.mark_handled(typespec_h);
         break;
     }
     case vpiShortIntTypespec: {
-        current_node->is_signed = true;
+        current_node->is_signed = vpi_get(vpiSigned, typespec_h);
         packed_ranges.push_back(make_range(15, 0));
         shared.report.mark_handled(typespec_h);
         break;
     }
     case vpiIntTypespec:
     case vpiIntegerTypespec: {
-        current_node->is_signed = true;
+        current_node->is_signed = vpi_get(vpiSigned, typespec_h);
         packed_ranges.push_back(make_range(31, 0));
         shared.report.mark_handled(typespec_h);
         break;
     }
     case vpiTimeTypespec:
     case vpiLongIntTypespec: {
-        current_node->is_signed = true;
+        current_node->is_signed = vpi_get(vpiSigned, typespec_h);
         packed_ranges.push_back(make_range(63, 0));
         shared.report.mark_handled(typespec_h);
         break;
@@ -1931,16 +2050,18 @@
         });
         break;
     case vpiVoidTypespec: {
-        report_error("%s:%d: Void typespecs are currently unsupported", object->VpiFile().c_str(), object->VpiLineNo());
+        report_error("%.*s:%d: Void typespecs are currently unsupported", (int)object->VpiFile().length(), object->VpiFile().data(),
+                     object->VpiLineNo());
         break;
     }
     case vpiClassTypespec: {
-        report_error("%s:%d: Class typespecs are unsupported", object->VpiFile().c_str(), object->VpiLineNo());
+        report_error("%.*s:%d: Class typespecs are unsupported", (int)object->VpiFile().length(), object->VpiFile().data(), object->VpiLineNo());
         break;
     }
     default: {
-        report_error("%s:%d: Encountered unhandled typespec in process_typespec_member: '%s' of type '%s'\n", object->VpiFile().c_str(),
-                     object->VpiLineNo(), object->VpiName().c_str(), UHDM::VpiTypeName(typespec_h).c_str());
+        report_error("%.*s:%d: Encountered unhandled typespec in process_typespec_member: '%.*s' of type '%s'\n", (int)object->VpiFile().length(),
+                     object->VpiFile().data(), object->VpiLineNo(), (int)object->VpiName().length(), object->VpiName().data(),
+                     UHDM::VpiTypeName(typespec_h).c_str());
         break;
     }
     }
@@ -1950,42 +2071,67 @@
 
 void UhdmAst::process_enum_typespec()
 {
+    // BaseTypespec specifies underlying type of the enum.
+    // The BaseTypespec has at most one explicit packed dimension (range).
+    // When base type is not specified in SystemVerilog code, it is assumed to be an int.
+    // Type of enum items (constants) is the same as the enum type.
     current_node = make_ast_node(AST::AST_ENUM);
+    bool has_base_type = false;
+    visit_one_to_one({vpiBaseTypespec}, obj_h, [&](AST::AstNode *node) {
+        has_base_type = true;
+        current_node->children = std::move(node->children);
+        current_node->attributes = std::move(node->attributes);
+        current_node->is_signed = node->is_signed;
+        current_node->is_logic = node->is_logic;
+        delete node;
+    });
+    if (!has_base_type) {
+        // Base typespec is `int` by default
+        // TODO (mglb): This is almost the same code as in `process_int_typespec()`. Put common code in dedicated function.
+        std::vector<AST::AstNode *> packed_ranges;
+        packed_ranges.push_back(make_range(31, 0));
+        add_multirange_wire(current_node, std::move(packed_ranges), {});
+        current_node->is_signed = true;
+    }
+    // We have to restore node's range_* properties if there's no range.
+    const auto range_left = current_node->range_left;
+    const auto range_right = current_node->range_right;
+    const auto range_valid = current_node->range_valid;
+    // Create a range from the typespec just for the purpose of copying it to consts.
+    convert_packed_unpacked_range(current_node);
+    const auto range_it = std::find_if(current_node->children.cbegin(), current_node->children.cend(),
+                                       [](const AST::AstNode *n) { return n->type == AST::AST_RANGE || n->type == AST::AST_MULTIRANGE; });
+    const auto *const range = range_it != current_node->children.cend() ? *range_it : nullptr;
+    if (range) {
+        current_node->children.erase(range_it);
+    } else {
+        current_node->range_left = range_left;
+        current_node->range_right = range_right;
+        current_node->range_valid = range_valid;
+    }
+
     visit_one_to_one({vpiTypedefAlias}, obj_h, [&](AST::AstNode *node) {
         if (node) {
-            current_node->attributes["\\enum_base_type"] = node->clone();
+            current_node->attributes["\\enum_base_type"] = node;
         }
     });
-    visit_one_to_many({vpiEnumConst}, obj_h, [&](AST::AstNode *node) { current_node->children.push_back(node); });
-    vpiHandle typespec_h = vpi_handle(vpiBaseTypespec, obj_h);
-    if (typespec_h) {
-        int typespec_type = vpi_get(vpiType, typespec_h);
-        switch (typespec_type) {
-        case vpiLogicTypespec: {
-            current_node->is_logic = true;
-            shared.report.mark_handled(typespec_h);
-            break;
+    visit_one_to_many({vpiEnumConst}, obj_h, [&](AST::AstNode *node) {
+        // Enum const must have the same type and ranges as the enum.
+        node->is_logic = current_node->is_logic;
+        node->is_signed = current_node->is_signed;
+        if (range) {
+            node->children.push_back(range->clone());
+            node->range_valid = true;
+        } else {
+            node->range_left = range_left;
+            node->range_right = range_right;
+            node->range_valid = range_valid;
         }
-        case vpiByteTypespec:
-        case vpiIntTypespec:
-        case vpiIntegerTypespec: {
-            current_node->is_signed = true;
-            shared.report.mark_handled(typespec_h);
-            break;
-        }
-        case vpiBitTypespec: {
-            shared.report.mark_handled(typespec_h);
-            break;
-        }
-        default: {
-            const uhdm_handle *const handle = (const uhdm_handle *)typespec_h;
-            const UHDM::BaseClass *const object = (const UHDM::BaseClass *)handle->object;
-            report_error("%s:%d: Encountered unhandled typespec in process_enum_typespec: '%s' of type '%s'\n", object->VpiFile().c_str(),
-                         object->VpiLineNo(), object->VpiName().c_str(), UHDM::VpiTypeName(typespec_h).c_str());
-            break;
-        }
-        }
-        vpi_release_handle(typespec_h);
+        // IMPORTANT: invalidates `range_it`!
+        current_node->children.push_back(node);
+    });
+    if (range) {
+        delete range;
     }
 }
 
@@ -1997,7 +2143,6 @@
         constant_node->filename = current_node->filename;
         constant_node->location = current_node->location;
         current_node->children.push_back(constant_node);
-        current_node->children.push_back(make_range(constant_node->range_left, constant_node->range_right, true));
     }
 }
 
@@ -2031,7 +2176,7 @@
     auto right_const = AST::AstNode::mkconst_int(0, true);
     auto range = new AST::AstNode(AST::AST_RANGE, left_const, right_const);
     current_node->children.push_back(range);
-    current_node->is_signed = true;
+    current_node->is_signed = vpi_get(vpiSigned, obj_h);
     visit_default_expr(obj_h);
 }
 
@@ -2262,10 +2407,14 @@
         process_cont_assign_net();
 }
 
-void UhdmAst::process_assignment()
+void UhdmAst::process_assignment(const UHDM::BaseClass *object)
 {
     auto type = vpi_get(vpiBlocking, obj_h) == 1 ? AST::AST_ASSIGN_EQ : AST::AST_ASSIGN_LE;
+    bool shift_unsigned = false;
+    int op_type = vpi_get(vpiOpType, obj_h);
+    AST::AstNodeType node_type;
     current_node = make_ast_node(type);
+
     visit_one_to_one({vpiLhs, vpiRhs}, obj_h, [&](AST::AstNode *node) {
         if (node) {
             if (node->type == AST::AST_PARAMETER || node->type == AST::AST_LOCALPARAM) {
@@ -2274,6 +2423,64 @@
             current_node->children.push_back(node);
         }
     });
+    if (op_type && op_type != vpiAssignmentOp) {
+        switch (op_type) {
+        case vpiSubOp:
+            node_type = AST::AST_SUB;
+            break;
+        case vpiDivOp:
+            node_type = AST::AST_DIV;
+            break;
+        case vpiModOp:
+            node_type = AST::AST_MOD;
+            break;
+        case vpiLShiftOp:
+            node_type = AST::AST_SHIFT_LEFT;
+            shift_unsigned = true;
+            break;
+        case vpiRShiftOp:
+            node_type = AST::AST_SHIFT_RIGHT;
+            shift_unsigned = true;
+            break;
+        case vpiAddOp:
+            node_type = AST::AST_ADD;
+            break;
+        case vpiMultOp:
+            node_type = AST::AST_MUL;
+            break;
+        case vpiBitAndOp:
+            node_type = AST::AST_BIT_AND;
+            break;
+        case vpiBitOrOp:
+            node_type = AST::AST_BIT_OR;
+            break;
+        case vpiBitXorOp:
+            node_type = AST::AST_BIT_XOR;
+            break;
+        case vpiArithLShiftOp:
+            node_type = AST::AST_SHIFT_SLEFT;
+            shift_unsigned = true;
+            break;
+        case vpiArithRShiftOp:
+            node_type = AST::AST_SHIFT_SRIGHT;
+            shift_unsigned = true;
+            break;
+        default:
+            delete current_node;
+            current_node = nullptr;
+            report_error("%.*s:%d: Encountered unhandled compound assignment with operation type %d\n", (int)object->VpiFile().length(),
+                         object->VpiFile().data(), object->VpiLineNo(), op_type);
+            return;
+        }
+        log_assert(current_node->children.size() == 2);
+        auto child_node = new AST::AstNode(node_type, current_node->children[0]->clone(), current_node->children[1]);
+        current_node->children[1] = child_node;
+        if (shift_unsigned) {
+            log_assert(current_node->children[1]->children.size() == 2);
+            auto unsigned_node = new AST::AstNode(AST::AST_TO_UNSIGNED, current_node->children[1]->children[1]);
+            current_node->children[1]->children[1] = unsigned_node;
+        }
+    }
     if (current_node->children.size() == 1 && current_node->children[0]->type == AST::AST_WIRE) {
         auto top_node = find_ancestor({AST::AST_MODULE});
         if (!top_node)
@@ -2377,7 +2584,7 @@
     if (shared.top_nodes.find(type) != shared.top_nodes.end()) {
         // Was created before, fill missing
         elaboratedInterface = shared.top_nodes[type];
-        visit_one_to_many({vpiPort}, obj_h, [&](AST::AstNode *node) {
+        visit_one_to_many({vpiPort, vpiVariables}, obj_h, [&](AST::AstNode *node) {
             if (node) {
                 add_or_replace_child(elaboratedInterface, node);
             }
@@ -2450,6 +2657,7 @@
                 current_node->is_logic = node->is_logic;
                 current_node->is_reg = node->is_reg;
             }
+            current_node->is_signed = node->is_signed;
             delete node;
         }
     });
@@ -2505,7 +2713,8 @@
         if (node) {
             auto process_node = find_ancestor({AST::AST_ALWAYS});
             if (!process_node) {
-                log_error("%s:%d: Currently supports only event control stmts inside 'always'\n", object->VpiFile().c_str(), object->VpiLineNo());
+                log_error("%.*s:%d: Currently supports only event control stmts inside 'always'\n", (int)object->VpiFile().length(),
+                          object->VpiFile().data(), object->VpiLineNo());
             }
             process_node->children.push_back(node);
         }
@@ -2604,7 +2813,8 @@
         break;
     case vpiWildEqOp:
     case vpiWildNeqOp: {
-        report_error("%s:%d: Wildcard operators are not supported yet\n", object->VpiFile().c_str(), object->VpiLineNo());
+        report_error("%.*s:%d: Wildcard operators are not supported yet\n", (int)object->VpiFile().length(), object->VpiFile().data(),
+                     object->VpiLineNo());
         break;
     }
     default: {
@@ -2640,14 +2850,26 @@
             current_node->type = AST::AST_REDUCE_XNOR;
             break;
         case vpiUnaryNandOp: {
-            current_node->type = AST::AST_REDUCE_AND;
-            auto not_node = new AST::AstNode(AST::AST_LOGIC_NOT, current_node);
+            auto not_node = new AST::AstNode(AST::AST_NONE, current_node);
+            if (current_node->children.size() == 2) {
+                current_node->type = AST::AST_BIT_AND;
+                not_node->type = AST::AST_BIT_NOT;
+            } else {
+                current_node->type = AST::AST_REDUCE_AND;
+                not_node->type = AST::AST_LOGIC_NOT;
+            }
             current_node = not_node;
             break;
         }
         case vpiUnaryNorOp: {
-            current_node->type = AST::AST_REDUCE_OR;
-            auto not_node = new AST::AstNode(AST::AST_LOGIC_NOT, current_node);
+            auto not_node = new AST::AstNode(AST::AST_NONE, current_node);
+            if (current_node->children.size() == 2) {
+                current_node->type = AST::AST_BIT_OR;
+                not_node->type = AST::AST_BIT_NOT;
+            } else {
+                current_node->type = AST::AST_REDUCE_OR;
+                not_node->type = AST::AST_LOGIC_NOT;
+            }
             current_node = not_node;
             break;
         }
@@ -2750,7 +2972,8 @@
             break;
         case vpiPostIncOp: {
             // TODO: Make this an actual post-increment op (currently it's a pre-increment)
-            log_warning("%s:%d: Post-incrementation operations are handled as pre-incrementation.\n", object->VpiFile().c_str(), object->VpiLineNo());
+            log_warning("%.*s:%d: Post-incrementation operations are handled as pre-incrementation.\n", (int)object->VpiFile().length(),
+                        object->VpiFile().data(), object->VpiLineNo());
             [[fallthrough]];
         }
         case vpiPreIncOp: {
@@ -2764,7 +2987,8 @@
         }
         case vpiPostDecOp: {
             // TODO: Make this an actual post-decrement op (currently it's a pre-decrement)
-            log_warning("%s:%d: Post-decrementation operations are handled as pre-decrementation.\n", object->VpiFile().c_str(), object->VpiLineNo());
+            log_warning("%.*s:%d: Post-decrementation operations are handled as pre-decrementation.\n", (int)object->VpiFile().length(),
+                        object->VpiFile().data(), object->VpiLineNo());
             [[fallthrough]];
         }
         case vpiPreDecOp: {
@@ -2814,7 +3038,8 @@
         default: {
             delete current_node;
             current_node = nullptr;
-            report_error("%s:%d: Encountered unhandled operation type %d\n", object->VpiFile().c_str(), object->VpiLineNo(), operation);
+            report_error("%.*s:%d: Encountered unhandled operation type %d\n", (int)object->VpiFile().length(), object->VpiFile().data(),
+                         object->VpiLineNo(), operation);
         }
         }
     }
@@ -3145,14 +3370,13 @@
     current_node->str = "$fordecl_block" + std::to_string(loop_id);
     auto loop = make_ast_node(AST::AST_FOR);
     loop->str = "$loop" + std::to_string(loop_id);
-    current_node->children.push_back(loop);
     visit_one_to_many({vpiForInitStmt}, obj_h, [&](AST::AstNode *node) {
         if (node->type == AST::AST_ASSIGN_LE)
             node->type = AST::AST_ASSIGN_EQ;
         auto lhs = node->children[0];
         if (lhs->type == AST::AST_WIRE) {
             auto *wire = lhs->clone();
-            wire->is_reg = true;
+            wire->is_logic = true;
             current_node->children.push_back(wire);
             lhs->type = AST::AST_IDENTIFIER;
             lhs->is_signed = false;
@@ -3179,6 +3403,7 @@
             loop->children.push_back(node);
         }
     });
+    current_node->children.push_back(loop);
     transform_breaks_continues(loop, current_node);
 }
 
@@ -3257,12 +3482,14 @@
     visit_one_to_one({vpiLeftRange, vpiRightRange}, obj_h, [&](AST::AstNode *node) { current_node->children.push_back(node); });
     if (current_node->children.size() > 0) {
         if (current_node->children[0]->str == "unsized") {
-            log_error("%s:%d: Currently not supported object of type 'unsized range'\n", object->VpiFile().c_str(), object->VpiLineNo());
+            log_error("%.*s:%d: Currently not supported object of type 'unsized range'\n", (int)object->VpiFile().length(), object->VpiFile().data(),
+                      object->VpiLineNo());
         }
     }
     if (current_node->children.size() > 1) {
         if (current_node->children[1]->str == "unsized") {
-            log_error("%s:%d: Currently not supported object of type 'unsized range'\n", object->VpiFile().c_str(), object->VpiLineNo());
+            log_error("%.*s:%d: Currently not supported object of type 'unsized range'\n", (int)object->VpiFile().length(), object->VpiFile().data(),
+                      object->VpiLineNo());
         }
     }
 }
@@ -3339,7 +3566,7 @@
                     log_assert(!node->children.empty());
                     top_node->children.push_back(node->children[0]);
                 } else {
-                    node->type = static_cast<AST::AstNodeType>(AST::AST_DOT);
+                    node->type = static_cast<AST::AstNodeType>(AST::Extended::AST_DOT);
                     top_node->children.push_back(node);
                     top_node = node;
                 }
@@ -3402,7 +3629,7 @@
     if (vpi_get(vpiType, typespec_h) == vpiStringTypespec) {
         std::string field_name = vpi_get_str(vpiName, typespec_h);
         if (field_name != "default") { // TODO: better support of the default keyword
-            auto field = new AST::AstNode(static_cast<AST::AstNodeType>(AST::AST_DOT));
+            auto field = new AST::AstNode(static_cast<AST::AstNodeType>(AST::Extended::AST_DOT));
             field->str = field_name;
             current_node->children[0]->children.push_back(field);
         }
@@ -3438,6 +3665,7 @@
             current_node->children.push_back(wiretype_node);
             current_node->is_custom_type = true;
         }
+        current_node->is_signed = node->is_signed;
         delete node;
     });
     // TODO: Handling below seems similar to other typespec accesses for range. Candidate for extraction to a function.
@@ -3485,9 +3713,9 @@
         current_node->str = current_node->str.substr(1);
 }
 
-void UhdmAst::process_func_call()
+void UhdmAst::process_tf_call(AST::AstNodeType type)
 {
-    current_node = make_ast_node(AST::AST_FCALL);
+    current_node = make_ast_node(type);
     visit_one_to_many({vpiArgument}, obj_h, [&](AST::AstNode *node) {
         if (node) {
             if (node->type == AST::AST_PARAMETER || node->type == AST::AST_LOCALPARAM) {
@@ -3527,6 +3755,7 @@
     }
     visit_one_to_many({vpiRange}, obj_h, [&](AST::AstNode *node) { packed_ranges.push_back(node); });
     add_multirange_wire(current_node, packed_ranges, unpacked_ranges);
+    current_node->is_signed = vpi_get(vpiSigned, obj_h);
 }
 
 void UhdmAst::process_int_typespec()
@@ -3536,7 +3765,7 @@
     current_node = make_ast_node(AST::AST_WIRE);
     packed_ranges.push_back(make_range(31, 0));
     add_multirange_wire(current_node, packed_ranges, unpacked_ranges);
-    current_node->is_signed = true;
+    current_node->is_signed = vpi_get(vpiSigned, obj_h);
 }
 
 void UhdmAst::process_shortint_typespec()
@@ -3546,7 +3775,7 @@
     current_node = make_ast_node(AST::AST_WIRE);
     packed_ranges.push_back(make_range(15, 0));
     add_multirange_wire(current_node, packed_ranges, unpacked_ranges);
-    current_node->is_signed = true;
+    current_node->is_signed = vpi_get(vpiSigned, obj_h);
 }
 
 void UhdmAst::process_longint_typespec()
@@ -3556,7 +3785,7 @@
     current_node = make_ast_node(AST::AST_WIRE);
     packed_ranges.push_back(make_range(63, 0));
     add_multirange_wire(current_node, packed_ranges, unpacked_ranges);
-    current_node->is_signed = true;
+    current_node->is_signed = vpi_get(vpiSigned, obj_h);
 }
 
 void UhdmAst::process_byte_typespec()
@@ -3566,7 +3795,7 @@
     current_node = make_ast_node(AST::AST_WIRE);
     packed_ranges.push_back(make_range(7, 0));
     add_multirange_wire(current_node, packed_ranges, unpacked_ranges);
-    current_node->is_signed = true;
+    current_node->is_signed = vpi_get(vpiSigned, obj_h);
 }
 
 void UhdmAst::process_time_typespec()
@@ -3629,6 +3858,7 @@
             current_node->children.push_back(node);
         }
     });
+    current_node->is_signed = vpi_get(vpiSigned, obj_h);
 }
 
 void UhdmAst::process_repeat()
@@ -3751,6 +3981,8 @@
         case vpiStructVar:
         case vpiUnionVar:
         case vpiEnumVar:
+        case vpiBitVar:
+        case vpiByteVar:
         case vpiShortIntVar:
         case vpiLongIntVar:
         case vpiIntVar:
@@ -3759,8 +3991,8 @@
         default: {
             const uhdm_handle *const handle = (const uhdm_handle *)actual_h;
             const UHDM::BaseClass *const object = (const UHDM::BaseClass *)handle->object;
-            report_error("%s:%d: Encountered unhandled type in process_port: %s\n", object->VpiFile().c_str(), object->VpiLineNo(),
-                         UHDM::VpiTypeName(actual_h).c_str());
+            report_error("%.*s:%d: Encountered unhandled type in process_port: %s\n", (int)object->VpiFile().length(), object->VpiFile().data(),
+                         object->VpiLineNo(), UHDM::VpiTypeName(actual_h).c_str());
             break;
         }
         }
@@ -3782,6 +4014,7 @@
                     current_node->children = std::move(node->children);
                 }
             }
+            current_node->is_signed = current_node->is_signed || node->is_signed;
             delete node;
         }
     });
@@ -3859,7 +4092,10 @@
         }
         case vpiIntTypespec:
         case vpiIntegerTypespec: {
-            packed_ranges.push_back(make_range(31, 0));
+            visit_one_to_many({vpiRange}, typespec_h, [&](AST::AstNode *node) { packed_ranges.push_back(node); });
+            if (packed_ranges.empty()) {
+                packed_ranges.push_back(make_range(31, 0));
+            }
             shared.report.mark_handled(typespec_h);
             break;
         }
@@ -3912,8 +4148,9 @@
         default: {
             const uhdm_handle *const handle = (const uhdm_handle *)typespec_h;
             const UHDM::BaseClass *const object = (const UHDM::BaseClass *)handle->object;
-            report_error("%s:%d: Encountered unhandled typespec in process_parameter: '%s' of type '%s'\n", object->VpiFile().c_str(),
-                         object->VpiLineNo(), object->VpiName().c_str(), UHDM::VpiTypeName(typespec_h).c_str());
+            report_error("%.*s:%d: Encountered unhandled typespec in process_parameter: '%.*s' of type '%s'\n", (int)object->VpiFile().length(),
+                         object->VpiFile().data(), object->VpiLineNo(), (int)object->VpiName().length(), object->VpiName().data(),
+                         UHDM::VpiTypeName(typespec_h).c_str());
             break;
         }
         }
@@ -4026,8 +4263,8 @@
 
 void UhdmAst::process_unsupported_stmt(const UHDM::BaseClass *object)
 {
-    log_error("%s:%d: Currently not supported object of type '%s'\n", object->VpiFile().c_str(), object->VpiLineNo(),
-              UHDM::VpiTypeName(obj_h).c_str());
+    log_error("%.*s:%d: Currently not supported object of type '%s'\n", (int)object->VpiFile().length(), object->VpiFile().data(),
+              object->VpiLineNo(), UHDM::VpiTypeName(obj_h).c_str());
 }
 
 AST::AstNode *UhdmAst::process_object(vpiHandle obj_handle)
@@ -4038,8 +4275,8 @@
     const UHDM::BaseClass *const object = (const UHDM::BaseClass *)handle->object;
     for (auto *obj : shared.nonSynthesizableObjects) {
         if (!object->Compare(obj)) {
-            log_warning("%s:%d: Skipping non-synthesizable object of type '%s'\n", object->VpiFile().c_str(), object->VpiLineNo(),
-                        UHDM::VpiTypeName(obj_h).c_str());
+            log_warning("%.*s:%d: Skipping non-synthesizable object of type '%s'\n", (int)object->VpiFile().length(), object->VpiFile().data(),
+                        object->VpiLineNo(), UHDM::VpiTypeName(obj_h).c_str());
             return nullptr;
         }
     }
@@ -4112,8 +4349,9 @@
         break;
     case vpiAssignStmt:
     case vpiAssignment:
-        process_assignment();
+        process_assignment(object);
         break;
+    case vpiInterfaceTypespec:
     case vpiRefVar:
     case vpiRefObj:
         current_node = make_ast_node(AST::AST_IDENTIFIER);
@@ -4182,11 +4420,11 @@
         break;
     case vpiBreak:
         // Will be resolved later by loop processor
-        current_node = make_ast_node(static_cast<AST::AstNodeType>(AST::AST_BREAK));
+        current_node = make_ast_node(static_cast<AST::AstNodeType>(AST::Extended::AST_BREAK));
         break;
     case vpiContinue:
         // Will be resolved later by loop processor
-        current_node = make_ast_node(static_cast<AST::AstNodeType>(AST::AST_CONTINUE));
+        current_node = make_ast_node(static_cast<AST::AstNodeType>(AST::Extended::AST_CONTINUE));
         break;
     case vpiGenScopeArray:
         process_gen_scope_array();
@@ -4221,10 +4459,10 @@
         process_sys_func_call();
         break;
     case vpiFuncCall:
-        process_func_call();
+        process_tf_call(AST::AST_FCALL);
         break;
     case vpiTaskCall:
-        current_node = make_ast_node(AST::AST_TCALL);
+        process_tf_call(AST::AST_TCALL);
         break;
     case vpiImmediateAssert:
         if (!shared.no_assert)
@@ -4299,8 +4537,8 @@
         break;
     case vpiProgram:
     default:
-        report_error("%s:%d: Encountered unhandled object '%s' of type '%s'\n", object->VpiFile().c_str(), object->VpiLineNo(),
-                     object->VpiName().c_str(), UHDM::VpiTypeName(obj_h).c_str());
+        report_error("%.*s:%d: Encountered unhandled object '%.*s' of type '%s'\n", (int)object->VpiFile().length(), object->VpiFile().data(),
+                     object->VpiLineNo(), (int)object->VpiName().length(), object->VpiName().data(), UHDM::VpiTypeName(obj_h).c_str());
         break;
     }
 
@@ -4339,4 +4577,4 @@
     }
 }
 
-YOSYS_NAMESPACE_END
+} // namespace systemverilog_plugin
diff --git a/systemverilog-plugin/UhdmAst.h b/systemverilog-plugin/UhdmAst.h
index b7877a6..6d6a8f6 100644
--- a/systemverilog-plugin/UhdmAst.h
+++ b/systemverilog-plugin/UhdmAst.h
@@ -8,7 +8,8 @@
 #include "uhdmastshared.h"
 #include <uhdm/uhdm.h>
 
-YOSYS_NAMESPACE_BEGIN
+namespace systemverilog_plugin
+{
 
 class UhdmAst
 {
@@ -16,43 +17,44 @@
     // Walks through one-to-many relationships from given parent
     // node through the VPI interface, visiting child nodes belonging to
     // ChildrenNodeTypes that are present in the given object.
-    void visit_one_to_many(const std::vector<int> child_node_types, vpiHandle parent_handle, const std::function<void(AST::AstNode *)> &f);
+    void visit_one_to_many(const std::vector<int> child_node_types, vpiHandle parent_handle, const std::function<void(::Yosys::AST::AstNode *)> &f);
 
     // Walks through one-to-one relationships from given parent
     // node through the VPI interface, visiting child nodes belonging to
     // ChildrenNodeTypes that are present in the given object.
-    void visit_one_to_one(const std::vector<int> child_node_types, vpiHandle parent_handle, const std::function<void(AST::AstNode *)> &f);
+    void visit_one_to_one(const std::vector<int> child_node_types, vpiHandle parent_handle, const std::function<void(::Yosys::AST::AstNode *)> &f);
 
     // Visit children of type vpiRange that belong to the given parent node.
-    void visit_range(vpiHandle obj_h, const std::function<void(AST::AstNode *)> &f);
+    void visit_range(vpiHandle obj_h, const std::function<void(::Yosys::AST::AstNode *)> &f);
 
     // Visit the default expression assigned to a variable.
     void visit_default_expr(vpiHandle obj_h);
 
     // Create an AstNode of the specified type with metadata extracted from
     // the given vpiHandle.
-    AST::AstNode *make_ast_node(AST::AstNodeType type, std::vector<AST::AstNode *> children = {}, bool prefer_full_name = false);
+    ::Yosys::AST::AstNode *make_ast_node(::Yosys::AST::AstNodeType type, std::vector<::Yosys::AST::AstNode *> children = {},
+                                         bool prefer_full_name = false);
 
     // Create an identifier AstNode
-    AST::AstNode *make_identifier(const std::string &name);
+    ::Yosys::AST::AstNode *make_identifier(const std::string &name);
 
     // Makes the passed node a cell node of the specified type
-    void make_cell(vpiHandle obj_h, AST::AstNode *node, AST::AstNode *type);
+    void make_cell(vpiHandle obj_h, ::Yosys::AST::AstNode *node, ::Yosys::AST::AstNode *type);
 
     // Moves a type node to the specified node
-    void move_type_to_new_typedef(AST::AstNode *current_node, AST::AstNode *type_node);
+    void move_type_to_new_typedef(::Yosys::AST::AstNode *current_node, ::Yosys::AST::AstNode *type_node);
 
     // Go up the UhdmAst to find a parent node of the specified type
-    AST::AstNode *find_ancestor(const std::unordered_set<AST::AstNodeType> &types);
+    ::Yosys::AST::AstNode *find_ancestor(const std::unordered_set<::Yosys::AST::AstNodeType> &types);
 
     // Reports that something went wrong with reading the UHDM file
     void report_error(const char *format, ...) const;
 
     // Processes the value connected to the specified node
-    AST::AstNode *process_value(vpiHandle obj_h);
+    ::Yosys::AST::AstNode *process_value(vpiHandle obj_h);
 
     // Transforms break and continue nodes into structures accepted by the AST frontend
-    void transform_breaks_continues(AST::AstNode *loop, AST::AstNode *decl_block);
+    void transform_breaks_continues(::Yosys::AST::AstNode *loop, ::Yosys::AST::AstNode *decl_block);
 
     // The parent UhdmAst
     UhdmAst *parent;
@@ -64,7 +66,7 @@
     vpiHandle obj_h = 0;
 
     // The current Yosys AST node
-    AST::AstNode *current_node = nullptr;
+    ::Yosys::AST::AstNode *current_node = nullptr;
 
     // Indentation used for debug printing
     std::string indent;
@@ -93,7 +95,7 @@
     void process_cont_assign();
     void process_cont_assign_net();
     void process_cont_assign_var_init();
-    void process_assignment();
+    void process_assignment(const UHDM::BaseClass *object);
     void process_net();
     void process_packed_array_net();
     void process_array_net(const UHDM::BaseClass *object);
@@ -127,7 +129,8 @@
     void process_function();
     void process_logic_var();
     void process_sys_func_call();
-    void process_func_call();
+    // use for task calls and function calls
+    void process_tf_call(::Yosys::AST::AstNodeType type);
     void process_immediate_assert();
     void process_hier_path();
     void process_logic_typespec();
@@ -147,7 +150,7 @@
     void process_while();
     void process_gate();
     void process_primterm();
-    void simplify_parameter(AST::AstNode *parameter, AST::AstNode *module_node = nullptr);
+    void simplify_parameter(::Yosys::AST::AstNode *parameter, ::Yosys::AST::AstNode *module_node = nullptr);
     void process_unsupported_stmt(const UHDM::BaseClass *object);
 
     UhdmAst(UhdmAst *p, UhdmAstShared &s, const std::string &i) : parent(p), shared(s), indent(i)
@@ -160,23 +163,20 @@
     UhdmAst(UhdmAstShared &s, const std::string &i = "") : UhdmAst(nullptr, s, i) {}
 
     // Visits single VPI object and creates proper AST node
-    AST::AstNode *process_object(vpiHandle obj_h);
+    ::Yosys::AST::AstNode *process_object(vpiHandle obj_h);
 
     // Visits all VPI design objects and returns created ASTs
-    AST::AstNode *visit_designs(const std::vector<vpiHandle> &designs);
+    ::Yosys::AST::AstNode *visit_designs(const std::vector<vpiHandle> &designs);
 
-    static const IdString &partial();
-    static const IdString &packed_ranges();
-    static const IdString &unpacked_ranges();
+    static const ::Yosys::IdString &partial();
+    static const ::Yosys::IdString &packed_ranges();
+    static const ::Yosys::IdString &unpacked_ranges();
     // set this attribute to force conversion of multirange wire to single range. It is useful to force-convert some memories.
-    static const IdString &force_convert();
-    static const IdString &is_imported();
+    static const ::Yosys::IdString &force_convert();
+    static const ::Yosys::IdString &is_imported();
+    static const ::Yosys::IdString &is_simplified_wire();
 };
 
-namespace VERILOG_FRONTEND
-{
-extern bool sv_mode;
-}
-YOSYS_NAMESPACE_END
+} // namespace systemverilog_plugin
 
 #endif
diff --git a/systemverilog-plugin/UhdmAstUpstream.cc b/systemverilog-plugin/UhdmAstUpstream.cc
deleted file mode 100644
index 921acf1..0000000
--- a/systemverilog-plugin/UhdmAstUpstream.cc
+++ /dev/null
@@ -1,216 +0,0 @@
-namespace AST
-{
-enum AstNodeTypeExtended {
-    AST_DOT = AST::AST_BIND + 1, // here we always want to point to the last element of yosys' AstNodeType
-    AST_BREAK,
-    AST_CONTINUE
-};
-}
-
-static AST::AstNode *mkconst_real(double d)
-{
-    AST::AstNode *node = new AST::AstNode(AST::AST_REALVALUE);
-    node->realvalue = d;
-    return node;
-}
-namespace VERILOG_FRONTEND
-{
-using namespace AST;
-// divide an arbitrary length decimal number by two and return the rest
-static int my_decimal_div_by_two(std::vector<uint8_t> &digits)
-{
-    int carry = 0;
-    for (size_t i = 0; i < digits.size(); i++) {
-        if (digits[i] >= 10)
-            log_file_error(current_filename, get_line_num(), "Invalid use of [a-fxz?] in decimal constant.\n");
-        digits[i] += carry * 10;
-        carry = digits[i] % 2;
-        digits[i] /= 2;
-    }
-    while (!digits.empty() && !digits.front())
-        digits.erase(digits.begin());
-    return carry;
-}
-
-// find the number of significant bits in a binary number (not including the sign bit)
-static int my_ilog2(int x)
-{
-    int ret = 0;
-    while (x != 0 && x != -1) {
-        x = x >> 1;
-        ret++;
-    }
-    return ret;
-}
-
-// parse a binary, decimal, hexadecimal or octal number with support for special bits ('x', 'z' and '?')
-static void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int len_in_bits, int base, char case_type, bool is_unsized)
-{
-    // all digits in string (MSB at index 0)
-    std::vector<uint8_t> digits;
-
-    while (*str) {
-        if ('0' <= *str && *str <= '9')
-            digits.push_back(*str - '0');
-        else if ('a' <= *str && *str <= 'f')
-            digits.push_back(10 + *str - 'a');
-        else if ('A' <= *str && *str <= 'F')
-            digits.push_back(10 + *str - 'A');
-        else if (*str == 'x' || *str == 'X')
-            digits.push_back(0xf0);
-        else if (*str == 'z' || *str == 'Z' || *str == '?')
-            digits.push_back(0xf1);
-        str++;
-    }
-
-    if (base == 10 && GetSize(digits) == 1 && digits.front() >= 0xf0)
-        base = 2;
-
-    data.clear();
-
-    if (base == 10) {
-        while (!digits.empty())
-            data.push_back(my_decimal_div_by_two(digits) ? State::S1 : State::S0);
-    } else {
-        int bits_per_digit = my_ilog2(base - 1);
-        for (auto it = digits.rbegin(), e = digits.rend(); it != e; it++) {
-            if (*it > (base - 1) && *it < 0xf0)
-                log_file_error(current_filename, get_line_num(), "Digit larger than %d used in in base-%d constant.\n", base - 1, base);
-            for (int i = 0; i < bits_per_digit; i++) {
-                int bitmask = 1 << i;
-                if (*it == 0xf0)
-                    data.push_back(case_type == 'x' ? RTLIL::Sa : RTLIL::Sx);
-                else if (*it == 0xf1)
-                    data.push_back(case_type == 'x' || case_type == 'z' ? RTLIL::Sa : RTLIL::Sz);
-                else
-                    data.push_back((*it & bitmask) ? State::S1 : State::S0);
-            }
-        }
-    }
-
-    int len = GetSize(data);
-    RTLIL::State msb = data.empty() ? State::S0 : data.back();
-
-    if (len_in_bits < 0) {
-        if (len < 32)
-            data.resize(32, msb == State::S0 || msb == State::S1 ? RTLIL::S0 : msb);
-        return;
-    }
-
-    if (is_unsized && (len > len_in_bits))
-        log_file_error(current_filename, get_line_num(), "Unsized constant must have width of 1 bit, but have %d bits!\n", len);
-
-    for (len = len - 1; len >= 0; len--)
-        if (data[len] == State::S1)
-            break;
-    if (msb == State::S0 || msb == State::S1) {
-        len += 1;
-        data.resize(len_in_bits, State::S0);
-    } else {
-        len += 2;
-        data.resize(len_in_bits, msb);
-    }
-
-    if (len_in_bits == 0)
-        log_file_error(current_filename, get_line_num(), "Illegal integer constant size of zero (IEEE 1800-2012, 5.7).\n");
-
-    if (len > len_in_bits)
-        log_warning("Literal has a width of %d bit, but value requires %d bit. (%s:%d)\n", len_in_bits, len, current_filename.c_str(),
-                    get_line_num());
-}
-
-// convert the Verilog code for a constant to an AST node
-static AST::AstNode *const2ast(std::string code, char case_type, bool warn_z)
-{
-    if (warn_z) {
-        AST::AstNode *ret = const2ast(code, case_type, false);
-        if (ret != nullptr && std::find(ret->bits.begin(), ret->bits.end(), RTLIL::State::Sz) != ret->bits.end())
-            log_warning("Yosys has only limited support for tri-state logic at the moment. (%s:%d)\n", current_filename.c_str(), get_line_num());
-        return ret;
-    }
-
-    const char *str = code.c_str();
-
-    // Strings
-    if (*str == '"') {
-        int len = strlen(str) - 2;
-        std::vector<RTLIL::State> data;
-        data.reserve(len * 8);
-        for (int i = 0; i < len; i++) {
-            unsigned char ch = str[len - i];
-            for (int j = 0; j < 8; j++) {
-                data.push_back((ch & 1) ? State::S1 : State::S0);
-                ch = ch >> 1;
-            }
-        }
-        AST::AstNode *ast = AST::AstNode::mkconst_bits(data, false);
-        ast->str = code;
-        return ast;
-    }
-
-    for (size_t i = 0; i < code.size(); i++)
-        if (code[i] == '_' || code[i] == ' ' || code[i] == '\t' || code[i] == '\r' || code[i] == '\n')
-            code.erase(code.begin() + (i--));
-    str = code.c_str();
-
-    char *endptr;
-    long len_in_bits = strtol(str, &endptr, 10);
-
-    // Simple base-10 integer
-    if (*endptr == 0) {
-        std::vector<RTLIL::State> data;
-        my_strtobin(data, str, -1, 10, case_type, false);
-        if (data.back() == State::S1)
-            data.push_back(State::S0);
-        return AST::AstNode::mkconst_bits(data, true);
-    }
-
-    // unsized constant
-    if (str == endptr)
-        len_in_bits = -1;
-
-    // The "<bits>'[sS]?[bodhBODH]<digits>" syntax
-    if (*endptr == '\'') {
-        std::vector<RTLIL::State> data;
-        bool is_signed = false;
-        bool is_unsized = len_in_bits < 0;
-        if (*(endptr + 1) == 's' || *(endptr + 1) == 'S') {
-            is_signed = true;
-            endptr++;
-        }
-        switch (*(endptr + 1)) {
-        case 'b':
-        case 'B':
-            my_strtobin(data, endptr + 2, len_in_bits, 2, case_type, is_unsized);
-            break;
-        case 'o':
-        case 'O':
-            my_strtobin(data, endptr + 2, len_in_bits, 8, case_type, is_unsized);
-            break;
-        case 'd':
-        case 'D':
-            my_strtobin(data, endptr + 2, len_in_bits, 10, case_type, is_unsized);
-            break;
-        case 'h':
-        case 'H':
-            my_strtobin(data, endptr + 2, len_in_bits, 16, case_type, is_unsized);
-            break;
-        default:
-            char next_char = char(tolower(*(endptr + 1)));
-            if (next_char == '0' || next_char == '1' || next_char == 'x' || next_char == 'z') {
-                is_unsized = true;
-                my_strtobin(data, endptr + 1, 1, 2, case_type, is_unsized);
-            } else {
-                return NULL;
-            }
-        }
-        if (len_in_bits < 0) {
-            if (is_signed && data.back() == State::S1)
-                data.push_back(State::S0);
-        }
-        return AST::AstNode::mkconst_bits(data, is_signed, is_unsized);
-    }
-
-    return NULL;
-}
-} // namespace VERILOG_FRONTEND
diff --git a/systemverilog-plugin/tests/Makefile b/systemverilog-plugin/tests/Makefile
index e078fa7..4312522 100644
--- a/systemverilog-plugin/tests/Makefile
+++ b/systemverilog-plugin/tests/Makefile
@@ -16,10 +16,20 @@
 
 TESTS = counter \
 		break_continue \
-		separate-compilation
+		separate-compilation \
+		debug-flag \
+		report-flag \
+		defines \
+		defaults \
+		formal
 
 include $(shell pwd)/../../Makefile_test.common
 
 counter_verify = true
 break_continue_verify = $(call diff_test,break_continue,out)
 separate-compilation_verify = true
+debug-flag_verify = true
+report-flag_verify = true
+defaults_verify = true
+defines_verify = true
+formal_verify = true
diff --git a/systemverilog-plugin/tests/debug-flag/debug-flag-buf.sv b/systemverilog-plugin/tests/debug-flag/debug-flag-buf.sv
new file mode 100644
index 0000000..565946b
--- /dev/null
+++ b/systemverilog-plugin/tests/debug-flag/debug-flag-buf.sv
@@ -0,0 +1,21 @@
+// Copyright 2020-2022 F4PGA Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+module BUF (
+  input I,
+  output O
+);
+  assign O = I;
+endmodule;
diff --git a/systemverilog-plugin/tests/debug-flag/debug-flag-pkg.sv b/systemverilog-plugin/tests/debug-flag/debug-flag-pkg.sv
new file mode 100644
index 0000000..b0362fc
--- /dev/null
+++ b/systemverilog-plugin/tests/debug-flag/debug-flag-pkg.sv
@@ -0,0 +1,19 @@
+// Copyright 2020-2022 F4PGA Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+package pkg;
+  parameter BITS = 4;
+  parameter LOG2DELAY = 22;
+endpackage
diff --git a/systemverilog-plugin/tests/debug-flag/debug-flag.tcl b/systemverilog-plugin/tests/debug-flag/debug-flag.tcl
new file mode 100644
index 0000000..86cfee5
--- /dev/null
+++ b/systemverilog-plugin/tests/debug-flag/debug-flag.tcl
@@ -0,0 +1,16 @@
+yosys -import
+if { [info procs read_uhdm] == {} } { plugin -i systemverilog }
+yosys -import  ;# ingest plugin commands
+
+set TMP_DIR /tmp
+if { [info exists ::env(TMPDIR) ] } {
+  set TMP_DIR $::env(TMPDIR)
+}
+
+# Testing simple round-trip
+read_systemverilog -debug -odir $TMP_DIR/debug-flag-test -defer $::env(DESIGN_TOP)-pkg.sv
+read_systemverilog -debug -odir $TMP_DIR/debug-flag-test -defer $::env(DESIGN_TOP)-buf.sv
+read_systemverilog -debug -odir $TMP_DIR/debug-flag-test -defer $::env(DESIGN_TOP).v
+read_systemverilog -debug -odir $TMP_DIR/debug-flag-test -link
+hierarchy
+write_verilog
diff --git a/systemverilog-plugin/tests/debug-flag/debug-flag.v b/systemverilog-plugin/tests/debug-flag/debug-flag.v
new file mode 100644
index 0000000..5bd294a
--- /dev/null
+++ b/systemverilog-plugin/tests/debug-flag/debug-flag.v
@@ -0,0 +1,31 @@
+// Copyright 2020-2022 F4PGA Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+module top (
+  input clk,
+  output [3:0] led
+);
+
+  wire bufg;
+  BUF bufgctrl (
+      .I(clk),
+      .O(bufg)
+  );
+  reg [pkg::BITS + pkg::LOG2DELAY-1 : 0] counter = 0;
+  always @(posedge bufg) begin
+    counter <= counter + 1;
+  end
+  assign led[3:0] = counter >> pkg::LOG2DELAY;
+endmodule
diff --git a/systemverilog-plugin/tests/defaults/defaults.tcl b/systemverilog-plugin/tests/defaults/defaults.tcl
new file mode 100644
index 0000000..a363895
--- /dev/null
+++ b/systemverilog-plugin/tests/defaults/defaults.tcl
@@ -0,0 +1,23 @@
+yosys -import
+if { [info procs read_uhdm] == {} } { plugin -i systemverilog }
+yosys -import  ;# ingest plugin commands
+
+set TMP_DIR /tmp
+if { [info exists ::env(TMPDIR) ] } {
+  set TMP_DIR $::env(TMPDIR)
+}
+
+# Define forbidden value
+systemverilog_defaults -add -DPAKALA
+# Stash it
+systemverilog_defaults -push
+systemverilog_defaults -clear
+read_systemverilog $::env(DESIGN_TOP).v
+# Allow parsing the module again
+delete top
+systemverilog_defaults -pop
+# Skip check for forbidden value
+systemverilog_defaults -add -Pbypass=1
+read_systemverilog $::env(DESIGN_TOP).v
+hierarchy
+write_verilog
diff --git a/systemverilog-plugin/tests/defaults/defaults.v b/systemverilog-plugin/tests/defaults/defaults.v
new file mode 100644
index 0000000..f565a77
--- /dev/null
+++ b/systemverilog-plugin/tests/defaults/defaults.v
@@ -0,0 +1,28 @@
+// Copyright 2020-2022 F4PGA Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
+module top #(
+  parameter bit bypass = 0
+)(
+  input clk,
+  output out
+);
+
+`ifdef PAKALA
+  initial if(!bypass) $stop("Defined forbidden value");
+`endif
+  assign out = clk;
+endmodule
diff --git a/systemverilog-plugin/tests/defines/defines.tcl b/systemverilog-plugin/tests/defines/defines.tcl
new file mode 100644
index 0000000..030c1ad
--- /dev/null
+++ b/systemverilog-plugin/tests/defines/defines.tcl
@@ -0,0 +1,15 @@
+yosys -import
+if { [info procs read_uhdm] == {} } { plugin -i systemverilog }
+yosys -import  ;# ingest plugin commands
+
+set TMP_DIR /tmp
+if { [info exists ::env(TMPDIR) ] } {
+  set TMP_DIR $::env(TMPDIR)
+}
+
+systemverilog_defines -DPONA
+systemverilog_defines -DPAKALA
+systemverilog_defines -UPAKALA
+read_systemverilog $::env(DESIGN_TOP).v
+hierarchy
+write_verilog
diff --git a/systemverilog-plugin/tests/defines/defines.v b/systemverilog-plugin/tests/defines/defines.v
new file mode 100644
index 0000000..528e9f1
--- /dev/null
+++ b/systemverilog-plugin/tests/defines/defines.v
@@ -0,0 +1,29 @@
+// Copyright 2020-2022 F4PGA Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
+module top (
+  input clk,
+  output out
+);
+
+`ifndef PONA
+  initial $stop("Define failed");
+`endif
+`ifdef PAKALA
+  initial $stop("Undefine failed");
+`endif
+  assign out = clk;
+endmodule
diff --git a/systemverilog-plugin/tests/formal/formal.tcl b/systemverilog-plugin/tests/formal/formal.tcl
new file mode 100644
index 0000000..2474219
--- /dev/null
+++ b/systemverilog-plugin/tests/formal/formal.tcl
@@ -0,0 +1,12 @@
+yosys -import
+if { [info procs read_uhdm] == {} } { plugin -i systemverilog }
+yosys -import  ;# ingest plugin commands
+
+set TMP_DIR /tmp
+if { [info exists ::env(TMPDIR) ] } {
+  set TMP_DIR $::env(TMPDIR)
+}
+
+read_systemverilog -formal $::env(DESIGN_TOP).v
+hierarchy
+write_verilog
diff --git a/systemverilog-plugin/tests/formal/formal.v b/systemverilog-plugin/tests/formal/formal.v
new file mode 100644
index 0000000..04e346c
--- /dev/null
+++ b/systemverilog-plugin/tests/formal/formal.v
@@ -0,0 +1,33 @@
+// Copyright 2020-2022 F4PGA Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
+module top #(
+)(
+  input clk,
+  output out
+);
+
+`ifdef SYNTHESIS
+  initial $stop("SYNTHESIS should be undefined");
+`endif
+`ifndef YOSYS
+  initial $stop("YOSYS should be defined");
+`endif
+`ifndef FORMAL
+  initial $stop("FORMAL should be defined");
+`endif
+  assign out = clk;
+endmodule
diff --git a/systemverilog-plugin/tests/report-flag/report-flag-buf.sv b/systemverilog-plugin/tests/report-flag/report-flag-buf.sv
new file mode 100644
index 0000000..565946b
--- /dev/null
+++ b/systemverilog-plugin/tests/report-flag/report-flag-buf.sv
@@ -0,0 +1,21 @@
+// Copyright 2020-2022 F4PGA Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+module BUF (
+  input I,
+  output O
+);
+  assign O = I;
+endmodule;
diff --git a/systemverilog-plugin/tests/report-flag/report-flag-pkg.sv b/systemverilog-plugin/tests/report-flag/report-flag-pkg.sv
new file mode 100644
index 0000000..b0362fc
--- /dev/null
+++ b/systemverilog-plugin/tests/report-flag/report-flag-pkg.sv
@@ -0,0 +1,19 @@
+// Copyright 2020-2022 F4PGA Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+package pkg;
+  parameter BITS = 4;
+  parameter LOG2DELAY = 22;
+endpackage
diff --git a/systemverilog-plugin/tests/report-flag/report-flag.tcl b/systemverilog-plugin/tests/report-flag/report-flag.tcl
new file mode 100644
index 0000000..3a3cc6d
--- /dev/null
+++ b/systemverilog-plugin/tests/report-flag/report-flag.tcl
@@ -0,0 +1,16 @@
+yosys -import
+if { [info procs read_uhdm] == {} } { plugin -i systemverilog }
+yosys -import  ;# ingest plugin commands
+
+set TMP_DIR /tmp
+if { [info exists ::env(TMPDIR) ] } {
+  set TMP_DIR $::env(TMPDIR)
+}
+
+# Testing simple round-trip
+read_systemverilog -report $TMP_DIR/report-flag-test -odir $TMP_DIR/report-flag-test -defer $::env(DESIGN_TOP)-pkg.sv
+read_systemverilog -report $TMP_DIR/report-flag-test -odir $TMP_DIR/report-flag-test -defer $::env(DESIGN_TOP)-buf.sv
+read_systemverilog -report $TMP_DIR/report-flag-test -odir $TMP_DIR/report-flag-test -defer $::env(DESIGN_TOP).v
+read_systemverilog -report $TMP_DIR/report-flag-test -odir $TMP_DIR/report-flag-test -link
+hierarchy
+write_verilog
diff --git a/systemverilog-plugin/tests/report-flag/report-flag.v b/systemverilog-plugin/tests/report-flag/report-flag.v
new file mode 100644
index 0000000..5bd294a
--- /dev/null
+++ b/systemverilog-plugin/tests/report-flag/report-flag.v
@@ -0,0 +1,31 @@
+// Copyright 2020-2022 F4PGA Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+module top (
+  input clk,
+  output [3:0] led
+);
+
+  wire bufg;
+  BUF bufgctrl (
+      .I(clk),
+      .O(bufg)
+  );
+  reg [pkg::BITS + pkg::LOG2DELAY-1 : 0] counter = 0;
+  always @(posedge bufg) begin
+    counter <= counter + 1;
+  end
+  assign led[3:0] = counter >> pkg::LOG2DELAY;
+endmodule
diff --git a/systemverilog-plugin/third_party/yosys/README b/systemverilog-plugin/third_party/yosys/README
new file mode 100644
index 0000000..ceb62a9
--- /dev/null
+++ b/systemverilog-plugin/third_party/yosys/README
@@ -0,0 +1,17 @@
+Files in this directory were copied from Yosys sources and slightly adapted.
+Original sources and their license available at https://github.com/YosysHQ/yosys.
+
+Copied files, their sources, changes & notes:
+
+- const2ast.cc: yosys/frontends/verilog/const2ast.cc (rev. 72787f5)
+  - The file is a part of Yosys Verilog frontend, which is not publicly exposed
+    by Yosys. Copy has been made to avoid relying on internal details.
+  - Changes:
+    - C++ includes adapted to not rely on `verilog_frontend.h` file.
+    - Removed Yosys namespace; `const2ast()` has been placed inside
+      `systemverilog_plugin` namespace to avoid conflicts with the symbol from
+      Yosys when statically linking.
+
+Non-copied files placed here for interfacing purposes:
+
+- const2ast.h
diff --git a/systemverilog-plugin/third_party/yosys/const2ast.cc b/systemverilog-plugin/third_party/yosys/const2ast.cc
new file mode 100644
index 0000000..96ea6cc
--- /dev/null
+++ b/systemverilog-plugin/third_party/yosys/const2ast.cc
@@ -0,0 +1,252 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ *  ---
+ *
+ *  The Verilog frontend.
+ *
+ *  This frontend is using the AST frontend library (see frontends/ast/).
+ *  Thus this frontend does not generate RTLIL code directly but creates an
+ *  AST directly from the Verilog parse tree and then passes this AST to
+ *  the AST frontend library.
+ *
+ *  ---
+ *
+ *  This file contains an ad-hoc parser for Verilog constants. The Verilog
+ *  lexer does only recognize a constant but does not actually split it to its
+ *  components. I.e. it just passes the Verilog code for the constant to the
+ *  bison parser. The parser then uses the function const2ast() from this file
+ *  to create an AST node for the constant.
+ *
+ *  ---
+ *
+ *  The file has been adapted for use in Yosys SystemVerilog Plugin.
+ *
+ */
+
+#include "const2ast.h"
+#include "frontends/ast/ast.h"
+#include "kernel/log.h"
+
+#include <string>
+#include <cmath>
+#include <vector>
+
+using namespace Yosys;
+using namespace Yosys::AST;
+
+// divide an arbitrary length decimal number by two and return the rest
+static int my_decimal_div_by_two(std::vector<uint8_t> &digits)
+{
+	int carry = 0;
+	for (size_t i = 0; i < digits.size(); i++) {
+		if (digits[i] >= 10)
+			log_file_error(current_filename, get_line_num(), "Invalid use of [a-fxz?] in decimal constant.\n");
+		digits[i] += carry * 10;
+		carry = digits[i] % 2;
+		digits[i] /= 2;
+	}
+	while (!digits.empty() && !digits.front())
+		digits.erase(digits.begin());
+	return carry;
+}
+
+// find the number of significant bits in a binary number (not including the sign bit)
+static int my_ilog2(int x)
+{
+	int ret = 0;
+	while (x != 0 && x != -1) {
+		x = x >> 1;
+		ret++;
+	}
+	return ret;
+}
+
+// parse a binary, decimal, hexadecimal or octal number with support for special bits ('x', 'z' and '?')
+static void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int len_in_bits, int base, char case_type, bool is_unsized)
+{
+	// all digits in string (MSB at index 0)
+	std::vector<uint8_t> digits;
+
+	while (*str) {
+		if ('0' <= *str && *str <= '9')
+			digits.push_back(*str - '0');
+		else if ('a' <= *str && *str <= 'f')
+			digits.push_back(10 + *str - 'a');
+		else if ('A' <= *str && *str <= 'F')
+			digits.push_back(10 + *str - 'A');
+		else if (*str == 'x' || *str == 'X')
+			digits.push_back(0xf0);
+		else if (*str == 'z' || *str == 'Z' || *str == '?')
+			digits.push_back(0xf1);
+		str++;
+	}
+
+	if (base == 10 && GetSize(digits) == 1 && digits.front() >= 0xf0)
+		base = 2;
+
+	data.clear();
+
+	if (base == 10) {
+		while (!digits.empty())
+			data.push_back(my_decimal_div_by_two(digits) ? State::S1 : State::S0);
+	} else {
+		int bits_per_digit = my_ilog2(base-1);
+		for (auto it = digits.rbegin(), e = digits.rend(); it != e; it++) {
+			if (*it > (base-1) && *it < 0xf0)
+				log_file_error(current_filename, get_line_num(), "Digit larger than %d used in in base-%d constant.\n",
+					       base-1, base);
+			for (int i = 0; i < bits_per_digit; i++) {
+				int bitmask = 1 << i;
+				if (*it == 0xf0)
+					data.push_back(case_type == 'x' ? RTLIL::Sa : RTLIL::Sx);
+				else if (*it == 0xf1)
+					data.push_back(case_type == 'x' || case_type == 'z' ? RTLIL::Sa : RTLIL::Sz);
+				else
+					data.push_back((*it & bitmask) ? State::S1 : State::S0);
+			}
+		}
+	}
+
+	int len = GetSize(data);
+	RTLIL::State msb = data.empty() ? State::S0 : data.back();
+
+	if (len_in_bits < 0) {
+		if (len < 32)
+			data.resize(32, msb == State::S0 || msb == State::S1 ? RTLIL::S0 : msb);
+		return;
+	}
+
+	if (is_unsized && (len > len_in_bits))
+		log_file_error(current_filename, get_line_num(), "Unsized constant must have width of 1 bit, but have %d bits!\n", len);
+
+	for (len = len - 1; len >= 0; len--)
+		if (data[len] == State::S1)
+			break;
+	if (msb == State::S0 || msb == State::S1) {
+		len += 1;
+		data.resize(len_in_bits, State::S0);
+	} else {
+		len += 2;
+		data.resize(len_in_bits, msb);
+	}
+
+	if (len_in_bits == 0)
+		log_file_error(current_filename, get_line_num(), "Illegal integer constant size of zero (IEEE 1800-2012, 5.7).\n");
+
+	if (len > len_in_bits)
+		log_warning("Literal has a width of %d bit, but value requires %d bit. (%s:%d)\n",
+			len_in_bits, len, current_filename.c_str(), get_line_num());
+}
+
+// convert the Verilog code for a constant to an AST node
+AstNode *systemverilog_plugin::const2ast(std::string code, char case_type, bool warn_z)
+{
+	if (warn_z) {
+		AstNode *ret = const2ast(code, case_type);
+		if (ret != nullptr && std::find(ret->bits.begin(), ret->bits.end(), RTLIL::State::Sz) != ret->bits.end())
+			log_warning("Yosys has only limited support for tri-state logic at the moment. (%s:%d)\n",
+				current_filename.c_str(), get_line_num());
+		return ret;
+	}
+
+	const char *str = code.c_str();
+
+	// Strings
+	if (*str == '"') {
+		int len = strlen(str) - 2;
+		std::vector<RTLIL::State> data;
+		data.reserve(len * 8);
+		for (int i = 0; i < len; i++) {
+			unsigned char ch = str[len - i];
+			for (int j = 0; j < 8; j++) {
+				data.push_back((ch & 1) ? State::S1 : State::S0);
+				ch = ch >> 1;
+			}
+		}
+		AstNode *ast = AstNode::mkconst_bits(data, false);
+		ast->str = code;
+		return ast;
+	}
+
+	for (size_t i = 0; i < code.size(); i++)
+		if (code[i] == '_' || code[i] == ' ' || code[i] == '\t' || code[i] == '\r' || code[i] == '\n')
+			code.erase(code.begin()+(i--));
+	str = code.c_str();
+
+	char *endptr;
+	long len_in_bits = strtol(str, &endptr, 10);
+
+	// Simple base-10 integer
+	if (*endptr == 0) {
+		std::vector<RTLIL::State> data;
+		my_strtobin(data, str, -1, 10, case_type, false);
+		if (data.back() == State::S1)
+			data.push_back(State::S0);
+		return AstNode::mkconst_bits(data, true);
+	}
+
+	// unsized constant
+	if (str == endptr)
+		len_in_bits = -1;
+
+	// The "<bits>'[sS]?[bodhBODH]<digits>" syntax
+	if (*endptr == '\'')
+	{
+		std::vector<RTLIL::State> data;
+		bool is_signed = false;
+		bool is_unsized = len_in_bits < 0;
+		if (*(endptr+1) == 's' || *(endptr+1) == 'S') {
+			is_signed = true;
+			endptr++;
+		}
+		switch (*(endptr+1))
+		{
+		case 'b':
+		case 'B':
+			my_strtobin(data, endptr+2, len_in_bits, 2, case_type, is_unsized);
+			break;
+		case 'o':
+		case 'O':
+			my_strtobin(data, endptr+2, len_in_bits, 8, case_type, is_unsized);
+			break;
+		case 'd':
+		case 'D':
+			my_strtobin(data, endptr+2, len_in_bits, 10, case_type, is_unsized);
+			break;
+		case 'h':
+		case 'H':
+			my_strtobin(data, endptr+2, len_in_bits, 16, case_type, is_unsized);
+			break;
+		default:
+			char next_char = char(tolower(*(endptr+1)));
+			if (next_char == '0' || next_char == '1' || next_char == 'x' || next_char == 'z') {
+				is_unsized = true;
+				my_strtobin(data, endptr+1, 1, 2, case_type, is_unsized);
+			} else {
+				return NULL;
+			}
+		}
+		if (len_in_bits < 0) {
+			if (is_signed && data.back() == State::S1)
+				data.push_back(State::S0);
+		}
+		return AstNode::mkconst_bits(data, is_signed, is_unsized);
+	}
+
+	return NULL;
+}
diff --git a/systemverilog-plugin/third_party/yosys/const2ast.h b/systemverilog-plugin/third_party/yosys/const2ast.h
new file mode 100644
index 0000000..f7130a2
--- /dev/null
+++ b/systemverilog-plugin/third_party/yosys/const2ast.h
@@ -0,0 +1,13 @@
+#ifndef SYSTEMVERILOG_PLUGIN_CONST2AST_H
+#define SYSTEMVERILOG_PLUGIN_CONST2AST_H
+
+#include "frontends/ast/ast.h"
+#include <string>
+
+namespace systemverilog_plugin
+{
+	// this function converts a Verilog constant to an AST_CONSTANT node
+	Yosys::AST::AstNode *const2ast(std::string code, char case_type = 0, bool warn_z = false);
+}
+
+#endif // SYSTEMVERILOG_PLUGIN_CONST2AST_H
diff --git a/systemverilog-plugin/uhdmastfrontend.cc b/systemverilog-plugin/uhdmastfrontend.cc
index c09688c..427fb37 100644
--- a/systemverilog-plugin/uhdmastfrontend.cc
+++ b/systemverilog-plugin/uhdmastfrontend.cc
@@ -25,7 +25,10 @@
                          bool shallowVisit = false);
 }
 
-YOSYS_NAMESPACE_BEGIN
+namespace systemverilog_plugin
+{
+
+using namespace ::Yosys;
 
 struct UhdmAstFrontend : public UhdmCommonFrontend {
     UhdmAstFrontend() : UhdmCommonFrontend("uhdm", "read UHDM file") {}
@@ -44,13 +47,14 @@
         UHDM::Serializer serializer;
 
         std::vector<vpiHandle> restoredDesigns = serializer.Restore(filename);
-        UHDM::SynthSubset *synthSubset = new UHDM::SynthSubset(&serializer, this->shared.nonSynthesizableObjects, false);
+        UHDM::SynthSubset *synthSubset =
+          make_new_object_with_optional_extra_true_arg<UHDM::SynthSubset>(&serializer, this->shared.nonSynthesizableObjects, false);
         synthSubset->listenDesigns(restoredDesigns);
         delete synthSubset;
         if (this->shared.debug_flag || !this->report_directory.empty()) {
             for (auto design : restoredDesigns) {
-                std::stringstream strstr;
-                UHDM::visit_object(design, 1, "", &this->shared.report.unhandled, this->shared.debug_flag ? std::cout : strstr);
+                std::ofstream null_stream;
+                UHDM::visit_object(design, 1, "", &this->shared.report.unhandled, this->shared.debug_flag ? std::cout : null_stream);
             }
         }
         UhdmAst uhdm_ast(this->shared);
@@ -67,4 +71,4 @@
     void call_log_header(RTLIL::Design *design) override { log_header(design, "Executing UHDM frontend.\n"); }
 } UhdmAstFrontend;
 
-YOSYS_NAMESPACE_END
+} // namespace systemverilog_plugin
diff --git a/systemverilog-plugin/uhdmastreport.cc b/systemverilog-plugin/uhdmastreport.cc
index 9a2832f..10d6a94 100644
--- a/systemverilog-plugin/uhdmastreport.cc
+++ b/systemverilog-plugin/uhdmastreport.cc
@@ -5,7 +5,10 @@
 #include <uhdm/BaseClass.h>
 #include <unordered_set>
 
-YOSYS_NAMESPACE_BEGIN
+namespace systemverilog_plugin
+{
+
+using namespace ::Yosys;
 
 void UhdmAstReport::mark_handled(const UHDM::BaseClass *object)
 {
@@ -13,7 +16,7 @@
     auto it = unhandled.find(object);
     if (it != unhandled.end()) {
         unhandled.erase(it);
-        handled_count_per_file.at(object->VpiFile())++;
+        handled_count_per_file.at(std::string(object->VpiFile()))++;
     }
 }
 
@@ -40,7 +43,7 @@
     for (auto object : unhandled) {
         if (!object->VpiFile().empty() && object->VpiFile() != AST::current_filename) {
             unhandled_per_file.insert(std::make_pair(object->VpiFile(), std::unordered_set<unsigned>()));
-            unhandled_per_file.at(object->VpiFile()).insert(object->VpiLineNo());
+            unhandled_per_file.at(std::string(object->VpiFile())).insert(object->VpiLineNo());
             handled_count_per_file.insert(std::make_pair(object->VpiFile(), 0));
         }
     }
@@ -84,4 +87,4 @@
     index_file << "</body>\n</html>" << std::endl;
 }
 
-YOSYS_NAMESPACE_END
+} // namespace systemverilog_plugin
diff --git a/systemverilog-plugin/uhdmastreport.h b/systemverilog-plugin/uhdmastreport.h
index ae16b95..e2403fc 100644
--- a/systemverilog-plugin/uhdmastreport.h
+++ b/systemverilog-plugin/uhdmastreport.h
@@ -8,7 +8,8 @@
 #undef cover
 #include <uhdm/uhdm.h>
 
-YOSYS_NAMESPACE_BEGIN
+namespace systemverilog_plugin
+{
 
 class UhdmAstReport
 {
@@ -30,6 +31,6 @@
     void write(const std::string &directory);
 };
 
-YOSYS_NAMESPACE_END
+} // namespace systemverilog_plugin
 
 #endif
diff --git a/systemverilog-plugin/uhdmastshared.h b/systemverilog-plugin/uhdmastshared.h
index a1ad1c6..475ba70 100644
--- a/systemverilog-plugin/uhdmastshared.h
+++ b/systemverilog-plugin/uhdmastshared.h
@@ -5,7 +5,8 @@
 #include <string>
 #include <unordered_map>
 
-YOSYS_NAMESPACE_BEGIN
+namespace systemverilog_plugin
+{
 
 class UhdmAstShared
 {
@@ -50,20 +51,25 @@
     // applies only to read_systemverilog command
     bool link = false;
 
+    // Flag equivalent to read_verilog -formal
+    // Defines FORMAL, undefines SYNTHESIS
+    // Allows verification constructs in Surelog
+    bool formal = false;
+
     // Top nodes of the design (modules, interfaces)
-    std::unordered_map<std::string, AST::AstNode *> top_nodes;
+    std::unordered_map<std::string, ::Yosys::AST::AstNode *> top_nodes;
 
     // UHDM node coverage report
     UhdmAstReport report;
 
     // Map from AST param nodes to their types (used for params with struct types)
-    std::unordered_map<std::string, AST::AstNode *> param_types;
+    std::unordered_map<std::string, ::Yosys::AST::AstNode *> param_types;
 
-    AST::AstNode *current_top_node = nullptr;
+    ::Yosys::AST::AstNode *current_top_node = nullptr;
     // Set of non-synthesizable objects to skip in current design;
     std::set<const UHDM::BaseClass *> nonSynthesizableObjects;
 };
 
-YOSYS_NAMESPACE_END
+} // namespace systemverilog_plugin
 
 #endif
diff --git a/systemverilog-plugin/uhdmcommonfrontend.cc b/systemverilog-plugin/uhdmcommonfrontend.cc
index 651552a..7fd3871 100644
--- a/systemverilog-plugin/uhdmcommonfrontend.cc
+++ b/systemverilog-plugin/uhdmcommonfrontend.cc
@@ -19,7 +19,10 @@
 
 #include "uhdmcommonfrontend.h"
 
-YOSYS_NAMESPACE_BEGIN
+namespace systemverilog_plugin
+{
+
+using namespace ::Yosys;
 
 /* Stub for AST::process */
 static void set_line_num(int) {}
@@ -62,13 +65,19 @@
     log("        parameters of modules yield invalid or not synthesizable code.\n");
     log("        Needs to be followed by read_systemverilog -link after reading\n");
     log("        all files.\n");
+    log("\n");
     log("    -link\n");
     log("        performs linking and elaboration of the files read with -defer\n");
+    log("\n");
     log("    -parse-only\n");
     log("        this parameter only applies to read_systemverilog command,\n");
     log("        it runs only Surelog to parse design, but doesn't load generated\n");
     log("        tree into Yosys.\n");
     log("\n");
+    log("    -formal\n");
+    log("        enable support for SystemVerilog assertions and some Yosys extensions\n");
+    log("        replace the implicit -D SYNTHESIS with -D FORMAL\n");
+    log("\n");
 }
 
 void UhdmCommonFrontend::execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
@@ -117,6 +126,10 @@
             this->shared.link = true;
             // Surelog needs it in the command line to link correctly
             unhandled_args.push_back(args[i]);
+        } else if (args[i] == "-formal") {
+            this->shared.formal = true;
+            // Surelog needs it in the command line to annotate UHDM
+            unhandled_args.push_back(args[i]);
         } else {
             unhandled_args.push_back(args[i]);
         }
@@ -147,4 +160,4 @@
     }
 }
 
-YOSYS_NAMESPACE_END
+} // namespace systemverilog_plugin
diff --git a/systemverilog-plugin/uhdmcommonfrontend.h b/systemverilog-plugin/uhdmcommonfrontend.h
index 3d5ff16..4c10d10 100644
--- a/systemverilog-plugin/uhdmcommonfrontend.h
+++ b/systemverilog-plugin/uhdmcommonfrontend.h
@@ -23,20 +23,39 @@
 #include "uhdm/SynthSubset.h"
 #include "uhdm/VpiListener.h"
 #include <string>
+#include <type_traits>
 #include <vector>
 
-YOSYS_NAMESPACE_BEGIN
+namespace systemverilog_plugin
+{
 
-struct UhdmCommonFrontend : public Frontend {
+// FIXME (mglb): temporary fix to support UHDM both before and after the following change:
+// https://github.com/chipsalliance/UHDM/commit/d78d094448bd94926644e48adea4df293b82f101
+// The commit introducing this code should to be reverted after Surelog is bumped to recent versions in all our repositories.
+template <typename ObjT, typename... ArgN, std::enable_if_t<std::is_constructible_v<ObjT, ArgN...>, bool> = true>
+static inline ObjT *make_new_object_with_optional_extra_true_arg(ArgN &&... arg_n)
+{
+    // Older UHDM version
+    return new ObjT(std::forward<ArgN>(arg_n)...);
+}
+
+template <typename ObjT, typename... ArgN, std::enable_if_t<!std::is_constructible_v<ObjT, ArgN...>, bool> = true>
+static inline ObjT *make_new_object_with_optional_extra_true_arg(ArgN &&... arg_n)
+{
+    // Newer UHDM version
+    return new ObjT(std::forward<ArgN>(arg_n)..., true);
+}
+
+struct UhdmCommonFrontend : public ::Yosys::Frontend {
     UhdmAstShared shared;
     std::string report_directory;
     std::vector<std::string> args;
     UhdmCommonFrontend(std::string name, std::string short_help) : Frontend(name, short_help) {}
     virtual void print_read_options();
     virtual void help() = 0;
-    virtual AST::AstNode *parse(std::string filename) = 0;
-    virtual void call_log_header(RTLIL::Design *design) = 0;
-    void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design);
+    virtual ::Yosys::AST::AstNode *parse(std::string filename) = 0;
+    virtual void call_log_header(::Yosys::RTLIL::Design *design) = 0;
+    void execute(std::istream *&f, std::string filename, std::vector<std::string> args, ::Yosys::RTLIL::Design *design);
 };
 
-YOSYS_NAMESPACE_END
+} // namespace systemverilog_plugin
diff --git a/systemverilog-plugin/uhdmsurelogastfrontend.cc b/systemverilog-plugin/uhdmsurelogastfrontend.cc
index 0a72d26..8801d8e 100644
--- a/systemverilog-plugin/uhdmsurelogastfrontend.cc
+++ b/systemverilog-plugin/uhdmsurelogastfrontend.cc
@@ -29,6 +29,9 @@
 #include <sys/param.h>
 #include <unistd.h>
 #endif
+#include <memory>
+
+#include <list>
 
 #include "Surelog/ErrorReporting/Report.h"
 #include "Surelog/surelog.h"
@@ -39,44 +42,78 @@
                          bool shallowVisit = false);
 }
 
-YOSYS_NAMESPACE_BEGIN
-
-std::vector<vpiHandle> executeCompilation(SURELOG::SymbolTable *symbolTable, SURELOG::ErrorContainer *errors, SURELOG::CommandLineParser *clp,
-                                          SURELOG::scompiler *compiler)
+namespace systemverilog_plugin
 {
-    bool success = true;
-    bool noFatalErrors = true;
-    unsigned int codedReturn = 0;
-    clp->setWriteUhdm(false);
-    errors->printMessages(clp->muteStdout());
-    std::vector<vpiHandle> the_design;
-    if (success && (!clp->help())) {
-        compiler = SURELOG::start_compiler(clp);
-        if (!compiler)
+
+using namespace ::Yosys;
+
+// Store systemverilog defaults to be passed for every invocation of read_systemverilog
+static std::vector<std::string> systemverilog_defaults;
+static std::list<std::vector<std::string>> systemverilog_defaults_stack;
+
+// Store global definitions for top-level defines
+static std::vector<std::string> systemverilog_defines;
+
+// SURELOG::scompiler wrapper.
+// Owns UHDM/VPI resources used by designs returned from `execute`
+class Compiler
+{
+  public:
+    Compiler() = default;
+    ~Compiler()
+    {
+        if (this->scompiler) {
+            SURELOG::shutdown_compiler(this->scompiler);
+        }
+    }
+
+    const std::vector<vpiHandle> &execute(std::unique_ptr<SURELOG::ErrorContainer> errors, std::unique_ptr<SURELOG::CommandLineParser> clp)
+    {
+        log_assert(!this->errors && !this->clp && !this->scompiler);
+
+        bool success = true;
+        bool noFatalErrors = true;
+        unsigned int codedReturn = 0;
+        clp->setWriteUhdm(false);
+        errors->printMessages(clp->muteStdout());
+        if (success && (!clp->help())) {
+            this->scompiler = SURELOG::start_compiler(clp.get());
+            if (!this->scompiler)
+                codedReturn |= 1;
+            this->designs.push_back(SURELOG::get_uhdm_design(this->scompiler));
+        }
+        SURELOG::ErrorContainer::Stats stats;
+        if (!clp->help()) {
+            stats = errors->getErrorStats();
+            if (stats.nbFatal)
+                codedReturn |= 1;
+            if (stats.nbSyntax)
+                codedReturn |= 2;
+        }
+        bool noFErrors = true;
+        if (!clp->help())
+            noFErrors = errors->printStats(stats, clp->muteStdout());
+        if (noFErrors == false) {
+            noFatalErrors = false;
+        }
+        if ((!noFatalErrors) || (!success) || (errors->getErrorStats().nbError))
             codedReturn |= 1;
-        the_design.push_back(SURELOG::get_uhdm_design(compiler));
+        if (codedReturn) {
+            log_error("Error when parsing design. Aborting!\n");
+        }
+
+        this->clp = std::move(clp);
+        this->errors = std::move(errors);
+
+        return this->designs;
     }
-    SURELOG::ErrorContainer::Stats stats;
-    if (!clp->help()) {
-        stats = errors->getErrorStats();
-        if (stats.nbFatal)
-            codedReturn |= 1;
-        if (stats.nbSyntax)
-            codedReturn |= 2;
-    }
-    bool noFErrors = true;
-    if (!clp->help())
-        noFErrors = errors->printStats(stats, clp->muteStdout());
-    if (noFErrors == false) {
-        noFatalErrors = false;
-    }
-    if ((!noFatalErrors) || (!success) || (errors->getErrorStats().nbError))
-        codedReturn |= 1;
-    if (codedReturn) {
-        log_error("Error when parsing design. Aborting!\n");
-    }
-    return the_design;
-}
+
+  private:
+    std::unique_ptr<SURELOG::ErrorContainer> errors = nullptr;
+    std::unique_ptr<SURELOG::CommandLineParser> clp = nullptr;
+    SURELOG::scompiler *scompiler = nullptr;
+    std::vector<vpiHandle> designs = {};
+};
 
 struct UhdmSurelogAstFrontend : public UhdmCommonFrontend {
     UhdmSurelogAstFrontend(std::string name, std::string short_help) : UhdmCommonFrontend(name, short_help) {}
@@ -94,13 +131,38 @@
     AST::AstNode *parse(std::string filename) override
     {
         std::vector<const char *> cstrings;
-        cstrings.reserve(this->args.size());
-        for (size_t i = 0; i < this->args.size(); ++i)
+        bool link = false;
+        if (this->shared.formal) {
+            systemverilog_defines.push_back("-DFORMAL=1");
+        } else {
+            systemverilog_defines.push_back("-DSYNTHESIS=1");
+        }
+        cstrings.reserve(this->args.size() + systemverilog_defaults.size() + systemverilog_defines.size());
+        for (size_t i = 0; i < this->args.size(); ++i) {
             cstrings.push_back(const_cast<char *>(this->args[i].c_str()));
+            if (this->args[i] == "-link")
+                link = true;
+        }
 
-        SURELOG::SymbolTable *symbolTable = new SURELOG::SymbolTable();
-        SURELOG::ErrorContainer *errors = new SURELOG::ErrorContainer(symbolTable);
-        SURELOG::CommandLineParser *clp = new SURELOG::CommandLineParser(errors, symbolTable, false, false);
+        if (!link) {
+            // Add systemverilog defaults args
+            for (size_t i = 0; i < systemverilog_defaults.size(); ++i) {
+                // Convert args to surelog compatible
+                if (systemverilog_defaults[i] == "-defer")
+                    this->shared.defer = true;
+                // Pass any remainings args directly to surelog
+                else
+                    cstrings.push_back(const_cast<char *>(systemverilog_defaults[i].c_str()));
+            }
+
+            // Add systemverilog defines args
+            for (size_t i = 0; i < systemverilog_defines.size(); ++i)
+                cstrings.push_back(const_cast<char *>(systemverilog_defines[i].c_str()));
+        }
+
+        auto symbolTable = std::make_unique<SURELOG::SymbolTable>();
+        auto errors = std::make_unique<SURELOG::ErrorContainer>(symbolTable.get());
+        auto clp = std::make_unique<SURELOG::CommandLineParser>(errors.get(), symbolTable.get(), false, false);
         bool success = clp->parseCommandLine(cstrings.size(), &cstrings[0]);
         if (!success) {
             log_error("Error parsing Surelog arguments!\n");
@@ -122,25 +184,21 @@
             clp->setLink(true);
         }
 
-        SURELOG::scompiler *compiler = nullptr;
-        const std::vector<vpiHandle> uhdm_design = executeCompilation(symbolTable, errors, clp, compiler);
+        Compiler compiler;
+        const auto &uhdm_designs = compiler.execute(std::move(errors), std::move(clp));
+
         if (this->shared.debug_flag || !this->report_directory.empty()) {
-            for (auto design : uhdm_design) {
-                std::stringstream strstr;
-                UHDM::visit_object(design, 1, "", &this->shared.report.unhandled, this->shared.debug_flag ? std::cout : strstr);
+            for (auto design : uhdm_designs) {
+                std::ofstream null_stream;
+                UHDM::visit_object(design, 1, "", &this->shared.report.unhandled, this->shared.debug_flag ? std::cout : null_stream);
             }
         }
 
-        SURELOG::shutdown_compiler(compiler);
-        delete clp;
-        delete symbolTable;
-        delete errors;
         // on parse_only mode, don't try to load design
         // into yosys
         if (this->shared.parse_only)
             return nullptr;
 
-        UhdmAst uhdm_ast(this->shared);
         if (this->shared.defer && !this->shared.link)
             return nullptr;
 
@@ -149,16 +207,21 @@
         // Should be called 1. for normal flow 2. after finishing with `-link`
         if (!this->shared.defer) {
             UHDM::Serializer serializer;
-            UHDM::SynthSubset *synthSubset = new UHDM::SynthSubset(&serializer, this->shared.nonSynthesizableObjects, false);
-            synthSubset->listenDesigns(uhdm_design);
+            UHDM::SynthSubset *synthSubset =
+              make_new_object_with_optional_extra_true_arg<UHDM::SynthSubset>(&serializer, this->shared.nonSynthesizableObjects, false);
+            synthSubset->listenDesigns(uhdm_designs);
             delete synthSubset;
         }
 
-        AST::AstNode *current_ast = uhdm_ast.visit_designs(uhdm_design);
+        UhdmAst uhdm_ast(this->shared);
+        AST::AstNode *current_ast = uhdm_ast.visit_designs(uhdm_designs);
         if (!this->report_directory.empty()) {
             this->shared.report.write(this->report_directory);
         }
 
+        // FIXME: Check and reset remaining shared data
+        this->shared.top_nodes.clear();
+        this->shared.nonSynthesizableObjects.clear();
         return current_ast;
     }
     void call_log_header(RTLIL::Design *design) override { log_header(design, "Executing Verilog with UHDM frontend.\n"); }
@@ -175,7 +238,164 @@
         log("Read SystemVerilog files using Surelog into the current design\n");
         log("\n");
         this->print_read_options();
+        log("    -Ipath\n");
+        log("        add include path.\n");
+        log("\n");
+        log("    -Pparameter=value\n");
+        log("        define parameter as value.\n");
+        log("\n");
     }
 } UhdmSystemVerilogFrontend;
 
-YOSYS_NAMESPACE_END
+struct SystemVerilogDefaults : public Pass {
+    SystemVerilogDefaults() : Pass("systemverilog_defaults", "set default options for read_systemverilog") {}
+    void help() override
+    {
+        //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+        log("\n");
+        log("    systemverilog_defaults -add [options]\n");
+        log("\n");
+        log("Add the specified options to the list of default options to read_systemverilog.\n");
+        log("\n");
+        log("\n");
+        log("    systemverilog_defaults -clear\n");
+        log("\n");
+        log("Clear the list of Systemverilog default options.\n");
+        log("\n");
+        log("\n");
+        log("    systemverilog_defaults -push\n");
+        log("    systemverilog_defaults -pop\n");
+        log("\n");
+        log("Push or pop the list of default options to a stack. Note that -push does\n");
+        log("not imply -clear.\n");
+        log("\n");
+    }
+    void execute(std::vector<std::string> args, RTLIL::Design *) override
+    {
+        if (args.size() < 2)
+            cmd_error(args, 1, "Missing argument.");
+
+        if (args[1] == "-add") {
+            systemverilog_defaults.insert(systemverilog_defaults.end(), args.begin() + 2, args.end());
+            return;
+        }
+
+        if (args.size() != 2)
+            cmd_error(args, 2, "Extra argument.");
+
+        if (args[1] == "-clear") {
+            systemverilog_defaults.clear();
+            return;
+        }
+
+        if (args[1] == "-push") {
+            systemverilog_defaults_stack.push_back(systemverilog_defaults);
+            return;
+        }
+
+        if (args[1] == "-pop") {
+            if (systemverilog_defaults_stack.empty()) {
+                systemverilog_defaults.clear();
+            } else {
+                systemverilog_defaults.swap(systemverilog_defaults_stack.back());
+                systemverilog_defaults_stack.pop_back();
+            }
+            return;
+        }
+    }
+} SystemVerilogDefaults;
+
+struct SystemVerilogDefines : public Pass {
+    SystemVerilogDefines() : Pass("systemverilog_defines", "define and undefine systemverilog defines")
+    {
+        systemverilog_defines.push_back("-DYOSYS=1");
+    }
+    void help() override
+    {
+        //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+        log("\n");
+        log("    systemverilog_defines [options]\n");
+        log("\n");
+        log("Define and undefine systemverilog preprocessor macros.\n");
+        log("\n");
+        log("    -Dname[=definition]\n");
+        log("        define the preprocessor symbol 'name' and set its optional value\n");
+        log("        'definition'\n");
+        log("\n");
+        log("    -Uname[=definition]\n");
+        log("        undefine the preprocessor symbol 'name'\n");
+        log("\n");
+        log("    -reset\n");
+        log("        clear list of defined preprocessor symbols\n");
+        log("\n");
+        log("    -list\n");
+        log("        list currently defined preprocessor symbols\n");
+        log("\n");
+    }
+    void remove(const std::string name)
+    {
+        auto it = systemverilog_defines.begin();
+        while (it != systemverilog_defines.end()) {
+            std::string nm;
+            size_t equal = (*it).find('=', 2);
+            if (equal == std::string::npos)
+                nm = (*it).substr(2, std::string::npos);
+            else
+                nm = (*it).substr(2, equal - 2);
+            if (name == nm)
+                systemverilog_defines.erase(it);
+            else
+                it++;
+        }
+    }
+    void dump(void)
+    {
+        for (size_t i = 0; i < systemverilog_defines.size(); ++i) {
+            std::string name, value = "";
+            size_t equal = systemverilog_defines[i].find('=', 2);
+            name = systemverilog_defines[i].substr(2, equal - 2);
+            if (equal != std::string::npos)
+                value = systemverilog_defines[i].substr(equal + 1, std::string::npos);
+            Yosys::log("`define %s %s\n", name.c_str(), value.c_str());
+        }
+    }
+    void execute(std::vector<std::string> args, RTLIL::Design *design) override
+    {
+        size_t argidx;
+        for (argidx = 1; argidx < args.size(); argidx++) {
+            std::string arg = args[argidx];
+            if (arg == "-D" && argidx + 1 < args.size()) {
+                systemverilog_defines.push_back("-D" + args[++argidx]);
+                continue;
+            }
+            if (arg.compare(0, 2, "-D") == 0) {
+                systemverilog_defines.push_back(arg);
+                continue;
+            }
+            if (arg == "-U" && argidx + 1 < args.size()) {
+                std::string name = args[++argidx];
+                this->remove(name);
+                continue;
+            }
+            if (arg.compare(0, 2, "-U") == 0) {
+                std::string name = arg.substr(2);
+                this->remove(name);
+                continue;
+            }
+            if (arg == "-reset") {
+                systemverilog_defines.erase(systemverilog_defines.begin() + 1, systemverilog_defines.end());
+                continue;
+            }
+            if (arg == "-list") {
+                this->dump();
+                continue;
+            }
+            break;
+        }
+
+        if (args.size() != argidx)
+            cmd_error(args, argidx, "Extra argument.");
+    }
+} SystemVerilogDefines;
+
+} // namespace systemverilog_plugin
diff --git a/third_party/make-env b/third_party/make-env
index 59adb0f..33b80bd 160000
--- a/third_party/make-env
+++ b/third_party/make-env
@@ -1 +1 @@
-Subproject commit 59adb0f248cc4a5d764b6b06224bf6adea7fa36e
+Subproject commit 33b80bd32c30fb8affd0fd5cda544d1bca075593
diff --git a/uhdm-plugin/Makefile b/uhdm-plugin/Makefile
index 3eea3d4..4f67830 100644
--- a/uhdm-plugin/Makefile
+++ b/uhdm-plugin/Makefile
@@ -14,6 +14,8 @@
 #
 # SPDX-License-Identifier: Apache-2.0
 
+PLUGIN_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
+
 NAME = uhdm
 SOURCES = uhdm.cc
 include ../Makefile_plugin.common
diff --git a/xdc-plugin/Makefile b/xdc-plugin/Makefile
index 06d61d7..b2ebd88 100644
--- a/xdc-plugin/Makefile
+++ b/xdc-plugin/Makefile
@@ -14,12 +14,14 @@
 #
 # SPDX-License-Identifier: Apache-2.0
 
+PLUGIN_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
+
 NAME = xdc
 SOURCES = xdc.cc
 include ../Makefile_plugin.common
 VERILOG_MODULES = BANK.v
 
 install_modules: $(VERILOG_MODULES)
-	install -D $< $(PLUGINS_DIR)/fasm_extra_modules/$<
+	install -D $< $(YOSYS_PLUGINS_DIR)/fasm_extra_modules/$<
 
 install: install_modules