)]}'
{
  "commit": "6bc9630fb7fb7527cadbb696eacbb17a6d4dc347",
  "tree": "eecd71c8c2cc5d071677bf79e62bb5d57759ba1a",
  "parents": [
    "75df29e1c68353d9c9b5b3db7f4748e057d3d6a1",
    "1fa23bca9060f265a405cce9c3a94cee6c37a4fd"
  ],
  "author": {
    "name": "Rafal Kapuscik",
    "email": "54976862+rkapuscik@users.noreply.github.com",
    "time": "Thu Jun 30 08:41:38 2022 +0200"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Thu Jun 30 08:41:38 2022 +0200"
  },
  "message": "Merge pull request #359 from antmicro/shift-unsigned\n\nSystemVerilog: Fix children handling in shift operations",
  "tree_diff": []
}