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parent 75df29e1c68353d9c9b5b3db7f4748e057d3d6a1
parent 1fa23bca9060f265a405cce9c3a94cee6c37a4fd
author Rafal Kapuscik <54976862+rkapuscik@users.noreply.github.com> 1656571298 +0200
committer GitHub <noreply@github.com> 1656571298 +0200
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Merge pull request #359 from antmicro/shift-unsigned

SystemVerilog: Fix children handling in shift operations