commit 6dc5a76eb36f96a1079a1203f96dce8aa9502c73
author Kamil Rakoczy <krakoczy@antmicro.com> Fri Apr 15 14:22:38 2022 +0200
committer GitHub <noreply@github.com> Fri Apr 15 14:22:38 2022 +0200
tree 26d18443f2e71d8b66f4708617aecb289df875c9
parent ff70a90fc36cc968618c5b47f7ba4f322af9b71e
parent a4e48ee88d1c5d2a69cc5d97caccff0d67223106

Merge pull request #301 from antmicro/abort-surelog-error

systemverilog: abort execution when Surelog report error in design

systemverilog-plugin/uhdmsurelogastfrontend.cc

diff --git a/systemverilog-plugin/uhdmsurelogastfrontend.cc b/systemverilog-plugin/uhdmsurelogastfrontend.cc
index 82f04e4..1f8472a 100644
--- a/systemverilog-plugin/uhdmsurelogastfrontend.cc
+++ b/systemverilog-plugin/uhdmsurelogastfrontend.cc
@@ -70,10 +70,10 @@
     if (noFErrors == false) {
         noFatalErrors = false;
     }
-    if ((!noFatalErrors) || (!success))
+    if ((!noFatalErrors) || (!success) || (errors->getErrorStats().nbError))
         codedReturn |= 1;
     if (codedReturn) {
-        log_error("Encoraged fatal error when executing Surelog. Aborting!\n");
+        log_error("Error when parsing design. Aborting!\n");
     }
     return the_design;
 }