commit 6e344d20e763bc692b7800842e49e06120ce92be
author Lalit Narain Sharma <lnsharma@github.com> Mon Jul 26 18:21:06 2021 +0530
committer Lalit Narain Sharma <lnsharma@github.com> Mon Jul 26 18:22:04 2021 +0530
tree bc00c1a95aacd03b45147c645c3fced1b27f6577
parent 5d91d446535d0ae349fbdb49a6a2867c9f7f41ef

Rectifying the port name as 'a' instead of 'A' for logic_0 and logic_1 for pp3 device family

Signed-off-by: Lalit Narain Sharma <lnsharma@github.com>

ql-qlf-plugin/pp3/pp3_cells_sim.v

diff --git a/ql-qlf-plugin/pp3/pp3_cells_sim.v b/ql-qlf-plugin/pp3/pp3_cells_sim.v
index 4155744..4c06215 100644
--- a/ql-qlf-plugin/pp3/pp3_cells_sim.v
+++ b/ql-qlf-plugin/pp3/pp3_cells_sim.v
@@ -21,15 +21,15 @@
 endmodule
 
 module logic_0 (
-    output A
+    output a
 );
-  assign A = 0;
+  assign a = 0;
 endmodule
 
 module logic_1 (
-    output A
+    output a
 );
-  assign A = 1;
+  assign a = 1;
 endmodule
 
 module gclkbuff (

ql-qlf-plugin/synth_quicklogic.cc

diff --git a/ql-qlf-plugin/synth_quicklogic.cc b/ql-qlf-plugin/synth_quicklogic.cc
index 5b31cee..be59c33 100644
--- a/ql-qlf-plugin/synth_quicklogic.cc
+++ b/ql-qlf-plugin/synth_quicklogic.cc
@@ -358,7 +358,7 @@
                 run("setundef -zero -params -undriven");
             }
             if (family == "pp3" || (check_label("edif") && (!edif_file.empty()))) {
-                run("hilomap -hicell logic_1 A -locell logic_0 A -singleton A:top");
+                run("hilomap -hicell logic_1 a -locell logic_0 a -singleton A:top");
             }
             run("opt_clean -purge");
             run("check");