commit 70cedb5f99b4eb21929e48e4dc7ae55bb3bca758
author Magdalena Andrys <mandrys@antmicro.com> Wed Nov 02 10:36:45 2022 +0000
committer Magdalena Andrys <mandrys@antmicro.com> Wed Nov 02 14:48:14 2022 +0000
tree 72c11c6184500225997e6aab21f151a1f3d69a11
parent c8f377ff7e19c59921657cbb9bcbabc3e987cf10

process_assignment: Use define for op type in case of simple assignment

systemverilog-plugin/UhdmAst.cc

diff --git a/systemverilog-plugin/UhdmAst.cc b/systemverilog-plugin/UhdmAst.cc
index 1ca30eb..d4c0b6b 100644
--- a/systemverilog-plugin/UhdmAst.cc
+++ b/systemverilog-plugin/UhdmAst.cc
@@ -2271,7 +2271,7 @@
     AST::AstNodeType node_type;
     current_node = make_ast_node(type);
 
-    if (op_type && op_type != 82) {
+    if (op_type && op_type != vpiAssignmentOp) {
         simple_assign = false;
         visit_one_to_one({vpiLhs}, obj_h, [&](AST::AstNode *node) {
             if (node) {