)]}'
{
  "commit": "72e2bffb73eda27093cac2b7ccfe78a702bd0896",
  "tree": "55320382f8a2322f60ec6d14ffc77ff959e14e3f",
  "parents": [
    "74059fa3ad0e1555173d5b820604b5825a50f3f2"
  ],
  "author": {
    "name": "Mariusz Glebocki",
    "email": "mglebocki@antmicro.com",
    "time": "Tue Aug 01 22:54:54 2023 +0200"
  },
  "committer": {
    "name": "Mariusz Glebocki",
    "email": "mglebocki@antmicro.com",
    "time": "Tue Aug 08 17:19:49 2023 +0200"
  },
  "message": "Use full function name when function is from another package.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "ae1de1b954d39539ccb0a4d9b5876702d1173bb0",
      "old_mode": 33188,
      "old_path": "systemverilog-plugin/UhdmAst.cc",
      "new_id": "0be44d71557e864b90174e3842c01f5bc14c2afa",
      "new_mode": 33188,
      "new_path": "systemverilog-plugin/UhdmAst.cc"
    }
  ]
}