systemverilog-plugin: update comment
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
diff --git a/systemverilog-plugin/UhdmAst.cc b/systemverilog-plugin/UhdmAst.cc
index 236fe7c..425c8dc 100644
--- a/systemverilog-plugin/UhdmAst.cc
+++ b/systemverilog-plugin/UhdmAst.cc
@@ -439,9 +439,15 @@
// mem <= '{default:0};
// mem[7:1] <= mem[6:0];
// end
+ // don't convert in case of accessing
+ // memory using address, e.g.
+ // mem[0] <= '{default:0}
+ //
+ // Access to whole memory
if (node->children.size() == 0) {
force_convert = true;
}
+ // Access to slice of memory
if (node->children.size() == 1 && node->children[0]->children.size() != 1) {
force_convert = true;
}
