SDC: Update tests after input clock phase shift fix
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
diff --git a/sdc-plugin/tests/Makefile b/sdc-plugin/tests/Makefile
index 68c3e45..b352043 100644
--- a/sdc-plugin/tests/Makefile
+++ b/sdc-plugin/tests/Makefile
@@ -1,9 +1,10 @@
-TESTS = counter counter2 pll
+TESTS = counter counter2 pll pll_div
.PHONY: $(TESTS)
counter_verify = $(call compare,counter,sdc) && $(call compare,counter,txt)
counter2_verify = $(call compare,counter2,sdc) && $(call compare,counter2,txt)
pll_verify = $(call compare,pll,sdc)
+pll_div_verify = $(call compare,pll_div,sdc)
all: $(TESTS)
compare = diff $(1)/$(1).golden.$(2) $(1)/$(1).$(2)
diff --git a/sdc-plugin/tests/counter/counter.golden.sdc b/sdc-plugin/tests/counter/counter.golden.sdc
index a70e95d..c1a2ea1 100644
--- a/sdc-plugin/tests/counter/counter.golden.sdc
+++ b/sdc-plugin/tests/counter/counter.golden.sdc
@@ -2,5 +2,5 @@
create_clock -period 10 -waveform {0 5} ibuf_proxy_out
create_clock -period 10 -waveform {0 5} \$auto\$clkbufmap.cc:247:execute\$1918
create_clock -period 10 -waveform {0 5} \$auto\$clkbufmap.cc:247:execute\$1920
-create_clock -period 10 -waveform {1 6} middle_inst_1.clk_int
-create_clock -period 10 -waveform {1 6} middle_inst_4.clk
+create_clock -period 10 -waveform {0 5} middle_inst_1.clk_int
+create_clock -period 10 -waveform {0 5} middle_inst_4.clk
diff --git a/sdc-plugin/tests/counter2/counter2.golden.sdc b/sdc-plugin/tests/counter2/counter2.golden.sdc
index b3e8cca..4bf0bf2 100644
--- a/sdc-plugin/tests/counter2/counter2.golden.sdc
+++ b/sdc-plugin/tests/counter2/counter2.golden.sdc
@@ -2,5 +2,5 @@
create_clock -period 10 -waveform {0 5} ibuf_proxy_out
create_clock -period 10 -waveform {0 5} \$auto\$clkbufmap.cc:247:execute\$1918
create_clock -period 10 -waveform {1 6} \$auto\$clkbufmap.cc:247:execute\$1920
-create_clock -period 10 -waveform {1 6} middle_inst_1.clk_int
-create_clock -period 10 -waveform {2 7} middle_inst_4.clk
+create_clock -period 10 -waveform {0 5} middle_inst_1.clk_int
+create_clock -period 10 -waveform {1 6} middle_inst_4.clk
diff --git a/sdc-plugin/tests/pll/pll.golden.sdc b/sdc-plugin/tests/pll/pll.golden.sdc
index 8f82a93..7fe2b2a 100644
--- a/sdc-plugin/tests/pll/pll.golden.sdc
+++ b/sdc-plugin/tests/pll/pll.golden.sdc
@@ -1,6 +1,8 @@
-create_clock -period 10 -waveform {0 5} \$auto\$clkbufmap.cc:247:execute\$1827
-create_clock -period 10 -waveform {1 6} \$techmap1716\FDCE_0.C
-create_clock -period 10 -waveform {3.5 8.5} \$auto\$clkbufmap.cc:247:execute\$1829
-create_clock -period 10 -waveform {4.5 9.5} main_clkout0
-create_clock -period 5 -waveform {1 3.5} \$auto\$clkbufmap.cc:247:execute\$1831
-create_clock -period 5 -waveform {2 4.5} main_clkout1
+create_clock -period 10 -waveform {0 5} \$auto\$clkbufmap.cc:247:execute\$1829
+create_clock -period 10 -waveform {0 5} \$techmap1716\FDCE_0.C
+create_clock -period 10 -waveform {2.5 7.5} \$auto\$clkbufmap.cc:247:execute\$1831
+create_clock -period 10 -waveform {2.5 7.5} main_clkout0
+create_clock -period 2.5 -waveform {0 1.25} \$auto\$clkbufmap.cc:247:execute\$1833
+create_clock -period 2.5 -waveform {0 1.25} main_clkout1
+create_clock -period 5 -waveform {1.25 3.75} \$auto\$clkbufmap.cc:247:execute\$1835
+create_clock -period 5 -waveform {1.25 3.75} main_clkout2
diff --git a/sdc-plugin/tests/pll/pll.v b/sdc-plugin/tests/pll/pll.v
index 64b9750..63542da 100644
--- a/sdc-plugin/tests/pll/pll.v
+++ b/sdc-plugin/tests/pll/pll.v
@@ -2,10 +2,10 @@
input clk,
input cpu_reset,
input data_in,
- output[4:0] data_out
+ output[5:0] data_out
);
-wire [4:0] data_out;
+wire [5:0] data_out;
wire builder_pll_fb;
wire fdce_0_out, fdce_1_out;
wire main_locked;
@@ -31,8 +31,10 @@
.CLKIN1_PERIOD(10.0),
.CLKOUT0_DIVIDE(4'd12),
.CLKOUT0_PHASE(90.0),
- .CLKOUT1_DIVIDE(3'd6),
+ .CLKOUT1_DIVIDE(2'd3),
.CLKOUT1_PHASE(0.0),
+ .CLKOUT2_DIVIDE(3'd6),
+ .CLKOUT2_PHASE(90.0),
.DIVCLK_DIVIDE(1'd1),
.REF_JITTER1(0.01),
.STARTUP_WAIT("FALSE")
@@ -43,10 +45,11 @@
.CLKFBOUT(builder_pll_fb),
.CLKOUT0(main_clkout0),
.CLKOUT1(main_clkout1),
+ .CLKOUT2(main_clkout2),
.LOCKED(main_locked)
);
-FDCE FDCE_PLLx1 (
+FDCE FDCE_PLLx1_PH90 (
.D(data_in),
.C(main_clkout0),
.CE(1'b1),
@@ -54,7 +57,7 @@
.Q(data_out[1])
);
-FDCE FDCE_PLLx4_0 (
+FDCE FDCE_PLLx4_PH0_0 (
.D(data_in),
.C(main_clkout1),
.CE(1'b1),
@@ -62,7 +65,7 @@
.Q(data_out[2])
);
-FDCE FDCE_PLLx4_1 (
+FDCE FDCE_PLLx4_PH0_1 (
.D(data_in),
.C(main_clkout1),
.CE(1'b1),
@@ -70,11 +73,19 @@
.Q(data_out[3])
);
-FDCE FDCE_PLLx4_2 (
+FDCE FDCE_PLLx4_PH0_2 (
.D(data_in),
.C(main_clkout1),
.CE(1'b1),
.CLR(1'b0),
.Q(data_out[4])
);
+
+FDCE FDCE_PLLx2_PH90_0 (
+ .D(data_in),
+ .C(main_clkout2),
+ .CE(1'b1),
+ .CLR(1'b0),
+ .Q(data_out[5])
+);
endmodule
diff --git a/sdc-plugin/tests/pll_div/pll_div.golden.sdc b/sdc-plugin/tests/pll_div/pll_div.golden.sdc
new file mode 100644
index 0000000..14ea0bc
--- /dev/null
+++ b/sdc-plugin/tests/pll_div/pll_div.golden.sdc
@@ -0,0 +1,8 @@
+create_clock -period 10 -waveform {0 5} \$auto\$clkbufmap.cc:247:execute\$1829
+create_clock -period 10 -waveform {0 5} \$techmap1716\FDCE_0.C
+create_clock -period 20 -waveform {5 15} \$auto\$clkbufmap.cc:247:execute\$1831
+create_clock -period 20 -waveform {5 15} main_clkout0
+create_clock -period 5 -waveform {0 2.5} \$auto\$clkbufmap.cc:247:execute\$1833
+create_clock -period 5 -waveform {0 2.5} main_clkout1
+create_clock -period 10 -waveform {2.5 7.5} \$auto\$clkbufmap.cc:247:execute\$1835
+create_clock -period 10 -waveform {2.5 7.5} main_clkout2
diff --git a/sdc-plugin/tests/pll_div/pll_div.input.sdc b/sdc-plugin/tests/pll_div/pll_div.input.sdc
new file mode 100644
index 0000000..00354d7
--- /dev/null
+++ b/sdc-plugin/tests/pll_div/pll_div.input.sdc
@@ -0,0 +1 @@
+create_clock -period 10 -waveform {0 5} clk
diff --git a/sdc-plugin/tests/pll_div/pll_div.tcl b/sdc-plugin/tests/pll_div/pll_div.tcl
new file mode 100644
index 0000000..f8f0a9f
--- /dev/null
+++ b/sdc-plugin/tests/pll_div/pll_div.tcl
@@ -0,0 +1,21 @@
+yosys -import
+plugin -i sdc
+# Import the commands from the plugins to the tcl interpreter
+yosys -import
+
+read_verilog pll_div.v
+read_verilog -specify -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v
+read_verilog -lib +/xilinx/cells_xtra.v
+hierarchy -check -auto-top
+
+# Start flow after library reading
+synth_xilinx -vpr -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check
+
+# Read the design timing constraints
+read_sdc $::env(INPUT_SDC_FILE)
+
+# Propagate the clocks
+propagate_clocks
+
+# Write out the SDC file after the clock propagation step
+write_sdc $::env(OUTPUT_SDC_FILE)
diff --git a/sdc-plugin/tests/pll_div/pll_div.v b/sdc-plugin/tests/pll_div/pll_div.v
new file mode 100644
index 0000000..b4055ef
--- /dev/null
+++ b/sdc-plugin/tests/pll_div/pll_div.v
@@ -0,0 +1,91 @@
+module top(
+ input clk,
+ input cpu_reset,
+ input data_in,
+ output[5:0] data_out
+);
+
+wire [5:0] data_out;
+wire builder_pll_fb;
+wire fdce_0_out, fdce_1_out;
+wire main_locked;
+
+FDCE FDCE_0 (
+ .D(data_in),
+ .C(clk),
+ .CE(1'b1),
+ .CLR(1'b0),
+ .Q(fdce_0_out)
+);
+
+FDCE FDCE_1 (
+ .D(fdce_0_out),
+ .C(clk),
+ .CE(1'b1),
+ .CLR(1'b0),
+ .Q(data_out[0])
+);
+
+PLLE2_ADV #(
+ .CLKFBOUT_MULT(4'd12),
+ .CLKIN1_PERIOD(10.0),
+ .CLKOUT0_DIVIDE(4'd12),
+ .CLKOUT0_PHASE(90.0),
+ .CLKOUT1_DIVIDE(2'd3),
+ .CLKOUT1_PHASE(0.0),
+ .CLKOUT2_DIVIDE(3'd6),
+ .CLKOUT2_PHASE(90.0),
+ .DIVCLK_DIVIDE(2'd2),
+ .REF_JITTER1(0.01),
+ .STARTUP_WAIT("FALSE")
+) PLLE2_ADV (
+ .CLKFBIN(builder_pll_fb),
+ .CLKIN1(clk),
+ .RST(cpu_reset),
+ .CLKFBOUT(builder_pll_fb),
+ .CLKOUT0(main_clkout0),
+ .CLKOUT1(main_clkout1),
+ .CLKOUT2(main_clkout2),
+ .LOCKED(main_locked)
+);
+
+FDCE FDCE_PLLx1_PH90 (
+ .D(data_in),
+ .C(main_clkout0),
+ .CE(1'b1),
+ .CLR(1'b0),
+ .Q(data_out[1])
+);
+
+FDCE FDCE_PLLx4_PH0_0 (
+ .D(data_in),
+ .C(main_clkout1),
+ .CE(1'b1),
+ .CLR(1'b0),
+ .Q(data_out[2])
+);
+
+FDCE FDCE_PLLx4_PH0_1 (
+ .D(data_in),
+ .C(main_clkout1),
+ .CE(1'b1),
+ .CLR(1'b0),
+ .Q(data_out[3])
+);
+
+FDCE FDCE_PLLx4_PH0_2 (
+ .D(data_in),
+ .C(main_clkout1),
+ .CE(1'b1),
+ .CLR(1'b0),
+ .Q(data_out[4])
+);
+
+FDCE FDCE_PLLx2_PH90_0 (
+ .D(data_in),
+ .C(main_clkout2),
+ .CE(1'b1),
+ .CLR(1'b0),
+ .Q(data_out[5])
+);
+endmodule
