diff --git a/systemverilog-plugin/UhdmAst.cc b/systemverilog-plugin/UhdmAst.cc
index 8f76bdc..ae1de1b 100644
--- a/systemverilog-plugin/UhdmAst.cc
+++ b/systemverilog-plugin/UhdmAst.cc
@@ -2214,7 +2214,13 @@
             });
         }
     } else {
-        // Not a top module, create instance
+        // A module instance inside another uhdmTopModules' module.
+        // Create standalone module instance AST and embed it in the instantiating module using AST_CELL.
+
+        const uhdm_handle *const handle = (const uhdm_handle *)obj_h;
+        const auto *const uhdm_obj = (const UHDM::any *)handle->object;
+        const auto current_instance_changer = ScopedValueChanger(shared.current_instance, uhdm_obj);
+
         current_node = make_ast_node(AST::AST_CELL);
         std::vector<std::pair<RTLIL::IdString, RTLIL::Const>> parameters;
 
@@ -2536,7 +2542,6 @@
 {
     log_assert(expr);
     log_assert(inst);
-    log_assert(pexpr);
 
     bool invalidvalue = false;
     UHDM::ExprEval eval;
@@ -2615,13 +2620,17 @@
 
             if (leftrange_obj->UhdmType() == UHDM::uhdmoperation) {
                 // Substitute the previous leftrange with the resolved operation result.
-                range_obj->Left_expr(reduce_expression(leftrange_obj, enum_object->Instance() ? enum_object->Instance() : enum_object->VpiParent(),
-                                                       enum_object->VpiParent()));
+                const UHDM::any *const instance =
+                  enum_object->Instance() ? enum_object->Instance() : enum_object->VpiParent() ? enum_object->VpiParent() : shared.current_instance;
+
+                range_obj->Left_expr(reduce_expression(leftrange_obj, instance, enum_object->VpiParent()));
             }
             if (rightrange_obj->UhdmType() == UHDM::uhdmoperation) {
                 // Substitute the previous rightrange with the resolved operation result.
-                range_obj->Right_expr(reduce_expression(rightrange_obj, enum_object->Instance() ? enum_object->Instance() : enum_object->VpiParent(),
-                                                        enum_object->VpiParent()));
+                const UHDM::any *const instance =
+                  enum_object->Instance() ? enum_object->Instance() : enum_object->VpiParent() ? enum_object->VpiParent() : shared.current_instance;
+
+                range_obj->Right_expr(reduce_expression(rightrange_obj, instance, enum_object->VpiParent()));
             }
         }
     }
diff --git a/systemverilog-plugin/uhdmastshared.h b/systemverilog-plugin/uhdmastshared.h
index bfa23d9..ef4ea04 100644
--- a/systemverilog-plugin/uhdmastshared.h
+++ b/systemverilog-plugin/uhdmastshared.h
@@ -88,6 +88,10 @@
 
     ::Yosys::AST::AstNode *current_top_node = nullptr;
 
+    // Currently processed UHDM module instance.
+    // Used as a fallback when obj->Instance() and obj->vpiParent() are not available.
+    const UHDM::any *current_instance = nullptr;
+
     // Set of non-synthesizable objects to skip in current design;
     std::set<const UHDM::BaseClass *> nonSynthesizableObjects;