)]}'
{
  "commit": "77fb7b17d96d9d5b1fcfb96711f4787cbf26bc4a",
  "tree": "fafcb3ec592241d08c94fdd9465ffdf6d04abe0d",
  "parents": [
    "aa128169490fdb3597ee0b03d9a12fd50a2f18e6",
    "8d56ddfe11a1c51de3c8f0c32578028f6db97a85"
  ],
  "author": {
    "name": "Rafal Kapuscik",
    "email": "54976862+rkapuscik@users.noreply.github.com",
    "time": "Tue Dec 13 08:07:38 2022 +0100"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Tue Dec 13 08:07:38 2022 +0100"
  },
  "message": "Merge pull request #417 from antmicro/rk/defaults-defines\n\nAdd systemverilog_defines, systemverilog_defaults",
  "tree_diff": []
}