)]}'
{
  "commit": "79d291d824a84bafe73818debaf5ba51e679edec",
  "tree": "6cb2b4fec185dcbc832fc5f441b1e928b502f6be",
  "parents": [
    "a20c6a96d9fd4b8989940a6608501784e02e78b1"
  ],
  "author": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Tue Feb 07 09:42:47 2023 +0100"
  },
  "committer": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Tue Feb 07 09:42:47 2023 +0100"
  },
  "message": "systemverilog-plugin: add support for case type\n\nSigned-off-by: Kamil Rakoczy \u003ckrakoczy@antmicro.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "3c2ae3ed82ce2f18371efffd4a4d5de350575e81",
      "old_mode": 33188,
      "old_path": "systemverilog-plugin/UhdmAst.cc",
      "new_id": "0a6f6c9d24ddc26b1be37b2ed4dfc5b888498d14",
      "new_mode": 33188,
      "new_path": "systemverilog-plugin/UhdmAst.cc"
    }
  ]
}