)]}'
{
  "commit": "7a01a4d1516bc281fbb790fd68837aaeaf660de3",
  "tree": "a1ce0f4f6b7922083539d34cd1faae383fbe8579",
  "parents": [
    "45781feffd33b87b6c111728eb0456749a218888",
    "b9c98a1d48905eb7d920971c60055088ee26eb12"
  ],
  "author": {
    "name": "Magdalena Andrys",
    "email": "55838283+mandrys@users.noreply.github.com",
    "time": "Fri Jan 13 12:05:48 2023 +0100"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Fri Jan 13 12:05:48 2023 +0100"
  },
  "message": "Merge pull request #435 from antmicro/signed-wire\n\nsystemverilog: Fix signed wire handling",
  "tree_diff": []
}