tree a1ce0f4f6b7922083539d34cd1faae383fbe8579
parent 45781feffd33b87b6c111728eb0456749a218888
parent b9c98a1d48905eb7d920971c60055088ee26eb12
author Magdalena Andrys <55838283+mandrys@users.noreply.github.com> 1673607948 +0100
committer GitHub <noreply@github.com> 1673607948 +0100
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Merge pull request #435 from antmicro/signed-wire

systemverilog: Fix signed wire handling