)]}'
{
  "commit": "7c89a55eb20efa4184fefa5c0bd1096d311a6ded",
  "tree": "d1a0be84bbd31538037ab8a4ed147545c6c3be66",
  "parents": [
    "9be2ac0cbca978d45e87fb9224ded236890a2f3d",
    "129ba8064e9e2dd5301cbab40e7c74ab8daf3fb6"
  ],
  "author": {
    "name": "Henner Zeller",
    "email": "h.zeller@acm.org",
    "time": "Thu Sep 07 11:17:05 2023 -0700"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Thu Sep 07 11:17:05 2023 -0700"
  },
  "message": "Merge pull request #546 from chipsalliance/remove-sv-plugin\n\nRemove the SystemVerilog plugin",
  "tree_diff": []
}