diff --git a/params-plugin/params.cc b/params-plugin/params.cc
index a386e1f..c4f169b 100644
--- a/params-plugin/params.cc
+++ b/params-plugin/params.cc
@@ -51,30 +51,30 @@
 		if (args.size() == 1) {
 			log_error("Incorrect number of arguments");
 		}
+		extra_args(args, 2, design);
 
 		auto param = RTLIL::IdString(RTLIL::escape_id(args.at(1)));
-		std::string value;
-		extra_args(args, 2, design);
+		Tcl_Interp *interp = yosys_get_tcl_interp();
+		Tcl_Obj* tcl_list = Tcl_NewListObj(0, NULL);
 
 		for (auto module : design->selected_modules()) {
 			for (auto cell : module->selected_cells()) {
 				auto params = cell->parameters;
 				auto it = params.find(param);
 				if (it != params.end()) {
+					std::string value;
 					auto param_obj = it->second;
 					if (param_obj.flags & RTLIL::CONST_FLAG_STRING) {
 						value = param_obj.decode_string();
 					} else {
 						value = std::to_string(param_obj.as_int());
 					}
+					Tcl_Obj* value_obj = Tcl_NewStringObj(value.c_str(), value.size());
+					Tcl_ListObjAppendElement(interp, tcl_list, value_obj);
 				}
 			}
 		}
-
-		char* tcl_param = Tcl_Alloc(value.size() + 1);
-		strcpy(tcl_param, value.c_str());
-		Tcl_Interp *interp = yosys_get_tcl_interp();
-		Tcl_SetResult(interp, tcl_param, TCL_DYNAMIC);
+		Tcl_SetObjResult(interp, tcl_list);
 	}
 
 } GetParam;
diff --git a/params-plugin/tests/pll/pll.golden.json b/params-plugin/tests/pll/pll.golden.json
index e3bf97d..bdc478e 100644
--- a/params-plugin/tests/pll/pll.golden.json
+++ b/params-plugin/tests/pll/pll.golden.json
@@ -61,5 +61,68 @@
     "TABLE": "1111110100",
     "ZINV_PWRDWN": "1",
     "ZINV_RST": "0"
+  },
+  "PLLE2_ADV_0": {
+    "CLKFBOUT_CLKOUT1_HIGH_TIME": "000110",
+    "CLKFBOUT_CLKOUT1_LOW_TIME": "000110",
+    "CLKFBOUT_CLKOUT1_OUTPUT_ENABLE": "1",
+    "CLKFBOUT_CLKOUT1_PHASE_MUX": "000",
+    "CLKFBOUT_CLKOUT2_DELAY_TIME": "000000",
+    "CLKFBOUT_CLKOUT2_EDGE": "0",
+    "CLKFBOUT_CLKOUT2_NO_COUNT": "0",
+    "CLKOUT0_CLKOUT1_HIGH_TIME": "001010",
+    "CLKOUT0_CLKOUT1_LOW_TIME": "001010",
+    "CLKOUT0_CLKOUT1_OUTPUT_ENABLE": "1",
+    "CLKOUT0_CLKOUT1_PHASE_MUX": "000",
+    "CLKOUT0_CLKOUT2_DELAY_TIME": "000000",
+    "CLKOUT0_CLKOUT2_EDGE": "0",
+    "CLKOUT0_CLKOUT2_NO_COUNT": "0",
+    "CLKOUT1_CLKOUT1_HIGH_TIME": "000010",
+    "CLKOUT1_CLKOUT1_LOW_TIME": "000011",
+    "CLKOUT1_CLKOUT1_OUTPUT_ENABLE": "1",
+    "CLKOUT1_CLKOUT1_PHASE_MUX": "000",
+    "CLKOUT1_CLKOUT2_DELAY_TIME": "000000",
+    "CLKOUT1_CLKOUT2_EDGE": "1",
+    "CLKOUT1_CLKOUT2_NO_COUNT": "0",
+    "CLKOUT2_CLKOUT1_HIGH_TIME": "000010",
+    "CLKOUT2_CLKOUT1_LOW_TIME": "000011",
+    "CLKOUT2_CLKOUT1_OUTPUT_ENABLE": "0",
+    "CLKOUT2_CLKOUT1_PHASE_MUX": "000",
+    "CLKOUT2_CLKOUT2_DELAY_TIME": "000000",
+    "CLKOUT2_CLKOUT2_EDGE": "1",
+    "CLKOUT2_CLKOUT2_NO_COUNT": "0",
+    "CLKOUT3_CLKOUT1_HIGH_TIME": "000011",
+    "CLKOUT3_CLKOUT1_LOW_TIME": "000011",
+    "CLKOUT3_CLKOUT1_OUTPUT_ENABLE": "0",
+    "CLKOUT3_CLKOUT1_PHASE_MUX": "000",
+    "CLKOUT3_CLKOUT2_DELAY_TIME": "000000",
+    "CLKOUT3_CLKOUT2_EDGE": "0",
+    "CLKOUT3_CLKOUT2_NO_COUNT": "0",
+    "CLKOUT4_CLKOUT1_HIGH_TIME": "000001",
+    "CLKOUT4_CLKOUT1_LOW_TIME": "000001",
+    "CLKOUT4_CLKOUT1_OUTPUT_ENABLE": "0",
+    "CLKOUT4_CLKOUT1_PHASE_MUX": "000",
+    "CLKOUT4_CLKOUT2_DELAY_TIME": "000000",
+    "CLKOUT4_CLKOUT2_EDGE": "0",
+    "CLKOUT4_CLKOUT2_NO_COUNT": "1",
+    "CLKOUT5_CLKOUT1_HIGH_TIME": "000001",
+    "CLKOUT5_CLKOUT1_LOW_TIME": "000001",
+    "CLKOUT5_CLKOUT1_OUTPUT_ENABLE": "0",
+    "CLKOUT5_CLKOUT1_PHASE_MUX": "000",
+    "CLKOUT5_CLKOUT2_DELAY_TIME": "000000",
+    "CLKOUT5_CLKOUT2_EDGE": "0",
+    "CLKOUT5_CLKOUT2_NO_COUNT": "1",
+    "DIVCLK_DIVCLK_EDGE": "0",
+    "DIVCLK_DIVCLK_HIGH_TIME": "000001",
+    "DIVCLK_DIVCLK_LOW_TIME": "000001",
+    "DIVCLK_DIVCLK_NO_COUNT": "1",
+    "FILTREG1_RESERVED": "000000001000",
+    "INV_CLKINSEL": "0",
+    "LKTABLE": "1111111111110011100111111010010000000001",
+    "LOCKREG3_RESERVED": "1",
+    "STARTUP_WAIT": "0",
+    "TABLE": "1111110100",
+    "ZINV_PWRDWN": "1",
+    "ZINV_RST": "0"
   }
 }
\ No newline at end of file
diff --git a/params-plugin/tests/pll/pll.tcl b/params-plugin/tests/pll/pll.tcl
index 0396236..3072cde 100644
--- a/params-plugin/tests/pll/pll.tcl
+++ b/params-plugin/tests/pll/pll.tcl
@@ -7,10 +7,11 @@
 read_verilog -specify -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v
 read_verilog -lib +/xilinx/cells_xtra.v
 hierarchy -check -auto-top
-set phase [getparam CLKOUT2_PHASE top/PLLE2_ADV]
+set phase [getparam CLKOUT2_PHASE top/PLLE2_ADV_0 top/PLLE2_ADV]
 puts "Phase before: $phase"
-setparam -set CLKOUT2_PHASE [expr $phase * 1000] top/PLLE2_ADV
-puts "Phase after: [getparam CLKOUT2_PHASE top/PLLE2_ADV]"
+setparam -set CLKOUT2_PHASE [expr [lindex $phase 0] * 1000] top/PLLE2_ADV
+puts "Phase after: [getparam CLKOUT2_PHASE top/PLLE2_ADV_0 top/PLLE2_ADV]"
+
 # Start flow after library reading
 synth_xilinx -vpr -flatten -abc9 -nosrl -noclkbuf -nodsp -iopad -run prepare:check
 
diff --git a/params-plugin/tests/pll/pll.v b/params-plugin/tests/pll/pll.v
index a1eeb38..b6ddcea 100644
--- a/params-plugin/tests/pll/pll.v
+++ b/params-plugin/tests/pll/pll.v
@@ -19,6 +19,29 @@
 	.CLKOUT1_DIVIDE(3'd5),
 	.CLKOUT1_PHASE(1'd0),
 	.CLKOUT2_DIVIDE(3'd5),
+	.CLKOUT2_PHASE(7'd70),
+	.CLKOUT3_DIVIDE(3'd6),
+	.CLKOUT3_PHASE(1'd0),
+	.DIVCLK_DIVIDE(1'd1),
+	.REF_JITTER1(0.01),
+	.STARTUP_WAIT("FALSE")
+) PLLE2_ADV_0 (
+	.CLKFBIN(builder_pll_fb),
+	.CLKIN1(clk100),
+	.RST(cpu_reset),
+	.CLKFBOUT(builder_pll_fb),
+	.CLKOUT0(main_clkout0),
+	.CLKOUT1(main_clkout1),
+	.LOCKED(main_locked)
+);
+PLLE2_ADV #(
+	.CLKFBOUT_MULT(4'd12),
+	.CLKIN1_PERIOD(10.0),
+	.CLKOUT0_DIVIDE(5'd20),
+	.CLKOUT0_PHASE(1'd0),
+	.CLKOUT1_DIVIDE(3'd5),
+	.CLKOUT1_PHASE(1'd0),
+	.CLKOUT2_DIVIDE(3'd5),
 	.CLKOUT2_PHASE(7'd90),
 	.CLKOUT3_DIVIDE(3'd6),
 	.CLKOUT3_PHASE(1'd0),