)]}'
{
  "commit": "7d274244e5f1b98ab440be1a74c2ec8b81a9bdb4",
  "tree": "ff5fd6bc744b034a03802b4a9f15066e48d79581",
  "parents": [
    "d852e75feff795ce4de9e207ff08055cbc0212c3"
  ],
  "author": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Mon May 15 16:50:56 2023 +0200"
  },
  "committer": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Tue May 16 08:19:45 2023 +0200"
  },
  "message": "systemverilog-plugin: update remove module message\n\nSigned-off-by: Kamil Rakoczy \u003ckrakoczy@antmicro.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "aa511b4f4c84ab7cfa704b61955219128dfcb5c7",
      "old_mode": 33188,
      "old_path": "systemverilog-plugin/UhdmAst.cc",
      "new_id": "5afb77ae55597f445a38d1af5143722b2d15bdde",
      "new_mode": 33188,
      "new_path": "systemverilog-plugin/UhdmAst.cc"
    }
  ]
}