diff --git a/sdc-plugin/tests/Makefile b/sdc-plugin/tests/Makefile
index 703acfb..400d516 100644
--- a/sdc-plugin/tests/Makefile
+++ b/sdc-plugin/tests/Makefile
@@ -1,15 +1,14 @@
-TESTS = base_litex counter pll
+TESTS = counter pll
+.PHONY: $(TESTS)
 
-base_litex_verify = $(call compare_json,base_litex)
-counter_verify = $(call compare_json,counter)
-pll_verify = $(call compare_json,pll)
+counter_verify = $(call compare,counter,sdc) && $(call compare,counter,txt)
+pll_verify = $(call compare,pll,sdc)
 
 all: $(TESTS)
-
-compare_json = python compare_output_json.py --json $(1)/$(1).json --golden $(1)/$(1).golden.json
+compare = diff $(1)/$(1).golden.$(2) $(1)/$(1).$(2)
 
 define test_tpl =
-$(1): $(1)/$(1).json
+$(1): $(1)/$(1).sdc
 	$$($(1)_verify)
 	RETVAL=$$$$? ; \
 	if [ $$$$RETVAL -eq 0 ]; then \
@@ -20,24 +19,15 @@
 		false; \
 	fi
 
-$(1)/$(1).json: $(1)/$(1).v
+$(1)/$(1).sdc: $(1)/$(1).v
 	cd $(1); \
-	PART_JSON=../xc7a35tcsg324-1.json \
-	OUT_JSON=$(1).json \
-	OUT_EBLIF=$(1).eblif \
-	INPUT_XDC_FILE=$(1).xdc \
-	INPUT_SDC_FILE=$(1).sdc \
+	INPUT_SDC_FILE=$(1).input.sdc \
+	OUTPUT_SDC_FILE=$(1).sdc \
 	yosys -p "tcl $(1).tcl" -l yosys.log
 
-update_$(1): $(1)/$(1).json
-	@python compare_output_json.py --json $$< --golden $(1)/$(1).golden.json --update
-
 endef
 
 $(foreach test,$(TESTS),$(eval $(call test_tpl,$(test))))
 
-update: $(foreach test,$(TESTS),update_$(test))
-
-
 clean:
-	rm -rf $(foreach test,$(TESTS),$(test)/$(test).json $(test)/$(test).eblif $(test)/$(test).txt $(test)/yosys.log)
+	rm -rf $(foreach test,$(TESTS),$(test)/$(test).sdc $(test)/$(test).txt $(test)/yosys.log)
diff --git a/sdc-plugin/tests/base_litex/VexRiscv_Linux.v b/sdc-plugin/tests/base_litex/VexRiscv_Linux.v
deleted file mode 100644
index 0833b57..0000000
--- a/sdc-plugin/tests/base_litex/VexRiscv_Linux.v
+++ /dev/null
@@ -1,7469 +0,0 @@
-// Generator : SpinalHDL v1.3.6    git head : 9bf01e7f360e003fac1dd5ca8b8f4bffec0e52b8
-// Date      : 16/06/2019, 23:08:47
-// Component : VexRiscv
-
-
-`define BranchCtrlEnum_defaultEncoding_type [1:0]
-`define BranchCtrlEnum_defaultEncoding_INC 2'b00
-`define BranchCtrlEnum_defaultEncoding_B 2'b01
-`define BranchCtrlEnum_defaultEncoding_JAL 2'b10
-`define BranchCtrlEnum_defaultEncoding_JALR 2'b11
-
-`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0]
-`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00
-`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01
-`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10
-
-`define Src1CtrlEnum_defaultEncoding_type [1:0]
-`define Src1CtrlEnum_defaultEncoding_RS 2'b00
-`define Src1CtrlEnum_defaultEncoding_IMU 2'b01
-`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10
-`define Src1CtrlEnum_defaultEncoding_URS1 2'b11
-
-`define Src2CtrlEnum_defaultEncoding_type [1:0]
-`define Src2CtrlEnum_defaultEncoding_RS 2'b00
-`define Src2CtrlEnum_defaultEncoding_IMI 2'b01
-`define Src2CtrlEnum_defaultEncoding_IMS 2'b10
-`define Src2CtrlEnum_defaultEncoding_PC 2'b11
-
-`define EnvCtrlEnum_defaultEncoding_type [1:0]
-`define EnvCtrlEnum_defaultEncoding_NONE 2'b00
-`define EnvCtrlEnum_defaultEncoding_XRET 2'b01
-`define EnvCtrlEnum_defaultEncoding_WFI 2'b10
-`define EnvCtrlEnum_defaultEncoding_ECALL 2'b11
-
-`define AluCtrlEnum_defaultEncoding_type [1:0]
-`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00
-`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01
-`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10
-
-`define ShiftCtrlEnum_defaultEncoding_type [1:0]
-`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00
-`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01
-`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10
-`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11
-
-`define MmuPlugin_shared_State_defaultEncoding_type [2:0]
-`define MmuPlugin_shared_State_defaultEncoding_IDLE 3'b000
-`define MmuPlugin_shared_State_defaultEncoding_L1_CMD 3'b001
-`define MmuPlugin_shared_State_defaultEncoding_L1_RSP 3'b010
-`define MmuPlugin_shared_State_defaultEncoding_L0_CMD 3'b011
-`define MmuPlugin_shared_State_defaultEncoding_L0_RSP 3'b100
-
-module InstructionCache (
-      input   io_flush,
-      input   io_cpu_prefetch_isValid,
-      output reg  io_cpu_prefetch_haltIt,
-      input  [31:0] io_cpu_prefetch_pc,
-      input   io_cpu_fetch_isValid,
-      input   io_cpu_fetch_isStuck,
-      input   io_cpu_fetch_isRemoved,
-      input  [31:0] io_cpu_fetch_pc,
-      output [31:0] io_cpu_fetch_data,
-      input   io_cpu_fetch_dataBypassValid,
-      input  [31:0] io_cpu_fetch_dataBypass,
-      output  io_cpu_fetch_mmuBus_cmd_isValid,
-      output [31:0] io_cpu_fetch_mmuBus_cmd_virtualAddress,
-      output  io_cpu_fetch_mmuBus_cmd_bypassTranslation,
-      input  [31:0] io_cpu_fetch_mmuBus_rsp_physicalAddress,
-      input   io_cpu_fetch_mmuBus_rsp_isIoAccess,
-      input   io_cpu_fetch_mmuBus_rsp_allowRead,
-      input   io_cpu_fetch_mmuBus_rsp_allowWrite,
-      input   io_cpu_fetch_mmuBus_rsp_allowExecute,
-      input   io_cpu_fetch_mmuBus_rsp_exception,
-      input   io_cpu_fetch_mmuBus_rsp_refilling,
-      output  io_cpu_fetch_mmuBus_end,
-      input   io_cpu_fetch_mmuBus_busy,
-      output [31:0] io_cpu_fetch_physicalAddress,
-      output  io_cpu_fetch_haltIt,
-      input   io_cpu_decode_isValid,
-      input   io_cpu_decode_isStuck,
-      input  [31:0] io_cpu_decode_pc,
-      output [31:0] io_cpu_decode_physicalAddress,
-      output [31:0] io_cpu_decode_data,
-      output  io_cpu_decode_cacheMiss,
-      output  io_cpu_decode_error,
-      output  io_cpu_decode_mmuRefilling,
-      output  io_cpu_decode_mmuException,
-      input   io_cpu_decode_isUser,
-      input   io_cpu_fill_valid,
-      input  [31:0] io_cpu_fill_payload,
-      output  io_mem_cmd_valid,
-      input   io_mem_cmd_ready,
-      output [31:0] io_mem_cmd_payload_address,
-      output [2:0] io_mem_cmd_payload_size,
-      input   io_mem_rsp_valid,
-      input  [31:0] io_mem_rsp_payload_data,
-      input   io_mem_rsp_payload_error,
-      input   clk,
-      input   reset);
-  reg [21:0] _zz_10_;
-  reg [31:0] _zz_11_;
-  wire  _zz_12_;
-  wire  _zz_13_;
-  wire [0:0] _zz_14_;
-  wire [0:0] _zz_15_;
-  wire [21:0] _zz_16_;
-  reg  _zz_1_;
-  reg  _zz_2_;
-  reg  lineLoader_fire;
-  reg  lineLoader_valid;
-  reg [31:0] lineLoader_address;
-  reg  lineLoader_hadError;
-  reg  lineLoader_flushPending;
-  reg [7:0] lineLoader_flushCounter;
-  reg  _zz_3_;
-  reg  lineLoader_cmdSent;
-  reg  lineLoader_wayToAllocate_willIncrement;
-  wire  lineLoader_wayToAllocate_willClear;
-  wire  lineLoader_wayToAllocate_willOverflowIfInc;
-  wire  lineLoader_wayToAllocate_willOverflow;
-  reg [2:0] lineLoader_wordIndex;
-  wire  lineLoader_write_tag_0_valid;
-  wire [6:0] lineLoader_write_tag_0_payload_address;
-  wire  lineLoader_write_tag_0_payload_data_valid;
-  wire  lineLoader_write_tag_0_payload_data_error;
-  wire [19:0] lineLoader_write_tag_0_payload_data_address;
-  wire  lineLoader_write_data_0_valid;
-  wire [9:0] lineLoader_write_data_0_payload_address;
-  wire [31:0] lineLoader_write_data_0_payload_data;
-  wire  _zz_4_;
-  wire [6:0] _zz_5_;
-  wire  _zz_6_;
-  wire  fetchStage_read_waysValues_0_tag_valid;
-  wire  fetchStage_read_waysValues_0_tag_error;
-  wire [19:0] fetchStage_read_waysValues_0_tag_address;
-  wire [21:0] _zz_7_;
-  wire [9:0] _zz_8_;
-  wire  _zz_9_;
-  wire [31:0] fetchStage_read_waysValues_0_data;
-  wire  fetchStage_hit_hits_0;
-  wire  fetchStage_hit_valid;
-  wire  fetchStage_hit_error;
-  wire [31:0] fetchStage_hit_data;
-  wire [31:0] fetchStage_hit_word;
-  reg [31:0] io_cpu_fetch_data_regNextWhen;
-  reg [31:0] decodeStage_mmuRsp_physicalAddress;
-  reg  decodeStage_mmuRsp_isIoAccess;
-  reg  decodeStage_mmuRsp_allowRead;
-  reg  decodeStage_mmuRsp_allowWrite;
-  reg  decodeStage_mmuRsp_allowExecute;
-  reg  decodeStage_mmuRsp_exception;
-  reg  decodeStage_mmuRsp_refilling;
-  reg  decodeStage_hit_valid;
-  reg  decodeStage_hit_error;
-  (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127];
-  (* ram_style = "block" *) reg [31:0] ways_0_datas [0:1023];
-  assign _zz_12_ = (! lineLoader_flushCounter[7]);
-  assign _zz_13_ = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid)));
-  assign _zz_14_ = _zz_7_[0 : 0];
-  assign _zz_15_ = _zz_7_[1 : 1];
-  assign _zz_16_ = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}};
-  always @ (posedge clk) begin
-    if(_zz_2_) begin
-      ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_16_;
-    end
-  end
-
-  always @ (posedge clk) begin
-    if(_zz_6_) begin
-      _zz_10_ <= ways_0_tags[_zz_5_];
-    end
-  end
-
-  always @ (posedge clk) begin
-    if(_zz_1_) begin
-      ways_0_datas[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data;
-    end
-  end
-
-  always @ (posedge clk) begin
-    if(_zz_9_) begin
-      _zz_11_ <= ways_0_datas[_zz_8_];
-    end
-  end
-
-  always @ (*) begin
-    _zz_1_ = 1'b0;
-    if(lineLoader_write_data_0_valid)begin
-      _zz_1_ = 1'b1;
-    end
-  end
-
-  always @ (*) begin
-    _zz_2_ = 1'b0;
-    if(lineLoader_write_tag_0_valid)begin
-      _zz_2_ = 1'b1;
-    end
-  end
-
-  assign io_cpu_fetch_haltIt = io_cpu_fetch_mmuBus_busy;
-  always @ (*) begin
-    lineLoader_fire = 1'b0;
-    if(io_mem_rsp_valid)begin
-      if((lineLoader_wordIndex == (3'b111)))begin
-        lineLoader_fire = 1'b1;
-      end
-    end
-  end
-
-  always @ (*) begin
-    io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending);
-    if(_zz_12_)begin
-      io_cpu_prefetch_haltIt = 1'b1;
-    end
-    if((! _zz_3_))begin
-      io_cpu_prefetch_haltIt = 1'b1;
-    end
-    if(io_flush)begin
-      io_cpu_prefetch_haltIt = 1'b1;
-    end
-  end
-
-  assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent));
-  assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],(5'b00000)};
-  assign io_mem_cmd_payload_size = (3'b101);
-  always @ (*) begin
-    lineLoader_wayToAllocate_willIncrement = 1'b0;
-    if((! lineLoader_valid))begin
-      lineLoader_wayToAllocate_willIncrement = 1'b1;
-    end
-  end
-
-  assign lineLoader_wayToAllocate_willClear = 1'b0;
-  assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1;
-  assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement);
-  assign _zz_4_ = 1'b1;
-  assign lineLoader_write_tag_0_valid = ((_zz_4_ && lineLoader_fire) || (! lineLoader_flushCounter[7]));
-  assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[7] ? lineLoader_address[11 : 5] : lineLoader_flushCounter[6 : 0]);
-  assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[7];
-  assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error);
-  assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 12];
-  assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && _zz_4_);
-  assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex};
-  assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data;
-  assign _zz_5_ = io_cpu_prefetch_pc[11 : 5];
-  assign _zz_6_ = (! io_cpu_fetch_isStuck);
-  assign _zz_7_ = _zz_10_;
-  assign fetchStage_read_waysValues_0_tag_valid = _zz_14_[0];
-  assign fetchStage_read_waysValues_0_tag_error = _zz_15_[0];
-  assign fetchStage_read_waysValues_0_tag_address = _zz_7_[21 : 2];
-  assign _zz_8_ = io_cpu_prefetch_pc[11 : 2];
-  assign _zz_9_ = (! io_cpu_fetch_isStuck);
-  assign fetchStage_read_waysValues_0_data = _zz_11_;
-  assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuBus_rsp_physicalAddress[31 : 12]));
-  assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != (1'b0));
-  assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error;
-  assign fetchStage_hit_data = fetchStage_read_waysValues_0_data;
-  assign fetchStage_hit_word = fetchStage_hit_data[31 : 0];
-  assign io_cpu_fetch_data = (io_cpu_fetch_dataBypassValid ? io_cpu_fetch_dataBypass : fetchStage_hit_word);
-  assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen;
-  assign io_cpu_fetch_mmuBus_cmd_isValid = io_cpu_fetch_isValid;
-  assign io_cpu_fetch_mmuBus_cmd_virtualAddress = io_cpu_fetch_pc;
-  assign io_cpu_fetch_mmuBus_cmd_bypassTranslation = 1'b0;
-  assign io_cpu_fetch_mmuBus_end = ((! io_cpu_fetch_isStuck) || io_cpu_fetch_isRemoved);
-  assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuBus_rsp_physicalAddress;
-  assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid);
-  assign io_cpu_decode_error = decodeStage_hit_error;
-  assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling;
-  assign io_cpu_decode_mmuException = ((! decodeStage_mmuRsp_refilling) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)));
-  assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress;
-  always @ (posedge clk) begin
-    if(reset) begin
-      lineLoader_valid <= 1'b0;
-      lineLoader_hadError <= 1'b0;
-      lineLoader_flushPending <= 1'b1;
-      lineLoader_cmdSent <= 1'b0;
-      lineLoader_wordIndex <= (3'b000);
-    end else begin
-      if(lineLoader_fire)begin
-        lineLoader_valid <= 1'b0;
-      end
-      if(lineLoader_fire)begin
-        lineLoader_hadError <= 1'b0;
-      end
-      if(io_cpu_fill_valid)begin
-        lineLoader_valid <= 1'b1;
-      end
-      if(io_flush)begin
-        lineLoader_flushPending <= 1'b1;
-      end
-      if(_zz_13_)begin
-        lineLoader_flushPending <= 1'b0;
-      end
-      if((io_mem_cmd_valid && io_mem_cmd_ready))begin
-        lineLoader_cmdSent <= 1'b1;
-      end
-      if(lineLoader_fire)begin
-        lineLoader_cmdSent <= 1'b0;
-      end
-      if(io_mem_rsp_valid)begin
-        lineLoader_wordIndex <= (lineLoader_wordIndex + (3'b001));
-        if(io_mem_rsp_payload_error)begin
-          lineLoader_hadError <= 1'b1;
-        end
-      end
-    end
-  end
-
-  always @ (posedge clk) begin
-    if(io_cpu_fill_valid)begin
-      lineLoader_address <= io_cpu_fill_payload;
-    end
-    if(_zz_12_)begin
-      lineLoader_flushCounter <= (lineLoader_flushCounter + (8'b00000001));
-    end
-    _zz_3_ <= lineLoader_flushCounter[7];
-    if(_zz_13_)begin
-      lineLoader_flushCounter <= (8'b00000000);
-    end
-    if((! io_cpu_decode_isStuck))begin
-      io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data;
-    end
-    if((! io_cpu_decode_isStuck))begin
-      decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuBus_rsp_physicalAddress;
-      decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuBus_rsp_isIoAccess;
-      decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuBus_rsp_allowRead;
-      decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuBus_rsp_allowWrite;
-      decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuBus_rsp_allowExecute;
-      decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuBus_rsp_exception;
-      decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuBus_rsp_refilling;
-    end
-    if((! io_cpu_decode_isStuck))begin
-      decodeStage_hit_valid <= fetchStage_hit_valid;
-    end
-    if((! io_cpu_decode_isStuck))begin
-      decodeStage_hit_error <= fetchStage_hit_error;
-    end
-  end
-
-endmodule
-
-module DataCache (
-      input   io_cpu_execute_isValid,
-      input  [31:0] io_cpu_execute_address,
-      input   io_cpu_execute_args_wr,
-      input  [31:0] io_cpu_execute_args_data,
-      input  [1:0] io_cpu_execute_args_size,
-      input   io_cpu_execute_args_isLrsc,
-      input   io_cpu_execute_args_isAmo,
-      input   io_cpu_execute_args_amoCtrl_swap,
-      input  [2:0] io_cpu_execute_args_amoCtrl_alu,
-      input   io_cpu_memory_isValid,
-      input   io_cpu_memory_isStuck,
-      input   io_cpu_memory_isRemoved,
-      output  io_cpu_memory_isWrite,
-      input  [31:0] io_cpu_memory_address,
-      output  io_cpu_memory_mmuBus_cmd_isValid,
-      output [31:0] io_cpu_memory_mmuBus_cmd_virtualAddress,
-      output  io_cpu_memory_mmuBus_cmd_bypassTranslation,
-      input  [31:0] io_cpu_memory_mmuBus_rsp_physicalAddress,
-      input   io_cpu_memory_mmuBus_rsp_isIoAccess,
-      input   io_cpu_memory_mmuBus_rsp_allowRead,
-      input   io_cpu_memory_mmuBus_rsp_allowWrite,
-      input   io_cpu_memory_mmuBus_rsp_allowExecute,
-      input   io_cpu_memory_mmuBus_rsp_exception,
-      input   io_cpu_memory_mmuBus_rsp_refilling,
-      output  io_cpu_memory_mmuBus_end,
-      input   io_cpu_memory_mmuBus_busy,
-      input   io_cpu_writeBack_isValid,
-      input   io_cpu_writeBack_isStuck,
-      input   io_cpu_writeBack_isUser,
-      output reg  io_cpu_writeBack_haltIt,
-      output  io_cpu_writeBack_isWrite,
-      output reg [31:0] io_cpu_writeBack_data,
-      input  [31:0] io_cpu_writeBack_address,
-      output  io_cpu_writeBack_mmuException,
-      output  io_cpu_writeBack_unalignedAccess,
-      output reg  io_cpu_writeBack_accessError,
-      input   io_cpu_writeBack_clearLrsc,
-      output reg  io_cpu_redo,
-      input   io_cpu_flush_valid,
-      output reg  io_cpu_flush_ready,
-      output reg  io_mem_cmd_valid,
-      input   io_mem_cmd_ready,
-      output reg  io_mem_cmd_payload_wr,
-      output reg [31:0] io_mem_cmd_payload_address,
-      output [31:0] io_mem_cmd_payload_data,
-      output [3:0] io_mem_cmd_payload_mask,
-      output reg [2:0] io_mem_cmd_payload_length,
-      output reg  io_mem_cmd_payload_last,
-      input   io_mem_rsp_valid,
-      input  [31:0] io_mem_rsp_payload_data,
-      input   io_mem_rsp_payload_error,
-      input   clk,
-      input   reset);
-  reg [21:0] _zz_10_;
-  reg [31:0] _zz_11_;
-  wire  _zz_12_;
-  wire  _zz_13_;
-  wire  _zz_14_;
-  wire  _zz_15_;
-  wire  _zz_16_;
-  wire  _zz_17_;
-  wire  _zz_18_;
-  wire  _zz_19_;
-  wire  _zz_20_;
-  wire  _zz_21_;
-  wire [2:0] _zz_22_;
-  wire [0:0] _zz_23_;
-  wire [0:0] _zz_24_;
-  wire [31:0] _zz_25_;
-  wire [31:0] _zz_26_;
-  wire [31:0] _zz_27_;
-  wire [31:0] _zz_28_;
-  wire [1:0] _zz_29_;
-  wire [31:0] _zz_30_;
-  wire [1:0] _zz_31_;
-  wire [1:0] _zz_32_;
-  wire [0:0] _zz_33_;
-  wire [0:0] _zz_34_;
-  wire [2:0] _zz_35_;
-  wire [1:0] _zz_36_;
-  wire [21:0] _zz_37_;
-  reg  _zz_1_;
-  reg  _zz_2_;
-  wire  haltCpu;
-  reg  tagsReadCmd_valid;
-  reg [6:0] tagsReadCmd_payload;
-  reg  tagsWriteCmd_valid;
-  reg [0:0] tagsWriteCmd_payload_way;
-  reg [6:0] tagsWriteCmd_payload_address;
-  reg  tagsWriteCmd_payload_data_valid;
-  reg  tagsWriteCmd_payload_data_error;
-  reg [19:0] tagsWriteCmd_payload_data_address;
-  reg  tagsWriteLastCmd_valid;
-  reg [0:0] tagsWriteLastCmd_payload_way;
-  reg [6:0] tagsWriteLastCmd_payload_address;
-  reg  tagsWriteLastCmd_payload_data_valid;
-  reg  tagsWriteLastCmd_payload_data_error;
-  reg [19:0] tagsWriteLastCmd_payload_data_address;
-  reg  dataReadCmd_valid;
-  reg [9:0] dataReadCmd_payload;
-  reg  dataWriteCmd_valid;
-  reg [0:0] dataWriteCmd_payload_way;
-  reg [9:0] dataWriteCmd_payload_address;
-  reg [31:0] dataWriteCmd_payload_data;
-  reg [3:0] dataWriteCmd_payload_mask;
-  wire  _zz_3_;
-  wire  ways_0_tagsReadRsp_valid;
-  wire  ways_0_tagsReadRsp_error;
-  wire [19:0] ways_0_tagsReadRsp_address;
-  wire [21:0] _zz_4_;
-  wire  _zz_5_;
-  wire [31:0] ways_0_dataReadRsp;
-  reg [3:0] _zz_6_;
-  wire [3:0] stage0_mask;
-  wire [0:0] stage0_colisions;
-  reg  stageA_request_wr;
-  reg [31:0] stageA_request_data;
-  reg [1:0] stageA_request_size;
-  reg  stageA_request_isLrsc;
-  reg  stageA_request_isAmo;
-  reg  stageA_request_amoCtrl_swap;
-  reg [2:0] stageA_request_amoCtrl_alu;
-  reg [3:0] stageA_mask;
-  wire  stageA_wayHits_0;
-  reg [0:0] stage0_colisions_regNextWhen;
-  wire [0:0] _zz_7_;
-  wire [0:0] stageA_colisions;
-  reg  stageB_request_wr;
-  reg [31:0] stageB_request_data;
-  reg [1:0] stageB_request_size;
-  reg  stageB_request_isLrsc;
-  reg  stageB_isAmo;
-  reg  stageB_request_amoCtrl_swap;
-  reg [2:0] stageB_request_amoCtrl_alu;
-  reg  stageB_mmuRspFreeze;
-  reg [31:0] stageB_mmuRsp_physicalAddress;
-  reg  stageB_mmuRsp_isIoAccess;
-  reg  stageB_mmuRsp_allowRead;
-  reg  stageB_mmuRsp_allowWrite;
-  reg  stageB_mmuRsp_allowExecute;
-  reg  stageB_mmuRsp_exception;
-  reg  stageB_mmuRsp_refilling;
-  reg  stageB_tagsReadRsp_0_valid;
-  reg  stageB_tagsReadRsp_0_error;
-  reg [19:0] stageB_tagsReadRsp_0_address;
-  reg [31:0] stageB_dataReadRsp_0;
-  wire [0:0] _zz_8_;
-  reg [0:0] stageB_waysHits;
-  wire  stageB_waysHit;
-  wire [31:0] stageB_dataMux;
-  reg [3:0] stageB_mask;
-  reg [0:0] stageB_colisions;
-  reg  stageB_loaderValid;
-  reg  stageB_flusher_valid;
-  reg  stageB_lrsc_reserved;
-  reg [31:0] stageB_requestDataBypass;
-  wire  stageB_amo_compare;
-  wire  stageB_amo_unsigned;
-  wire [31:0] stageB_amo_addSub;
-  wire  stageB_amo_less;
-  wire  stageB_amo_selectRf;
-  reg [31:0] stageB_amo_result;
-  reg  stageB_amo_resultRegValid;
-  reg [31:0] stageB_amo_resultReg;
-  reg  stageB_memCmdSent;
-  wire [0:0] _zz_9_;
-  reg  loader_valid;
-  reg  loader_counter_willIncrement;
-  wire  loader_counter_willClear;
-  reg [2:0] loader_counter_valueNext;
-  reg [2:0] loader_counter_value;
-  wire  loader_counter_willOverflowIfInc;
-  wire  loader_counter_willOverflow;
-  reg [0:0] loader_waysAllocator;
-  reg  loader_error;
-  (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127];
-  (* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023];
-  (* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023];
-  (* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023];
-  (* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023];
-  reg [7:0] _zz_38_;
-  reg [7:0] _zz_39_;
-  reg [7:0] _zz_40_;
-  reg [7:0] _zz_41_;
-  assign _zz_12_ = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck));
-  assign _zz_13_ = (((stageB_mmuRsp_refilling || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess);
-  assign _zz_14_ = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmo)));
-  assign _zz_15_ = (! stageB_amo_resultRegValid);
-  assign _zz_16_ = (stageB_request_isLrsc && (! stageB_lrsc_reserved));
-  assign _zz_17_ = (loader_valid && io_mem_rsp_valid);
-  assign _zz_18_ = (stageB_request_isLrsc && (! stageB_lrsc_reserved));
-  assign _zz_19_ = ((((io_cpu_flush_valid && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo));
-  assign _zz_20_ = (((! stageB_request_wr) || stageB_isAmo) && ((stageB_colisions & stageB_waysHits) != (1'b0)));
-  assign _zz_21_ = ((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze));
-  assign _zz_22_ = (stageB_request_amoCtrl_alu | {stageB_request_amoCtrl_swap,(2'b00)});
-  assign _zz_23_ = _zz_4_[0 : 0];
-  assign _zz_24_ = _zz_4_[1 : 1];
-  assign _zz_25_ = ($signed(_zz_26_) + $signed(_zz_30_));
-  assign _zz_26_ = ($signed(_zz_27_) + $signed(_zz_28_));
-  assign _zz_27_ = stageB_request_data;
-  assign _zz_28_ = (stageB_amo_compare ? (~ stageB_dataMux) : stageB_dataMux);
-  assign _zz_29_ = (stageB_amo_compare ? _zz_31_ : _zz_32_);
-  assign _zz_30_ = {{30{_zz_29_[1]}}, _zz_29_};
-  assign _zz_31_ = (2'b01);
-  assign _zz_32_ = (2'b00);
-  assign _zz_33_ = (! stageB_lrsc_reserved);
-  assign _zz_34_ = loader_counter_willIncrement;
-  assign _zz_35_ = {2'd0, _zz_34_};
-  assign _zz_36_ = {loader_waysAllocator,loader_waysAllocator[0]};
-  assign _zz_37_ = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}};
-  always @ (posedge clk) begin
-    if(_zz_2_) begin
-      ways_0_tags[tagsWriteCmd_payload_address] <= _zz_37_;
-    end
-  end
-
-  always @ (posedge clk) begin
-    if(_zz_3_) begin
-      _zz_10_ <= ways_0_tags[tagsReadCmd_payload];
-    end
-  end
-
-  always @ (*) begin
-    _zz_11_ = {_zz_41_, _zz_40_, _zz_39_, _zz_38_};
-  end
-  always @ (posedge clk) begin
-    if(dataWriteCmd_payload_mask[0] && _zz_1_) begin
-      ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0];
-    end
-    if(dataWriteCmd_payload_mask[1] && _zz_1_) begin
-      ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8];
-    end
-    if(dataWriteCmd_payload_mask[2] && _zz_1_) begin
-      ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16];
-    end
-    if(dataWriteCmd_payload_mask[3] && _zz_1_) begin
-      ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24];
-    end
-  end
-
-  always @ (posedge clk) begin
-    if(_zz_5_) begin
-      _zz_38_ <= ways_0_data_symbol0[dataReadCmd_payload];
-      _zz_39_ <= ways_0_data_symbol1[dataReadCmd_payload];
-      _zz_40_ <= ways_0_data_symbol2[dataReadCmd_payload];
-      _zz_41_ <= ways_0_data_symbol3[dataReadCmd_payload];
-    end
-  end
-
-  always @ (*) begin
-    _zz_1_ = 1'b0;
-    if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin
-      _zz_1_ = 1'b1;
-    end
-  end
-
-  always @ (*) begin
-    _zz_2_ = 1'b0;
-    if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin
-      _zz_2_ = 1'b1;
-    end
-  end
-
-  assign haltCpu = 1'b0;
-  assign _zz_3_ = (tagsReadCmd_valid && (! io_cpu_memory_isStuck));
-  assign _zz_4_ = _zz_10_;
-  assign ways_0_tagsReadRsp_valid = _zz_23_[0];
-  assign ways_0_tagsReadRsp_error = _zz_24_[0];
-  assign ways_0_tagsReadRsp_address = _zz_4_[21 : 2];
-  assign _zz_5_ = (dataReadCmd_valid && (! io_cpu_memory_isStuck));
-  assign ways_0_dataReadRsp = _zz_11_;
-  always @ (*) begin
-    tagsReadCmd_valid = 1'b0;
-    if(_zz_12_)begin
-      tagsReadCmd_valid = 1'b1;
-    end
-  end
-
-  always @ (*) begin
-    tagsReadCmd_payload = (7'bxxxxxxx);
-    if(_zz_12_)begin
-      tagsReadCmd_payload = io_cpu_execute_address[11 : 5];
-    end
-  end
-
-  always @ (*) begin
-    dataReadCmd_valid = 1'b0;
-    if(_zz_12_)begin
-      dataReadCmd_valid = 1'b1;
-    end
-  end
-
-  always @ (*) begin
-    dataReadCmd_payload = (10'bxxxxxxxxxx);
-    if(_zz_12_)begin
-      dataReadCmd_payload = io_cpu_execute_address[11 : 2];
-    end
-  end
-
-  always @ (*) begin
-    tagsWriteCmd_valid = 1'b0;
-    if(stageB_flusher_valid)begin
-      tagsWriteCmd_valid = stageB_flusher_valid;
-    end
-    if(_zz_13_)begin
-      tagsWriteCmd_valid = 1'b0;
-    end
-    if(loader_counter_willOverflow)begin
-      tagsWriteCmd_valid = 1'b1;
-    end
-  end
-
-  always @ (*) begin
-    tagsWriteCmd_payload_way = (1'bx);
-    if(stageB_flusher_valid)begin
-      tagsWriteCmd_payload_way = (1'b1);
-    end
-    if(loader_counter_willOverflow)begin
-      tagsWriteCmd_payload_way = loader_waysAllocator;
-    end
-  end
-
-  always @ (*) begin
-    tagsWriteCmd_payload_address = (7'bxxxxxxx);
-    if(stageB_flusher_valid)begin
-      tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5];
-    end
-    if(loader_counter_willOverflow)begin
-      tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5];
-    end
-  end
-
-  always @ (*) begin
-    tagsWriteCmd_payload_data_valid = 1'bx;
-    if(stageB_flusher_valid)begin
-      tagsWriteCmd_payload_data_valid = 1'b0;
-    end
-    if(loader_counter_willOverflow)begin
-      tagsWriteCmd_payload_data_valid = 1'b1;
-    end
-  end
-
-  always @ (*) begin
-    tagsWriteCmd_payload_data_error = 1'bx;
-    if(loader_counter_willOverflow)begin
-      tagsWriteCmd_payload_data_error = (loader_error || io_mem_rsp_payload_error);
-    end
-  end
-
-  always @ (*) begin
-    tagsWriteCmd_payload_data_address = (20'bxxxxxxxxxxxxxxxxxxxx);
-    if(loader_counter_willOverflow)begin
-      tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12];
-    end
-  end
-
-  always @ (*) begin
-    dataWriteCmd_valid = 1'b0;
-    if(io_cpu_writeBack_isValid)begin
-      if(! stageB_mmuRsp_isIoAccess) begin
-        if(_zz_14_)begin
-          if((stageB_request_wr && stageB_waysHit))begin
-            dataWriteCmd_valid = 1'b1;
-          end
-          if(stageB_isAmo)begin
-            if(_zz_15_)begin
-              dataWriteCmd_valid = 1'b0;
-            end
-          end
-          if(_zz_16_)begin
-            dataWriteCmd_valid = 1'b0;
-          end
-        end
-      end
-    end
-    if(_zz_13_)begin
-      dataWriteCmd_valid = 1'b0;
-    end
-    if(_zz_17_)begin
-      dataWriteCmd_valid = 1'b1;
-    end
-  end
-
-  always @ (*) begin
-    dataWriteCmd_payload_way = (1'bx);
-    if(io_cpu_writeBack_isValid)begin
-      if(! stageB_mmuRsp_isIoAccess) begin
-        if(_zz_14_)begin
-          dataWriteCmd_payload_way = stageB_waysHits;
-        end
-      end
-    end
-    if(_zz_17_)begin
-      dataWriteCmd_payload_way = loader_waysAllocator;
-    end
-  end
-
-  always @ (*) begin
-    dataWriteCmd_payload_address = (10'bxxxxxxxxxx);
-    if(io_cpu_writeBack_isValid)begin
-      if(! stageB_mmuRsp_isIoAccess) begin
-        if(_zz_14_)begin
-          dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2];
-        end
-      end
-    end
-    if(_zz_17_)begin
-      dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value};
-    end
-  end
-
-  always @ (*) begin
-    dataWriteCmd_payload_data = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx);
-    if(io_cpu_writeBack_isValid)begin
-      if(! stageB_mmuRsp_isIoAccess) begin
-        if(_zz_14_)begin
-          dataWriteCmd_payload_data = stageB_requestDataBypass;
-        end
-      end
-    end
-    if(_zz_17_)begin
-      dataWriteCmd_payload_data = io_mem_rsp_payload_data;
-    end
-  end
-
-  always @ (*) begin
-    dataWriteCmd_payload_mask = (4'bxxxx);
-    if(io_cpu_writeBack_isValid)begin
-      if(! stageB_mmuRsp_isIoAccess) begin
-        if(_zz_14_)begin
-          dataWriteCmd_payload_mask = stageB_mask;
-        end
-      end
-    end
-    if(_zz_17_)begin
-      dataWriteCmd_payload_mask = (4'b1111);
-    end
-  end
-
-  always @ (*) begin
-    case(io_cpu_execute_args_size)
-      2'b00 : begin
-        _zz_6_ = (4'b0001);
-      end
-      2'b01 : begin
-        _zz_6_ = (4'b0011);
-      end
-      default : begin
-        _zz_6_ = (4'b1111);
-      end
-    endcase
-  end
-
-  assign stage0_mask = (_zz_6_ <<< io_cpu_execute_address[1 : 0]);
-  assign stage0_colisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == io_cpu_execute_address[11 : 2])) && ((stage0_mask & dataWriteCmd_payload_mask) != (4'b0000)));
-  assign io_cpu_memory_mmuBus_cmd_isValid = io_cpu_memory_isValid;
-  assign io_cpu_memory_mmuBus_cmd_virtualAddress = io_cpu_memory_address;
-  assign io_cpu_memory_mmuBus_cmd_bypassTranslation = 1'b0;
-  assign io_cpu_memory_mmuBus_end = ((! io_cpu_memory_isStuck) || io_cpu_memory_isRemoved);
-  assign io_cpu_memory_isWrite = stageA_request_wr;
-  assign stageA_wayHits_0 = ((io_cpu_memory_mmuBus_rsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid);
-  assign _zz_7_[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == io_cpu_memory_address[11 : 2])) && ((stageA_mask & dataWriteCmd_payload_mask) != (4'b0000)));
-  assign stageA_colisions = (stage0_colisions_regNextWhen | _zz_7_);
-  always @ (*) begin
-    stageB_mmuRspFreeze = 1'b0;
-    if((stageB_loaderValid || loader_valid))begin
-      stageB_mmuRspFreeze = 1'b1;
-    end
-  end
-
-  assign _zz_8_[0] = stageA_wayHits_0;
-  assign stageB_waysHit = (stageB_waysHits != (1'b0));
-  assign stageB_dataMux = stageB_dataReadRsp_0;
-  always @ (*) begin
-    stageB_loaderValid = 1'b0;
-    if(io_cpu_writeBack_isValid)begin
-      if(! stageB_mmuRsp_isIoAccess) begin
-        if(! _zz_14_) begin
-          if(io_mem_cmd_ready)begin
-            stageB_loaderValid = 1'b1;
-          end
-        end
-      end
-    end
-    if(_zz_13_)begin
-      stageB_loaderValid = 1'b0;
-    end
-  end
-
-  always @ (*) begin
-    io_cpu_writeBack_haltIt = io_cpu_writeBack_isValid;
-    if(stageB_flusher_valid)begin
-      io_cpu_writeBack_haltIt = 1'b1;
-    end
-    if(io_cpu_writeBack_isValid)begin
-      if(stageB_mmuRsp_isIoAccess)begin
-        if((stageB_request_wr ? io_mem_cmd_ready : io_mem_rsp_valid))begin
-          io_cpu_writeBack_haltIt = 1'b0;
-        end
-        if(_zz_18_)begin
-          io_cpu_writeBack_haltIt = 1'b0;
-        end
-      end else begin
-        if(_zz_14_)begin
-          if(((! stageB_request_wr) || io_mem_cmd_ready))begin
-            io_cpu_writeBack_haltIt = 1'b0;
-          end
-          if(stageB_isAmo)begin
-            if(_zz_15_)begin
-              io_cpu_writeBack_haltIt = 1'b1;
-            end
-          end
-          if(_zz_16_)begin
-            io_cpu_writeBack_haltIt = 1'b0;
-          end
-        end
-      end
-    end
-    if(_zz_13_)begin
-      io_cpu_writeBack_haltIt = 1'b0;
-    end
-  end
-
-  always @ (*) begin
-    io_cpu_flush_ready = 1'b0;
-    if(_zz_19_)begin
-      io_cpu_flush_ready = 1'b1;
-    end
-  end
-
-  always @ (*) begin
-    stageB_requestDataBypass = stageB_request_data;
-    if(stageB_isAmo)begin
-      stageB_requestDataBypass = stageB_amo_resultReg;
-    end
-  end
-
-  assign stageB_amo_compare = stageB_request_amoCtrl_alu[2];
-  assign stageB_amo_unsigned = (stageB_request_amoCtrl_alu[2 : 1] == (2'b11));
-  assign stageB_amo_addSub = _zz_25_;
-  assign stageB_amo_less = ((stageB_request_data[31] == stageB_dataMux[31]) ? stageB_amo_addSub[31] : (stageB_amo_unsigned ? stageB_dataMux[31] : stageB_request_data[31]));
-  assign stageB_amo_selectRf = (stageB_request_amoCtrl_swap ? 1'b1 : (stageB_request_amoCtrl_alu[0] ^ stageB_amo_less));
-  always @ (*) begin
-    case(_zz_22_)
-      3'b000 : begin
-        stageB_amo_result = stageB_amo_addSub;
-      end
-      3'b001 : begin
-        stageB_amo_result = (stageB_request_data ^ stageB_dataMux);
-      end
-      3'b010 : begin
-        stageB_amo_result = (stageB_request_data | stageB_dataMux);
-      end
-      3'b011 : begin
-        stageB_amo_result = (stageB_request_data & stageB_dataMux);
-      end
-      default : begin
-        stageB_amo_result = (stageB_amo_selectRf ? stageB_request_data : stageB_dataMux);
-      end
-    endcase
-  end
-
-  always @ (*) begin
-    io_cpu_redo = 1'b0;
-    if(io_cpu_writeBack_isValid)begin
-      if(! stageB_mmuRsp_isIoAccess) begin
-        if(_zz_14_)begin
-          if(_zz_20_)begin
-            io_cpu_redo = 1'b1;
-          end
-        end
-      end
-    end
-    if((io_cpu_writeBack_isValid && stageB_mmuRsp_refilling))begin
-      io_cpu_redo = 1'b1;
-    end
-    if(loader_valid)begin
-      io_cpu_redo = 1'b1;
-    end
-  end
-
-  always @ (*) begin
-    io_cpu_writeBack_accessError = 1'b0;
-    if(stageB_mmuRsp_isIoAccess)begin
-      io_cpu_writeBack_accessError = (io_mem_rsp_valid && io_mem_rsp_payload_error);
-    end else begin
-      io_cpu_writeBack_accessError = ((stageB_waysHits & _zz_9_) != (1'b0));
-    end
-  end
-
-  assign io_cpu_writeBack_mmuException = (io_cpu_writeBack_isValid && ((stageB_mmuRsp_exception || ((! stageB_mmuRsp_allowWrite) && stageB_request_wr)) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo))));
-  assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && (((stageB_request_size == (2'b10)) && (stageB_mmuRsp_physicalAddress[1 : 0] != (2'b00))) || ((stageB_request_size == (2'b01)) && (stageB_mmuRsp_physicalAddress[0 : 0] != (1'b0)))));
-  assign io_cpu_writeBack_isWrite = stageB_request_wr;
-  always @ (*) begin
-    io_mem_cmd_valid = 1'b0;
-    if(io_cpu_writeBack_isValid)begin
-      if(stageB_mmuRsp_isIoAccess)begin
-        io_mem_cmd_valid = (! stageB_memCmdSent);
-        if(_zz_18_)begin
-          io_mem_cmd_valid = 1'b0;
-        end
-      end else begin
-        if(_zz_14_)begin
-          if(stageB_request_wr)begin
-            io_mem_cmd_valid = 1'b1;
-          end
-          if(stageB_isAmo)begin
-            if(_zz_15_)begin
-              io_mem_cmd_valid = 1'b0;
-            end
-          end
-          if(_zz_20_)begin
-            io_mem_cmd_valid = 1'b0;
-          end
-          if(_zz_16_)begin
-            io_mem_cmd_valid = 1'b0;
-          end
-        end else begin
-          if((! stageB_memCmdSent))begin
-            io_mem_cmd_valid = 1'b1;
-          end
-        end
-      end
-    end
-    if(_zz_13_)begin
-      io_mem_cmd_valid = 1'b0;
-    end
-  end
-
-  always @ (*) begin
-    io_mem_cmd_payload_address = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx);
-    if(io_cpu_writeBack_isValid)begin
-      if(stageB_mmuRsp_isIoAccess)begin
-        io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],(2'b00)};
-      end else begin
-        if(_zz_14_)begin
-          io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],(2'b00)};
-        end else begin
-          io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 5],(5'b00000)};
-        end
-      end
-    end
-  end
-
-  always @ (*) begin
-    io_mem_cmd_payload_length = (3'bxxx);
-    if(io_cpu_writeBack_isValid)begin
-      if(stageB_mmuRsp_isIoAccess)begin
-        io_mem_cmd_payload_length = (3'b000);
-      end else begin
-        if(_zz_14_)begin
-          io_mem_cmd_payload_length = (3'b000);
-        end else begin
-          io_mem_cmd_payload_length = (3'b111);
-        end
-      end
-    end
-  end
-
-  always @ (*) begin
-    io_mem_cmd_payload_last = 1'bx;
-    if(io_cpu_writeBack_isValid)begin
-      if(stageB_mmuRsp_isIoAccess)begin
-        io_mem_cmd_payload_last = 1'b1;
-      end else begin
-        if(_zz_14_)begin
-          io_mem_cmd_payload_last = 1'b1;
-        end else begin
-          io_mem_cmd_payload_last = 1'b1;
-        end
-      end
-    end
-  end
-
-  always @ (*) begin
-    io_mem_cmd_payload_wr = stageB_request_wr;
-    if(io_cpu_writeBack_isValid)begin
-      if(! stageB_mmuRsp_isIoAccess) begin
-        if(! _zz_14_) begin
-          io_mem_cmd_payload_wr = 1'b0;
-        end
-      end
-    end
-  end
-
-  assign io_mem_cmd_payload_mask = stageB_mask;
-  assign io_mem_cmd_payload_data = stageB_requestDataBypass;
-  always @ (*) begin
-    if(stageB_mmuRsp_isIoAccess)begin
-      io_cpu_writeBack_data = io_mem_rsp_payload_data;
-    end else begin
-      io_cpu_writeBack_data = stageB_dataMux;
-    end
-    if((stageB_request_isLrsc && stageB_request_wr))begin
-      io_cpu_writeBack_data = {31'd0, _zz_33_};
-    end
-  end
-
-  assign _zz_9_[0] = stageB_tagsReadRsp_0_error;
-  always @ (*) begin
-    loader_counter_willIncrement = 1'b0;
-    if(_zz_17_)begin
-      loader_counter_willIncrement = 1'b1;
-    end
-  end
-
-  assign loader_counter_willClear = 1'b0;
-  assign loader_counter_willOverflowIfInc = (loader_counter_value == (3'b111));
-  assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement);
-  always @ (*) begin
-    loader_counter_valueNext = (loader_counter_value + _zz_35_);
-    if(loader_counter_willClear)begin
-      loader_counter_valueNext = (3'b000);
-    end
-  end
-
-  always @ (posedge clk) begin
-    tagsWriteLastCmd_valid <= tagsWriteCmd_valid;
-    tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way;
-    tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address;
-    tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid;
-    tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error;
-    tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address;
-    if((! io_cpu_memory_isStuck))begin
-      stageA_request_wr <= io_cpu_execute_args_wr;
-      stageA_request_data <= io_cpu_execute_args_data;
-      stageA_request_size <= io_cpu_execute_args_size;
-      stageA_request_isLrsc <= io_cpu_execute_args_isLrsc;
-      stageA_request_isAmo <= io_cpu_execute_args_isAmo;
-      stageA_request_amoCtrl_swap <= io_cpu_execute_args_amoCtrl_swap;
-      stageA_request_amoCtrl_alu <= io_cpu_execute_args_amoCtrl_alu;
-    end
-    if((! io_cpu_memory_isStuck))begin
-      stageA_mask <= stage0_mask;
-    end
-    if((! io_cpu_memory_isStuck))begin
-      stage0_colisions_regNextWhen <= stage0_colisions;
-    end
-    if((! io_cpu_writeBack_isStuck))begin
-      stageB_request_wr <= stageA_request_wr;
-      stageB_request_data <= stageA_request_data;
-      stageB_request_size <= stageA_request_size;
-      stageB_request_isLrsc <= stageA_request_isLrsc;
-      stageB_isAmo <= stageA_request_isAmo;
-      stageB_request_amoCtrl_swap <= stageA_request_amoCtrl_swap;
-      stageB_request_amoCtrl_alu <= stageA_request_amoCtrl_alu;
-    end
-    if(_zz_21_)begin
-      stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuBus_rsp_isIoAccess;
-      stageB_mmuRsp_allowRead <= io_cpu_memory_mmuBus_rsp_allowRead;
-      stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuBus_rsp_allowWrite;
-      stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuBus_rsp_allowExecute;
-      stageB_mmuRsp_exception <= io_cpu_memory_mmuBus_rsp_exception;
-      stageB_mmuRsp_refilling <= io_cpu_memory_mmuBus_rsp_refilling;
-    end
-    if((! io_cpu_writeBack_isStuck))begin
-      stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid;
-      stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error;
-      stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address;
-    end
-    if((! io_cpu_writeBack_isStuck))begin
-      stageB_dataReadRsp_0 <= ways_0_dataReadRsp;
-    end
-    if((! io_cpu_writeBack_isStuck))begin
-      stageB_waysHits <= _zz_8_;
-    end
-    if((! io_cpu_writeBack_isStuck))begin
-      stageB_mask <= stageA_mask;
-    end
-    if((! io_cpu_writeBack_isStuck))begin
-      stageB_colisions <= stageA_colisions;
-    end
-    stageB_amo_resultRegValid <= 1'b1;
-    if((! io_cpu_writeBack_isStuck))begin
-      stageB_amo_resultRegValid <= 1'b0;
-    end
-    stageB_amo_resultReg <= stageB_amo_result;
-    if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin
-      $display("ERROR writeBack stuck by another plugin is not allowed");
-    end
-  end
-
-  always @ (posedge clk) begin
-    if(reset) begin
-      stageB_flusher_valid <= 1'b1;
-      stageB_mmuRsp_physicalAddress <= (32'b00000000000000000000000000000000);
-      stageB_lrsc_reserved <= 1'b0;
-      stageB_memCmdSent <= 1'b0;
-      loader_valid <= 1'b0;
-      loader_counter_value <= (3'b000);
-      loader_waysAllocator <= (1'b1);
-      loader_error <= 1'b0;
-    end else begin
-      if(_zz_21_)begin
-        stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuBus_rsp_physicalAddress;
-      end
-      if(stageB_flusher_valid)begin
-        if((stageB_mmuRsp_physicalAddress[11 : 5] != (7'b1111111)))begin
-          stageB_mmuRsp_physicalAddress[11 : 5] <= (stageB_mmuRsp_physicalAddress[11 : 5] + (7'b0000001));
-        end else begin
-          stageB_flusher_valid <= 1'b0;
-        end
-      end
-      if(_zz_19_)begin
-        stageB_mmuRsp_physicalAddress[11 : 5] <= (7'b0000000);
-        stageB_flusher_valid <= 1'b1;
-      end
-      if(((((io_cpu_writeBack_isValid && (! io_cpu_writeBack_isStuck)) && (! io_cpu_redo)) && stageB_request_isLrsc) && (! stageB_request_wr)))begin
-        stageB_lrsc_reserved <= 1'b1;
-      end
-      if(io_cpu_writeBack_clearLrsc)begin
-        stageB_lrsc_reserved <= 1'b0;
-      end
-      if(io_mem_cmd_ready)begin
-        stageB_memCmdSent <= 1'b1;
-      end
-      if((! io_cpu_writeBack_isStuck))begin
-        stageB_memCmdSent <= 1'b0;
-      end
-      if(stageB_loaderValid)begin
-        loader_valid <= 1'b1;
-      end
-      loader_counter_value <= loader_counter_valueNext;
-      if(_zz_17_)begin
-        loader_error <= (loader_error || io_mem_rsp_payload_error);
-      end
-      if(loader_counter_willOverflow)begin
-        loader_valid <= 1'b0;
-        loader_error <= 1'b0;
-      end
-      if((! loader_valid))begin
-        loader_waysAllocator <= _zz_36_[0:0];
-      end
-    end
-  end
-
-endmodule
-
-module VexRiscv (
-      input  [31:0] externalResetVector,
-      input   timerInterrupt,
-      input   softwareInterrupt,
-      input  [31:0] externalInterruptArray,
-      output reg  iBusWishbone_CYC,
-      output reg  iBusWishbone_STB,
-      input   iBusWishbone_ACK,
-      output  iBusWishbone_WE,
-      output [29:0] iBusWishbone_ADR,
-      input  [31:0] iBusWishbone_DAT_MISO,
-      output [31:0] iBusWishbone_DAT_MOSI,
-      output [3:0] iBusWishbone_SEL,
-      input   iBusWishbone_ERR,
-      output [1:0] iBusWishbone_BTE,
-      output [2:0] iBusWishbone_CTI,
-      output  dBusWishbone_CYC,
-      output  dBusWishbone_STB,
-      input   dBusWishbone_ACK,
-      output  dBusWishbone_WE,
-      output [29:0] dBusWishbone_ADR,
-      input  [31:0] dBusWishbone_DAT_MISO,
-      output [31:0] dBusWishbone_DAT_MOSI,
-      output [3:0] dBusWishbone_SEL,
-      input   dBusWishbone_ERR,
-      output [1:0] dBusWishbone_BTE,
-      output [2:0] dBusWishbone_CTI,
-      input   clk,
-      input   reset);
-  wire  _zz_220_;
-  wire  _zz_221_;
-  wire  _zz_222_;
-  wire  _zz_223_;
-  wire [31:0] _zz_224_;
-  wire  _zz_225_;
-  wire  _zz_226_;
-  wire  _zz_227_;
-  reg  _zz_228_;
-  reg  _zz_229_;
-  reg [31:0] _zz_230_;
-  reg  _zz_231_;
-  reg [31:0] _zz_232_;
-  reg [1:0] _zz_233_;
-  reg  _zz_234_;
-  reg  _zz_235_;
-  wire  _zz_236_;
-  wire [2:0] _zz_237_;
-  reg  _zz_238_;
-  wire [31:0] _zz_239_;
-  reg  _zz_240_;
-  reg  _zz_241_;
-  wire  _zz_242_;
-  wire [31:0] _zz_243_;
-  wire  _zz_244_;
-  wire  _zz_245_;
-  reg [31:0] _zz_246_;
-  reg [31:0] _zz_247_;
-  reg [31:0] _zz_248_;
-  reg  _zz_249_;
-  reg  _zz_250_;
-  reg  _zz_251_;
-  reg [9:0] _zz_252_;
-  reg [9:0] _zz_253_;
-  reg [9:0] _zz_254_;
-  reg [9:0] _zz_255_;
-  reg  _zz_256_;
-  reg  _zz_257_;
-  reg  _zz_258_;
-  reg  _zz_259_;
-  reg  _zz_260_;
-  reg  _zz_261_;
-  reg  _zz_262_;
-  reg [9:0] _zz_263_;
-  reg [9:0] _zz_264_;
-  reg [9:0] _zz_265_;
-  reg [9:0] _zz_266_;
-  reg  _zz_267_;
-  reg  _zz_268_;
-  reg  _zz_269_;
-  reg  _zz_270_;
-  wire  IBusCachedPlugin_cache_io_cpu_prefetch_haltIt;
-  wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data;
-  wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress;
-  wire  IBusCachedPlugin_cache_io_cpu_fetch_haltIt;
-  wire  IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid;
-  wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress;
-  wire  IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation;
-  wire  IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end;
-  wire  IBusCachedPlugin_cache_io_cpu_decode_error;
-  wire  IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling;
-  wire  IBusCachedPlugin_cache_io_cpu_decode_mmuException;
-  wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data;
-  wire  IBusCachedPlugin_cache_io_cpu_decode_cacheMiss;
-  wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress;
-  wire  IBusCachedPlugin_cache_io_mem_cmd_valid;
-  wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address;
-  wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size;
-  wire  dataCache_1__io_cpu_memory_isWrite;
-  wire  dataCache_1__io_cpu_memory_mmuBus_cmd_isValid;
-  wire [31:0] dataCache_1__io_cpu_memory_mmuBus_cmd_virtualAddress;
-  wire  dataCache_1__io_cpu_memory_mmuBus_cmd_bypassTranslation;
-  wire  dataCache_1__io_cpu_memory_mmuBus_end;
-  wire  dataCache_1__io_cpu_writeBack_haltIt;
-  wire [31:0] dataCache_1__io_cpu_writeBack_data;
-  wire  dataCache_1__io_cpu_writeBack_mmuException;
-  wire  dataCache_1__io_cpu_writeBack_unalignedAccess;
-  wire  dataCache_1__io_cpu_writeBack_accessError;
-  wire  dataCache_1__io_cpu_writeBack_isWrite;
-  wire  dataCache_1__io_cpu_flush_ready;
-  wire  dataCache_1__io_cpu_redo;
-  wire  dataCache_1__io_mem_cmd_valid;
-  wire  dataCache_1__io_mem_cmd_payload_wr;
-  wire [31:0] dataCache_1__io_mem_cmd_payload_address;
-  wire [31:0] dataCache_1__io_mem_cmd_payload_data;
-  wire [3:0] dataCache_1__io_mem_cmd_payload_mask;
-  wire [2:0] dataCache_1__io_mem_cmd_payload_length;
-  wire  dataCache_1__io_mem_cmd_payload_last;
-  wire  _zz_271_;
-  wire  _zz_272_;
-  wire  _zz_273_;
-  wire  _zz_274_;
-  wire  _zz_275_;
-  wire  _zz_276_;
-  wire  _zz_277_;
-  wire  _zz_278_;
-  wire  _zz_279_;
-  wire  _zz_280_;
-  wire  _zz_281_;
-  wire  _zz_282_;
-  wire  _zz_283_;
-  wire  _zz_284_;
-  wire  _zz_285_;
-  wire  _zz_286_;
-  wire  _zz_287_;
-  wire [1:0] _zz_288_;
-  wire  _zz_289_;
-  wire  _zz_290_;
-  wire  _zz_291_;
-  wire  _zz_292_;
-  wire  _zz_293_;
-  wire  _zz_294_;
-  wire  _zz_295_;
-  wire  _zz_296_;
-  wire  _zz_297_;
-  wire  _zz_298_;
-  wire  _zz_299_;
-  wire  _zz_300_;
-  wire  _zz_301_;
-  wire  _zz_302_;
-  wire  _zz_303_;
-  wire  _zz_304_;
-  wire  _zz_305_;
-  wire  _zz_306_;
-  wire  _zz_307_;
-  wire  _zz_308_;
-  wire  _zz_309_;
-  wire  _zz_310_;
-  wire  _zz_311_;
-  wire  _zz_312_;
-  wire  _zz_313_;
-  wire  _zz_314_;
-  wire  _zz_315_;
-  wire  _zz_316_;
-  wire  _zz_317_;
-  wire  _zz_318_;
-  wire  _zz_319_;
-  wire  _zz_320_;
-  wire  _zz_321_;
-  wire  _zz_322_;
-  wire  _zz_323_;
-  wire  _zz_324_;
-  wire  _zz_325_;
-  wire  _zz_326_;
-  wire  _zz_327_;
-  wire [1:0] _zz_328_;
-  wire  _zz_329_;
-  wire [3:0] _zz_330_;
-  wire [2:0] _zz_331_;
-  wire [31:0] _zz_332_;
-  wire [2:0] _zz_333_;
-  wire [2:0] _zz_334_;
-  wire [0:0] _zz_335_;
-  wire [1:0] _zz_336_;
-  wire [0:0] _zz_337_;
-  wire [1:0] _zz_338_;
-  wire [0:0] _zz_339_;
-  wire [0:0] _zz_340_;
-  wire [0:0] _zz_341_;
-  wire [0:0] _zz_342_;
-  wire [0:0] _zz_343_;
-  wire [0:0] _zz_344_;
-  wire [0:0] _zz_345_;
-  wire [0:0] _zz_346_;
-  wire [0:0] _zz_347_;
-  wire [0:0] _zz_348_;
-  wire [0:0] _zz_349_;
-  wire [0:0] _zz_350_;
-  wire [0:0] _zz_351_;
-  wire [0:0] _zz_352_;
-  wire [0:0] _zz_353_;
-  wire [0:0] _zz_354_;
-  wire [0:0] _zz_355_;
-  wire [0:0] _zz_356_;
-  wire [0:0] _zz_357_;
-  wire [0:0] _zz_358_;
-  wire [0:0] _zz_359_;
-  wire [0:0] _zz_360_;
-  wire [0:0] _zz_361_;
-  wire [0:0] _zz_362_;
-  wire [0:0] _zz_363_;
-  wire [0:0] _zz_364_;
-  wire [0:0] _zz_365_;
-  wire [0:0] _zz_366_;
-  wire [0:0] _zz_367_;
-  wire [2:0] _zz_368_;
-  wire [4:0] _zz_369_;
-  wire [11:0] _zz_370_;
-  wire [11:0] _zz_371_;
-  wire [31:0] _zz_372_;
-  wire [31:0] _zz_373_;
-  wire [31:0] _zz_374_;
-  wire [31:0] _zz_375_;
-  wire [31:0] _zz_376_;
-  wire [31:0] _zz_377_;
-  wire [31:0] _zz_378_;
-  wire [32:0] _zz_379_;
-  wire [31:0] _zz_380_;
-  wire [32:0] _zz_381_;
-  wire [19:0] _zz_382_;
-  wire [11:0] _zz_383_;
-  wire [11:0] _zz_384_;
-  wire [1:0] _zz_385_;
-  wire [1:0] _zz_386_;
-  wire [0:0] _zz_387_;
-  wire [5:0] _zz_388_;
-  wire [33:0] _zz_389_;
-  wire [32:0] _zz_390_;
-  wire [33:0] _zz_391_;
-  wire [32:0] _zz_392_;
-  wire [33:0] _zz_393_;
-  wire [32:0] _zz_394_;
-  wire [0:0] _zz_395_;
-  wire [5:0] _zz_396_;
-  wire [32:0] _zz_397_;
-  wire [32:0] _zz_398_;
-  wire [31:0] _zz_399_;
-  wire [31:0] _zz_400_;
-  wire [32:0] _zz_401_;
-  wire [32:0] _zz_402_;
-  wire [32:0] _zz_403_;
-  wire [0:0] _zz_404_;
-  wire [32:0] _zz_405_;
-  wire [0:0] _zz_406_;
-  wire [32:0] _zz_407_;
-  wire [0:0] _zz_408_;
-  wire [31:0] _zz_409_;
-  wire [0:0] _zz_410_;
-  wire [0:0] _zz_411_;
-  wire [0:0] _zz_412_;
-  wire [0:0] _zz_413_;
-  wire [0:0] _zz_414_;
-  wire [0:0] _zz_415_;
-  wire [0:0] _zz_416_;
-  wire [0:0] _zz_417_;
-  wire [0:0] _zz_418_;
-  wire [0:0] _zz_419_;
-  wire [0:0] _zz_420_;
-  wire [0:0] _zz_421_;
-  wire [0:0] _zz_422_;
-  wire [0:0] _zz_423_;
-  wire [0:0] _zz_424_;
-  wire [0:0] _zz_425_;
-  wire [0:0] _zz_426_;
-  wire [0:0] _zz_427_;
-  wire [0:0] _zz_428_;
-  wire [0:0] _zz_429_;
-  wire [0:0] _zz_430_;
-  wire [0:0] _zz_431_;
-  wire [0:0] _zz_432_;
-  wire [0:0] _zz_433_;
-  wire [0:0] _zz_434_;
-  wire [0:0] _zz_435_;
-  wire [0:0] _zz_436_;
-  wire [0:0] _zz_437_;
-  wire [0:0] _zz_438_;
-  wire [0:0] _zz_439_;
-  wire [0:0] _zz_440_;
-  wire [0:0] _zz_441_;
-  wire [0:0] _zz_442_;
-  wire [0:0] _zz_443_;
-  wire [0:0] _zz_444_;
-  wire [0:0] _zz_445_;
-  wire [0:0] _zz_446_;
-  wire [0:0] _zz_447_;
-  wire [0:0] _zz_448_;
-  wire [0:0] _zz_449_;
-  wire [0:0] _zz_450_;
-  wire [0:0] _zz_451_;
-  wire [0:0] _zz_452_;
-  wire [0:0] _zz_453_;
-  wire [0:0] _zz_454_;
-  wire [26:0] _zz_455_;
-  wire  _zz_456_;
-  wire  _zz_457_;
-  wire [1:0] _zz_458_;
-  wire [31:0] _zz_459_;
-  wire  _zz_460_;
-  wire [0:0] _zz_461_;
-  wire [1:0] _zz_462_;
-  wire [0:0] _zz_463_;
-  wire [1:0] _zz_464_;
-  wire [4:0] _zz_465_;
-  wire [4:0] _zz_466_;
-  wire  _zz_467_;
-  wire [0:0] _zz_468_;
-  wire [28:0] _zz_469_;
-  wire [31:0] _zz_470_;
-  wire [31:0] _zz_471_;
-  wire [31:0] _zz_472_;
-  wire  _zz_473_;
-  wire  _zz_474_;
-  wire [31:0] _zz_475_;
-  wire [31:0] _zz_476_;
-  wire  _zz_477_;
-  wire  _zz_478_;
-  wire  _zz_479_;
-  wire [0:0] _zz_480_;
-  wire [2:0] _zz_481_;
-  wire [0:0] _zz_482_;
-  wire [1:0] _zz_483_;
-  wire [1:0] _zz_484_;
-  wire [1:0] _zz_485_;
-  wire  _zz_486_;
-  wire [0:0] _zz_487_;
-  wire [26:0] _zz_488_;
-  wire [31:0] _zz_489_;
-  wire [31:0] _zz_490_;
-  wire [31:0] _zz_491_;
-  wire [31:0] _zz_492_;
-  wire [31:0] _zz_493_;
-  wire [31:0] _zz_494_;
-  wire [31:0] _zz_495_;
-  wire  _zz_496_;
-  wire [0:0] _zz_497_;
-  wire [0:0] _zz_498_;
-  wire  _zz_499_;
-  wire  _zz_500_;
-  wire [0:0] _zz_501_;
-  wire [0:0] _zz_502_;
-  wire [1:0] _zz_503_;
-  wire [1:0] _zz_504_;
-  wire  _zz_505_;
-  wire [0:0] _zz_506_;
-  wire [24:0] _zz_507_;
-  wire [31:0] _zz_508_;
-  wire [31:0] _zz_509_;
-  wire [31:0] _zz_510_;
-  wire [31:0] _zz_511_;
-  wire [31:0] _zz_512_;
-  wire [31:0] _zz_513_;
-  wire [31:0] _zz_514_;
-  wire  _zz_515_;
-  wire [0:0] _zz_516_;
-  wire [0:0] _zz_517_;
-  wire [0:0] _zz_518_;
-  wire [0:0] _zz_519_;
-  wire  _zz_520_;
-  wire [0:0] _zz_521_;
-  wire [22:0] _zz_522_;
-  wire [31:0] _zz_523_;
-  wire [31:0] _zz_524_;
-  wire [31:0] _zz_525_;
-  wire [31:0] _zz_526_;
-  wire  _zz_527_;
-  wire [1:0] _zz_528_;
-  wire [1:0] _zz_529_;
-  wire  _zz_530_;
-  wire [0:0] _zz_531_;
-  wire [18:0] _zz_532_;
-  wire [31:0] _zz_533_;
-  wire [31:0] _zz_534_;
-  wire [31:0] _zz_535_;
-  wire [31:0] _zz_536_;
-  wire [31:0] _zz_537_;
-  wire [31:0] _zz_538_;
-  wire [31:0] _zz_539_;
-  wire [0:0] _zz_540_;
-  wire [0:0] _zz_541_;
-  wire  _zz_542_;
-  wire [0:0] _zz_543_;
-  wire [14:0] _zz_544_;
-  wire [31:0] _zz_545_;
-  wire [31:0] _zz_546_;
-  wire [31:0] _zz_547_;
-  wire [31:0] _zz_548_;
-  wire  _zz_549_;
-  wire [0:0] _zz_550_;
-  wire [3:0] _zz_551_;
-  wire  _zz_552_;
-  wire [2:0] _zz_553_;
-  wire [2:0] _zz_554_;
-  wire  _zz_555_;
-  wire [0:0] _zz_556_;
-  wire [10:0] _zz_557_;
-  wire [31:0] _zz_558_;
-  wire [31:0] _zz_559_;
-  wire [31:0] _zz_560_;
-  wire  _zz_561_;
-  wire [0:0] _zz_562_;
-  wire [1:0] _zz_563_;
-  wire [31:0] _zz_564_;
-  wire [0:0] _zz_565_;
-  wire [0:0] _zz_566_;
-  wire [0:0] _zz_567_;
-  wire [3:0] _zz_568_;
-  wire [0:0] _zz_569_;
-  wire [0:0] _zz_570_;
-  wire  _zz_571_;
-  wire [0:0] _zz_572_;
-  wire [8:0] _zz_573_;
-  wire [31:0] _zz_574_;
-  wire [31:0] _zz_575_;
-  wire [31:0] _zz_576_;
-  wire  _zz_577_;
-  wire  _zz_578_;
-  wire  _zz_579_;
-  wire [0:0] _zz_580_;
-  wire [1:0] _zz_581_;
-  wire [31:0] _zz_582_;
-  wire [31:0] _zz_583_;
-  wire  _zz_584_;
-  wire [0:0] _zz_585_;
-  wire [0:0] _zz_586_;
-  wire  _zz_587_;
-  wire [0:0] _zz_588_;
-  wire [6:0] _zz_589_;
-  wire [31:0] _zz_590_;
-  wire [31:0] _zz_591_;
-  wire [31:0] _zz_592_;
-  wire [31:0] _zz_593_;
-  wire [31:0] _zz_594_;
-  wire  _zz_595_;
-  wire  _zz_596_;
-  wire [31:0] _zz_597_;
-  wire [31:0] _zz_598_;
-  wire [31:0] _zz_599_;
-  wire  _zz_600_;
-  wire [0:0] _zz_601_;
-  wire [0:0] _zz_602_;
-  wire  _zz_603_;
-  wire [0:0] _zz_604_;
-  wire [4:0] _zz_605_;
-  wire [31:0] _zz_606_;
-  wire  _zz_607_;
-  wire [0:0] _zz_608_;
-  wire [0:0] _zz_609_;
-  wire  _zz_610_;
-  wire [0:0] _zz_611_;
-  wire [0:0] _zz_612_;
-  wire  _zz_613_;
-  wire [0:0] _zz_614_;
-  wire [1:0] _zz_615_;
-  wire [31:0] _zz_616_;
-  wire [31:0] _zz_617_;
-  wire [31:0] _zz_618_;
-  wire  _zz_619_;
-  wire  _zz_620_;
-  wire [0:0] _zz_621_;
-  wire [1:0] _zz_622_;
-  wire [6:0] _zz_623_;
-  wire [6:0] _zz_624_;
-  wire [0:0] _zz_625_;
-  wire [0:0] _zz_626_;
-  wire [31:0] _zz_627_;
-  wire [31:0] _zz_628_;
-  wire [31:0] _zz_629_;
-  wire [31:0] _zz_630_;
-  wire  _zz_631_;
-  wire [0:0] _zz_632_;
-  wire [2:0] _zz_633_;
-  wire [31:0] _zz_634_;
-  wire [31:0] _zz_635_;
-  wire [31:0] _zz_636_;
-  wire  _zz_637_;
-  wire [0:0] _zz_638_;
-  wire [17:0] _zz_639_;
-  wire [31:0] _zz_640_;
-  wire [31:0] _zz_641_;
-  wire [31:0] _zz_642_;
-  wire  _zz_643_;
-  wire [0:0] _zz_644_;
-  wire [11:0] _zz_645_;
-  wire [31:0] _zz_646_;
-  wire [31:0] _zz_647_;
-  wire [31:0] _zz_648_;
-  wire  _zz_649_;
-  wire [0:0] _zz_650_;
-  wire [5:0] _zz_651_;
-  wire [31:0] _zz_652_;
-  wire [31:0] _zz_653_;
-  wire [31:0] _zz_654_;
-  wire  _zz_655_;
-  wire  _zz_656_;
-  wire  decode_SRC2_FORCE_ZERO;
-  wire  decode_BYPASSABLE_EXECUTE_STAGE;
-  wire  decode_IS_RS2_SIGNED;
-  wire [31:0] execute_BRANCH_CALC;
-  wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL;
-  wire `BranchCtrlEnum_defaultEncoding_type _zz_1_;
-  wire `BranchCtrlEnum_defaultEncoding_type _zz_2_;
-  wire `BranchCtrlEnum_defaultEncoding_type _zz_3_;
-  wire  decode_CSR_WRITE_OPCODE;
-  wire [31:0] execute_REGFILE_WRITE_DATA;
-  wire  memory_IS_SFENCE_VMA;
-  wire  execute_IS_SFENCE_VMA;
-  wire  decode_IS_SFENCE_VMA;
-  wire  execute_IS_DBUS_SHARING;
-  wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL;
-  wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_4_;
-  wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_5_;
-  wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_6_;
-  wire [1:0] memory_MEMORY_ADDRESS_LOW;
-  wire [1:0] execute_MEMORY_ADDRESS_LOW;
-  wire  decode_IS_DIV;
-  wire  decode_IS_RS1_SIGNED;
-  wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL;
-  wire `Src1CtrlEnum_defaultEncoding_type _zz_7_;
-  wire `Src1CtrlEnum_defaultEncoding_type _zz_8_;
-  wire `Src1CtrlEnum_defaultEncoding_type _zz_9_;
-  wire  memory_MEMORY_WR;
-  wire  decode_MEMORY_WR;
-  wire [31:0] writeBack_FORMAL_PC_NEXT;
-  wire [31:0] memory_FORMAL_PC_NEXT;
-  wire [31:0] execute_FORMAL_PC_NEXT;
-  wire [31:0] decode_FORMAL_PC_NEXT;
-  wire  decode_MEMORY_AMO;
-  wire  decode_CSR_READ_OPCODE;
-  wire  execute_BYPASSABLE_MEMORY_STAGE;
-  wire  decode_BYPASSABLE_MEMORY_STAGE;
-  wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL;
-  wire `Src2CtrlEnum_defaultEncoding_type _zz_10_;
-  wire `Src2CtrlEnum_defaultEncoding_type _zz_11_;
-  wire `Src2CtrlEnum_defaultEncoding_type _zz_12_;
-  wire [31:0] memory_PC;
-  wire `EnvCtrlEnum_defaultEncoding_type _zz_13_;
-  wire `EnvCtrlEnum_defaultEncoding_type _zz_14_;
-  wire `EnvCtrlEnum_defaultEncoding_type _zz_15_;
-  wire `EnvCtrlEnum_defaultEncoding_type _zz_16_;
-  wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL;
-  wire `EnvCtrlEnum_defaultEncoding_type _zz_17_;
-  wire `EnvCtrlEnum_defaultEncoding_type _zz_18_;
-  wire `EnvCtrlEnum_defaultEncoding_type _zz_19_;
-  wire  decode_SRC_LESS_UNSIGNED;
-  wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL;
-  wire `AluCtrlEnum_defaultEncoding_type _zz_20_;
-  wire `AluCtrlEnum_defaultEncoding_type _zz_21_;
-  wire `AluCtrlEnum_defaultEncoding_type _zz_22_;
-  wire [31:0] execute_SHIFT_RIGHT;
-  wire  decode_IS_CSR;
-  wire  decode_IS_MUL;
-  wire  decode_MEMORY_MANAGMENT;
-  wire `ShiftCtrlEnum_defaultEncoding_type _zz_23_;
-  wire `ShiftCtrlEnum_defaultEncoding_type _zz_24_;
-  wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL;
-  wire `ShiftCtrlEnum_defaultEncoding_type _zz_25_;
-  wire `ShiftCtrlEnum_defaultEncoding_type _zz_26_;
-  wire `ShiftCtrlEnum_defaultEncoding_type _zz_27_;
-  wire  decode_MEMORY_LRSC;
-  wire  execute_BRANCH_DO;
-  wire  execute_IS_RS1_SIGNED;
-  wire  execute_IS_DIV;
-  wire  execute_IS_MUL;
-  wire  execute_IS_RS2_SIGNED;
-  wire  memory_IS_DIV;
-  wire  memory_IS_MUL;
-  wire  execute_CSR_READ_OPCODE;
-  wire  execute_CSR_WRITE_OPCODE;
-  wire  execute_IS_CSR;
-  wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL;
-  wire `EnvCtrlEnum_defaultEncoding_type _zz_28_;
-  wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL;
-  wire `EnvCtrlEnum_defaultEncoding_type _zz_29_;
-  wire  _zz_30_;
-  wire  _zz_31_;
-  wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL;
-  wire `EnvCtrlEnum_defaultEncoding_type _zz_32_;
-  wire [31:0] memory_BRANCH_CALC;
-  wire  memory_BRANCH_DO;
-  wire [31:0] _zz_33_;
-  wire [31:0] execute_PC;
-  wire [31:0] execute_RS1;
-  wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL;
-  wire `BranchCtrlEnum_defaultEncoding_type _zz_34_;
-  wire  _zz_35_;
-  wire  decode_RS2_USE;
-  wire  decode_RS1_USE;
-  reg [31:0] _zz_36_;
-  wire  execute_REGFILE_WRITE_VALID;
-  wire  execute_BYPASSABLE_EXECUTE_STAGE;
-  wire  memory_REGFILE_WRITE_VALID;
-  wire [31:0] memory_INSTRUCTION;
-  wire  memory_BYPASSABLE_MEMORY_STAGE;
-  wire  writeBack_REGFILE_WRITE_VALID;
-  reg [31:0] decode_RS2;
-  reg [31:0] decode_RS1;
-  wire [31:0] memory_SHIFT_RIGHT;
-  reg [31:0] _zz_37_;
-  wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL;
-  wire `ShiftCtrlEnum_defaultEncoding_type _zz_38_;
-  wire [31:0] _zz_39_;
-  wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL;
-  wire `ShiftCtrlEnum_defaultEncoding_type _zz_40_;
-  wire  _zz_41_;
-  wire [31:0] _zz_42_;
-  wire [31:0] _zz_43_;
-  wire  execute_SRC_LESS_UNSIGNED;
-  wire  execute_SRC2_FORCE_ZERO;
-  wire  execute_SRC_USE_SUB_LESS;
-  wire [31:0] _zz_44_;
-  wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL;
-  wire `Src2CtrlEnum_defaultEncoding_type _zz_45_;
-  wire [31:0] _zz_46_;
-  wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL;
-  wire `Src1CtrlEnum_defaultEncoding_type _zz_47_;
-  wire [31:0] _zz_48_;
-  wire  decode_SRC_USE_SUB_LESS;
-  wire  decode_SRC_ADD_ZERO;
-  wire  _zz_49_;
-  wire [31:0] execute_SRC_ADD_SUB;
-  wire  execute_SRC_LESS;
-  wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL;
-  wire `AluCtrlEnum_defaultEncoding_type _zz_50_;
-  wire [31:0] _zz_51_;
-  wire [31:0] execute_SRC2;
-  wire [31:0] execute_SRC1;
-  wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL;
-  wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_52_;
-  wire [31:0] _zz_53_;
-  wire  _zz_54_;
-  reg  _zz_55_;
-  wire [31:0] _zz_56_;
-  wire [31:0] _zz_57_;
-  wire [31:0] decode_INSTRUCTION_ANTICIPATED;
-  reg  decode_REGFILE_WRITE_VALID;
-  wire  decode_LEGAL_INSTRUCTION;
-  wire  decode_INSTRUCTION_READY;
-  wire  _zz_58_;
-  wire  _zz_59_;
-  wire  _zz_60_;
-  wire  _zz_61_;
-  wire `Src1CtrlEnum_defaultEncoding_type _zz_62_;
-  wire `Src2CtrlEnum_defaultEncoding_type _zz_63_;
-  wire  _zz_64_;
-  wire  _zz_65_;
-  wire `BranchCtrlEnum_defaultEncoding_type _zz_66_;
-  wire  _zz_67_;
-  wire  _zz_68_;
-  wire  _zz_69_;
-  wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_70_;
-  wire  _zz_71_;
-  wire  _zz_72_;
-  wire  _zz_73_;
-  wire  _zz_74_;
-  wire  _zz_75_;
-  wire  _zz_76_;
-  wire  _zz_77_;
-  wire `EnvCtrlEnum_defaultEncoding_type _zz_78_;
-  wire  _zz_79_;
-  wire  _zz_80_;
-  wire `AluCtrlEnum_defaultEncoding_type _zz_81_;
-  wire `ShiftCtrlEnum_defaultEncoding_type _zz_82_;
-  wire  _zz_83_;
-  wire  _zz_84_;
-  wire  _zz_85_;
-  wire  writeBack_IS_SFENCE_VMA;
-  wire  writeBack_IS_DBUS_SHARING;
-  wire  memory_IS_DBUS_SHARING;
-  wire  _zz_86_;
-  reg [31:0] _zz_87_;
-  wire [1:0] writeBack_MEMORY_ADDRESS_LOW;
-  wire  writeBack_MEMORY_WR;
-  wire [31:0] writeBack_REGFILE_WRITE_DATA;
-  wire  writeBack_MEMORY_ENABLE;
-  wire [31:0] memory_REGFILE_WRITE_DATA;
-  wire  memory_MEMORY_ENABLE;
-  wire [1:0] _zz_88_;
-  wire  execute_MEMORY_AMO;
-  wire  execute_MEMORY_LRSC;
-  wire  execute_MEMORY_MANAGMENT;
-  wire [31:0] execute_RS2;
-  wire  execute_MEMORY_WR;
-  wire [31:0] execute_SRC_ADD;
-  wire  execute_MEMORY_ENABLE;
-  wire [31:0] execute_INSTRUCTION;
-  wire  decode_MEMORY_ENABLE;
-  wire  decode_FLUSH_ALL;
-  reg  IBusCachedPlugin_rsp_issueDetected;
-  reg  _zz_89_;
-  reg  _zz_90_;
-  reg  _zz_91_;
-  wire [31:0] decode_INSTRUCTION;
-  wire [31:0] _zz_92_;
-  reg [31:0] _zz_93_;
-  reg [31:0] _zz_94_;
-  wire [31:0] decode_PC;
-  wire [31:0] _zz_95_;
-  wire [31:0] _zz_96_;
-  wire [31:0] _zz_97_;
-  wire [31:0] writeBack_PC;
-  wire [31:0] writeBack_INSTRUCTION;
-  reg  decode_arbitration_haltItself;
-  reg  decode_arbitration_haltByOther;
-  reg  decode_arbitration_removeIt;
-  wire  decode_arbitration_flushIt;
-  reg  decode_arbitration_flushNext;
-  wire  decode_arbitration_isValid;
-  wire  decode_arbitration_isStuck;
-  wire  decode_arbitration_isStuckByOthers;
-  wire  decode_arbitration_isFlushed;
-  wire  decode_arbitration_isMoving;
-  wire  decode_arbitration_isFiring;
-  reg  execute_arbitration_haltItself;
-  wire  execute_arbitration_haltByOther;
-  reg  execute_arbitration_removeIt;
-  wire  execute_arbitration_flushIt;
-  reg  execute_arbitration_flushNext;
-  reg  execute_arbitration_isValid;
-  wire  execute_arbitration_isStuck;
-  wire  execute_arbitration_isStuckByOthers;
-  wire  execute_arbitration_isFlushed;
-  wire  execute_arbitration_isMoving;
-  wire  execute_arbitration_isFiring;
-  reg  memory_arbitration_haltItself;
-  wire  memory_arbitration_haltByOther;
-  reg  memory_arbitration_removeIt;
-  wire  memory_arbitration_flushIt;
-  reg  memory_arbitration_flushNext;
-  reg  memory_arbitration_isValid;
-  wire  memory_arbitration_isStuck;
-  wire  memory_arbitration_isStuckByOthers;
-  wire  memory_arbitration_isFlushed;
-  wire  memory_arbitration_isMoving;
-  wire  memory_arbitration_isFiring;
-  reg  writeBack_arbitration_haltItself;
-  wire  writeBack_arbitration_haltByOther;
-  reg  writeBack_arbitration_removeIt;
-  reg  writeBack_arbitration_flushIt;
-  reg  writeBack_arbitration_flushNext;
-  reg  writeBack_arbitration_isValid;
-  wire  writeBack_arbitration_isStuck;
-  wire  writeBack_arbitration_isStuckByOthers;
-  wire  writeBack_arbitration_isFlushed;
-  wire  writeBack_arbitration_isMoving;
-  wire  writeBack_arbitration_isFiring;
-  wire [31:0] lastStageInstruction /* verilator public */ ;
-  wire [31:0] lastStagePc /* verilator public */ ;
-  wire  lastStageIsValid /* verilator public */ ;
-  wire  lastStageIsFiring /* verilator public */ ;
-  reg  IBusCachedPlugin_fetcherHalt;
-  reg  IBusCachedPlugin_fetcherflushIt;
-  reg  IBusCachedPlugin_incomingInstruction;
-  wire  IBusCachedPlugin_pcValids_0;
-  wire  IBusCachedPlugin_pcValids_1;
-  wire  IBusCachedPlugin_pcValids_2;
-  wire  IBusCachedPlugin_pcValids_3;
-  wire  IBusCachedPlugin_redoBranch_valid;
-  wire [31:0] IBusCachedPlugin_redoBranch_payload;
-  reg  IBusCachedPlugin_decodeExceptionPort_valid;
-  reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code;
-  wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr;
-  wire  IBusCachedPlugin_mmuBus_cmd_isValid;
-  wire [31:0] IBusCachedPlugin_mmuBus_cmd_virtualAddress;
-  wire  IBusCachedPlugin_mmuBus_cmd_bypassTranslation;
-  reg [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress;
-  wire  IBusCachedPlugin_mmuBus_rsp_isIoAccess;
-  reg  IBusCachedPlugin_mmuBus_rsp_allowRead;
-  reg  IBusCachedPlugin_mmuBus_rsp_allowWrite;
-  reg  IBusCachedPlugin_mmuBus_rsp_allowExecute;
-  reg  IBusCachedPlugin_mmuBus_rsp_exception;
-  reg  IBusCachedPlugin_mmuBus_rsp_refilling;
-  wire  IBusCachedPlugin_mmuBus_end;
-  wire  IBusCachedPlugin_mmuBus_busy;
-  wire  DBusCachedPlugin_mmuBus_cmd_isValid;
-  wire [31:0] DBusCachedPlugin_mmuBus_cmd_virtualAddress;
-  reg  DBusCachedPlugin_mmuBus_cmd_bypassTranslation;
-  reg [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress;
-  wire  DBusCachedPlugin_mmuBus_rsp_isIoAccess;
-  reg  DBusCachedPlugin_mmuBus_rsp_allowRead;
-  reg  DBusCachedPlugin_mmuBus_rsp_allowWrite;
-  reg  DBusCachedPlugin_mmuBus_rsp_allowExecute;
-  reg  DBusCachedPlugin_mmuBus_rsp_exception;
-  reg  DBusCachedPlugin_mmuBus_rsp_refilling;
-  wire  DBusCachedPlugin_mmuBus_end;
-  wire  DBusCachedPlugin_mmuBus_busy;
-  reg  DBusCachedPlugin_redoBranch_valid;
-  wire [31:0] DBusCachedPlugin_redoBranch_payload;
-  reg  DBusCachedPlugin_exceptionBus_valid;
-  reg [3:0] DBusCachedPlugin_exceptionBus_payload_code;
-  wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr;
-  reg  MmuPlugin_dBusAccess_cmd_valid;
-  reg  MmuPlugin_dBusAccess_cmd_ready;
-  reg [31:0] MmuPlugin_dBusAccess_cmd_payload_address;
-  wire [1:0] MmuPlugin_dBusAccess_cmd_payload_size;
-  wire  MmuPlugin_dBusAccess_cmd_payload_write;
-  wire [31:0] MmuPlugin_dBusAccess_cmd_payload_data;
-  wire [3:0] MmuPlugin_dBusAccess_cmd_payload_writeMask;
-  wire  MmuPlugin_dBusAccess_rsp_valid;
-  wire [31:0] MmuPlugin_dBusAccess_rsp_payload_data;
-  wire  MmuPlugin_dBusAccess_rsp_payload_error;
-  wire  MmuPlugin_dBusAccess_rsp_payload_redo;
-  wire  decodeExceptionPort_valid;
-  wire [3:0] decodeExceptionPort_payload_code;
-  wire [31:0] decodeExceptionPort_payload_badAddr;
-  wire  BranchPlugin_jumpInterface_valid;
-  wire [31:0] BranchPlugin_jumpInterface_payload;
-  wire  BranchPlugin_branchExceptionPort_valid;
-  wire [3:0] BranchPlugin_branchExceptionPort_payload_code;
-  wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr;
-  reg  CsrPlugin_jumpInterface_valid;
-  reg [31:0] CsrPlugin_jumpInterface_payload;
-  wire  CsrPlugin_exceptionPendings_0;
-  wire  CsrPlugin_exceptionPendings_1;
-  wire  CsrPlugin_exceptionPendings_2;
-  wire  CsrPlugin_exceptionPendings_3;
-  wire  externalInterrupt;
-  wire  externalInterruptS;
-  wire  contextSwitching;
-  reg [1:0] CsrPlugin_privilege;
-  wire  CsrPlugin_forceMachineWire;
-  reg  CsrPlugin_selfException_valid;
-  reg [3:0] CsrPlugin_selfException_payload_code;
-  wire [31:0] CsrPlugin_selfException_payload_badAddr;
-  wire  CsrPlugin_allowInterrupts;
-  wire  CsrPlugin_allowException;
-  wire  IBusCachedPlugin_jump_pcLoad_valid;
-  wire [31:0] IBusCachedPlugin_jump_pcLoad_payload;
-  wire [3:0] _zz_98_;
-  wire [3:0] _zz_99_;
-  wire  _zz_100_;
-  wire  _zz_101_;
-  wire  _zz_102_;
-  wire  IBusCachedPlugin_fetchPc_output_valid;
-  wire  IBusCachedPlugin_fetchPc_output_ready;
-  wire [31:0] IBusCachedPlugin_fetchPc_output_payload;
-  reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ;
-  reg  IBusCachedPlugin_fetchPc_corrected;
-  reg  IBusCachedPlugin_fetchPc_pcRegPropagate;
-  reg  IBusCachedPlugin_fetchPc_booted;
-  reg  IBusCachedPlugin_fetchPc_inc;
-  reg [31:0] IBusCachedPlugin_fetchPc_pc;
-  wire  IBusCachedPlugin_iBusRsp_stages_0_input_valid;
-  wire  IBusCachedPlugin_iBusRsp_stages_0_input_ready;
-  wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload;
-  wire  IBusCachedPlugin_iBusRsp_stages_0_output_valid;
-  wire  IBusCachedPlugin_iBusRsp_stages_0_output_ready;
-  wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload;
-  wire  IBusCachedPlugin_iBusRsp_stages_0_halt;
-  wire  IBusCachedPlugin_iBusRsp_stages_0_inputSample;
-  wire  IBusCachedPlugin_iBusRsp_stages_1_input_valid;
-  wire  IBusCachedPlugin_iBusRsp_stages_1_input_ready;
-  wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload;
-  wire  IBusCachedPlugin_iBusRsp_stages_1_output_valid;
-  wire  IBusCachedPlugin_iBusRsp_stages_1_output_ready;
-  wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload;
-  reg  IBusCachedPlugin_iBusRsp_stages_1_halt;
-  wire  IBusCachedPlugin_iBusRsp_stages_1_inputSample;
-  wire  IBusCachedPlugin_iBusRsp_stages_2_input_valid;
-  wire  IBusCachedPlugin_iBusRsp_stages_2_input_ready;
-  wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_input_payload;
-  wire  IBusCachedPlugin_iBusRsp_stages_2_output_valid;
-  wire  IBusCachedPlugin_iBusRsp_stages_2_output_ready;
-  wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload;
-  reg  IBusCachedPlugin_iBusRsp_stages_2_halt;
-  wire  IBusCachedPlugin_iBusRsp_stages_2_inputSample;
-  wire  IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid;
-  wire  IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready;
-  wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload;
-  wire  IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid;
-  wire  IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready;
-  wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload;
-  reg  IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt;
-  wire  IBusCachedPlugin_iBusRsp_cacheRspArbitration_inputSample;
-  wire  _zz_103_;
-  wire  _zz_104_;
-  wire  _zz_105_;
-  wire  _zz_106_;
-  wire  _zz_107_;
-  wire  _zz_108_;
-  reg  _zz_109_;
-  wire  _zz_110_;
-  reg  _zz_111_;
-  reg [31:0] _zz_112_;
-  wire  _zz_113_;
-  reg  _zz_114_;
-  reg [31:0] _zz_115_;
-  reg  IBusCachedPlugin_iBusRsp_readyForError;
-  wire  IBusCachedPlugin_iBusRsp_decodeInput_valid;
-  wire  IBusCachedPlugin_iBusRsp_decodeInput_ready;
-  wire [31:0] IBusCachedPlugin_iBusRsp_decodeInput_payload_pc;
-  wire  IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_error;
-  wire [31:0] IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst;
-  wire  IBusCachedPlugin_iBusRsp_decodeInput_payload_isRvc;
-  reg  IBusCachedPlugin_injector_nextPcCalc_valids_0;
-  reg  IBusCachedPlugin_injector_nextPcCalc_valids_1;
-  reg  IBusCachedPlugin_injector_nextPcCalc_valids_2;
-  reg  IBusCachedPlugin_injector_nextPcCalc_valids_3;
-  reg  IBusCachedPlugin_injector_nextPcCalc_valids_4;
-  reg  IBusCachedPlugin_injector_nextPcCalc_valids_5;
-  reg  IBusCachedPlugin_injector_decodeRemoved;
-  wire  iBus_cmd_valid;
-  wire  iBus_cmd_ready;
-  reg [31:0] iBus_cmd_payload_address;
-  wire [2:0] iBus_cmd_payload_size;
-  wire  iBus_rsp_valid;
-  wire [31:0] iBus_rsp_payload_data;
-  wire  iBus_rsp_payload_error;
-  wire [31:0] _zz_116_;
-  reg [31:0] IBusCachedPlugin_rspCounter;
-  wire  IBusCachedPlugin_s0_tightlyCoupledHit;
-  reg  IBusCachedPlugin_s1_tightlyCoupledHit;
-  reg  IBusCachedPlugin_s2_tightlyCoupledHit;
-  wire  IBusCachedPlugin_rsp_iBusRspOutputHalt;
-  reg  IBusCachedPlugin_rsp_redoFetch;
-  wire  dBus_cmd_valid;
-  wire  dBus_cmd_ready;
-  wire  dBus_cmd_payload_wr;
-  wire [31:0] dBus_cmd_payload_address;
-  wire [31:0] dBus_cmd_payload_data;
-  wire [3:0] dBus_cmd_payload_mask;
-  wire [2:0] dBus_cmd_payload_length;
-  wire  dBus_cmd_payload_last;
-  wire  dBus_rsp_valid;
-  wire [31:0] dBus_rsp_payload_data;
-  wire  dBus_rsp_payload_error;
-  wire  dataCache_1__io_mem_cmd_s2mPipe_valid;
-  wire  dataCache_1__io_mem_cmd_s2mPipe_ready;
-  wire  dataCache_1__io_mem_cmd_s2mPipe_payload_wr;
-  wire [31:0] dataCache_1__io_mem_cmd_s2mPipe_payload_address;
-  wire [31:0] dataCache_1__io_mem_cmd_s2mPipe_payload_data;
-  wire [3:0] dataCache_1__io_mem_cmd_s2mPipe_payload_mask;
-  wire [2:0] dataCache_1__io_mem_cmd_s2mPipe_payload_length;
-  wire  dataCache_1__io_mem_cmd_s2mPipe_payload_last;
-  reg  _zz_117_;
-  reg  _zz_118_;
-  reg [31:0] _zz_119_;
-  reg [31:0] _zz_120_;
-  reg [3:0] _zz_121_;
-  reg [2:0] _zz_122_;
-  reg  _zz_123_;
-  wire  dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_valid;
-  wire  dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_ready;
-  wire  dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_wr;
-  wire [31:0] dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_address;
-  wire [31:0] dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_data;
-  wire [3:0] dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_mask;
-  wire [2:0] dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_length;
-  wire  dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_last;
-  reg  _zz_124_;
-  reg  _zz_125_;
-  reg [31:0] _zz_126_;
-  reg [31:0] _zz_127_;
-  reg [3:0] _zz_128_;
-  reg [2:0] _zz_129_;
-  reg  _zz_130_;
-  wire [31:0] _zz_131_;
-  reg [31:0] DBusCachedPlugin_rspCounter;
-  wire [1:0] execute_DBusCachedPlugin_size;
-  reg [31:0] _zz_132_;
-  reg [31:0] writeBack_DBusCachedPlugin_rspShifted;
-  wire  _zz_133_;
-  reg [31:0] _zz_134_;
-  wire  _zz_135_;
-  reg [31:0] _zz_136_;
-  reg [31:0] writeBack_DBusCachedPlugin_rspFormated;
-  reg  DBusCachedPlugin_forceDatapath;
-  reg  MmuPlugin_status_sum;
-  reg  MmuPlugin_status_mxr;
-  reg  MmuPlugin_status_mprv;
-  reg  MmuPlugin_satp_mode;
-  reg [19:0] MmuPlugin_satp_ppn;
-  reg  MmuPlugin_ports_0_cache_0_valid;
-  reg  MmuPlugin_ports_0_cache_0_exception;
-  reg  MmuPlugin_ports_0_cache_0_superPage;
-  reg [9:0] MmuPlugin_ports_0_cache_0_virtualAddress_0;
-  reg [9:0] MmuPlugin_ports_0_cache_0_virtualAddress_1;
-  reg [9:0] MmuPlugin_ports_0_cache_0_physicalAddress_0;
-  reg [9:0] MmuPlugin_ports_0_cache_0_physicalAddress_1;
-  reg  MmuPlugin_ports_0_cache_0_allowRead;
-  reg  MmuPlugin_ports_0_cache_0_allowWrite;
-  reg  MmuPlugin_ports_0_cache_0_allowExecute;
-  reg  MmuPlugin_ports_0_cache_0_allowUser;
-  reg  MmuPlugin_ports_0_cache_1_valid;
-  reg  MmuPlugin_ports_0_cache_1_exception;
-  reg  MmuPlugin_ports_0_cache_1_superPage;
-  reg [9:0] MmuPlugin_ports_0_cache_1_virtualAddress_0;
-  reg [9:0] MmuPlugin_ports_0_cache_1_virtualAddress_1;
-  reg [9:0] MmuPlugin_ports_0_cache_1_physicalAddress_0;
-  reg [9:0] MmuPlugin_ports_0_cache_1_physicalAddress_1;
-  reg  MmuPlugin_ports_0_cache_1_allowRead;
-  reg  MmuPlugin_ports_0_cache_1_allowWrite;
-  reg  MmuPlugin_ports_0_cache_1_allowExecute;
-  reg  MmuPlugin_ports_0_cache_1_allowUser;
-  reg  MmuPlugin_ports_0_cache_2_valid;
-  reg  MmuPlugin_ports_0_cache_2_exception;
-  reg  MmuPlugin_ports_0_cache_2_superPage;
-  reg [9:0] MmuPlugin_ports_0_cache_2_virtualAddress_0;
-  reg [9:0] MmuPlugin_ports_0_cache_2_virtualAddress_1;
-  reg [9:0] MmuPlugin_ports_0_cache_2_physicalAddress_0;
-  reg [9:0] MmuPlugin_ports_0_cache_2_physicalAddress_1;
-  reg  MmuPlugin_ports_0_cache_2_allowRead;
-  reg  MmuPlugin_ports_0_cache_2_allowWrite;
-  reg  MmuPlugin_ports_0_cache_2_allowExecute;
-  reg  MmuPlugin_ports_0_cache_2_allowUser;
-  reg  MmuPlugin_ports_0_cache_3_valid;
-  reg  MmuPlugin_ports_0_cache_3_exception;
-  reg  MmuPlugin_ports_0_cache_3_superPage;
-  reg [9:0] MmuPlugin_ports_0_cache_3_virtualAddress_0;
-  reg [9:0] MmuPlugin_ports_0_cache_3_virtualAddress_1;
-  reg [9:0] MmuPlugin_ports_0_cache_3_physicalAddress_0;
-  reg [9:0] MmuPlugin_ports_0_cache_3_physicalAddress_1;
-  reg  MmuPlugin_ports_0_cache_3_allowRead;
-  reg  MmuPlugin_ports_0_cache_3_allowWrite;
-  reg  MmuPlugin_ports_0_cache_3_allowExecute;
-  reg  MmuPlugin_ports_0_cache_3_allowUser;
-  wire  MmuPlugin_ports_0_cacheHits_0;
-  wire  MmuPlugin_ports_0_cacheHits_1;
-  wire  MmuPlugin_ports_0_cacheHits_2;
-  wire  MmuPlugin_ports_0_cacheHits_3;
-  wire  MmuPlugin_ports_0_cacheHit;
-  wire  _zz_137_;
-  wire  _zz_138_;
-  wire [1:0] _zz_139_;
-  wire  MmuPlugin_ports_0_cacheLine_valid;
-  wire  MmuPlugin_ports_0_cacheLine_exception;
-  wire  MmuPlugin_ports_0_cacheLine_superPage;
-  wire [9:0] MmuPlugin_ports_0_cacheLine_virtualAddress_0;
-  wire [9:0] MmuPlugin_ports_0_cacheLine_virtualAddress_1;
-  wire [9:0] MmuPlugin_ports_0_cacheLine_physicalAddress_0;
-  wire [9:0] MmuPlugin_ports_0_cacheLine_physicalAddress_1;
-  wire  MmuPlugin_ports_0_cacheLine_allowRead;
-  wire  MmuPlugin_ports_0_cacheLine_allowWrite;
-  wire  MmuPlugin_ports_0_cacheLine_allowExecute;
-  wire  MmuPlugin_ports_0_cacheLine_allowUser;
-  reg  MmuPlugin_ports_0_entryToReplace_willIncrement;
-  wire  MmuPlugin_ports_0_entryToReplace_willClear;
-  reg [1:0] MmuPlugin_ports_0_entryToReplace_valueNext;
-  reg [1:0] MmuPlugin_ports_0_entryToReplace_value;
-  wire  MmuPlugin_ports_0_entryToReplace_willOverflowIfInc;
-  wire  MmuPlugin_ports_0_entryToReplace_willOverflow;
-  reg  MmuPlugin_ports_0_requireMmuLockup;
-  reg  MmuPlugin_ports_1_cache_0_valid;
-  reg  MmuPlugin_ports_1_cache_0_exception;
-  reg  MmuPlugin_ports_1_cache_0_superPage;
-  reg [9:0] MmuPlugin_ports_1_cache_0_virtualAddress_0;
-  reg [9:0] MmuPlugin_ports_1_cache_0_virtualAddress_1;
-  reg [9:0] MmuPlugin_ports_1_cache_0_physicalAddress_0;
-  reg [9:0] MmuPlugin_ports_1_cache_0_physicalAddress_1;
-  reg  MmuPlugin_ports_1_cache_0_allowRead;
-  reg  MmuPlugin_ports_1_cache_0_allowWrite;
-  reg  MmuPlugin_ports_1_cache_0_allowExecute;
-  reg  MmuPlugin_ports_1_cache_0_allowUser;
-  reg  MmuPlugin_ports_1_cache_1_valid;
-  reg  MmuPlugin_ports_1_cache_1_exception;
-  reg  MmuPlugin_ports_1_cache_1_superPage;
-  reg [9:0] MmuPlugin_ports_1_cache_1_virtualAddress_0;
-  reg [9:0] MmuPlugin_ports_1_cache_1_virtualAddress_1;
-  reg [9:0] MmuPlugin_ports_1_cache_1_physicalAddress_0;
-  reg [9:0] MmuPlugin_ports_1_cache_1_physicalAddress_1;
-  reg  MmuPlugin_ports_1_cache_1_allowRead;
-  reg  MmuPlugin_ports_1_cache_1_allowWrite;
-  reg  MmuPlugin_ports_1_cache_1_allowExecute;
-  reg  MmuPlugin_ports_1_cache_1_allowUser;
-  reg  MmuPlugin_ports_1_cache_2_valid;
-  reg  MmuPlugin_ports_1_cache_2_exception;
-  reg  MmuPlugin_ports_1_cache_2_superPage;
-  reg [9:0] MmuPlugin_ports_1_cache_2_virtualAddress_0;
-  reg [9:0] MmuPlugin_ports_1_cache_2_virtualAddress_1;
-  reg [9:0] MmuPlugin_ports_1_cache_2_physicalAddress_0;
-  reg [9:0] MmuPlugin_ports_1_cache_2_physicalAddress_1;
-  reg  MmuPlugin_ports_1_cache_2_allowRead;
-  reg  MmuPlugin_ports_1_cache_2_allowWrite;
-  reg  MmuPlugin_ports_1_cache_2_allowExecute;
-  reg  MmuPlugin_ports_1_cache_2_allowUser;
-  reg  MmuPlugin_ports_1_cache_3_valid;
-  reg  MmuPlugin_ports_1_cache_3_exception;
-  reg  MmuPlugin_ports_1_cache_3_superPage;
-  reg [9:0] MmuPlugin_ports_1_cache_3_virtualAddress_0;
-  reg [9:0] MmuPlugin_ports_1_cache_3_virtualAddress_1;
-  reg [9:0] MmuPlugin_ports_1_cache_3_physicalAddress_0;
-  reg [9:0] MmuPlugin_ports_1_cache_3_physicalAddress_1;
-  reg  MmuPlugin_ports_1_cache_3_allowRead;
-  reg  MmuPlugin_ports_1_cache_3_allowWrite;
-  reg  MmuPlugin_ports_1_cache_3_allowExecute;
-  reg  MmuPlugin_ports_1_cache_3_allowUser;
-  wire  MmuPlugin_ports_1_cacheHits_0;
-  wire  MmuPlugin_ports_1_cacheHits_1;
-  wire  MmuPlugin_ports_1_cacheHits_2;
-  wire  MmuPlugin_ports_1_cacheHits_3;
-  wire  MmuPlugin_ports_1_cacheHit;
-  wire  _zz_140_;
-  wire  _zz_141_;
-  wire [1:0] _zz_142_;
-  wire  MmuPlugin_ports_1_cacheLine_valid;
-  wire  MmuPlugin_ports_1_cacheLine_exception;
-  wire  MmuPlugin_ports_1_cacheLine_superPage;
-  wire [9:0] MmuPlugin_ports_1_cacheLine_virtualAddress_0;
-  wire [9:0] MmuPlugin_ports_1_cacheLine_virtualAddress_1;
-  wire [9:0] MmuPlugin_ports_1_cacheLine_physicalAddress_0;
-  wire [9:0] MmuPlugin_ports_1_cacheLine_physicalAddress_1;
-  wire  MmuPlugin_ports_1_cacheLine_allowRead;
-  wire  MmuPlugin_ports_1_cacheLine_allowWrite;
-  wire  MmuPlugin_ports_1_cacheLine_allowExecute;
-  wire  MmuPlugin_ports_1_cacheLine_allowUser;
-  reg  MmuPlugin_ports_1_entryToReplace_willIncrement;
-  wire  MmuPlugin_ports_1_entryToReplace_willClear;
-  reg [1:0] MmuPlugin_ports_1_entryToReplace_valueNext;
-  reg [1:0] MmuPlugin_ports_1_entryToReplace_value;
-  wire  MmuPlugin_ports_1_entryToReplace_willOverflowIfInc;
-  wire  MmuPlugin_ports_1_entryToReplace_willOverflow;
-  reg  MmuPlugin_ports_1_requireMmuLockup;
-  reg `MmuPlugin_shared_State_defaultEncoding_type MmuPlugin_shared_state_1_;
-  reg [9:0] MmuPlugin_shared_vpn_0;
-  reg [9:0] MmuPlugin_shared_vpn_1;
-  reg [0:0] MmuPlugin_shared_portId;
-  wire  MmuPlugin_shared_dBusRsp_pte_V;
-  wire  MmuPlugin_shared_dBusRsp_pte_R;
-  wire  MmuPlugin_shared_dBusRsp_pte_W;
-  wire  MmuPlugin_shared_dBusRsp_pte_X;
-  wire  MmuPlugin_shared_dBusRsp_pte_U;
-  wire  MmuPlugin_shared_dBusRsp_pte_G;
-  wire  MmuPlugin_shared_dBusRsp_pte_A;
-  wire  MmuPlugin_shared_dBusRsp_pte_D;
-  wire [1:0] MmuPlugin_shared_dBusRsp_pte_RSW;
-  wire [9:0] MmuPlugin_shared_dBusRsp_pte_PPN0;
-  wire [11:0] MmuPlugin_shared_dBusRsp_pte_PPN1;
-  wire  MmuPlugin_shared_dBusRsp_exception;
-  wire  MmuPlugin_shared_dBusRsp_leaf;
-  reg  MmuPlugin_shared_pteBuffer_V;
-  reg  MmuPlugin_shared_pteBuffer_R;
-  reg  MmuPlugin_shared_pteBuffer_W;
-  reg  MmuPlugin_shared_pteBuffer_X;
-  reg  MmuPlugin_shared_pteBuffer_U;
-  reg  MmuPlugin_shared_pteBuffer_G;
-  reg  MmuPlugin_shared_pteBuffer_A;
-  reg  MmuPlugin_shared_pteBuffer_D;
-  reg [1:0] MmuPlugin_shared_pteBuffer_RSW;
-  reg [9:0] MmuPlugin_shared_pteBuffer_PPN0;
-  reg [11:0] MmuPlugin_shared_pteBuffer_PPN1;
-  wire [34:0] _zz_143_;
-  wire  _zz_144_;
-  wire  _zz_145_;
-  wire  _zz_146_;
-  wire  _zz_147_;
-  wire  _zz_148_;
-  wire  _zz_149_;
-  wire  _zz_150_;
-  wire  _zz_151_;
-  wire `ShiftCtrlEnum_defaultEncoding_type _zz_152_;
-  wire `AluCtrlEnum_defaultEncoding_type _zz_153_;
-  wire `EnvCtrlEnum_defaultEncoding_type _zz_154_;
-  wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_155_;
-  wire `BranchCtrlEnum_defaultEncoding_type _zz_156_;
-  wire `Src2CtrlEnum_defaultEncoding_type _zz_157_;
-  wire `Src1CtrlEnum_defaultEncoding_type _zz_158_;
-  wire [4:0] decode_RegFilePlugin_regFileReadAddress1;
-  wire [4:0] decode_RegFilePlugin_regFileReadAddress2;
-  wire [31:0] decode_RegFilePlugin_rs1Data;
-  wire [31:0] decode_RegFilePlugin_rs2Data;
-  reg  lastStageRegFileWrite_valid /* verilator public */ ;
-  wire [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ;
-  wire [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ;
-  reg  _zz_159_;
-  reg [31:0] execute_IntAluPlugin_bitwise;
-  reg [31:0] _zz_160_;
-  reg [31:0] _zz_161_;
-  wire  _zz_162_;
-  reg [19:0] _zz_163_;
-  wire  _zz_164_;
-  reg [19:0] _zz_165_;
-  reg [31:0] _zz_166_;
-  reg [31:0] execute_SrcPlugin_addSub;
-  wire  execute_SrcPlugin_less;
-  wire [4:0] execute_FullBarrelShifterPlugin_amplitude;
-  reg [31:0] _zz_167_;
-  wire [31:0] execute_FullBarrelShifterPlugin_reversed;
-  reg [31:0] _zz_168_;
-  reg  _zz_169_;
-  reg  _zz_170_;
-  wire  _zz_171_;
-  reg  _zz_172_;
-  reg [4:0] _zz_173_;
-  reg [31:0] _zz_174_;
-  wire  _zz_175_;
-  wire  _zz_176_;
-  wire  _zz_177_;
-  wire  _zz_178_;
-  wire  _zz_179_;
-  wire  _zz_180_;
-  wire  execute_BranchPlugin_eq;
-  wire [2:0] _zz_181_;
-  reg  _zz_182_;
-  reg  _zz_183_;
-  wire [31:0] execute_BranchPlugin_branch_src1;
-  wire  _zz_184_;
-  reg [10:0] _zz_185_;
-  wire  _zz_186_;
-  reg [19:0] _zz_187_;
-  wire  _zz_188_;
-  reg [18:0] _zz_189_;
-  reg [31:0] _zz_190_;
-  wire [31:0] execute_BranchPlugin_branch_src2;
-  wire [31:0] execute_BranchPlugin_branchAdder;
-  reg [1:0] _zz_191_;
-  wire [1:0] CsrPlugin_misa_base;
-  wire [25:0] CsrPlugin_misa_extensions;
-  reg [1:0] CsrPlugin_mtvec_mode;
-  reg [29:0] CsrPlugin_mtvec_base;
-  reg [31:0] CsrPlugin_mepc;
-  reg  CsrPlugin_mstatus_MIE;
-  reg  CsrPlugin_mstatus_MPIE;
-  reg [1:0] CsrPlugin_mstatus_MPP;
-  reg  CsrPlugin_mip_MEIP;
-  reg  CsrPlugin_mip_MTIP;
-  reg  CsrPlugin_mip_MSIP;
-  reg  CsrPlugin_mie_MEIE;
-  reg  CsrPlugin_mie_MTIE;
-  reg  CsrPlugin_mie_MSIE;
-  reg [31:0] CsrPlugin_mscratch;
-  reg  CsrPlugin_mcause_interrupt;
-  reg [3:0] CsrPlugin_mcause_exceptionCode;
-  reg [31:0] CsrPlugin_mtval;
-  reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000;
-  reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000;
-  reg  CsrPlugin_medeleg_IAM;
-  reg  CsrPlugin_medeleg_IAF;
-  reg  CsrPlugin_medeleg_II;
-  reg  CsrPlugin_medeleg_LAM;
-  reg  CsrPlugin_medeleg_LAF;
-  reg  CsrPlugin_medeleg_SAM;
-  reg  CsrPlugin_medeleg_SAF;
-  reg  CsrPlugin_medeleg_EU;
-  reg  CsrPlugin_medeleg_ES;
-  reg  CsrPlugin_medeleg_IPF;
-  reg  CsrPlugin_medeleg_LPF;
-  reg  CsrPlugin_medeleg_SPF;
-  reg  CsrPlugin_mideleg_ST;
-  reg  CsrPlugin_mideleg_SE;
-  reg  CsrPlugin_mideleg_SS;
-  reg  CsrPlugin_sstatus_SIE;
-  reg  CsrPlugin_sstatus_SPIE;
-  reg [0:0] CsrPlugin_sstatus_SPP;
-  reg  CsrPlugin_sip_SEIP_SOFT;
-  reg  CsrPlugin_sip_SEIP_INPUT;
-  wire  CsrPlugin_sip_SEIP_OR;
-  reg  CsrPlugin_sip_STIP;
-  reg  CsrPlugin_sip_SSIP;
-  reg  CsrPlugin_sie_SEIE;
-  reg  CsrPlugin_sie_STIE;
-  reg  CsrPlugin_sie_SSIE;
-  reg [1:0] CsrPlugin_stvec_mode;
-  reg [29:0] CsrPlugin_stvec_base;
-  reg [31:0] CsrPlugin_sscratch;
-  reg  CsrPlugin_scause_interrupt;
-  reg [3:0] CsrPlugin_scause_exceptionCode;
-  reg [31:0] CsrPlugin_stval;
-  reg [31:0] CsrPlugin_sepc;
-  reg [21:0] CsrPlugin_satp_PPN;
-  reg [8:0] CsrPlugin_satp_ASID;
-  reg [0:0] CsrPlugin_satp_MODE;
-  wire  _zz_192_;
-  wire  _zz_193_;
-  wire  _zz_194_;
-  wire  _zz_195_;
-  wire  _zz_196_;
-  wire  _zz_197_;
-  reg  CsrPlugin_exceptionPortCtrl_exceptionValids_decode;
-  reg  CsrPlugin_exceptionPortCtrl_exceptionValids_execute;
-  reg  CsrPlugin_exceptionPortCtrl_exceptionValids_memory;
-  reg  CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack;
-  reg  CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
-  reg  CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
-  reg  CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory;
-  reg  CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack;
-  reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code;
-  reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr;
-  reg [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped;
-  wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege;
-  wire [1:0] _zz_198_;
-  wire  _zz_199_;
-  reg  CsrPlugin_interrupt_valid;
-  reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ;
-  reg [1:0] CsrPlugin_interrupt_targetPrivilege;
-  wire  CsrPlugin_exception;
-  reg  CsrPlugin_lastStageWasWfi;
-  reg  CsrPlugin_pipelineLiberator_done;
-  wire  CsrPlugin_interruptJump /* verilator public */ ;
-  reg  CsrPlugin_hadException;
-  reg [1:0] CsrPlugin_targetPrivilege;
-  reg [3:0] CsrPlugin_trapCause;
-  reg [1:0] CsrPlugin_xtvec_mode;
-  reg [29:0] CsrPlugin_xtvec_base;
-  reg  execute_CsrPlugin_inWfi /* verilator public */ ;
-  reg  execute_CsrPlugin_wfiWake;
-  wire  execute_CsrPlugin_blockedBySideEffects;
-  reg  execute_CsrPlugin_illegalAccess;
-  reg  execute_CsrPlugin_illegalInstruction;
-  reg [31:0] execute_CsrPlugin_readData;
-  wire  execute_CsrPlugin_writeInstruction;
-  wire  execute_CsrPlugin_readInstruction;
-  wire  execute_CsrPlugin_writeEnable;
-  wire  execute_CsrPlugin_readEnable;
-  reg [31:0] execute_CsrPlugin_readToWriteData;
-  reg [31:0] execute_CsrPlugin_writeData;
-  wire [11:0] execute_CsrPlugin_csrAddress;
-  reg [32:0] memory_MulDivIterativePlugin_rs1;
-  reg [31:0] memory_MulDivIterativePlugin_rs2;
-  reg [64:0] memory_MulDivIterativePlugin_accumulator;
-  reg  memory_MulDivIterativePlugin_mul_counter_willIncrement;
-  reg  memory_MulDivIterativePlugin_mul_counter_willClear;
-  reg [5:0] memory_MulDivIterativePlugin_mul_counter_valueNext;
-  reg [5:0] memory_MulDivIterativePlugin_mul_counter_value;
-  wire  memory_MulDivIterativePlugin_mul_willOverflowIfInc;
-  wire  memory_MulDivIterativePlugin_mul_counter_willOverflow;
-  reg  memory_MulDivIterativePlugin_div_needRevert;
-  reg  memory_MulDivIterativePlugin_div_counter_willIncrement;
-  reg  memory_MulDivIterativePlugin_div_counter_willClear;
-  reg [5:0] memory_MulDivIterativePlugin_div_counter_valueNext;
-  reg [5:0] memory_MulDivIterativePlugin_div_counter_value;
-  wire  memory_MulDivIterativePlugin_div_counter_willOverflowIfInc;
-  wire  memory_MulDivIterativePlugin_div_counter_willOverflow;
-  reg  memory_MulDivIterativePlugin_div_done;
-  reg [31:0] memory_MulDivIterativePlugin_div_result;
-  wire [31:0] _zz_200_;
-  wire [32:0] _zz_201_;
-  wire [32:0] _zz_202_;
-  wire [31:0] _zz_203_;
-  wire  _zz_204_;
-  wire  _zz_205_;
-  reg [32:0] _zz_206_;
-  reg [31:0] externalInterruptArray_regNext;
-  reg [31:0] _zz_207_;
-  wire [31:0] _zz_208_;
-  reg [31:0] _zz_209_;
-  wire [31:0] _zz_210_;
-  reg  execute_to_memory_BRANCH_DO;
-  reg  decode_to_execute_MEMORY_LRSC;
-  reg [31:0] decode_to_execute_RS2;
-  reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL;
-  reg `ShiftCtrlEnum_defaultEncoding_type execute_to_memory_SHIFT_CTRL;
-  reg [31:0] decode_to_execute_INSTRUCTION;
-  reg [31:0] execute_to_memory_INSTRUCTION;
-  reg [31:0] memory_to_writeBack_INSTRUCTION;
-  reg  decode_to_execute_MEMORY_MANAGMENT;
-  reg  decode_to_execute_IS_MUL;
-  reg  execute_to_memory_IS_MUL;
-  reg  decode_to_execute_IS_CSR;
-  reg [31:0] execute_to_memory_SHIFT_RIGHT;
-  reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL;
-  reg  decode_to_execute_SRC_LESS_UNSIGNED;
-  reg  decode_to_execute_REGFILE_WRITE_VALID;
-  reg  execute_to_memory_REGFILE_WRITE_VALID;
-  reg  memory_to_writeBack_REGFILE_WRITE_VALID;
-  reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL;
-  reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL;
-  reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL;
-  reg [31:0] decode_to_execute_PC;
-  reg [31:0] execute_to_memory_PC;
-  reg [31:0] memory_to_writeBack_PC;
-  reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL;
-  reg  decode_to_execute_BYPASSABLE_MEMORY_STAGE;
-  reg  execute_to_memory_BYPASSABLE_MEMORY_STAGE;
-  reg  decode_to_execute_SRC_USE_SUB_LESS;
-  reg  decode_to_execute_CSR_READ_OPCODE;
-  reg  decode_to_execute_MEMORY_AMO;
-  reg [31:0] decode_to_execute_FORMAL_PC_NEXT;
-  reg [31:0] execute_to_memory_FORMAL_PC_NEXT;
-  reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT;
-  reg  decode_to_execute_MEMORY_WR;
-  reg  execute_to_memory_MEMORY_WR;
-  reg  memory_to_writeBack_MEMORY_WR;
-  reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL;
-  reg  decode_to_execute_IS_RS1_SIGNED;
-  reg  decode_to_execute_IS_DIV;
-  reg  execute_to_memory_IS_DIV;
-  reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW;
-  reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW;
-  reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL;
-  reg  execute_to_memory_IS_DBUS_SHARING;
-  reg  memory_to_writeBack_IS_DBUS_SHARING;
-  reg  decode_to_execute_IS_SFENCE_VMA;
-  reg  execute_to_memory_IS_SFENCE_VMA;
-  reg  memory_to_writeBack_IS_SFENCE_VMA;
-  reg  decode_to_execute_MEMORY_ENABLE;
-  reg  execute_to_memory_MEMORY_ENABLE;
-  reg  memory_to_writeBack_MEMORY_ENABLE;
-  reg [31:0] execute_to_memory_REGFILE_WRITE_DATA;
-  reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA;
-  reg  decode_to_execute_CSR_WRITE_OPCODE;
-  reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL;
-  reg [31:0] decode_to_execute_RS1;
-  reg [31:0] execute_to_memory_BRANCH_CALC;
-  reg  decode_to_execute_IS_RS2_SIGNED;
-  reg  decode_to_execute_BYPASSABLE_EXECUTE_STAGE;
-  reg  decode_to_execute_SRC2_FORCE_ZERO;
-  reg [2:0] _zz_211_;
-  reg  _zz_212_;
-  reg [31:0] iBusWishbone_DAT_MISO_regNext;
-  reg [2:0] _zz_213_;
-  wire  _zz_214_;
-  wire  _zz_215_;
-  wire  _zz_216_;
-  wire  _zz_217_;
-  wire  _zz_218_;
-  reg  _zz_219_;
-  reg [31:0] dBusWishbone_DAT_MISO_regNext;
-  `ifndef SYNTHESIS
-  reg [31:0] decode_BRANCH_CTRL_string;
-  reg [31:0] _zz_1__string;
-  reg [31:0] _zz_2__string;
-  reg [31:0] _zz_3__string;
-  reg [39:0] decode_ALU_BITWISE_CTRL_string;
-  reg [39:0] _zz_4__string;
-  reg [39:0] _zz_5__string;
-  reg [39:0] _zz_6__string;
-  reg [95:0] decode_SRC1_CTRL_string;
-  reg [95:0] _zz_7__string;
-  reg [95:0] _zz_8__string;
-  reg [95:0] _zz_9__string;
-  reg [23:0] decode_SRC2_CTRL_string;
-  reg [23:0] _zz_10__string;
-  reg [23:0] _zz_11__string;
-  reg [23:0] _zz_12__string;
-  reg [39:0] _zz_13__string;
-  reg [39:0] _zz_14__string;
-  reg [39:0] _zz_15__string;
-  reg [39:0] _zz_16__string;
-  reg [39:0] decode_ENV_CTRL_string;
-  reg [39:0] _zz_17__string;
-  reg [39:0] _zz_18__string;
-  reg [39:0] _zz_19__string;
-  reg [63:0] decode_ALU_CTRL_string;
-  reg [63:0] _zz_20__string;
-  reg [63:0] _zz_21__string;
-  reg [63:0] _zz_22__string;
-  reg [71:0] _zz_23__string;
-  reg [71:0] _zz_24__string;
-  reg [71:0] decode_SHIFT_CTRL_string;
-  reg [71:0] _zz_25__string;
-  reg [71:0] _zz_26__string;
-  reg [71:0] _zz_27__string;
-  reg [39:0] memory_ENV_CTRL_string;
-  reg [39:0] _zz_28__string;
-  reg [39:0] execute_ENV_CTRL_string;
-  reg [39:0] _zz_29__string;
-  reg [39:0] writeBack_ENV_CTRL_string;
-  reg [39:0] _zz_32__string;
-  reg [31:0] execute_BRANCH_CTRL_string;
-  reg [31:0] _zz_34__string;
-  reg [71:0] memory_SHIFT_CTRL_string;
-  reg [71:0] _zz_38__string;
-  reg [71:0] execute_SHIFT_CTRL_string;
-  reg [71:0] _zz_40__string;
-  reg [23:0] execute_SRC2_CTRL_string;
-  reg [23:0] _zz_45__string;
-  reg [95:0] execute_SRC1_CTRL_string;
-  reg [95:0] _zz_47__string;
-  reg [63:0] execute_ALU_CTRL_string;
-  reg [63:0] _zz_50__string;
-  reg [39:0] execute_ALU_BITWISE_CTRL_string;
-  reg [39:0] _zz_52__string;
-  reg [95:0] _zz_62__string;
-  reg [23:0] _zz_63__string;
-  reg [31:0] _zz_66__string;
-  reg [39:0] _zz_70__string;
-  reg [39:0] _zz_78__string;
-  reg [63:0] _zz_81__string;
-  reg [71:0] _zz_82__string;
-  reg [47:0] MmuPlugin_shared_state_1__string;
-  reg [71:0] _zz_152__string;
-  reg [63:0] _zz_153__string;
-  reg [39:0] _zz_154__string;
-  reg [39:0] _zz_155__string;
-  reg [31:0] _zz_156__string;
-  reg [23:0] _zz_157__string;
-  reg [95:0] _zz_158__string;
-  reg [71:0] decode_to_execute_SHIFT_CTRL_string;
-  reg [71:0] execute_to_memory_SHIFT_CTRL_string;
-  reg [63:0] decode_to_execute_ALU_CTRL_string;
-  reg [39:0] decode_to_execute_ENV_CTRL_string;
-  reg [39:0] execute_to_memory_ENV_CTRL_string;
-  reg [39:0] memory_to_writeBack_ENV_CTRL_string;
-  reg [23:0] decode_to_execute_SRC2_CTRL_string;
-  reg [95:0] decode_to_execute_SRC1_CTRL_string;
-  reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string;
-  reg [31:0] decode_to_execute_BRANCH_CTRL_string;
-  `endif
-
-  (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ;
-  assign _zz_271_ = (execute_arbitration_isValid && execute_IS_CSR);
-  assign _zz_272_ = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID);
-  assign _zz_273_ = 1'b1;
-  assign _zz_274_ = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID);
-  assign _zz_275_ = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID);
-  assign _zz_276_ = (memory_arbitration_isValid && memory_IS_MUL);
-  assign _zz_277_ = (memory_arbitration_isValid && memory_IS_DIV);
-  assign _zz_278_ = ((_zz_225_ && IBusCachedPlugin_cache_io_cpu_decode_error) && (! _zz_89_));
-  assign _zz_279_ = ((_zz_225_ && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! _zz_90_));
-  assign _zz_280_ = ((_zz_225_ && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! _zz_91_));
-  assign _zz_281_ = ((_zz_225_ && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! 1'b0));
-  assign _zz_282_ = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != (2'b00));
-  assign _zz_283_ = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI));
-  assign _zz_284_ = (! memory_MulDivIterativePlugin_mul_willOverflowIfInc);
-  assign _zz_285_ = (! memory_MulDivIterativePlugin_div_done);
-  assign _zz_286_ = (CsrPlugin_hadException || CsrPlugin_interruptJump);
-  assign _zz_287_ = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET));
-  assign _zz_288_ = writeBack_INSTRUCTION[29 : 28];
-  assign _zz_289_ = (! IBusCachedPlugin_iBusRsp_readyForError);
-  assign _zz_290_ = (! ({(writeBack_arbitration_isValid || CsrPlugin_exceptionPendings_3),{(memory_arbitration_isValid || CsrPlugin_exceptionPendings_2),(execute_arbitration_isValid || CsrPlugin_exceptionPendings_1)}} != (3'b000)));
-  assign _zz_291_ = (! dataCache_1__io_cpu_redo);
-  assign _zz_292_ = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE);
-  assign _zz_293_ = ((MmuPlugin_dBusAccess_rsp_valid && (! MmuPlugin_dBusAccess_rsp_payload_redo)) && (MmuPlugin_shared_dBusRsp_leaf || MmuPlugin_shared_dBusRsp_exception));
-  assign _zz_294_ = (MmuPlugin_shared_portId == (1'b1));
-  assign _zz_295_ = (MmuPlugin_shared_portId == (1'b0));
-  assign _zz_296_ = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID);
-  assign _zz_297_ = (1'b0 || (! 1'b1));
-  assign _zz_298_ = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID);
-  assign _zz_299_ = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE));
-  assign _zz_300_ = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID);
-  assign _zz_301_ = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE));
-  assign _zz_302_ = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction);
-  assign _zz_303_ = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL));
-  assign _zz_304_ = (! memory_arbitration_isStuck);
-  assign _zz_305_ = (iBus_cmd_valid || (_zz_211_ != (3'b000)));
-  assign _zz_306_ = (_zz_245_ && (! dataCache_1__io_mem_cmd_s2mPipe_ready));
-  assign _zz_307_ = (IBusCachedPlugin_mmuBus_cmd_isValid && IBusCachedPlugin_mmuBus_rsp_refilling);
-  assign _zz_308_ = (DBusCachedPlugin_mmuBus_cmd_isValid && DBusCachedPlugin_mmuBus_rsp_refilling);
-  assign _zz_309_ = (MmuPlugin_ports_0_entryToReplace_value == (2'b00));
-  assign _zz_310_ = (MmuPlugin_ports_0_entryToReplace_value == (2'b01));
-  assign _zz_311_ = (MmuPlugin_ports_0_entryToReplace_value == (2'b10));
-  assign _zz_312_ = (MmuPlugin_ports_0_entryToReplace_value == (2'b11));
-  assign _zz_313_ = (MmuPlugin_ports_1_entryToReplace_value == (2'b00));
-  assign _zz_314_ = (MmuPlugin_ports_1_entryToReplace_value == (2'b01));
-  assign _zz_315_ = (MmuPlugin_ports_1_entryToReplace_value == (2'b10));
-  assign _zz_316_ = (MmuPlugin_ports_1_entryToReplace_value == (2'b11));
-  assign _zz_317_ = ((CsrPlugin_sstatus_SIE && (CsrPlugin_privilege == (2'b01))) || (CsrPlugin_privilege < (2'b01)));
-  assign _zz_318_ = ((_zz_192_ && (1'b1 && CsrPlugin_mideleg_ST)) && (! 1'b0));
-  assign _zz_319_ = ((_zz_193_ && (1'b1 && CsrPlugin_mideleg_SS)) && (! 1'b0));
-  assign _zz_320_ = ((_zz_194_ && (1'b1 && CsrPlugin_mideleg_SE)) && (! 1'b0));
-  assign _zz_321_ = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < (2'b11)));
-  assign _zz_322_ = ((_zz_192_ && 1'b1) && (! (CsrPlugin_mideleg_ST != (1'b0))));
-  assign _zz_323_ = ((_zz_193_ && 1'b1) && (! (CsrPlugin_mideleg_SS != (1'b0))));
-  assign _zz_324_ = ((_zz_194_ && 1'b1) && (! (CsrPlugin_mideleg_SE != (1'b0))));
-  assign _zz_325_ = ((_zz_195_ && 1'b1) && (! 1'b0));
-  assign _zz_326_ = ((_zz_196_ && 1'b1) && (! 1'b0));
-  assign _zz_327_ = ((_zz_197_ && 1'b1) && (! 1'b0));
-  assign _zz_328_ = writeBack_INSTRUCTION[13 : 12];
-  assign _zz_329_ = execute_INSTRUCTION[13];
-  assign _zz_330_ = (_zz_98_ - (4'b0001));
-  assign _zz_331_ = {IBusCachedPlugin_fetchPc_inc,(2'b00)};
-  assign _zz_332_ = {29'd0, _zz_331_};
-  assign _zz_333_ = (writeBack_MEMORY_WR ? (3'b111) : (3'b101));
-  assign _zz_334_ = (writeBack_MEMORY_WR ? (3'b110) : (3'b100));
-  assign _zz_335_ = MmuPlugin_ports_0_entryToReplace_willIncrement;
-  assign _zz_336_ = {1'd0, _zz_335_};
-  assign _zz_337_ = MmuPlugin_ports_1_entryToReplace_willIncrement;
-  assign _zz_338_ = {1'd0, _zz_337_};
-  assign _zz_339_ = MmuPlugin_dBusAccess_rsp_payload_data[0 : 0];
-  assign _zz_340_ = MmuPlugin_dBusAccess_rsp_payload_data[1 : 1];
-  assign _zz_341_ = MmuPlugin_dBusAccess_rsp_payload_data[2 : 2];
-  assign _zz_342_ = MmuPlugin_dBusAccess_rsp_payload_data[3 : 3];
-  assign _zz_343_ = MmuPlugin_dBusAccess_rsp_payload_data[4 : 4];
-  assign _zz_344_ = MmuPlugin_dBusAccess_rsp_payload_data[5 : 5];
-  assign _zz_345_ = MmuPlugin_dBusAccess_rsp_payload_data[6 : 6];
-  assign _zz_346_ = MmuPlugin_dBusAccess_rsp_payload_data[7 : 7];
-  assign _zz_347_ = _zz_143_[0 : 0];
-  assign _zz_348_ = _zz_143_[1 : 1];
-  assign _zz_349_ = _zz_143_[6 : 6];
-  assign _zz_350_ = _zz_143_[7 : 7];
-  assign _zz_351_ = _zz_143_[10 : 10];
-  assign _zz_352_ = _zz_143_[11 : 11];
-  assign _zz_353_ = _zz_143_[12 : 12];
-  assign _zz_354_ = _zz_143_[13 : 13];
-  assign _zz_355_ = _zz_143_[14 : 14];
-  assign _zz_356_ = _zz_143_[16 : 16];
-  assign _zz_357_ = _zz_143_[17 : 17];
-  assign _zz_358_ = _zz_143_[20 : 20];
-  assign _zz_359_ = _zz_143_[21 : 21];
-  assign _zz_360_ = _zz_143_[22 : 22];
-  assign _zz_361_ = _zz_143_[25 : 25];
-  assign _zz_362_ = _zz_143_[26 : 26];
-  assign _zz_363_ = _zz_143_[31 : 31];
-  assign _zz_364_ = _zz_143_[32 : 32];
-  assign _zz_365_ = _zz_143_[33 : 33];
-  assign _zz_366_ = _zz_143_[34 : 34];
-  assign _zz_367_ = execute_SRC_LESS;
-  assign _zz_368_ = (3'b100);
-  assign _zz_369_ = execute_INSTRUCTION[19 : 15];
-  assign _zz_370_ = execute_INSTRUCTION[31 : 20];
-  assign _zz_371_ = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]};
-  assign _zz_372_ = ($signed(_zz_373_) + $signed(_zz_376_));
-  assign _zz_373_ = ($signed(_zz_374_) + $signed(_zz_375_));
-  assign _zz_374_ = execute_SRC1;
-  assign _zz_375_ = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2);
-  assign _zz_376_ = (execute_SRC_USE_SUB_LESS ? _zz_377_ : _zz_378_);
-  assign _zz_377_ = (32'b00000000000000000000000000000001);
-  assign _zz_378_ = (32'b00000000000000000000000000000000);
-  assign _zz_379_ = ($signed(_zz_381_) >>> execute_FullBarrelShifterPlugin_amplitude);
-  assign _zz_380_ = _zz_379_[31 : 0];
-  assign _zz_381_ = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed};
-  assign _zz_382_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]};
-  assign _zz_383_ = execute_INSTRUCTION[31 : 20];
-  assign _zz_384_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]};
-  assign _zz_385_ = (_zz_198_ & (~ _zz_386_));
-  assign _zz_386_ = (_zz_198_ - (2'b01));
-  assign _zz_387_ = memory_MulDivIterativePlugin_mul_counter_willIncrement;
-  assign _zz_388_ = {5'd0, _zz_387_};
-  assign _zz_389_ = (_zz_391_ + _zz_393_);
-  assign _zz_390_ = (memory_MulDivIterativePlugin_rs2[0] ? memory_MulDivIterativePlugin_rs1 : (33'b000000000000000000000000000000000));
-  assign _zz_391_ = {{1{_zz_390_[32]}}, _zz_390_};
-  assign _zz_392_ = _zz_394_;
-  assign _zz_393_ = {{1{_zz_392_[32]}}, _zz_392_};
-  assign _zz_394_ = (memory_MulDivIterativePlugin_accumulator >>> 32);
-  assign _zz_395_ = memory_MulDivIterativePlugin_div_counter_willIncrement;
-  assign _zz_396_ = {5'd0, _zz_395_};
-  assign _zz_397_ = {1'd0, memory_MulDivIterativePlugin_rs2};
-  assign _zz_398_ = {_zz_200_,(! _zz_202_[32])};
-  assign _zz_399_ = _zz_202_[31:0];
-  assign _zz_400_ = _zz_201_[31:0];
-  assign _zz_401_ = _zz_402_;
-  assign _zz_402_ = _zz_403_;
-  assign _zz_403_ = ({1'b0,(memory_MulDivIterativePlugin_div_needRevert ? (~ _zz_203_) : _zz_203_)} + _zz_405_);
-  assign _zz_404_ = memory_MulDivIterativePlugin_div_needRevert;
-  assign _zz_405_ = {32'd0, _zz_404_};
-  assign _zz_406_ = _zz_205_;
-  assign _zz_407_ = {32'd0, _zz_406_};
-  assign _zz_408_ = _zz_204_;
-  assign _zz_409_ = {31'd0, _zz_408_};
-  assign _zz_410_ = execute_CsrPlugin_writeData[19 : 19];
-  assign _zz_411_ = execute_CsrPlugin_writeData[18 : 18];
-  assign _zz_412_ = execute_CsrPlugin_writeData[17 : 17];
-  assign _zz_413_ = execute_CsrPlugin_writeData[7 : 7];
-  assign _zz_414_ = execute_CsrPlugin_writeData[3 : 3];
-  assign _zz_415_ = execute_CsrPlugin_writeData[5 : 5];
-  assign _zz_416_ = execute_CsrPlugin_writeData[1 : 1];
-  assign _zz_417_ = execute_CsrPlugin_writeData[9 : 9];
-  assign _zz_418_ = execute_CsrPlugin_writeData[5 : 5];
-  assign _zz_419_ = execute_CsrPlugin_writeData[1 : 1];
-  assign _zz_420_ = execute_CsrPlugin_writeData[31 : 31];
-  assign _zz_421_ = execute_CsrPlugin_writeData[19 : 19];
-  assign _zz_422_ = execute_CsrPlugin_writeData[18 : 18];
-  assign _zz_423_ = execute_CsrPlugin_writeData[17 : 17];
-  assign _zz_424_ = execute_CsrPlugin_writeData[5 : 5];
-  assign _zz_425_ = execute_CsrPlugin_writeData[1 : 1];
-  assign _zz_426_ = execute_CsrPlugin_writeData[8 : 8];
-  assign _zz_427_ = execute_CsrPlugin_writeData[2 : 2];
-  assign _zz_428_ = execute_CsrPlugin_writeData[5 : 5];
-  assign _zz_429_ = execute_CsrPlugin_writeData[13 : 13];
-  assign _zz_430_ = execute_CsrPlugin_writeData[4 : 4];
-  assign _zz_431_ = execute_CsrPlugin_writeData[7 : 7];
-  assign _zz_432_ = execute_CsrPlugin_writeData[1 : 1];
-  assign _zz_433_ = execute_CsrPlugin_writeData[9 : 9];
-  assign _zz_434_ = execute_CsrPlugin_writeData[12 : 12];
-  assign _zz_435_ = execute_CsrPlugin_writeData[15 : 15];
-  assign _zz_436_ = execute_CsrPlugin_writeData[6 : 6];
-  assign _zz_437_ = execute_CsrPlugin_writeData[0 : 0];
-  assign _zz_438_ = execute_CsrPlugin_writeData[3 : 3];
-  assign _zz_439_ = execute_CsrPlugin_writeData[5 : 5];
-  assign _zz_440_ = execute_CsrPlugin_writeData[1 : 1];
-  assign _zz_441_ = execute_CsrPlugin_writeData[9 : 9];
-  assign _zz_442_ = execute_CsrPlugin_writeData[31 : 31];
-  assign _zz_443_ = execute_CsrPlugin_writeData[5 : 5];
-  assign _zz_444_ = execute_CsrPlugin_writeData[1 : 1];
-  assign _zz_445_ = execute_CsrPlugin_writeData[9 : 9];
-  assign _zz_446_ = execute_CsrPlugin_writeData[11 : 11];
-  assign _zz_447_ = execute_CsrPlugin_writeData[7 : 7];
-  assign _zz_448_ = execute_CsrPlugin_writeData[3 : 3];
-  assign _zz_449_ = execute_CsrPlugin_writeData[9 : 9];
-  assign _zz_450_ = execute_CsrPlugin_writeData[5 : 5];
-  assign _zz_451_ = execute_CsrPlugin_writeData[1 : 1];
-  assign _zz_452_ = execute_CsrPlugin_writeData[9 : 9];
-  assign _zz_453_ = execute_CsrPlugin_writeData[5 : 5];
-  assign _zz_454_ = execute_CsrPlugin_writeData[1 : 1];
-  assign _zz_455_ = (iBus_cmd_payload_address >>> 5);
-  assign _zz_456_ = 1'b1;
-  assign _zz_457_ = 1'b1;
-  assign _zz_458_ = {_zz_102_,_zz_101_};
-  assign _zz_459_ = (32'b00010000000000000000000000001000);
-  assign _zz_460_ = ((decode_INSTRUCTION & _zz_470_) == (32'b00000000000000000000000000100000));
-  assign _zz_461_ = (_zz_471_ == _zz_472_);
-  assign _zz_462_ = {_zz_473_,_zz_474_};
-  assign _zz_463_ = (_zz_475_ == _zz_476_);
-  assign _zz_464_ = {_zz_477_,_zz_478_};
-  assign _zz_465_ = {_zz_479_,{_zz_480_,_zz_481_}};
-  assign _zz_466_ = (5'b00000);
-  assign _zz_467_ = ({_zz_482_,_zz_483_} != (3'b000));
-  assign _zz_468_ = (_zz_484_ != _zz_485_);
-  assign _zz_469_ = {_zz_486_,{_zz_487_,_zz_488_}};
-  assign _zz_470_ = (32'b00000000000000000000000000110100);
-  assign _zz_471_ = (decode_INSTRUCTION & (32'b00000000000000000000000001100100));
-  assign _zz_472_ = (32'b00000000000000000000000000100000);
-  assign _zz_473_ = ((decode_INSTRUCTION & _zz_489_) == (32'b00001000000000000000000000100000));
-  assign _zz_474_ = ((decode_INSTRUCTION & _zz_490_) == (32'b00000000000000000000000000100000));
-  assign _zz_475_ = (decode_INSTRUCTION & (32'b00000000000000000000000001000100));
-  assign _zz_476_ = (32'b00000000000000000000000001000000);
-  assign _zz_477_ = ((decode_INSTRUCTION & _zz_491_) == (32'b00000000000000000010000000010000));
-  assign _zz_478_ = ((decode_INSTRUCTION & _zz_492_) == (32'b01000000000000000000000000110000));
-  assign _zz_479_ = ((decode_INSTRUCTION & _zz_493_) == (32'b00000000000000000000000000000000));
-  assign _zz_480_ = (_zz_494_ == _zz_495_);
-  assign _zz_481_ = {_zz_496_,{_zz_497_,_zz_498_}};
-  assign _zz_482_ = _zz_145_;
-  assign _zz_483_ = {_zz_151_,_zz_499_};
-  assign _zz_484_ = {_zz_151_,_zz_500_};
-  assign _zz_485_ = (2'b00);
-  assign _zz_486_ = ({_zz_501_,_zz_502_} != (2'b00));
-  assign _zz_487_ = (_zz_503_ != _zz_504_);
-  assign _zz_488_ = {_zz_505_,{_zz_506_,_zz_507_}};
-  assign _zz_489_ = (32'b00001000000000000000000001110000);
-  assign _zz_490_ = (32'b00010000000000000000000001110000);
-  assign _zz_491_ = (32'b00000000000000000010000000010100);
-  assign _zz_492_ = (32'b01000000000000000000000000110100);
-  assign _zz_493_ = (32'b00000000000000000000000001000100);
-  assign _zz_494_ = (decode_INSTRUCTION & (32'b00000000000000000000000000011000));
-  assign _zz_495_ = (32'b00000000000000000000000000000000);
-  assign _zz_496_ = ((decode_INSTRUCTION & _zz_508_) == (32'b00000000000000000010000000000000));
-  assign _zz_497_ = (_zz_509_ == _zz_510_);
-  assign _zz_498_ = _zz_149_;
-  assign _zz_499_ = ((decode_INSTRUCTION & _zz_511_) == (32'b00000000000000000000000000000100));
-  assign _zz_500_ = ((decode_INSTRUCTION & _zz_512_) == (32'b00000000000000000000000000000100));
-  assign _zz_501_ = _zz_150_;
-  assign _zz_502_ = (_zz_513_ == _zz_514_);
-  assign _zz_503_ = {_zz_150_,_zz_515_};
-  assign _zz_504_ = (2'b00);
-  assign _zz_505_ = ({_zz_516_,_zz_517_} != (2'b00));
-  assign _zz_506_ = (_zz_518_ != _zz_519_);
-  assign _zz_507_ = {_zz_520_,{_zz_521_,_zz_522_}};
-  assign _zz_508_ = (32'b00000000000000000110000000000100);
-  assign _zz_509_ = (decode_INSTRUCTION & (32'b00000000000000000101000000000100));
-  assign _zz_510_ = (32'b00000000000000000001000000000000);
-  assign _zz_511_ = (32'b00000000000000000010000000010100);
-  assign _zz_512_ = (32'b00000000000000000000000001001100);
-  assign _zz_513_ = (decode_INSTRUCTION & (32'b00000000000000000000000001110000));
-  assign _zz_514_ = (32'b00000000000000000000000000100000);
-  assign _zz_515_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000100000)) == (32'b00000000000000000000000000000000));
-  assign _zz_516_ = _zz_148_;
-  assign _zz_517_ = _zz_146_;
-  assign _zz_518_ = ((decode_INSTRUCTION & (32'b00000010000000000100000001110100)) == (32'b00000010000000000000000000110000));
-  assign _zz_519_ = (1'b0);
-  assign _zz_520_ = ({_zz_145_,(_zz_523_ == _zz_524_)} != (2'b00));
-  assign _zz_521_ = ((_zz_525_ == _zz_526_) != (1'b0));
-  assign _zz_522_ = {(_zz_527_ != (1'b0)),{(_zz_528_ != _zz_529_),{_zz_530_,{_zz_531_,_zz_532_}}}};
-  assign _zz_523_ = (decode_INSTRUCTION & (32'b00000000000000000000000000011100));
-  assign _zz_524_ = (32'b00000000000000000000000000000100);
-  assign _zz_525_ = (decode_INSTRUCTION & (32'b00000000000000000000000001011000));
-  assign _zz_526_ = (32'b00000000000000000000000001000000);
-  assign _zz_527_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001100100)) == (32'b00000000000000000000000000100100));
-  assign _zz_528_ = {_zz_149_,((decode_INSTRUCTION & _zz_533_) == (32'b00000000000000000000000000000000))};
-  assign _zz_529_ = (2'b00);
-  assign _zz_530_ = ({(_zz_534_ == _zz_535_),(_zz_536_ == _zz_537_)} != (2'b00));
-  assign _zz_531_ = ((_zz_538_ == _zz_539_) != (1'b0));
-  assign _zz_532_ = {(_zz_147_ != (1'b0)),{(_zz_540_ != _zz_541_),{_zz_542_,{_zz_543_,_zz_544_}}}};
-  assign _zz_533_ = (32'b00000000000000000000000001011000);
-  assign _zz_534_ = (decode_INSTRUCTION & (32'b00000000000000000001000001010000));
-  assign _zz_535_ = (32'b00000000000000000001000001010000);
-  assign _zz_536_ = (decode_INSTRUCTION & (32'b00000000000000000010000001010000));
-  assign _zz_537_ = (32'b00000000000000000010000001010000);
-  assign _zz_538_ = (decode_INSTRUCTION & (32'b00000000000000000001000000000000));
-  assign _zz_539_ = (32'b00000000000000000001000000000000);
-  assign _zz_540_ = ((decode_INSTRUCTION & (32'b00000010000000000011000001010000)) == (32'b00000010000000000000000001010000));
-  assign _zz_541_ = (1'b0);
-  assign _zz_542_ = ({(_zz_545_ == _zz_546_),(_zz_547_ == _zz_548_)} != (2'b00));
-  assign _zz_543_ = ({_zz_549_,{_zz_550_,_zz_551_}} != (6'b000000));
-  assign _zz_544_ = {(_zz_552_ != (1'b0)),{(_zz_553_ != _zz_554_),{_zz_555_,{_zz_556_,_zz_557_}}}};
-  assign _zz_545_ = (decode_INSTRUCTION & (32'b00000000000000000010000000010000));
-  assign _zz_546_ = (32'b00000000000000000010000000000000);
-  assign _zz_547_ = (decode_INSTRUCTION & (32'b00000000000000000101000000000000));
-  assign _zz_548_ = (32'b00000000000000000001000000000000);
-  assign _zz_549_ = ((decode_INSTRUCTION & _zz_558_) == (32'b00000000000000000010000001000000));
-  assign _zz_550_ = (_zz_559_ == _zz_560_);
-  assign _zz_551_ = {_zz_561_,{_zz_562_,_zz_563_}};
-  assign _zz_552_ = ((decode_INSTRUCTION & _zz_564_) == (32'b00010000000000000000000000001000));
-  assign _zz_553_ = {_zz_148_,{_zz_565_,_zz_566_}};
-  assign _zz_554_ = (3'b000);
-  assign _zz_555_ = ({_zz_567_,_zz_568_} != (5'b00000));
-  assign _zz_556_ = (_zz_569_ != _zz_570_);
-  assign _zz_557_ = {_zz_571_,{_zz_572_,_zz_573_}};
-  assign _zz_558_ = (32'b00000000000000000010000001000000);
-  assign _zz_559_ = (decode_INSTRUCTION & (32'b00000000000000000001000001000000));
-  assign _zz_560_ = (32'b00000000000000000001000001000000);
-  assign _zz_561_ = ((decode_INSTRUCTION & _zz_574_) == (32'b00000000000000000000000001000000));
-  assign _zz_562_ = (_zz_575_ == _zz_576_);
-  assign _zz_563_ = {_zz_577_,_zz_578_};
-  assign _zz_564_ = (32'b00010000000000000000000000001000);
-  assign _zz_565_ = _zz_147_;
-  assign _zz_566_ = _zz_146_;
-  assign _zz_567_ = _zz_144_;
-  assign _zz_568_ = {_zz_579_,{_zz_580_,_zz_581_}};
-  assign _zz_569_ = (_zz_582_ == _zz_583_);
-  assign _zz_570_ = (1'b0);
-  assign _zz_571_ = (_zz_584_ != (1'b0));
-  assign _zz_572_ = (_zz_585_ != _zz_586_);
-  assign _zz_573_ = {_zz_587_,{_zz_588_,_zz_589_}};
-  assign _zz_574_ = (32'b00000000000000000000000001010000);
-  assign _zz_575_ = (decode_INSTRUCTION & (32'b00000010010000000000000001000000));
-  assign _zz_576_ = (32'b00000000000000000000000001000000);
-  assign _zz_577_ = ((decode_INSTRUCTION & _zz_590_) == (32'b00000000000000000000000000000000));
-  assign _zz_578_ = ((decode_INSTRUCTION & _zz_591_) == (32'b00010000000000000010000000001000));
-  assign _zz_579_ = ((decode_INSTRUCTION & _zz_592_) == (32'b00000000000000000010000000010000));
-  assign _zz_580_ = (_zz_593_ == _zz_594_);
-  assign _zz_581_ = {_zz_595_,_zz_596_};
-  assign _zz_582_ = (decode_INSTRUCTION & (32'b00000010000000000100000001100100));
-  assign _zz_583_ = (32'b00000010000000000100000000100000);
-  assign _zz_584_ = ((decode_INSTRUCTION & _zz_597_) == (32'b00000000000000000001000000001000));
-  assign _zz_585_ = (_zz_598_ == _zz_599_);
-  assign _zz_586_ = (1'b0);
-  assign _zz_587_ = (_zz_600_ != (1'b0));
-  assign _zz_588_ = (_zz_601_ != _zz_602_);
-  assign _zz_589_ = {_zz_603_,{_zz_604_,_zz_605_}};
-  assign _zz_590_ = (32'b00000000000000000000000000111000);
-  assign _zz_591_ = (32'b00011000000000000010000000001000);
-  assign _zz_592_ = (32'b00000000000000000010000000110000);
-  assign _zz_593_ = (decode_INSTRUCTION & (32'b00000000000000000001000000110000));
-  assign _zz_594_ = (32'b00000000000000000000000000010000);
-  assign _zz_595_ = ((decode_INSTRUCTION & (32'b00000010000000000011000000100000)) == (32'b00000000000000000000000000100000));
-  assign _zz_596_ = ((decode_INSTRUCTION & (32'b00000010000000000010000001101000)) == (32'b00000000000000000010000000100000));
-  assign _zz_597_ = (32'b00000000000000000101000001001000);
-  assign _zz_598_ = (decode_INSTRUCTION & (32'b00000010001000000011000001010000));
-  assign _zz_599_ = (32'b00000000000000000000000001010000);
-  assign _zz_600_ = ((decode_INSTRUCTION & (32'b00000010010000000011000001010000)) == (32'b00000000000000000000000001010000));
-  assign _zz_601_ = ((decode_INSTRUCTION & _zz_606_) == (32'b00000000000000000000000000010000));
-  assign _zz_602_ = (1'b0);
-  assign _zz_603_ = ({_zz_607_,{_zz_608_,_zz_609_}} != (3'b000));
-  assign _zz_604_ = (_zz_610_ != (1'b0));
-  assign _zz_605_ = {(_zz_611_ != _zz_612_),{_zz_613_,{_zz_614_,_zz_615_}}};
-  assign _zz_606_ = (32'b00000000000000000000000000010000);
-  assign _zz_607_ = ((decode_INSTRUCTION & (32'b00001000000000000000000000100000)) == (32'b00001000000000000000000000100000));
-  assign _zz_608_ = ((decode_INSTRUCTION & _zz_616_) == (32'b00000000000000000000000000100000));
-  assign _zz_609_ = ((decode_INSTRUCTION & _zz_617_) == (32'b00000000000000000000000000100000));
-  assign _zz_610_ = ((decode_INSTRUCTION & (32'b00000000000000000100000000010100)) == (32'b00000000000000000100000000010000));
-  assign _zz_611_ = ((decode_INSTRUCTION & _zz_618_) == (32'b00000000000000000010000000010000));
-  assign _zz_612_ = (1'b0);
-  assign _zz_613_ = ({_zz_619_,_zz_620_} != (2'b00));
-  assign _zz_614_ = ({_zz_621_,_zz_622_} != (3'b000));
-  assign _zz_615_ = {(_zz_623_ != _zz_624_),(_zz_625_ != _zz_626_)};
-  assign _zz_616_ = (32'b00010000000000000000000000100000);
-  assign _zz_617_ = (32'b00000000000000000000000000101000);
-  assign _zz_618_ = (32'b00000000000000000110000000010100);
-  assign _zz_619_ = ((decode_INSTRUCTION & (32'b00000000000000000111000000110100)) == (32'b00000000000000000101000000010000));
-  assign _zz_620_ = ((decode_INSTRUCTION & (32'b00000010000000000111000001100100)) == (32'b00000000000000000101000000100000));
-  assign _zz_621_ = ((decode_INSTRUCTION & (32'b01000000000000000011000001010100)) == (32'b01000000000000000001000000010000));
-  assign _zz_622_ = {((decode_INSTRUCTION & _zz_627_) == (32'b00000000000000000001000000010000)),((decode_INSTRUCTION & _zz_628_) == (32'b00000000000000000001000000010000))};
-  assign _zz_623_ = {_zz_145_,{(_zz_629_ == _zz_630_),{_zz_631_,{_zz_632_,_zz_633_}}}};
-  assign _zz_624_ = (7'b0000000);
-  assign _zz_625_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001001000)) == (32'b00000000000000000100000000001000));
-  assign _zz_626_ = (1'b0);
-  assign _zz_627_ = (32'b00000000000000000111000000110100);
-  assign _zz_628_ = (32'b00000010000000000111000001010100);
-  assign _zz_629_ = (decode_INSTRUCTION & (32'b00000000000000000001000000010000));
-  assign _zz_630_ = (32'b00000000000000000001000000010000);
-  assign _zz_631_ = ((decode_INSTRUCTION & (32'b00000000000000000010000000010000)) == (32'b00000000000000000010000000010000));
-  assign _zz_632_ = ((decode_INSTRUCTION & (32'b00000000000000000010000000001000)) == (32'b00000000000000000010000000001000));
-  assign _zz_633_ = {((decode_INSTRUCTION & (32'b00000000000000000000000001010000)) == (32'b00000000000000000000000000010000)),{_zz_144_,((decode_INSTRUCTION & (32'b00000000000000000000000000101000)) == (32'b00000000000000000000000000000000))}};
-  assign _zz_634_ = (32'b00000000000000000001000001111111);
-  assign _zz_635_ = (decode_INSTRUCTION & (32'b00000000000000000010000001111111));
-  assign _zz_636_ = (32'b00000000000000000010000001110011);
-  assign _zz_637_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001111111)) == (32'b00000000000000000100000001100011));
-  assign _zz_638_ = ((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000010000000010011));
-  assign _zz_639_ = {((decode_INSTRUCTION & (32'b00000000000000000110000000111111)) == (32'b00000000000000000000000000100011)),{((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_640_) == (32'b00000000000000000000000000000011)),{(_zz_641_ == _zz_642_),{_zz_643_,{_zz_644_,_zz_645_}}}}}};
-  assign _zz_640_ = (32'b00000000000000000101000001011111);
-  assign _zz_641_ = (decode_INSTRUCTION & (32'b00000000000000000111000001111011));
-  assign _zz_642_ = (32'b00000000000000000000000001100011);
-  assign _zz_643_ = ((decode_INSTRUCTION & (32'b00000000000000000110000001111111)) == (32'b00000000000000000000000000001111));
-  assign _zz_644_ = ((decode_INSTRUCTION & (32'b00011000000000000111000001111111)) == (32'b00000000000000000010000000101111));
-  assign _zz_645_ = {((decode_INSTRUCTION & (32'b11111100000000000000000001111111)) == (32'b00000000000000000000000000110011)),{((decode_INSTRUCTION & (32'b11101000000000000111000001111111)) == (32'b00001000000000000010000000101111)),{((decode_INSTRUCTION & _zz_646_) == (32'b00000000000000000001000000010011)),{(_zz_647_ == _zz_648_),{_zz_649_,{_zz_650_,_zz_651_}}}}}};
-  assign _zz_646_ = (32'b11111100000000000011000001011111);
-  assign _zz_647_ = (decode_INSTRUCTION & (32'b00000001111100000111000001111111));
-  assign _zz_648_ = (32'b00000000000000000101000000001111);
-  assign _zz_649_ = ((decode_INSTRUCTION & (32'b10111100000000000111000001111111)) == (32'b00000000000000000101000000010011));
-  assign _zz_650_ = ((decode_INSTRUCTION & (32'b10111110000000000111000001111111)) == (32'b00000000000000000101000000110011));
-  assign _zz_651_ = {((decode_INSTRUCTION & (32'b10111110000000000111000001111111)) == (32'b00000000000000000000000000110011)),{((decode_INSTRUCTION & (32'b11111001111100000111000001111111)) == (32'b00010000000000000010000000101111)),{((decode_INSTRUCTION & _zz_652_) == (32'b00010010000000000000000001110011)),{(_zz_653_ == _zz_654_),{_zz_655_,_zz_656_}}}}};
-  assign _zz_652_ = (32'b11111110000000000111111111111111);
-  assign _zz_653_ = (decode_INSTRUCTION & (32'b11011111111111111111111111111111));
-  assign _zz_654_ = (32'b00010000001000000000000001110011);
-  assign _zz_655_ = ((decode_INSTRUCTION & (32'b11111111111111111111111111111111)) == (32'b00010000010100000000000001110011));
-  assign _zz_656_ = ((decode_INSTRUCTION & (32'b11111111111111111111111111111111)) == (32'b00000000000000000000000001110011));
-  always @ (posedge clk) begin
-    if(_zz_55_) begin
-      RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data;
-    end
-  end
-
-  always @ (posedge clk) begin
-    if(_zz_456_) begin
-      _zz_246_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1];
-    end
-  end
-
-  always @ (posedge clk) begin
-    if(_zz_457_) begin
-      _zz_247_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2];
-    end
-  end
-
-  InstructionCache IBusCachedPlugin_cache (
-    .io_flush(_zz_220_),
-    .io_cpu_prefetch_isValid(_zz_221_),
-    .io_cpu_prefetch_haltIt(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt),
-    .io_cpu_prefetch_pc(IBusCachedPlugin_iBusRsp_stages_1_input_payload),
-    .io_cpu_fetch_isValid(_zz_222_),
-    .io_cpu_fetch_isStuck(_zz_223_),
-    .io_cpu_fetch_isRemoved(IBusCachedPlugin_fetcherflushIt),
-    .io_cpu_fetch_pc(IBusCachedPlugin_iBusRsp_stages_2_input_payload),
-    .io_cpu_fetch_data(IBusCachedPlugin_cache_io_cpu_fetch_data),
-    .io_cpu_fetch_dataBypassValid(IBusCachedPlugin_s1_tightlyCoupledHit),
-    .io_cpu_fetch_dataBypass(_zz_224_),
-    .io_cpu_fetch_mmuBus_cmd_isValid(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid),
-    .io_cpu_fetch_mmuBus_cmd_virtualAddress(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress),
-    .io_cpu_fetch_mmuBus_cmd_bypassTranslation(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation),
-    .io_cpu_fetch_mmuBus_rsp_physicalAddress(IBusCachedPlugin_mmuBus_rsp_physicalAddress),
-    .io_cpu_fetch_mmuBus_rsp_isIoAccess(IBusCachedPlugin_mmuBus_rsp_isIoAccess),
-    .io_cpu_fetch_mmuBus_rsp_allowRead(IBusCachedPlugin_mmuBus_rsp_allowRead),
-    .io_cpu_fetch_mmuBus_rsp_allowWrite(IBusCachedPlugin_mmuBus_rsp_allowWrite),
-    .io_cpu_fetch_mmuBus_rsp_allowExecute(IBusCachedPlugin_mmuBus_rsp_allowExecute),
-    .io_cpu_fetch_mmuBus_rsp_exception(IBusCachedPlugin_mmuBus_rsp_exception),
-    .io_cpu_fetch_mmuBus_rsp_refilling(IBusCachedPlugin_mmuBus_rsp_refilling),
-    .io_cpu_fetch_mmuBus_end(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end),
-    .io_cpu_fetch_mmuBus_busy(IBusCachedPlugin_mmuBus_busy),
-    .io_cpu_fetch_physicalAddress(IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress),
-    .io_cpu_fetch_haltIt(IBusCachedPlugin_cache_io_cpu_fetch_haltIt),
-    .io_cpu_decode_isValid(_zz_225_),
-    .io_cpu_decode_isStuck(_zz_226_),
-    .io_cpu_decode_pc(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload),
-    .io_cpu_decode_physicalAddress(IBusCachedPlugin_cache_io_cpu_decode_physicalAddress),
-    .io_cpu_decode_data(IBusCachedPlugin_cache_io_cpu_decode_data),
-    .io_cpu_decode_cacheMiss(IBusCachedPlugin_cache_io_cpu_decode_cacheMiss),
-    .io_cpu_decode_error(IBusCachedPlugin_cache_io_cpu_decode_error),
-    .io_cpu_decode_mmuRefilling(IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling),
-    .io_cpu_decode_mmuException(IBusCachedPlugin_cache_io_cpu_decode_mmuException),
-    .io_cpu_decode_isUser(_zz_227_),
-    .io_cpu_fill_valid(_zz_228_),
-    .io_cpu_fill_payload(IBusCachedPlugin_cache_io_cpu_decode_physicalAddress),
-    .io_mem_cmd_valid(IBusCachedPlugin_cache_io_mem_cmd_valid),
-    .io_mem_cmd_ready(iBus_cmd_ready),
-    .io_mem_cmd_payload_address(IBusCachedPlugin_cache_io_mem_cmd_payload_address),
-    .io_mem_cmd_payload_size(IBusCachedPlugin_cache_io_mem_cmd_payload_size),
-    .io_mem_rsp_valid(iBus_rsp_valid),
-    .io_mem_rsp_payload_data(iBus_rsp_payload_data),
-    .io_mem_rsp_payload_error(iBus_rsp_payload_error),
-    .clk(clk),
-    .reset(reset)
-  );
-  DataCache dataCache_1_ (
-    .io_cpu_execute_isValid(_zz_229_),
-    .io_cpu_execute_address(_zz_230_),
-    .io_cpu_execute_args_wr(_zz_231_),
-    .io_cpu_execute_args_data(_zz_232_),
-    .io_cpu_execute_args_size(_zz_233_),
-    .io_cpu_execute_args_isLrsc(_zz_234_),
-    .io_cpu_execute_args_isAmo(_zz_235_),
-    .io_cpu_execute_args_amoCtrl_swap(_zz_236_),
-    .io_cpu_execute_args_amoCtrl_alu(_zz_237_),
-    .io_cpu_memory_isValid(_zz_238_),
-    .io_cpu_memory_isStuck(memory_arbitration_isStuck),
-    .io_cpu_memory_isRemoved(memory_arbitration_removeIt),
-    .io_cpu_memory_isWrite(dataCache_1__io_cpu_memory_isWrite),
-    .io_cpu_memory_address(_zz_239_),
-    .io_cpu_memory_mmuBus_cmd_isValid(dataCache_1__io_cpu_memory_mmuBus_cmd_isValid),
-    .io_cpu_memory_mmuBus_cmd_virtualAddress(dataCache_1__io_cpu_memory_mmuBus_cmd_virtualAddress),
-    .io_cpu_memory_mmuBus_cmd_bypassTranslation(dataCache_1__io_cpu_memory_mmuBus_cmd_bypassTranslation),
-    .io_cpu_memory_mmuBus_rsp_physicalAddress(DBusCachedPlugin_mmuBus_rsp_physicalAddress),
-    .io_cpu_memory_mmuBus_rsp_isIoAccess(_zz_240_),
-    .io_cpu_memory_mmuBus_rsp_allowRead(DBusCachedPlugin_mmuBus_rsp_allowRead),
-    .io_cpu_memory_mmuBus_rsp_allowWrite(DBusCachedPlugin_mmuBus_rsp_allowWrite),
-    .io_cpu_memory_mmuBus_rsp_allowExecute(DBusCachedPlugin_mmuBus_rsp_allowExecute),
-    .io_cpu_memory_mmuBus_rsp_exception(DBusCachedPlugin_mmuBus_rsp_exception),
-    .io_cpu_memory_mmuBus_rsp_refilling(DBusCachedPlugin_mmuBus_rsp_refilling),
-    .io_cpu_memory_mmuBus_end(dataCache_1__io_cpu_memory_mmuBus_end),
-    .io_cpu_memory_mmuBus_busy(DBusCachedPlugin_mmuBus_busy),
-    .io_cpu_writeBack_isValid(_zz_241_),
-    .io_cpu_writeBack_isStuck(writeBack_arbitration_isStuck),
-    .io_cpu_writeBack_isUser(_zz_242_),
-    .io_cpu_writeBack_haltIt(dataCache_1__io_cpu_writeBack_haltIt),
-    .io_cpu_writeBack_isWrite(dataCache_1__io_cpu_writeBack_isWrite),
-    .io_cpu_writeBack_data(dataCache_1__io_cpu_writeBack_data),
-    .io_cpu_writeBack_address(_zz_243_),
-    .io_cpu_writeBack_mmuException(dataCache_1__io_cpu_writeBack_mmuException),
-    .io_cpu_writeBack_unalignedAccess(dataCache_1__io_cpu_writeBack_unalignedAccess),
-    .io_cpu_writeBack_accessError(dataCache_1__io_cpu_writeBack_accessError),
-    .io_cpu_writeBack_clearLrsc(contextSwitching),
-    .io_cpu_redo(dataCache_1__io_cpu_redo),
-    .io_cpu_flush_valid(_zz_244_),
-    .io_cpu_flush_ready(dataCache_1__io_cpu_flush_ready),
-    .io_mem_cmd_valid(dataCache_1__io_mem_cmd_valid),
-    .io_mem_cmd_ready(_zz_245_),
-    .io_mem_cmd_payload_wr(dataCache_1__io_mem_cmd_payload_wr),
-    .io_mem_cmd_payload_address(dataCache_1__io_mem_cmd_payload_address),
-    .io_mem_cmd_payload_data(dataCache_1__io_mem_cmd_payload_data),
-    .io_mem_cmd_payload_mask(dataCache_1__io_mem_cmd_payload_mask),
-    .io_mem_cmd_payload_length(dataCache_1__io_mem_cmd_payload_length),
-    .io_mem_cmd_payload_last(dataCache_1__io_mem_cmd_payload_last),
-    .io_mem_rsp_valid(dBus_rsp_valid),
-    .io_mem_rsp_payload_data(dBus_rsp_payload_data),
-    .io_mem_rsp_payload_error(dBus_rsp_payload_error),
-    .clk(clk),
-    .reset(reset)
-  );
-  always @(*) begin
-    case(_zz_458_)
-      2'b00 : begin
-        _zz_248_ = DBusCachedPlugin_redoBranch_payload;
-      end
-      2'b01 : begin
-        _zz_248_ = CsrPlugin_jumpInterface_payload;
-      end
-      2'b10 : begin
-        _zz_248_ = BranchPlugin_jumpInterface_payload;
-      end
-      default : begin
-        _zz_248_ = IBusCachedPlugin_redoBranch_payload;
-      end
-    endcase
-  end
-
-  always @(*) begin
-    case(_zz_139_)
-      2'b00 : begin
-        _zz_249_ = MmuPlugin_ports_0_cache_0_valid;
-        _zz_250_ = MmuPlugin_ports_0_cache_0_exception;
-        _zz_251_ = MmuPlugin_ports_0_cache_0_superPage;
-        _zz_252_ = MmuPlugin_ports_0_cache_0_virtualAddress_0;
-        _zz_253_ = MmuPlugin_ports_0_cache_0_virtualAddress_1;
-        _zz_254_ = MmuPlugin_ports_0_cache_0_physicalAddress_0;
-        _zz_255_ = MmuPlugin_ports_0_cache_0_physicalAddress_1;
-        _zz_256_ = MmuPlugin_ports_0_cache_0_allowRead;
-        _zz_257_ = MmuPlugin_ports_0_cache_0_allowWrite;
-        _zz_258_ = MmuPlugin_ports_0_cache_0_allowExecute;
-        _zz_259_ = MmuPlugin_ports_0_cache_0_allowUser;
-      end
-      2'b01 : begin
-        _zz_249_ = MmuPlugin_ports_0_cache_1_valid;
-        _zz_250_ = MmuPlugin_ports_0_cache_1_exception;
-        _zz_251_ = MmuPlugin_ports_0_cache_1_superPage;
-        _zz_252_ = MmuPlugin_ports_0_cache_1_virtualAddress_0;
-        _zz_253_ = MmuPlugin_ports_0_cache_1_virtualAddress_1;
-        _zz_254_ = MmuPlugin_ports_0_cache_1_physicalAddress_0;
-        _zz_255_ = MmuPlugin_ports_0_cache_1_physicalAddress_1;
-        _zz_256_ = MmuPlugin_ports_0_cache_1_allowRead;
-        _zz_257_ = MmuPlugin_ports_0_cache_1_allowWrite;
-        _zz_258_ = MmuPlugin_ports_0_cache_1_allowExecute;
-        _zz_259_ = MmuPlugin_ports_0_cache_1_allowUser;
-      end
-      2'b10 : begin
-        _zz_249_ = MmuPlugin_ports_0_cache_2_valid;
-        _zz_250_ = MmuPlugin_ports_0_cache_2_exception;
-        _zz_251_ = MmuPlugin_ports_0_cache_2_superPage;
-        _zz_252_ = MmuPlugin_ports_0_cache_2_virtualAddress_0;
-        _zz_253_ = MmuPlugin_ports_0_cache_2_virtualAddress_1;
-        _zz_254_ = MmuPlugin_ports_0_cache_2_physicalAddress_0;
-        _zz_255_ = MmuPlugin_ports_0_cache_2_physicalAddress_1;
-        _zz_256_ = MmuPlugin_ports_0_cache_2_allowRead;
-        _zz_257_ = MmuPlugin_ports_0_cache_2_allowWrite;
-        _zz_258_ = MmuPlugin_ports_0_cache_2_allowExecute;
-        _zz_259_ = MmuPlugin_ports_0_cache_2_allowUser;
-      end
-      default : begin
-        _zz_249_ = MmuPlugin_ports_0_cache_3_valid;
-        _zz_250_ = MmuPlugin_ports_0_cache_3_exception;
-        _zz_251_ = MmuPlugin_ports_0_cache_3_superPage;
-        _zz_252_ = MmuPlugin_ports_0_cache_3_virtualAddress_0;
-        _zz_253_ = MmuPlugin_ports_0_cache_3_virtualAddress_1;
-        _zz_254_ = MmuPlugin_ports_0_cache_3_physicalAddress_0;
-        _zz_255_ = MmuPlugin_ports_0_cache_3_physicalAddress_1;
-        _zz_256_ = MmuPlugin_ports_0_cache_3_allowRead;
-        _zz_257_ = MmuPlugin_ports_0_cache_3_allowWrite;
-        _zz_258_ = MmuPlugin_ports_0_cache_3_allowExecute;
-        _zz_259_ = MmuPlugin_ports_0_cache_3_allowUser;
-      end
-    endcase
-  end
-
-  always @(*) begin
-    case(_zz_142_)
-      2'b00 : begin
-        _zz_260_ = MmuPlugin_ports_1_cache_0_valid;
-        _zz_261_ = MmuPlugin_ports_1_cache_0_exception;
-        _zz_262_ = MmuPlugin_ports_1_cache_0_superPage;
-        _zz_263_ = MmuPlugin_ports_1_cache_0_virtualAddress_0;
-        _zz_264_ = MmuPlugin_ports_1_cache_0_virtualAddress_1;
-        _zz_265_ = MmuPlugin_ports_1_cache_0_physicalAddress_0;
-        _zz_266_ = MmuPlugin_ports_1_cache_0_physicalAddress_1;
-        _zz_267_ = MmuPlugin_ports_1_cache_0_allowRead;
-        _zz_268_ = MmuPlugin_ports_1_cache_0_allowWrite;
-        _zz_269_ = MmuPlugin_ports_1_cache_0_allowExecute;
-        _zz_270_ = MmuPlugin_ports_1_cache_0_allowUser;
-      end
-      2'b01 : begin
-        _zz_260_ = MmuPlugin_ports_1_cache_1_valid;
-        _zz_261_ = MmuPlugin_ports_1_cache_1_exception;
-        _zz_262_ = MmuPlugin_ports_1_cache_1_superPage;
-        _zz_263_ = MmuPlugin_ports_1_cache_1_virtualAddress_0;
-        _zz_264_ = MmuPlugin_ports_1_cache_1_virtualAddress_1;
-        _zz_265_ = MmuPlugin_ports_1_cache_1_physicalAddress_0;
-        _zz_266_ = MmuPlugin_ports_1_cache_1_physicalAddress_1;
-        _zz_267_ = MmuPlugin_ports_1_cache_1_allowRead;
-        _zz_268_ = MmuPlugin_ports_1_cache_1_allowWrite;
-        _zz_269_ = MmuPlugin_ports_1_cache_1_allowExecute;
-        _zz_270_ = MmuPlugin_ports_1_cache_1_allowUser;
-      end
-      2'b10 : begin
-        _zz_260_ = MmuPlugin_ports_1_cache_2_valid;
-        _zz_261_ = MmuPlugin_ports_1_cache_2_exception;
-        _zz_262_ = MmuPlugin_ports_1_cache_2_superPage;
-        _zz_263_ = MmuPlugin_ports_1_cache_2_virtualAddress_0;
-        _zz_264_ = MmuPlugin_ports_1_cache_2_virtualAddress_1;
-        _zz_265_ = MmuPlugin_ports_1_cache_2_physicalAddress_0;
-        _zz_266_ = MmuPlugin_ports_1_cache_2_physicalAddress_1;
-        _zz_267_ = MmuPlugin_ports_1_cache_2_allowRead;
-        _zz_268_ = MmuPlugin_ports_1_cache_2_allowWrite;
-        _zz_269_ = MmuPlugin_ports_1_cache_2_allowExecute;
-        _zz_270_ = MmuPlugin_ports_1_cache_2_allowUser;
-      end
-      default : begin
-        _zz_260_ = MmuPlugin_ports_1_cache_3_valid;
-        _zz_261_ = MmuPlugin_ports_1_cache_3_exception;
-        _zz_262_ = MmuPlugin_ports_1_cache_3_superPage;
-        _zz_263_ = MmuPlugin_ports_1_cache_3_virtualAddress_0;
-        _zz_264_ = MmuPlugin_ports_1_cache_3_virtualAddress_1;
-        _zz_265_ = MmuPlugin_ports_1_cache_3_physicalAddress_0;
-        _zz_266_ = MmuPlugin_ports_1_cache_3_physicalAddress_1;
-        _zz_267_ = MmuPlugin_ports_1_cache_3_allowRead;
-        _zz_268_ = MmuPlugin_ports_1_cache_3_allowWrite;
-        _zz_269_ = MmuPlugin_ports_1_cache_3_allowExecute;
-        _zz_270_ = MmuPlugin_ports_1_cache_3_allowUser;
-      end
-    endcase
-  end
-
-  `ifndef SYNTHESIS
-  always @(*) begin
-    case(decode_BRANCH_CTRL)
-      `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC ";
-      `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B   ";
-      `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL ";
-      `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR";
-      default : decode_BRANCH_CTRL_string = "????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_1_)
-      `BranchCtrlEnum_defaultEncoding_INC : _zz_1__string = "INC ";
-      `BranchCtrlEnum_defaultEncoding_B : _zz_1__string = "B   ";
-      `BranchCtrlEnum_defaultEncoding_JAL : _zz_1__string = "JAL ";
-      `BranchCtrlEnum_defaultEncoding_JALR : _zz_1__string = "JALR";
-      default : _zz_1__string = "????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_2_)
-      `BranchCtrlEnum_defaultEncoding_INC : _zz_2__string = "INC ";
-      `BranchCtrlEnum_defaultEncoding_B : _zz_2__string = "B   ";
-      `BranchCtrlEnum_defaultEncoding_JAL : _zz_2__string = "JAL ";
-      `BranchCtrlEnum_defaultEncoding_JALR : _zz_2__string = "JALR";
-      default : _zz_2__string = "????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_3_)
-      `BranchCtrlEnum_defaultEncoding_INC : _zz_3__string = "INC ";
-      `BranchCtrlEnum_defaultEncoding_B : _zz_3__string = "B   ";
-      `BranchCtrlEnum_defaultEncoding_JAL : _zz_3__string = "JAL ";
-      `BranchCtrlEnum_defaultEncoding_JALR : _zz_3__string = "JALR";
-      default : _zz_3__string = "????";
-    endcase
-  end
-  always @(*) begin
-    case(decode_ALU_BITWISE_CTRL)
-      `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1";
-      `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 ";
-      `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1";
-      default : decode_ALU_BITWISE_CTRL_string = "?????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_4_)
-      `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_4__string = "XOR_1";
-      `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_4__string = "OR_1 ";
-      `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_4__string = "AND_1";
-      default : _zz_4__string = "?????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_5_)
-      `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_5__string = "XOR_1";
-      `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_5__string = "OR_1 ";
-      `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_5__string = "AND_1";
-      default : _zz_5__string = "?????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_6_)
-      `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_6__string = "XOR_1";
-      `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_6__string = "OR_1 ";
-      `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_6__string = "AND_1";
-      default : _zz_6__string = "?????";
-    endcase
-  end
-  always @(*) begin
-    case(decode_SRC1_CTRL)
-      `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS          ";
-      `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU         ";
-      `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT";
-      `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1        ";
-      default : decode_SRC1_CTRL_string = "????????????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_7_)
-      `Src1CtrlEnum_defaultEncoding_RS : _zz_7__string = "RS          ";
-      `Src1CtrlEnum_defaultEncoding_IMU : _zz_7__string = "IMU         ";
-      `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_7__string = "PC_INCREMENT";
-      `Src1CtrlEnum_defaultEncoding_URS1 : _zz_7__string = "URS1        ";
-      default : _zz_7__string = "????????????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_8_)
-      `Src1CtrlEnum_defaultEncoding_RS : _zz_8__string = "RS          ";
-      `Src1CtrlEnum_defaultEncoding_IMU : _zz_8__string = "IMU         ";
-      `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_8__string = "PC_INCREMENT";
-      `Src1CtrlEnum_defaultEncoding_URS1 : _zz_8__string = "URS1        ";
-      default : _zz_8__string = "????????????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_9_)
-      `Src1CtrlEnum_defaultEncoding_RS : _zz_9__string = "RS          ";
-      `Src1CtrlEnum_defaultEncoding_IMU : _zz_9__string = "IMU         ";
-      `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_9__string = "PC_INCREMENT";
-      `Src1CtrlEnum_defaultEncoding_URS1 : _zz_9__string = "URS1        ";
-      default : _zz_9__string = "????????????";
-    endcase
-  end
-  always @(*) begin
-    case(decode_SRC2_CTRL)
-      `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS ";
-      `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI";
-      `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS";
-      `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC ";
-      default : decode_SRC2_CTRL_string = "???";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_10_)
-      `Src2CtrlEnum_defaultEncoding_RS : _zz_10__string = "RS ";
-      `Src2CtrlEnum_defaultEncoding_IMI : _zz_10__string = "IMI";
-      `Src2CtrlEnum_defaultEncoding_IMS : _zz_10__string = "IMS";
-      `Src2CtrlEnum_defaultEncoding_PC : _zz_10__string = "PC ";
-      default : _zz_10__string = "???";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_11_)
-      `Src2CtrlEnum_defaultEncoding_RS : _zz_11__string = "RS ";
-      `Src2CtrlEnum_defaultEncoding_IMI : _zz_11__string = "IMI";
-      `Src2CtrlEnum_defaultEncoding_IMS : _zz_11__string = "IMS";
-      `Src2CtrlEnum_defaultEncoding_PC : _zz_11__string = "PC ";
-      default : _zz_11__string = "???";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_12_)
-      `Src2CtrlEnum_defaultEncoding_RS : _zz_12__string = "RS ";
-      `Src2CtrlEnum_defaultEncoding_IMI : _zz_12__string = "IMI";
-      `Src2CtrlEnum_defaultEncoding_IMS : _zz_12__string = "IMS";
-      `Src2CtrlEnum_defaultEncoding_PC : _zz_12__string = "PC ";
-      default : _zz_12__string = "???";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_13_)
-      `EnvCtrlEnum_defaultEncoding_NONE : _zz_13__string = "NONE ";
-      `EnvCtrlEnum_defaultEncoding_XRET : _zz_13__string = "XRET ";
-      `EnvCtrlEnum_defaultEncoding_WFI : _zz_13__string = "WFI  ";
-      `EnvCtrlEnum_defaultEncoding_ECALL : _zz_13__string = "ECALL";
-      default : _zz_13__string = "?????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_14_)
-      `EnvCtrlEnum_defaultEncoding_NONE : _zz_14__string = "NONE ";
-      `EnvCtrlEnum_defaultEncoding_XRET : _zz_14__string = "XRET ";
-      `EnvCtrlEnum_defaultEncoding_WFI : _zz_14__string = "WFI  ";
-      `EnvCtrlEnum_defaultEncoding_ECALL : _zz_14__string = "ECALL";
-      default : _zz_14__string = "?????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_15_)
-      `EnvCtrlEnum_defaultEncoding_NONE : _zz_15__string = "NONE ";
-      `EnvCtrlEnum_defaultEncoding_XRET : _zz_15__string = "XRET ";
-      `EnvCtrlEnum_defaultEncoding_WFI : _zz_15__string = "WFI  ";
-      `EnvCtrlEnum_defaultEncoding_ECALL : _zz_15__string = "ECALL";
-      default : _zz_15__string = "?????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_16_)
-      `EnvCtrlEnum_defaultEncoding_NONE : _zz_16__string = "NONE ";
-      `EnvCtrlEnum_defaultEncoding_XRET : _zz_16__string = "XRET ";
-      `EnvCtrlEnum_defaultEncoding_WFI : _zz_16__string = "WFI  ";
-      `EnvCtrlEnum_defaultEncoding_ECALL : _zz_16__string = "ECALL";
-      default : _zz_16__string = "?????";
-    endcase
-  end
-  always @(*) begin
-    case(decode_ENV_CTRL)
-      `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE ";
-      `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET ";
-      `EnvCtrlEnum_defaultEncoding_WFI : decode_ENV_CTRL_string = "WFI  ";
-      `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL";
-      default : decode_ENV_CTRL_string = "?????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_17_)
-      `EnvCtrlEnum_defaultEncoding_NONE : _zz_17__string = "NONE ";
-      `EnvCtrlEnum_defaultEncoding_XRET : _zz_17__string = "XRET ";
-      `EnvCtrlEnum_defaultEncoding_WFI : _zz_17__string = "WFI  ";
-      `EnvCtrlEnum_defaultEncoding_ECALL : _zz_17__string = "ECALL";
-      default : _zz_17__string = "?????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_18_)
-      `EnvCtrlEnum_defaultEncoding_NONE : _zz_18__string = "NONE ";
-      `EnvCtrlEnum_defaultEncoding_XRET : _zz_18__string = "XRET ";
-      `EnvCtrlEnum_defaultEncoding_WFI : _zz_18__string = "WFI  ";
-      `EnvCtrlEnum_defaultEncoding_ECALL : _zz_18__string = "ECALL";
-      default : _zz_18__string = "?????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_19_)
-      `EnvCtrlEnum_defaultEncoding_NONE : _zz_19__string = "NONE ";
-      `EnvCtrlEnum_defaultEncoding_XRET : _zz_19__string = "XRET ";
-      `EnvCtrlEnum_defaultEncoding_WFI : _zz_19__string = "WFI  ";
-      `EnvCtrlEnum_defaultEncoding_ECALL : _zz_19__string = "ECALL";
-      default : _zz_19__string = "?????";
-    endcase
-  end
-  always @(*) begin
-    case(decode_ALU_CTRL)
-      `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB ";
-      `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU";
-      `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE ";
-      default : decode_ALU_CTRL_string = "????????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_20_)
-      `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_20__string = "ADD_SUB ";
-      `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_20__string = "SLT_SLTU";
-      `AluCtrlEnum_defaultEncoding_BITWISE : _zz_20__string = "BITWISE ";
-      default : _zz_20__string = "????????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_21_)
-      `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_21__string = "ADD_SUB ";
-      `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_21__string = "SLT_SLTU";
-      `AluCtrlEnum_defaultEncoding_BITWISE : _zz_21__string = "BITWISE ";
-      default : _zz_21__string = "????????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_22_)
-      `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_22__string = "ADD_SUB ";
-      `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_22__string = "SLT_SLTU";
-      `AluCtrlEnum_defaultEncoding_BITWISE : _zz_22__string = "BITWISE ";
-      default : _zz_22__string = "????????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_23_)
-      `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_23__string = "DISABLE_1";
-      `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_23__string = "SLL_1    ";
-      `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_23__string = "SRL_1    ";
-      `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_23__string = "SRA_1    ";
-      default : _zz_23__string = "?????????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_24_)
-      `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_24__string = "DISABLE_1";
-      `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_24__string = "SLL_1    ";
-      `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_24__string = "SRL_1    ";
-      `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_24__string = "SRA_1    ";
-      default : _zz_24__string = "?????????";
-    endcase
-  end
-  always @(*) begin
-    case(decode_SHIFT_CTRL)
-      `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1";
-      `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1    ";
-      `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1    ";
-      `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1    ";
-      default : decode_SHIFT_CTRL_string = "?????????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_25_)
-      `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_25__string = "DISABLE_1";
-      `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_25__string = "SLL_1    ";
-      `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_25__string = "SRL_1    ";
-      `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_25__string = "SRA_1    ";
-      default : _zz_25__string = "?????????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_26_)
-      `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_26__string = "DISABLE_1";
-      `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_26__string = "SLL_1    ";
-      `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_26__string = "SRL_1    ";
-      `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_26__string = "SRA_1    ";
-      default : _zz_26__string = "?????????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_27_)
-      `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_27__string = "DISABLE_1";
-      `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_27__string = "SLL_1    ";
-      `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_27__string = "SRL_1    ";
-      `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_27__string = "SRA_1    ";
-      default : _zz_27__string = "?????????";
-    endcase
-  end
-  always @(*) begin
-    case(memory_ENV_CTRL)
-      `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE ";
-      `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET ";
-      `EnvCtrlEnum_defaultEncoding_WFI : memory_ENV_CTRL_string = "WFI  ";
-      `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL";
-      default : memory_ENV_CTRL_string = "?????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_28_)
-      `EnvCtrlEnum_defaultEncoding_NONE : _zz_28__string = "NONE ";
-      `EnvCtrlEnum_defaultEncoding_XRET : _zz_28__string = "XRET ";
-      `EnvCtrlEnum_defaultEncoding_WFI : _zz_28__string = "WFI  ";
-      `EnvCtrlEnum_defaultEncoding_ECALL : _zz_28__string = "ECALL";
-      default : _zz_28__string = "?????";
-    endcase
-  end
-  always @(*) begin
-    case(execute_ENV_CTRL)
-      `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE ";
-      `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET ";
-      `EnvCtrlEnum_defaultEncoding_WFI : execute_ENV_CTRL_string = "WFI  ";
-      `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL";
-      default : execute_ENV_CTRL_string = "?????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_29_)
-      `EnvCtrlEnum_defaultEncoding_NONE : _zz_29__string = "NONE ";
-      `EnvCtrlEnum_defaultEncoding_XRET : _zz_29__string = "XRET ";
-      `EnvCtrlEnum_defaultEncoding_WFI : _zz_29__string = "WFI  ";
-      `EnvCtrlEnum_defaultEncoding_ECALL : _zz_29__string = "ECALL";
-      default : _zz_29__string = "?????";
-    endcase
-  end
-  always @(*) begin
-    case(writeBack_ENV_CTRL)
-      `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE ";
-      `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET ";
-      `EnvCtrlEnum_defaultEncoding_WFI : writeBack_ENV_CTRL_string = "WFI  ";
-      `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL";
-      default : writeBack_ENV_CTRL_string = "?????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_32_)
-      `EnvCtrlEnum_defaultEncoding_NONE : _zz_32__string = "NONE ";
-      `EnvCtrlEnum_defaultEncoding_XRET : _zz_32__string = "XRET ";
-      `EnvCtrlEnum_defaultEncoding_WFI : _zz_32__string = "WFI  ";
-      `EnvCtrlEnum_defaultEncoding_ECALL : _zz_32__string = "ECALL";
-      default : _zz_32__string = "?????";
-    endcase
-  end
-  always @(*) begin
-    case(execute_BRANCH_CTRL)
-      `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC ";
-      `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B   ";
-      `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL ";
-      `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR";
-      default : execute_BRANCH_CTRL_string = "????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_34_)
-      `BranchCtrlEnum_defaultEncoding_INC : _zz_34__string = "INC ";
-      `BranchCtrlEnum_defaultEncoding_B : _zz_34__string = "B   ";
-      `BranchCtrlEnum_defaultEncoding_JAL : _zz_34__string = "JAL ";
-      `BranchCtrlEnum_defaultEncoding_JALR : _zz_34__string = "JALR";
-      default : _zz_34__string = "????";
-    endcase
-  end
-  always @(*) begin
-    case(memory_SHIFT_CTRL)
-      `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1";
-      `ShiftCtrlEnum_defaultEncoding_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1    ";
-      `ShiftCtrlEnum_defaultEncoding_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1    ";
-      `ShiftCtrlEnum_defaultEncoding_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1    ";
-      default : memory_SHIFT_CTRL_string = "?????????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_38_)
-      `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_38__string = "DISABLE_1";
-      `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_38__string = "SLL_1    ";
-      `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_38__string = "SRL_1    ";
-      `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_38__string = "SRA_1    ";
-      default : _zz_38__string = "?????????";
-    endcase
-  end
-  always @(*) begin
-    case(execute_SHIFT_CTRL)
-      `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1";
-      `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1    ";
-      `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1    ";
-      `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1    ";
-      default : execute_SHIFT_CTRL_string = "?????????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_40_)
-      `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_40__string = "DISABLE_1";
-      `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_40__string = "SLL_1    ";
-      `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_40__string = "SRL_1    ";
-      `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_40__string = "SRA_1    ";
-      default : _zz_40__string = "?????????";
-    endcase
-  end
-  always @(*) begin
-    case(execute_SRC2_CTRL)
-      `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS ";
-      `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI";
-      `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS";
-      `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC ";
-      default : execute_SRC2_CTRL_string = "???";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_45_)
-      `Src2CtrlEnum_defaultEncoding_RS : _zz_45__string = "RS ";
-      `Src2CtrlEnum_defaultEncoding_IMI : _zz_45__string = "IMI";
-      `Src2CtrlEnum_defaultEncoding_IMS : _zz_45__string = "IMS";
-      `Src2CtrlEnum_defaultEncoding_PC : _zz_45__string = "PC ";
-      default : _zz_45__string = "???";
-    endcase
-  end
-  always @(*) begin
-    case(execute_SRC1_CTRL)
-      `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS          ";
-      `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU         ";
-      `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT";
-      `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1        ";
-      default : execute_SRC1_CTRL_string = "????????????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_47_)
-      `Src1CtrlEnum_defaultEncoding_RS : _zz_47__string = "RS          ";
-      `Src1CtrlEnum_defaultEncoding_IMU : _zz_47__string = "IMU         ";
-      `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_47__string = "PC_INCREMENT";
-      `Src1CtrlEnum_defaultEncoding_URS1 : _zz_47__string = "URS1        ";
-      default : _zz_47__string = "????????????";
-    endcase
-  end
-  always @(*) begin
-    case(execute_ALU_CTRL)
-      `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB ";
-      `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU";
-      `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE ";
-      default : execute_ALU_CTRL_string = "????????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_50_)
-      `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_50__string = "ADD_SUB ";
-      `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_50__string = "SLT_SLTU";
-      `AluCtrlEnum_defaultEncoding_BITWISE : _zz_50__string = "BITWISE ";
-      default : _zz_50__string = "????????";
-    endcase
-  end
-  always @(*) begin
-    case(execute_ALU_BITWISE_CTRL)
-      `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1";
-      `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 ";
-      `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1";
-      default : execute_ALU_BITWISE_CTRL_string = "?????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_52_)
-      `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_52__string = "XOR_1";
-      `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_52__string = "OR_1 ";
-      `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_52__string = "AND_1";
-      default : _zz_52__string = "?????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_62_)
-      `Src1CtrlEnum_defaultEncoding_RS : _zz_62__string = "RS          ";
-      `Src1CtrlEnum_defaultEncoding_IMU : _zz_62__string = "IMU         ";
-      `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_62__string = "PC_INCREMENT";
-      `Src1CtrlEnum_defaultEncoding_URS1 : _zz_62__string = "URS1        ";
-      default : _zz_62__string = "????????????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_63_)
-      `Src2CtrlEnum_defaultEncoding_RS : _zz_63__string = "RS ";
-      `Src2CtrlEnum_defaultEncoding_IMI : _zz_63__string = "IMI";
-      `Src2CtrlEnum_defaultEncoding_IMS : _zz_63__string = "IMS";
-      `Src2CtrlEnum_defaultEncoding_PC : _zz_63__string = "PC ";
-      default : _zz_63__string = "???";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_66_)
-      `BranchCtrlEnum_defaultEncoding_INC : _zz_66__string = "INC ";
-      `BranchCtrlEnum_defaultEncoding_B : _zz_66__string = "B   ";
-      `BranchCtrlEnum_defaultEncoding_JAL : _zz_66__string = "JAL ";
-      `BranchCtrlEnum_defaultEncoding_JALR : _zz_66__string = "JALR";
-      default : _zz_66__string = "????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_70_)
-      `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_70__string = "XOR_1";
-      `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_70__string = "OR_1 ";
-      `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_70__string = "AND_1";
-      default : _zz_70__string = "?????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_78_)
-      `EnvCtrlEnum_defaultEncoding_NONE : _zz_78__string = "NONE ";
-      `EnvCtrlEnum_defaultEncoding_XRET : _zz_78__string = "XRET ";
-      `EnvCtrlEnum_defaultEncoding_WFI : _zz_78__string = "WFI  ";
-      `EnvCtrlEnum_defaultEncoding_ECALL : _zz_78__string = "ECALL";
-      default : _zz_78__string = "?????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_81_)
-      `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_81__string = "ADD_SUB ";
-      `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_81__string = "SLT_SLTU";
-      `AluCtrlEnum_defaultEncoding_BITWISE : _zz_81__string = "BITWISE ";
-      default : _zz_81__string = "????????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_82_)
-      `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_82__string = "DISABLE_1";
-      `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_82__string = "SLL_1    ";
-      `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_82__string = "SRL_1    ";
-      `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_82__string = "SRA_1    ";
-      default : _zz_82__string = "?????????";
-    endcase
-  end
-  always @(*) begin
-    case(MmuPlugin_shared_state_1_)
-      `MmuPlugin_shared_State_defaultEncoding_IDLE : MmuPlugin_shared_state_1__string = "IDLE  ";
-      `MmuPlugin_shared_State_defaultEncoding_L1_CMD : MmuPlugin_shared_state_1__string = "L1_CMD";
-      `MmuPlugin_shared_State_defaultEncoding_L1_RSP : MmuPlugin_shared_state_1__string = "L1_RSP";
-      `MmuPlugin_shared_State_defaultEncoding_L0_CMD : MmuPlugin_shared_state_1__string = "L0_CMD";
-      `MmuPlugin_shared_State_defaultEncoding_L0_RSP : MmuPlugin_shared_state_1__string = "L0_RSP";
-      default : MmuPlugin_shared_state_1__string = "??????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_152_)
-      `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_152__string = "DISABLE_1";
-      `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_152__string = "SLL_1    ";
-      `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_152__string = "SRL_1    ";
-      `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_152__string = "SRA_1    ";
-      default : _zz_152__string = "?????????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_153_)
-      `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_153__string = "ADD_SUB ";
-      `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_153__string = "SLT_SLTU";
-      `AluCtrlEnum_defaultEncoding_BITWISE : _zz_153__string = "BITWISE ";
-      default : _zz_153__string = "????????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_154_)
-      `EnvCtrlEnum_defaultEncoding_NONE : _zz_154__string = "NONE ";
-      `EnvCtrlEnum_defaultEncoding_XRET : _zz_154__string = "XRET ";
-      `EnvCtrlEnum_defaultEncoding_WFI : _zz_154__string = "WFI  ";
-      `EnvCtrlEnum_defaultEncoding_ECALL : _zz_154__string = "ECALL";
-      default : _zz_154__string = "?????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_155_)
-      `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_155__string = "XOR_1";
-      `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_155__string = "OR_1 ";
-      `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_155__string = "AND_1";
-      default : _zz_155__string = "?????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_156_)
-      `BranchCtrlEnum_defaultEncoding_INC : _zz_156__string = "INC ";
-      `BranchCtrlEnum_defaultEncoding_B : _zz_156__string = "B   ";
-      `BranchCtrlEnum_defaultEncoding_JAL : _zz_156__string = "JAL ";
-      `BranchCtrlEnum_defaultEncoding_JALR : _zz_156__string = "JALR";
-      default : _zz_156__string = "????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_157_)
-      `Src2CtrlEnum_defaultEncoding_RS : _zz_157__string = "RS ";
-      `Src2CtrlEnum_defaultEncoding_IMI : _zz_157__string = "IMI";
-      `Src2CtrlEnum_defaultEncoding_IMS : _zz_157__string = "IMS";
-      `Src2CtrlEnum_defaultEncoding_PC : _zz_157__string = "PC ";
-      default : _zz_157__string = "???";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_158_)
-      `Src1CtrlEnum_defaultEncoding_RS : _zz_158__string = "RS          ";
-      `Src1CtrlEnum_defaultEncoding_IMU : _zz_158__string = "IMU         ";
-      `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_158__string = "PC_INCREMENT";
-      `Src1CtrlEnum_defaultEncoding_URS1 : _zz_158__string = "URS1        ";
-      default : _zz_158__string = "????????????";
-    endcase
-  end
-  always @(*) begin
-    case(decode_to_execute_SHIFT_CTRL)
-      `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1";
-      `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1    ";
-      `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1    ";
-      `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1    ";
-      default : decode_to_execute_SHIFT_CTRL_string = "?????????";
-    endcase
-  end
-  always @(*) begin
-    case(execute_to_memory_SHIFT_CTRL)
-      `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1";
-      `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1    ";
-      `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1    ";
-      `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1    ";
-      default : execute_to_memory_SHIFT_CTRL_string = "?????????";
-    endcase
-  end
-  always @(*) begin
-    case(decode_to_execute_ALU_CTRL)
-      `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB ";
-      `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU";
-      `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE ";
-      default : decode_to_execute_ALU_CTRL_string = "????????";
-    endcase
-  end
-  always @(*) begin
-    case(decode_to_execute_ENV_CTRL)
-      `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE ";
-      `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET ";
-      `EnvCtrlEnum_defaultEncoding_WFI : decode_to_execute_ENV_CTRL_string = "WFI  ";
-      `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL";
-      default : decode_to_execute_ENV_CTRL_string = "?????";
-    endcase
-  end
-  always @(*) begin
-    case(execute_to_memory_ENV_CTRL)
-      `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE ";
-      `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET ";
-      `EnvCtrlEnum_defaultEncoding_WFI : execute_to_memory_ENV_CTRL_string = "WFI  ";
-      `EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL";
-      default : execute_to_memory_ENV_CTRL_string = "?????";
-    endcase
-  end
-  always @(*) begin
-    case(memory_to_writeBack_ENV_CTRL)
-      `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE ";
-      `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET ";
-      `EnvCtrlEnum_defaultEncoding_WFI : memory_to_writeBack_ENV_CTRL_string = "WFI  ";
-      `EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL";
-      default : memory_to_writeBack_ENV_CTRL_string = "?????";
-    endcase
-  end
-  always @(*) begin
-    case(decode_to_execute_SRC2_CTRL)
-      `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS ";
-      `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI";
-      `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS";
-      `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC ";
-      default : decode_to_execute_SRC2_CTRL_string = "???";
-    endcase
-  end
-  always @(*) begin
-    case(decode_to_execute_SRC1_CTRL)
-      `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS          ";
-      `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU         ";
-      `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT";
-      `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1        ";
-      default : decode_to_execute_SRC1_CTRL_string = "????????????";
-    endcase
-  end
-  always @(*) begin
-    case(decode_to_execute_ALU_BITWISE_CTRL)
-      `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1";
-      `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 ";
-      `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1";
-      default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????";
-    endcase
-  end
-  always @(*) begin
-    case(decode_to_execute_BRANCH_CTRL)
-      `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC ";
-      `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B   ";
-      `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL ";
-      `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR";
-      default : decode_to_execute_BRANCH_CTRL_string = "????";
-    endcase
-  end
-  `endif
-
-  assign decode_SRC2_FORCE_ZERO = _zz_49_;
-  assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_75_;
-  assign decode_IS_RS2_SIGNED = _zz_64_;
-  assign execute_BRANCH_CALC = _zz_33_;
-  assign decode_BRANCH_CTRL = _zz_1_;
-  assign _zz_2_ = _zz_3_;
-  assign decode_CSR_WRITE_OPCODE = _zz_31_;
-  assign execute_REGFILE_WRITE_DATA = _zz_51_;
-  assign memory_IS_SFENCE_VMA = execute_to_memory_IS_SFENCE_VMA;
-  assign execute_IS_SFENCE_VMA = decode_to_execute_IS_SFENCE_VMA;
-  assign decode_IS_SFENCE_VMA = _zz_71_;
-  assign execute_IS_DBUS_SHARING = _zz_86_;
-  assign decode_ALU_BITWISE_CTRL = _zz_4_;
-  assign _zz_5_ = _zz_6_;
-  assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW;
-  assign execute_MEMORY_ADDRESS_LOW = _zz_88_;
-  assign decode_IS_DIV = _zz_76_;
-  assign decode_IS_RS1_SIGNED = _zz_74_;
-  assign decode_SRC1_CTRL = _zz_7_;
-  assign _zz_8_ = _zz_9_;
-  assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR;
-  assign decode_MEMORY_WR = _zz_80_;
-  assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT;
-  assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT;
-  assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT;
-  assign decode_FORMAL_PC_NEXT = _zz_95_;
-  assign decode_MEMORY_AMO = _zz_58_;
-  assign decode_CSR_READ_OPCODE = _zz_30_;
-  assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE;
-  assign decode_BYPASSABLE_MEMORY_STAGE = _zz_79_;
-  assign decode_SRC2_CTRL = _zz_10_;
-  assign _zz_11_ = _zz_12_;
-  assign memory_PC = execute_to_memory_PC;
-  assign _zz_13_ = _zz_14_;
-  assign _zz_15_ = _zz_16_;
-  assign decode_ENV_CTRL = _zz_17_;
-  assign _zz_18_ = _zz_19_;
-  assign decode_SRC_LESS_UNSIGNED = _zz_72_;
-  assign decode_ALU_CTRL = _zz_20_;
-  assign _zz_21_ = _zz_22_;
-  assign execute_SHIFT_RIGHT = _zz_39_;
-  assign decode_IS_CSR = _zz_69_;
-  assign decode_IS_MUL = _zz_65_;
-  assign decode_MEMORY_MANAGMENT = _zz_84_;
-  assign _zz_23_ = _zz_24_;
-  assign decode_SHIFT_CTRL = _zz_25_;
-  assign _zz_26_ = _zz_27_;
-  assign decode_MEMORY_LRSC = _zz_73_;
-  assign execute_BRANCH_DO = _zz_35_;
-  assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED;
-  assign execute_IS_DIV = decode_to_execute_IS_DIV;
-  assign execute_IS_MUL = decode_to_execute_IS_MUL;
-  assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED;
-  assign memory_IS_DIV = execute_to_memory_IS_DIV;
-  assign memory_IS_MUL = execute_to_memory_IS_MUL;
-  assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE;
-  assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE;
-  assign execute_IS_CSR = decode_to_execute_IS_CSR;
-  assign memory_ENV_CTRL = _zz_28_;
-  assign execute_ENV_CTRL = _zz_29_;
-  assign writeBack_ENV_CTRL = _zz_32_;
-  assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC;
-  assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO;
-  assign execute_PC = decode_to_execute_PC;
-  assign execute_RS1 = decode_to_execute_RS1;
-  assign execute_BRANCH_CTRL = _zz_34_;
-  assign decode_RS2_USE = _zz_59_;
-  assign decode_RS1_USE = _zz_61_;
-  always @ (*) begin
-    _zz_36_ = execute_REGFILE_WRITE_DATA;
-    if(_zz_271_)begin
-      _zz_36_ = execute_CsrPlugin_readData;
-    end
-    if(DBusCachedPlugin_forceDatapath)begin
-      _zz_36_ = MmuPlugin_dBusAccess_cmd_payload_address;
-    end
-  end
-
-  assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID;
-  assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE;
-  assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID;
-  assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION;
-  assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE;
-  assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID;
-  always @ (*) begin
-    decode_RS2 = _zz_56_;
-    if(_zz_172_)begin
-      if((_zz_173_ == decode_INSTRUCTION[24 : 20]))begin
-        decode_RS2 = _zz_174_;
-      end
-    end
-    if(_zz_272_)begin
-      if(_zz_273_)begin
-        if(_zz_176_)begin
-          decode_RS2 = _zz_87_;
-        end
-      end
-    end
-    if(_zz_274_)begin
-      if(memory_BYPASSABLE_MEMORY_STAGE)begin
-        if(_zz_178_)begin
-          decode_RS2 = _zz_37_;
-        end
-      end
-    end
-    if(_zz_275_)begin
-      if(execute_BYPASSABLE_EXECUTE_STAGE)begin
-        if(_zz_180_)begin
-          decode_RS2 = _zz_36_;
-        end
-      end
-    end
-  end
-
-  always @ (*) begin
-    decode_RS1 = _zz_57_;
-    if(_zz_172_)begin
-      if((_zz_173_ == decode_INSTRUCTION[19 : 15]))begin
-        decode_RS1 = _zz_174_;
-      end
-    end
-    if(_zz_272_)begin
-      if(_zz_273_)begin
-        if(_zz_175_)begin
-          decode_RS1 = _zz_87_;
-        end
-      end
-    end
-    if(_zz_274_)begin
-      if(memory_BYPASSABLE_MEMORY_STAGE)begin
-        if(_zz_177_)begin
-          decode_RS1 = _zz_37_;
-        end
-      end
-    end
-    if(_zz_275_)begin
-      if(execute_BYPASSABLE_EXECUTE_STAGE)begin
-        if(_zz_179_)begin
-          decode_RS1 = _zz_36_;
-        end
-      end
-    end
-  end
-
-  assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT;
-  always @ (*) begin
-    _zz_37_ = memory_REGFILE_WRITE_DATA;
-    if(memory_arbitration_isValid)begin
-      case(memory_SHIFT_CTRL)
-        `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin
-          _zz_37_ = _zz_168_;
-        end
-        `ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin
-          _zz_37_ = memory_SHIFT_RIGHT;
-        end
-        default : begin
-        end
-      endcase
-    end
-    if(_zz_276_)begin
-      _zz_37_ = ((memory_INSTRUCTION[13 : 12] == (2'b00)) ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_accumulator[63 : 32]);
-    end
-    if(_zz_277_)begin
-      _zz_37_ = memory_MulDivIterativePlugin_div_result;
-    end
-  end
-
-  assign memory_SHIFT_CTRL = _zz_38_;
-  assign execute_SHIFT_CTRL = _zz_40_;
-  assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED;
-  assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO;
-  assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS;
-  assign _zz_44_ = execute_PC;
-  assign execute_SRC2_CTRL = _zz_45_;
-  assign execute_SRC1_CTRL = _zz_47_;
-  assign decode_SRC_USE_SUB_LESS = _zz_60_;
-  assign decode_SRC_ADD_ZERO = _zz_67_;
-  assign execute_SRC_ADD_SUB = _zz_43_;
-  assign execute_SRC_LESS = _zz_41_;
-  assign execute_ALU_CTRL = _zz_50_;
-  assign execute_SRC2 = _zz_46_;
-  assign execute_SRC1 = _zz_48_;
-  assign execute_ALU_BITWISE_CTRL = _zz_52_;
-  assign _zz_53_ = writeBack_INSTRUCTION;
-  assign _zz_54_ = writeBack_REGFILE_WRITE_VALID;
-  always @ (*) begin
-    _zz_55_ = 1'b0;
-    if(lastStageRegFileWrite_valid)begin
-      _zz_55_ = 1'b1;
-    end
-  end
-
-  assign decode_INSTRUCTION_ANTICIPATED = _zz_92_;
-  always @ (*) begin
-    decode_REGFILE_WRITE_VALID = _zz_83_;
-    if((decode_INSTRUCTION[11 : 7] == (5'b00000)))begin
-      decode_REGFILE_WRITE_VALID = 1'b0;
-    end
-  end
-
-  assign decode_LEGAL_INSTRUCTION = _zz_85_;
-  assign decode_INSTRUCTION_READY = 1'b1;
-  assign writeBack_IS_SFENCE_VMA = memory_to_writeBack_IS_SFENCE_VMA;
-  assign writeBack_IS_DBUS_SHARING = memory_to_writeBack_IS_DBUS_SHARING;
-  assign memory_IS_DBUS_SHARING = execute_to_memory_IS_DBUS_SHARING;
-  always @ (*) begin
-    _zz_87_ = writeBack_REGFILE_WRITE_DATA;
-    if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin
-      _zz_87_ = writeBack_DBusCachedPlugin_rspFormated;
-    end
-  end
-
-  assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW;
-  assign writeBack_MEMORY_WR = memory_to_writeBack_MEMORY_WR;
-  assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA;
-  assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE;
-  assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA;
-  assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE;
-  assign execute_MEMORY_AMO = decode_to_execute_MEMORY_AMO;
-  assign execute_MEMORY_LRSC = decode_to_execute_MEMORY_LRSC;
-  assign execute_MEMORY_MANAGMENT = decode_to_execute_MEMORY_MANAGMENT;
-  assign execute_RS2 = decode_to_execute_RS2;
-  assign execute_MEMORY_WR = decode_to_execute_MEMORY_WR;
-  assign execute_SRC_ADD = _zz_42_;
-  assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE;
-  assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION;
-  assign decode_MEMORY_ENABLE = _zz_68_;
-  assign decode_FLUSH_ALL = _zz_77_;
-  always @ (*) begin
-    IBusCachedPlugin_rsp_issueDetected = _zz_89_;
-    if(_zz_278_)begin
-      IBusCachedPlugin_rsp_issueDetected = 1'b1;
-    end
-  end
-
-  always @ (*) begin
-    _zz_89_ = _zz_90_;
-    if(_zz_279_)begin
-      _zz_89_ = 1'b1;
-    end
-  end
-
-  always @ (*) begin
-    _zz_90_ = _zz_91_;
-    if(_zz_280_)begin
-      _zz_90_ = 1'b1;
-    end
-  end
-
-  always @ (*) begin
-    _zz_91_ = 1'b0;
-    if(_zz_281_)begin
-      _zz_91_ = 1'b1;
-    end
-  end
-
-  assign decode_INSTRUCTION = _zz_96_;
-  always @ (*) begin
-    _zz_93_ = memory_FORMAL_PC_NEXT;
-    if(BranchPlugin_jumpInterface_valid)begin
-      _zz_93_ = BranchPlugin_jumpInterface_payload;
-    end
-  end
-
-  always @ (*) begin
-    _zz_94_ = decode_FORMAL_PC_NEXT;
-    if(IBusCachedPlugin_redoBranch_valid)begin
-      _zz_94_ = IBusCachedPlugin_redoBranch_payload;
-    end
-  end
-
-  assign decode_PC = _zz_97_;
-  assign writeBack_PC = memory_to_writeBack_PC;
-  assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION;
-  always @ (*) begin
-    decode_arbitration_haltItself = 1'b0;
-    if(((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin
-      decode_arbitration_haltItself = 1'b1;
-    end
-  end
-
-  always @ (*) begin
-    decode_arbitration_haltByOther = 1'b0;
-    if(MmuPlugin_dBusAccess_cmd_valid)begin
-      decode_arbitration_haltByOther = 1'b1;
-    end
-    if((decode_arbitration_isValid && (_zz_169_ || _zz_170_)))begin
-      decode_arbitration_haltByOther = 1'b1;
-    end
-    if((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts))begin
-      decode_arbitration_haltByOther = decode_arbitration_isValid;
-    end
-    if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != (3'b000)))begin
-      decode_arbitration_haltByOther = 1'b1;
-    end
-  end
-
-  always @ (*) begin
-    decode_arbitration_removeIt = 1'b0;
-    if(_zz_282_)begin
-      decode_arbitration_removeIt = 1'b1;
-    end
-    if(decode_arbitration_isFlushed)begin
-      decode_arbitration_removeIt = 1'b1;
-    end
-  end
-
-  assign decode_arbitration_flushIt = 1'b0;
-  always @ (*) begin
-    decode_arbitration_flushNext = 1'b0;
-    if(IBusCachedPlugin_redoBranch_valid)begin
-      decode_arbitration_flushNext = 1'b1;
-    end
-    if(_zz_282_)begin
-      decode_arbitration_flushNext = 1'b1;
-    end
-  end
-
-  always @ (*) begin
-    execute_arbitration_haltItself = 1'b0;
-    if((_zz_244_ && (! dataCache_1__io_cpu_flush_ready)))begin
-      execute_arbitration_haltItself = 1'b1;
-    end
-    if(((dataCache_1__io_cpu_redo && execute_arbitration_isValid) && execute_MEMORY_ENABLE))begin
-      execute_arbitration_haltItself = 1'b1;
-    end
-    if(_zz_283_)begin
-      if((! execute_CsrPlugin_wfiWake))begin
-        execute_arbitration_haltItself = 1'b1;
-      end
-    end
-    if(_zz_271_)begin
-      if(execute_CsrPlugin_blockedBySideEffects)begin
-        execute_arbitration_haltItself = 1'b1;
-      end
-    end
-  end
-
-  assign execute_arbitration_haltByOther = 1'b0;
-  always @ (*) begin
-    execute_arbitration_removeIt = 1'b0;
-    if(CsrPlugin_selfException_valid)begin
-      execute_arbitration_removeIt = 1'b1;
-    end
-    if(execute_arbitration_isFlushed)begin
-      execute_arbitration_removeIt = 1'b1;
-    end
-  end
-
-  assign execute_arbitration_flushIt = 1'b0;
-  always @ (*) begin
-    execute_arbitration_flushNext = 1'b0;
-    if(CsrPlugin_selfException_valid)begin
-      execute_arbitration_flushNext = 1'b1;
-    end
-  end
-
-  always @ (*) begin
-    memory_arbitration_haltItself = 1'b0;
-    if(_zz_276_)begin
-      if(_zz_284_)begin
-        memory_arbitration_haltItself = 1'b1;
-      end
-    end
-    if(_zz_277_)begin
-      if(_zz_285_)begin
-        memory_arbitration_haltItself = 1'b1;
-      end
-    end
-  end
-
-  assign memory_arbitration_haltByOther = 1'b0;
-  always @ (*) begin
-    memory_arbitration_removeIt = 1'b0;
-    if(BranchPlugin_branchExceptionPort_valid)begin
-      memory_arbitration_removeIt = 1'b1;
-    end
-    if(memory_arbitration_isFlushed)begin
-      memory_arbitration_removeIt = 1'b1;
-    end
-  end
-
-  assign memory_arbitration_flushIt = 1'b0;
-  always @ (*) begin
-    memory_arbitration_flushNext = 1'b0;
-    if(BranchPlugin_jumpInterface_valid)begin
-      memory_arbitration_flushNext = 1'b1;
-    end
-    if(BranchPlugin_branchExceptionPort_valid)begin
-      memory_arbitration_flushNext = 1'b1;
-    end
-  end
-
-  always @ (*) begin
-    writeBack_arbitration_haltItself = 1'b0;
-    if(dataCache_1__io_cpu_writeBack_haltIt)begin
-      writeBack_arbitration_haltItself = 1'b1;
-    end
-  end
-
-  assign writeBack_arbitration_haltByOther = 1'b0;
-  always @ (*) begin
-    writeBack_arbitration_removeIt = 1'b0;
-    if(DBusCachedPlugin_exceptionBus_valid)begin
-      writeBack_arbitration_removeIt = 1'b1;
-    end
-    if(writeBack_arbitration_isFlushed)begin
-      writeBack_arbitration_removeIt = 1'b1;
-    end
-  end
-
-  always @ (*) begin
-    writeBack_arbitration_flushIt = 1'b0;
-    if(DBusCachedPlugin_redoBranch_valid)begin
-      writeBack_arbitration_flushIt = 1'b1;
-    end
-  end
-
-  always @ (*) begin
-    writeBack_arbitration_flushNext = 1'b0;
-    if(DBusCachedPlugin_redoBranch_valid)begin
-      writeBack_arbitration_flushNext = 1'b1;
-    end
-    if(DBusCachedPlugin_exceptionBus_valid)begin
-      writeBack_arbitration_flushNext = 1'b1;
-    end
-    if(_zz_286_)begin
-      writeBack_arbitration_flushNext = 1'b1;
-    end
-    if(_zz_287_)begin
-      writeBack_arbitration_flushNext = 1'b1;
-    end
-  end
-
-  assign lastStageInstruction = writeBack_INSTRUCTION;
-  assign lastStagePc = writeBack_PC;
-  assign lastStageIsValid = writeBack_arbitration_isValid;
-  assign lastStageIsFiring = writeBack_arbitration_isFiring;
-  always @ (*) begin
-    IBusCachedPlugin_fetcherHalt = 1'b0;
-    if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != (4'b0000)))begin
-      IBusCachedPlugin_fetcherHalt = 1'b1;
-    end
-    if(_zz_286_)begin
-      IBusCachedPlugin_fetcherHalt = 1'b1;
-    end
-    if(_zz_287_)begin
-      IBusCachedPlugin_fetcherHalt = 1'b1;
-    end
-  end
-
-  always @ (*) begin
-    IBusCachedPlugin_fetcherflushIt = 1'b0;
-    if(({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != (4'b0000)))begin
-      IBusCachedPlugin_fetcherflushIt = 1'b1;
-    end
-  end
-
-  always @ (*) begin
-    IBusCachedPlugin_incomingInstruction = 1'b0;
-    if(((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid) || IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid))begin
-      IBusCachedPlugin_incomingInstruction = 1'b1;
-    end
-  end
-
-  always @ (*) begin
-    CsrPlugin_jumpInterface_valid = 1'b0;
-    if(_zz_286_)begin
-      CsrPlugin_jumpInterface_valid = 1'b1;
-    end
-    if(_zz_287_)begin
-      CsrPlugin_jumpInterface_valid = 1'b1;
-    end
-  end
-
-  always @ (*) begin
-    CsrPlugin_jumpInterface_payload = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx);
-    if(_zz_286_)begin
-      CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,(2'b00)};
-    end
-    if(_zz_287_)begin
-      case(_zz_288_)
-        2'b11 : begin
-          CsrPlugin_jumpInterface_payload = CsrPlugin_mepc;
-        end
-        2'b01 : begin
-          CsrPlugin_jumpInterface_payload = CsrPlugin_sepc;
-        end
-        default : begin
-        end
-      endcase
-    end
-  end
-
-  assign CsrPlugin_forceMachineWire = 1'b0;
-  assign CsrPlugin_allowInterrupts = 1'b1;
-  assign CsrPlugin_allowException = 1'b1;
-  assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_redoBranch_valid}}} != (4'b0000));
-  assign _zz_98_ = {IBusCachedPlugin_redoBranch_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}};
-  assign _zz_99_ = (_zz_98_ & (~ _zz_330_));
-  assign _zz_100_ = _zz_99_[3];
-  assign _zz_101_ = (_zz_99_[1] || _zz_100_);
-  assign _zz_102_ = (_zz_99_[2] || _zz_100_);
-  assign IBusCachedPlugin_jump_pcLoad_payload = _zz_248_;
-  always @ (*) begin
-    IBusCachedPlugin_fetchPc_corrected = 1'b0;
-    if(IBusCachedPlugin_jump_pcLoad_valid)begin
-      IBusCachedPlugin_fetchPc_corrected = 1'b1;
-    end
-  end
-
-  always @ (*) begin
-    IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0;
-    if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin
-      IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1;
-    end
-  end
-
-  always @ (*) begin
-    IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_332_);
-    if(IBusCachedPlugin_jump_pcLoad_valid)begin
-      IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload;
-    end
-    IBusCachedPlugin_fetchPc_pc[0] = 1'b0;
-    IBusCachedPlugin_fetchPc_pc[1] = 1'b0;
-  end
-
-  assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted);
-  assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc;
-  assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid;
-  assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready;
-  assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload;
-  assign IBusCachedPlugin_iBusRsp_stages_0_inputSample = 1'b1;
-  assign IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0;
-  assign _zz_103_ = (! IBusCachedPlugin_iBusRsp_stages_0_halt);
-  assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_103_);
-  assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_103_);
-  assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload;
-  always @ (*) begin
-    IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0;
-    if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin
-      IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1;
-    end
-  end
-
-  assign _zz_104_ = (! IBusCachedPlugin_iBusRsp_stages_1_halt);
-  assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_104_);
-  assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_104_);
-  assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload;
-  always @ (*) begin
-    IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0;
-    if(IBusCachedPlugin_cache_io_cpu_fetch_haltIt)begin
-      IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1;
-    end
-  end
-
-  assign _zz_105_ = (! IBusCachedPlugin_iBusRsp_stages_2_halt);
-  assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_105_);
-  assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_105_);
-  assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload;
-  always @ (*) begin
-    IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b0;
-    if((IBusCachedPlugin_rsp_issueDetected || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin
-      IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b1;
-    end
-  end
-
-  assign _zz_106_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt);
-  assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready && _zz_106_);
-  assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && _zz_106_);
-  assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload;
-  assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_107_;
-  assign _zz_107_ = ((1'b0 && (! _zz_108_)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready);
-  assign _zz_108_ = _zz_109_;
-  assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_108_;
-  assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg;
-  assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_110_)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready);
-  assign _zz_110_ = _zz_111_;
-  assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_110_;
-  assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_112_;
-  assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = ((1'b0 && (! _zz_113_)) || IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready);
-  assign _zz_113_ = _zz_114_;
-  assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid = _zz_113_;
-  assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload = _zz_115_;
-  always @ (*) begin
-    IBusCachedPlugin_iBusRsp_readyForError = 1'b1;
-    if((! IBusCachedPlugin_pcValids_0))begin
-      IBusCachedPlugin_iBusRsp_readyForError = 1'b0;
-    end
-  end
-
-  assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_2;
-  assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_3;
-  assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_4;
-  assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_5;
-  assign IBusCachedPlugin_iBusRsp_decodeInput_ready = (! decode_arbitration_isStuck);
-  assign decode_arbitration_isValid = (IBusCachedPlugin_iBusRsp_decodeInput_valid && (! IBusCachedPlugin_injector_decodeRemoved));
-  assign _zz_97_ = IBusCachedPlugin_iBusRsp_decodeInput_payload_pc;
-  assign _zz_96_ = IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst;
-  assign _zz_95_ = (decode_PC + (32'b00000000000000000000000000000100));
-  assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid;
-  always @ (*) begin
-    iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address;
-    iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address;
-  end
-
-  assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size;
-  assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0;
-  assign _zz_221_ = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit));
-  assign _zz_224_ = (32'b00000000000000000000000000000000);
-  assign _zz_222_ = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit));
-  assign _zz_223_ = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready);
-  assign _zz_225_ = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit));
-  assign _zz_226_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready);
-  assign _zz_227_ = (CsrPlugin_privilege == (2'b00));
-  assign _zz_92_ = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data);
-  assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0;
-  always @ (*) begin
-    IBusCachedPlugin_rsp_redoFetch = 1'b0;
-    if(_zz_281_)begin
-      IBusCachedPlugin_rsp_redoFetch = 1'b1;
-    end
-    if(_zz_279_)begin
-      IBusCachedPlugin_rsp_redoFetch = 1'b1;
-    end
-    if(_zz_289_)begin
-      IBusCachedPlugin_rsp_redoFetch = 1'b0;
-    end
-  end
-
-  always @ (*) begin
-    _zz_228_ = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling));
-    if(_zz_279_)begin
-      _zz_228_ = 1'b1;
-    end
-    if(_zz_289_)begin
-      _zz_228_ = 1'b0;
-    end
-  end
-
-  always @ (*) begin
-    IBusCachedPlugin_decodeExceptionPort_valid = 1'b0;
-    if(_zz_280_)begin
-      IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError;
-    end
-    if(_zz_278_)begin
-      IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError;
-    end
-  end
-
-  always @ (*) begin
-    IBusCachedPlugin_decodeExceptionPort_payload_code = (4'bxxxx);
-    if(_zz_280_)begin
-      IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b1100);
-    end
-    if(_zz_278_)begin
-      IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b0001);
-    end
-  end
-
-  assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload[31 : 2],(2'b00)};
-  assign IBusCachedPlugin_redoBranch_valid = IBusCachedPlugin_rsp_redoFetch;
-  assign IBusCachedPlugin_redoBranch_payload = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload;
-  assign IBusCachedPlugin_iBusRsp_decodeInput_valid = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid;
-  assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready = IBusCachedPlugin_iBusRsp_decodeInput_ready;
-  assign IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data;
-  assign IBusCachedPlugin_iBusRsp_decodeInput_payload_pc = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload;
-  assign IBusCachedPlugin_mmuBus_cmd_isValid = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid;
-  assign IBusCachedPlugin_mmuBus_cmd_virtualAddress = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress;
-  assign IBusCachedPlugin_mmuBus_cmd_bypassTranslation = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation;
-  assign IBusCachedPlugin_mmuBus_end = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end;
-  assign _zz_220_ = (decode_arbitration_isValid && decode_FLUSH_ALL);
-  assign dataCache_1__io_mem_cmd_s2mPipe_valid = (dataCache_1__io_mem_cmd_valid || _zz_117_);
-  assign _zz_245_ = (! _zz_117_);
-  assign dataCache_1__io_mem_cmd_s2mPipe_payload_wr = (_zz_117_ ? _zz_118_ : dataCache_1__io_mem_cmd_payload_wr);
-  assign dataCache_1__io_mem_cmd_s2mPipe_payload_address = (_zz_117_ ? _zz_119_ : dataCache_1__io_mem_cmd_payload_address);
-  assign dataCache_1__io_mem_cmd_s2mPipe_payload_data = (_zz_117_ ? _zz_120_ : dataCache_1__io_mem_cmd_payload_data);
-  assign dataCache_1__io_mem_cmd_s2mPipe_payload_mask = (_zz_117_ ? _zz_121_ : dataCache_1__io_mem_cmd_payload_mask);
-  assign dataCache_1__io_mem_cmd_s2mPipe_payload_length = (_zz_117_ ? _zz_122_ : dataCache_1__io_mem_cmd_payload_length);
-  assign dataCache_1__io_mem_cmd_s2mPipe_payload_last = (_zz_117_ ? _zz_123_ : dataCache_1__io_mem_cmd_payload_last);
-  assign dataCache_1__io_mem_cmd_s2mPipe_ready = ((1'b1 && (! dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_valid)) || dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_ready);
-  assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_valid = _zz_124_;
-  assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_wr = _zz_125_;
-  assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_address = _zz_126_;
-  assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_data = _zz_127_;
-  assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_mask = _zz_128_;
-  assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_length = _zz_129_;
-  assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_last = _zz_130_;
-  assign dBus_cmd_valid = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_valid;
-  assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready;
-  assign dBus_cmd_payload_wr = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_wr;
-  assign dBus_cmd_payload_address = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_address;
-  assign dBus_cmd_payload_data = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_data;
-  assign dBus_cmd_payload_mask = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_mask;
-  assign dBus_cmd_payload_length = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_length;
-  assign dBus_cmd_payload_last = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_last;
-  assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12];
-  always @ (*) begin
-    _zz_229_ = (execute_arbitration_isValid && execute_MEMORY_ENABLE);
-    if(MmuPlugin_dBusAccess_cmd_valid)begin
-      if(_zz_290_)begin
-        if(_zz_291_)begin
-          _zz_229_ = 1'b1;
-        end
-      end
-    end
-  end
-
-  always @ (*) begin
-    _zz_230_ = execute_SRC_ADD;
-    if(MmuPlugin_dBusAccess_cmd_valid)begin
-      if(_zz_290_)begin
-        _zz_230_ = MmuPlugin_dBusAccess_cmd_payload_address;
-      end
-    end
-  end
-
-  always @ (*) begin
-    _zz_231_ = execute_MEMORY_WR;
-    if(MmuPlugin_dBusAccess_cmd_valid)begin
-      if(_zz_290_)begin
-        _zz_231_ = MmuPlugin_dBusAccess_cmd_payload_write;
-      end
-    end
-  end
-
-  always @ (*) begin
-    case(execute_DBusCachedPlugin_size)
-      2'b00 : begin
-        _zz_132_ = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]};
-      end
-      2'b01 : begin
-        _zz_132_ = {execute_RS2[15 : 0],execute_RS2[15 : 0]};
-      end
-      default : begin
-        _zz_132_ = execute_RS2[31 : 0];
-      end
-    endcase
-  end
-
-  always @ (*) begin
-    _zz_232_ = _zz_132_;
-    if(MmuPlugin_dBusAccess_cmd_valid)begin
-      if(_zz_290_)begin
-        _zz_232_ = MmuPlugin_dBusAccess_cmd_payload_data;
-      end
-    end
-  end
-
-  always @ (*) begin
-    _zz_233_ = execute_DBusCachedPlugin_size;
-    if(MmuPlugin_dBusAccess_cmd_valid)begin
-      if(_zz_290_)begin
-        _zz_233_ = MmuPlugin_dBusAccess_cmd_payload_size;
-      end
-    end
-  end
-
-  assign _zz_244_ = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT);
-  always @ (*) begin
-    _zz_234_ = 1'b0;
-    if(execute_MEMORY_LRSC)begin
-      _zz_234_ = 1'b1;
-    end
-    if(MmuPlugin_dBusAccess_cmd_valid)begin
-      if(_zz_290_)begin
-        _zz_234_ = 1'b0;
-      end
-    end
-  end
-
-  always @ (*) begin
-    _zz_235_ = execute_MEMORY_AMO;
-    if(MmuPlugin_dBusAccess_cmd_valid)begin
-      if(_zz_290_)begin
-        _zz_235_ = 1'b0;
-      end
-    end
-  end
-
-  assign _zz_237_ = execute_INSTRUCTION[31 : 29];
-  assign _zz_236_ = execute_INSTRUCTION[27];
-  assign _zz_88_ = _zz_230_[1 : 0];
-  always @ (*) begin
-    _zz_238_ = (memory_arbitration_isValid && memory_MEMORY_ENABLE);
-    if(memory_IS_DBUS_SHARING)begin
-      _zz_238_ = 1'b1;
-    end
-  end
-
-  assign _zz_239_ = memory_REGFILE_WRITE_DATA;
-  assign DBusCachedPlugin_mmuBus_cmd_isValid = dataCache_1__io_cpu_memory_mmuBus_cmd_isValid;
-  assign DBusCachedPlugin_mmuBus_cmd_virtualAddress = dataCache_1__io_cpu_memory_mmuBus_cmd_virtualAddress;
-  always @ (*) begin
-    DBusCachedPlugin_mmuBus_cmd_bypassTranslation = dataCache_1__io_cpu_memory_mmuBus_cmd_bypassTranslation;
-    if(memory_IS_DBUS_SHARING)begin
-      DBusCachedPlugin_mmuBus_cmd_bypassTranslation = 1'b1;
-    end
-  end
-
-  always @ (*) begin
-    _zz_240_ = DBusCachedPlugin_mmuBus_rsp_isIoAccess;
-    if((1'b0 && (! dataCache_1__io_cpu_memory_isWrite)))begin
-      _zz_240_ = 1'b1;
-    end
-  end
-
-  assign DBusCachedPlugin_mmuBus_end = dataCache_1__io_cpu_memory_mmuBus_end;
-  always @ (*) begin
-    _zz_241_ = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE);
-    if(writeBack_IS_DBUS_SHARING)begin
-      _zz_241_ = 1'b1;
-    end
-  end
-
-  assign _zz_242_ = (CsrPlugin_privilege == (2'b00));
-  assign _zz_243_ = writeBack_REGFILE_WRITE_DATA;
-  always @ (*) begin
-    DBusCachedPlugin_redoBranch_valid = 1'b0;
-    if(_zz_292_)begin
-      if(dataCache_1__io_cpu_redo)begin
-        DBusCachedPlugin_redoBranch_valid = 1'b1;
-      end
-    end
-  end
-
-  assign DBusCachedPlugin_redoBranch_payload = writeBack_PC;
-  always @ (*) begin
-    DBusCachedPlugin_exceptionBus_valid = 1'b0;
-    if(_zz_292_)begin
-      if(dataCache_1__io_cpu_writeBack_accessError)begin
-        DBusCachedPlugin_exceptionBus_valid = 1'b1;
-      end
-      if(dataCache_1__io_cpu_writeBack_unalignedAccess)begin
-        DBusCachedPlugin_exceptionBus_valid = 1'b1;
-      end
-      if(dataCache_1__io_cpu_writeBack_mmuException)begin
-        DBusCachedPlugin_exceptionBus_valid = 1'b1;
-      end
-      if(dataCache_1__io_cpu_redo)begin
-        DBusCachedPlugin_exceptionBus_valid = 1'b0;
-      end
-    end
-  end
-
-  assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA;
-  always @ (*) begin
-    DBusCachedPlugin_exceptionBus_payload_code = (4'bxxxx);
-    if(_zz_292_)begin
-      if(dataCache_1__io_cpu_writeBack_accessError)begin
-        DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_333_};
-      end
-      if(dataCache_1__io_cpu_writeBack_unalignedAccess)begin
-        DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_334_};
-      end
-      if(dataCache_1__io_cpu_writeBack_mmuException)begin
-        DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? (4'b1111) : (4'b1101));
-      end
-    end
-  end
-
-  always @ (*) begin
-    writeBack_DBusCachedPlugin_rspShifted = dataCache_1__io_cpu_writeBack_data;
-    case(writeBack_MEMORY_ADDRESS_LOW)
-      2'b01 : begin
-        writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1__io_cpu_writeBack_data[15 : 8];
-      end
-      2'b10 : begin
-        writeBack_DBusCachedPlugin_rspShifted[15 : 0] = dataCache_1__io_cpu_writeBack_data[31 : 16];
-      end
-      2'b11 : begin
-        writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1__io_cpu_writeBack_data[31 : 24];
-      end
-      default : begin
-      end
-    endcase
-  end
-
-  assign _zz_133_ = (writeBack_DBusCachedPlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14]));
-  always @ (*) begin
-    _zz_134_[31] = _zz_133_;
-    _zz_134_[30] = _zz_133_;
-    _zz_134_[29] = _zz_133_;
-    _zz_134_[28] = _zz_133_;
-    _zz_134_[27] = _zz_133_;
-    _zz_134_[26] = _zz_133_;
-    _zz_134_[25] = _zz_133_;
-    _zz_134_[24] = _zz_133_;
-    _zz_134_[23] = _zz_133_;
-    _zz_134_[22] = _zz_133_;
-    _zz_134_[21] = _zz_133_;
-    _zz_134_[20] = _zz_133_;
-    _zz_134_[19] = _zz_133_;
-    _zz_134_[18] = _zz_133_;
-    _zz_134_[17] = _zz_133_;
-    _zz_134_[16] = _zz_133_;
-    _zz_134_[15] = _zz_133_;
-    _zz_134_[14] = _zz_133_;
-    _zz_134_[13] = _zz_133_;
-    _zz_134_[12] = _zz_133_;
-    _zz_134_[11] = _zz_133_;
-    _zz_134_[10] = _zz_133_;
-    _zz_134_[9] = _zz_133_;
-    _zz_134_[8] = _zz_133_;
-    _zz_134_[7 : 0] = writeBack_DBusCachedPlugin_rspShifted[7 : 0];
-  end
-
-  assign _zz_135_ = (writeBack_DBusCachedPlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14]));
-  always @ (*) begin
-    _zz_136_[31] = _zz_135_;
-    _zz_136_[30] = _zz_135_;
-    _zz_136_[29] = _zz_135_;
-    _zz_136_[28] = _zz_135_;
-    _zz_136_[27] = _zz_135_;
-    _zz_136_[26] = _zz_135_;
-    _zz_136_[25] = _zz_135_;
-    _zz_136_[24] = _zz_135_;
-    _zz_136_[23] = _zz_135_;
-    _zz_136_[22] = _zz_135_;
-    _zz_136_[21] = _zz_135_;
-    _zz_136_[20] = _zz_135_;
-    _zz_136_[19] = _zz_135_;
-    _zz_136_[18] = _zz_135_;
-    _zz_136_[17] = _zz_135_;
-    _zz_136_[16] = _zz_135_;
-    _zz_136_[15 : 0] = writeBack_DBusCachedPlugin_rspShifted[15 : 0];
-  end
-
-  always @ (*) begin
-    case(_zz_328_)
-      2'b00 : begin
-        writeBack_DBusCachedPlugin_rspFormated = _zz_134_;
-      end
-      2'b01 : begin
-        writeBack_DBusCachedPlugin_rspFormated = _zz_136_;
-      end
-      default : begin
-        writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspShifted;
-      end
-    endcase
-  end
-
-  always @ (*) begin
-    MmuPlugin_dBusAccess_cmd_ready = 1'b0;
-    if(MmuPlugin_dBusAccess_cmd_valid)begin
-      if(_zz_290_)begin
-        if(_zz_291_)begin
-          MmuPlugin_dBusAccess_cmd_ready = (! execute_arbitration_isStuck);
-        end
-      end
-    end
-  end
-
-  always @ (*) begin
-    DBusCachedPlugin_forceDatapath = 1'b0;
-    if(MmuPlugin_dBusAccess_cmd_valid)begin
-      if(_zz_290_)begin
-        DBusCachedPlugin_forceDatapath = 1'b1;
-      end
-    end
-  end
-
-  assign _zz_86_ = (MmuPlugin_dBusAccess_cmd_valid && MmuPlugin_dBusAccess_cmd_ready);
-  assign MmuPlugin_dBusAccess_rsp_valid = ((writeBack_IS_DBUS_SHARING && (! dataCache_1__io_cpu_writeBack_isWrite)) && (dataCache_1__io_cpu_redo || (! dataCache_1__io_cpu_writeBack_haltIt)));
-  assign MmuPlugin_dBusAccess_rsp_payload_data = dataCache_1__io_cpu_writeBack_data;
-  assign MmuPlugin_dBusAccess_rsp_payload_error = (dataCache_1__io_cpu_writeBack_unalignedAccess || dataCache_1__io_cpu_writeBack_accessError);
-  assign MmuPlugin_dBusAccess_rsp_payload_redo = dataCache_1__io_cpu_redo;
-  assign MmuPlugin_ports_0_cacheHits_0 = ((MmuPlugin_ports_0_cache_0_valid && (MmuPlugin_ports_0_cache_0_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_0_superPage || (MmuPlugin_ports_0_cache_0_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_virtualAddress[21 : 12])));
-  assign MmuPlugin_ports_0_cacheHits_1 = ((MmuPlugin_ports_0_cache_1_valid && (MmuPlugin_ports_0_cache_1_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_1_superPage || (MmuPlugin_ports_0_cache_1_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_virtualAddress[21 : 12])));
-  assign MmuPlugin_ports_0_cacheHits_2 = ((MmuPlugin_ports_0_cache_2_valid && (MmuPlugin_ports_0_cache_2_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_2_superPage || (MmuPlugin_ports_0_cache_2_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_virtualAddress[21 : 12])));
-  assign MmuPlugin_ports_0_cacheHits_3 = ((MmuPlugin_ports_0_cache_3_valid && (MmuPlugin_ports_0_cache_3_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_3_superPage || (MmuPlugin_ports_0_cache_3_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_virtualAddress[21 : 12])));
-  assign MmuPlugin_ports_0_cacheHit = ({MmuPlugin_ports_0_cacheHits_3,{MmuPlugin_ports_0_cacheHits_2,{MmuPlugin_ports_0_cacheHits_1,MmuPlugin_ports_0_cacheHits_0}}} != (4'b0000));
-  assign _zz_137_ = (MmuPlugin_ports_0_cacheHits_1 || MmuPlugin_ports_0_cacheHits_3);
-  assign _zz_138_ = (MmuPlugin_ports_0_cacheHits_2 || MmuPlugin_ports_0_cacheHits_3);
-  assign _zz_139_ = {_zz_138_,_zz_137_};
-  assign MmuPlugin_ports_0_cacheLine_valid = _zz_249_;
-  assign MmuPlugin_ports_0_cacheLine_exception = _zz_250_;
-  assign MmuPlugin_ports_0_cacheLine_superPage = _zz_251_;
-  assign MmuPlugin_ports_0_cacheLine_virtualAddress_0 = _zz_252_;
-  assign MmuPlugin_ports_0_cacheLine_virtualAddress_1 = _zz_253_;
-  assign MmuPlugin_ports_0_cacheLine_physicalAddress_0 = _zz_254_;
-  assign MmuPlugin_ports_0_cacheLine_physicalAddress_1 = _zz_255_;
-  assign MmuPlugin_ports_0_cacheLine_allowRead = _zz_256_;
-  assign MmuPlugin_ports_0_cacheLine_allowWrite = _zz_257_;
-  assign MmuPlugin_ports_0_cacheLine_allowExecute = _zz_258_;
-  assign MmuPlugin_ports_0_cacheLine_allowUser = _zz_259_;
-  always @ (*) begin
-    MmuPlugin_ports_0_entryToReplace_willIncrement = 1'b0;
-    if(_zz_293_)begin
-      if(_zz_294_)begin
-        MmuPlugin_ports_0_entryToReplace_willIncrement = 1'b1;
-      end
-    end
-  end
-
-  assign MmuPlugin_ports_0_entryToReplace_willClear = 1'b0;
-  assign MmuPlugin_ports_0_entryToReplace_willOverflowIfInc = (MmuPlugin_ports_0_entryToReplace_value == (2'b11));
-  assign MmuPlugin_ports_0_entryToReplace_willOverflow = (MmuPlugin_ports_0_entryToReplace_willOverflowIfInc && MmuPlugin_ports_0_entryToReplace_willIncrement);
-  always @ (*) begin
-    MmuPlugin_ports_0_entryToReplace_valueNext = (MmuPlugin_ports_0_entryToReplace_value + _zz_336_);
-    if(MmuPlugin_ports_0_entryToReplace_willClear)begin
-      MmuPlugin_ports_0_entryToReplace_valueNext = (2'b00);
-    end
-  end
-
-  always @ (*) begin
-    MmuPlugin_ports_0_requireMmuLockup = ((1'b1 && (! DBusCachedPlugin_mmuBus_cmd_bypassTranslation)) && MmuPlugin_satp_mode);
-    if(((! MmuPlugin_status_mprv) && (CsrPlugin_privilege == (2'b11))))begin
-      MmuPlugin_ports_0_requireMmuLockup = 1'b0;
-    end
-    if((CsrPlugin_privilege == (2'b11)))begin
-      if(((! MmuPlugin_status_mprv) || (CsrPlugin_mstatus_MPP == (2'b11))))begin
-        MmuPlugin_ports_0_requireMmuLockup = 1'b0;
-      end
-    end
-  end
-
-  always @ (*) begin
-    if(MmuPlugin_ports_0_requireMmuLockup)begin
-      DBusCachedPlugin_mmuBus_rsp_physicalAddress = {{MmuPlugin_ports_0_cacheLine_physicalAddress_1,(MmuPlugin_ports_0_cacheLine_superPage ? DBusCachedPlugin_mmuBus_cmd_virtualAddress[21 : 12] : MmuPlugin_ports_0_cacheLine_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_virtualAddress[11 : 0]};
-    end else begin
-      DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_virtualAddress;
-    end
-  end
-
-  always @ (*) begin
-    if(MmuPlugin_ports_0_requireMmuLockup)begin
-      DBusCachedPlugin_mmuBus_rsp_allowRead = (MmuPlugin_ports_0_cacheLine_allowRead || (MmuPlugin_status_mxr && MmuPlugin_ports_0_cacheLine_allowExecute));
-    end else begin
-      DBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1;
-    end
-  end
-
-  always @ (*) begin
-    if(MmuPlugin_ports_0_requireMmuLockup)begin
-      DBusCachedPlugin_mmuBus_rsp_allowWrite = MmuPlugin_ports_0_cacheLine_allowWrite;
-    end else begin
-      DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1;
-    end
-  end
-
-  always @ (*) begin
-    if(MmuPlugin_ports_0_requireMmuLockup)begin
-      DBusCachedPlugin_mmuBus_rsp_allowExecute = MmuPlugin_ports_0_cacheLine_allowExecute;
-    end else begin
-      DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1;
-    end
-  end
-
-  always @ (*) begin
-    if(MmuPlugin_ports_0_requireMmuLockup)begin
-      DBusCachedPlugin_mmuBus_rsp_exception = (MmuPlugin_ports_0_cacheHit && ((MmuPlugin_ports_0_cacheLine_exception || ((MmuPlugin_ports_0_cacheLine_allowUser && (CsrPlugin_privilege == (2'b01))) && (! MmuPlugin_status_sum))) || ((! MmuPlugin_ports_0_cacheLine_allowUser) && (CsrPlugin_privilege == (2'b00)))));
-    end else begin
-      DBusCachedPlugin_mmuBus_rsp_exception = 1'b0;
-    end
-  end
-
-  always @ (*) begin
-    if(MmuPlugin_ports_0_requireMmuLockup)begin
-      DBusCachedPlugin_mmuBus_rsp_refilling = (! MmuPlugin_ports_0_cacheHit);
-    end else begin
-      DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0;
-    end
-  end
-
-  assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = (((DBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == (4'b1011)) || (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == (4'b1110))) || (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == (4'b1111)));
-  assign MmuPlugin_ports_1_cacheHits_0 = ((MmuPlugin_ports_1_cache_0_valid && (MmuPlugin_ports_1_cache_0_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_0_superPage || (MmuPlugin_ports_1_cache_0_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_virtualAddress[21 : 12])));
-  assign MmuPlugin_ports_1_cacheHits_1 = ((MmuPlugin_ports_1_cache_1_valid && (MmuPlugin_ports_1_cache_1_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_1_superPage || (MmuPlugin_ports_1_cache_1_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_virtualAddress[21 : 12])));
-  assign MmuPlugin_ports_1_cacheHits_2 = ((MmuPlugin_ports_1_cache_2_valid && (MmuPlugin_ports_1_cache_2_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_2_superPage || (MmuPlugin_ports_1_cache_2_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_virtualAddress[21 : 12])));
-  assign MmuPlugin_ports_1_cacheHits_3 = ((MmuPlugin_ports_1_cache_3_valid && (MmuPlugin_ports_1_cache_3_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_3_superPage || (MmuPlugin_ports_1_cache_3_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_virtualAddress[21 : 12])));
-  assign MmuPlugin_ports_1_cacheHit = ({MmuPlugin_ports_1_cacheHits_3,{MmuPlugin_ports_1_cacheHits_2,{MmuPlugin_ports_1_cacheHits_1,MmuPlugin_ports_1_cacheHits_0}}} != (4'b0000));
-  assign _zz_140_ = (MmuPlugin_ports_1_cacheHits_1 || MmuPlugin_ports_1_cacheHits_3);
-  assign _zz_141_ = (MmuPlugin_ports_1_cacheHits_2 || MmuPlugin_ports_1_cacheHits_3);
-  assign _zz_142_ = {_zz_141_,_zz_140_};
-  assign MmuPlugin_ports_1_cacheLine_valid = _zz_260_;
-  assign MmuPlugin_ports_1_cacheLine_exception = _zz_261_;
-  assign MmuPlugin_ports_1_cacheLine_superPage = _zz_262_;
-  assign MmuPlugin_ports_1_cacheLine_virtualAddress_0 = _zz_263_;
-  assign MmuPlugin_ports_1_cacheLine_virtualAddress_1 = _zz_264_;
-  assign MmuPlugin_ports_1_cacheLine_physicalAddress_0 = _zz_265_;
-  assign MmuPlugin_ports_1_cacheLine_physicalAddress_1 = _zz_266_;
-  assign MmuPlugin_ports_1_cacheLine_allowRead = _zz_267_;
-  assign MmuPlugin_ports_1_cacheLine_allowWrite = _zz_268_;
-  assign MmuPlugin_ports_1_cacheLine_allowExecute = _zz_269_;
-  assign MmuPlugin_ports_1_cacheLine_allowUser = _zz_270_;
-  always @ (*) begin
-    MmuPlugin_ports_1_entryToReplace_willIncrement = 1'b0;
-    if(_zz_293_)begin
-      if(_zz_295_)begin
-        MmuPlugin_ports_1_entryToReplace_willIncrement = 1'b1;
-      end
-    end
-  end
-
-  assign MmuPlugin_ports_1_entryToReplace_willClear = 1'b0;
-  assign MmuPlugin_ports_1_entryToReplace_willOverflowIfInc = (MmuPlugin_ports_1_entryToReplace_value == (2'b11));
-  assign MmuPlugin_ports_1_entryToReplace_willOverflow = (MmuPlugin_ports_1_entryToReplace_willOverflowIfInc && MmuPlugin_ports_1_entryToReplace_willIncrement);
-  always @ (*) begin
-    MmuPlugin_ports_1_entryToReplace_valueNext = (MmuPlugin_ports_1_entryToReplace_value + _zz_338_);
-    if(MmuPlugin_ports_1_entryToReplace_willClear)begin
-      MmuPlugin_ports_1_entryToReplace_valueNext = (2'b00);
-    end
-  end
-
-  always @ (*) begin
-    MmuPlugin_ports_1_requireMmuLockup = ((1'b1 && (! IBusCachedPlugin_mmuBus_cmd_bypassTranslation)) && MmuPlugin_satp_mode);
-    if(((! MmuPlugin_status_mprv) && (CsrPlugin_privilege == (2'b11))))begin
-      MmuPlugin_ports_1_requireMmuLockup = 1'b0;
-    end
-    if((CsrPlugin_privilege == (2'b11)))begin
-      MmuPlugin_ports_1_requireMmuLockup = 1'b0;
-    end
-  end
-
-  always @ (*) begin
-    if(MmuPlugin_ports_1_requireMmuLockup)begin
-      IBusCachedPlugin_mmuBus_rsp_physicalAddress = {{MmuPlugin_ports_1_cacheLine_physicalAddress_1,(MmuPlugin_ports_1_cacheLine_superPage ? IBusCachedPlugin_mmuBus_cmd_virtualAddress[21 : 12] : MmuPlugin_ports_1_cacheLine_physicalAddress_0)},IBusCachedPlugin_mmuBus_cmd_virtualAddress[11 : 0]};
-    end else begin
-      IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_virtualAddress;
-    end
-  end
-
-  always @ (*) begin
-    if(MmuPlugin_ports_1_requireMmuLockup)begin
-      IBusCachedPlugin_mmuBus_rsp_allowRead = (MmuPlugin_ports_1_cacheLine_allowRead || (MmuPlugin_status_mxr && MmuPlugin_ports_1_cacheLine_allowExecute));
-    end else begin
-      IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1;
-    end
-  end
-
-  always @ (*) begin
-    if(MmuPlugin_ports_1_requireMmuLockup)begin
-      IBusCachedPlugin_mmuBus_rsp_allowWrite = MmuPlugin_ports_1_cacheLine_allowWrite;
-    end else begin
-      IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1;
-    end
-  end
-
-  always @ (*) begin
-    if(MmuPlugin_ports_1_requireMmuLockup)begin
-      IBusCachedPlugin_mmuBus_rsp_allowExecute = MmuPlugin_ports_1_cacheLine_allowExecute;
-    end else begin
-      IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1;
-    end
-  end
-
-  always @ (*) begin
-    if(MmuPlugin_ports_1_requireMmuLockup)begin
-      IBusCachedPlugin_mmuBus_rsp_exception = (MmuPlugin_ports_1_cacheHit && ((MmuPlugin_ports_1_cacheLine_exception || ((MmuPlugin_ports_1_cacheLine_allowUser && (CsrPlugin_privilege == (2'b01))) && (! MmuPlugin_status_sum))) || ((! MmuPlugin_ports_1_cacheLine_allowUser) && (CsrPlugin_privilege == (2'b00)))));
-    end else begin
-      IBusCachedPlugin_mmuBus_rsp_exception = 1'b0;
-    end
-  end
-
-  always @ (*) begin
-    if(MmuPlugin_ports_1_requireMmuLockup)begin
-      IBusCachedPlugin_mmuBus_rsp_refilling = (! MmuPlugin_ports_1_cacheHit);
-    end else begin
-      IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0;
-    end
-  end
-
-  assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = (((IBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == (4'b1011)) || (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == (4'b1110))) || (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == (4'b1111)));
-  assign MmuPlugin_shared_dBusRsp_pte_V = _zz_339_[0];
-  assign MmuPlugin_shared_dBusRsp_pte_R = _zz_340_[0];
-  assign MmuPlugin_shared_dBusRsp_pte_W = _zz_341_[0];
-  assign MmuPlugin_shared_dBusRsp_pte_X = _zz_342_[0];
-  assign MmuPlugin_shared_dBusRsp_pte_U = _zz_343_[0];
-  assign MmuPlugin_shared_dBusRsp_pte_G = _zz_344_[0];
-  assign MmuPlugin_shared_dBusRsp_pte_A = _zz_345_[0];
-  assign MmuPlugin_shared_dBusRsp_pte_D = _zz_346_[0];
-  assign MmuPlugin_shared_dBusRsp_pte_RSW = MmuPlugin_dBusAccess_rsp_payload_data[9 : 8];
-  assign MmuPlugin_shared_dBusRsp_pte_PPN0 = MmuPlugin_dBusAccess_rsp_payload_data[19 : 10];
-  assign MmuPlugin_shared_dBusRsp_pte_PPN1 = MmuPlugin_dBusAccess_rsp_payload_data[31 : 20];
-  assign MmuPlugin_shared_dBusRsp_exception = (((! MmuPlugin_shared_dBusRsp_pte_V) || ((! MmuPlugin_shared_dBusRsp_pte_R) && MmuPlugin_shared_dBusRsp_pte_W)) || MmuPlugin_dBusAccess_rsp_payload_error);
-  assign MmuPlugin_shared_dBusRsp_leaf = (MmuPlugin_shared_dBusRsp_pte_R || MmuPlugin_shared_dBusRsp_pte_X);
-  always @ (*) begin
-    MmuPlugin_dBusAccess_cmd_valid = 1'b0;
-    case(MmuPlugin_shared_state_1_)
-      `MmuPlugin_shared_State_defaultEncoding_IDLE : begin
-      end
-      `MmuPlugin_shared_State_defaultEncoding_L1_CMD : begin
-        MmuPlugin_dBusAccess_cmd_valid = 1'b1;
-      end
-      `MmuPlugin_shared_State_defaultEncoding_L1_RSP : begin
-      end
-      `MmuPlugin_shared_State_defaultEncoding_L0_CMD : begin
-        MmuPlugin_dBusAccess_cmd_valid = 1'b1;
-      end
-      default : begin
-      end
-    endcase
-  end
-
-  assign MmuPlugin_dBusAccess_cmd_payload_write = 1'b0;
-  assign MmuPlugin_dBusAccess_cmd_payload_size = (2'b10);
-  always @ (*) begin
-    MmuPlugin_dBusAccess_cmd_payload_address = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx);
-    case(MmuPlugin_shared_state_1_)
-      `MmuPlugin_shared_State_defaultEncoding_IDLE : begin
-      end
-      `MmuPlugin_shared_State_defaultEncoding_L1_CMD : begin
-        MmuPlugin_dBusAccess_cmd_payload_address = {{MmuPlugin_satp_ppn,MmuPlugin_shared_vpn_1},(2'b00)};
-      end
-      `MmuPlugin_shared_State_defaultEncoding_L1_RSP : begin
-      end
-      `MmuPlugin_shared_State_defaultEncoding_L0_CMD : begin
-        MmuPlugin_dBusAccess_cmd_payload_address = {{{MmuPlugin_shared_pteBuffer_PPN1[9 : 0],MmuPlugin_shared_pteBuffer_PPN0},MmuPlugin_shared_vpn_0},(2'b00)};
-      end
-      default : begin
-      end
-    endcase
-  end
-
-  assign MmuPlugin_dBusAccess_cmd_payload_data = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx);
-  assign MmuPlugin_dBusAccess_cmd_payload_writeMask = (4'bxxxx);
-  assign DBusCachedPlugin_mmuBus_busy = ((MmuPlugin_shared_state_1_ != `MmuPlugin_shared_State_defaultEncoding_IDLE) && (MmuPlugin_shared_portId == (1'b1)));
-  assign IBusCachedPlugin_mmuBus_busy = ((MmuPlugin_shared_state_1_ != `MmuPlugin_shared_State_defaultEncoding_IDLE) && (MmuPlugin_shared_portId == (1'b0)));
-  assign _zz_144_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000001100)) == (32'b00000000000000000000000000000100));
-  assign _zz_145_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001001000)) == (32'b00000000000000000000000001001000));
-  assign _zz_146_ = ((decode_INSTRUCTION & (32'b00000000000000000111000000000000)) == (32'b00000000000000000001000000000000));
-  assign _zz_147_ = ((decode_INSTRUCTION & (32'b00000000000000000011000000000000)) == (32'b00000000000000000010000000000000));
-  assign _zz_148_ = ((decode_INSTRUCTION & (32'b00000000000000000101000000000000)) == (32'b00000000000000000100000000000000));
-  assign _zz_149_ = ((decode_INSTRUCTION & (32'b00000000000000000010000001010000)) == (32'b00000000000000000010000000000000));
-  assign _zz_150_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000000100)) == (32'b00000000000000000000000000000100));
-  assign _zz_151_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001010000)) == (32'b00000000000000000100000001010000));
-  assign _zz_143_ = {(((decode_INSTRUCTION & _zz_459_) == (32'b00000000000000000000000000001000)) != (1'b0)),{({_zz_460_,{_zz_461_,_zz_462_}} != (4'b0000)),{({_zz_463_,_zz_464_} != (3'b000)),{(_zz_465_ != _zz_466_),{_zz_467_,{_zz_468_,_zz_469_}}}}}};
-  assign _zz_85_ = ({((decode_INSTRUCTION & (32'b00000000000000000000000001011111)) == (32'b00000000000000000000000000010111)),{((decode_INSTRUCTION & (32'b00000000000000000000000001111111)) == (32'b00000000000000000000000001101111)),{((decode_INSTRUCTION & (32'b00000000000000000001000001101111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_634_) == (32'b00000000000000000001000001110011)),{(_zz_635_ == _zz_636_),{_zz_637_,{_zz_638_,_zz_639_}}}}}}} != (25'b0000000000000000000000000));
-  assign _zz_84_ = _zz_347_[0];
-  assign _zz_83_ = _zz_348_[0];
-  assign _zz_152_ = _zz_143_[3 : 2];
-  assign _zz_82_ = _zz_152_;
-  assign _zz_153_ = _zz_143_[5 : 4];
-  assign _zz_81_ = _zz_153_;
-  assign _zz_80_ = _zz_349_[0];
-  assign _zz_79_ = _zz_350_[0];
-  assign _zz_154_ = _zz_143_[9 : 8];
-  assign _zz_78_ = _zz_154_;
-  assign _zz_77_ = _zz_351_[0];
-  assign _zz_76_ = _zz_352_[0];
-  assign _zz_75_ = _zz_353_[0];
-  assign _zz_74_ = _zz_354_[0];
-  assign _zz_73_ = _zz_355_[0];
-  assign _zz_72_ = _zz_356_[0];
-  assign _zz_71_ = _zz_357_[0];
-  assign _zz_155_ = _zz_143_[19 : 18];
-  assign _zz_70_ = _zz_155_;
-  assign _zz_69_ = _zz_358_[0];
-  assign _zz_68_ = _zz_359_[0];
-  assign _zz_67_ = _zz_360_[0];
-  assign _zz_156_ = _zz_143_[24 : 23];
-  assign _zz_66_ = _zz_156_;
-  assign _zz_65_ = _zz_361_[0];
-  assign _zz_64_ = _zz_362_[0];
-  assign _zz_157_ = _zz_143_[28 : 27];
-  assign _zz_63_ = _zz_157_;
-  assign _zz_158_ = _zz_143_[30 : 29];
-  assign _zz_62_ = _zz_158_;
-  assign _zz_61_ = _zz_363_[0];
-  assign _zz_60_ = _zz_364_[0];
-  assign _zz_59_ = _zz_365_[0];
-  assign _zz_58_ = _zz_366_[0];
-  assign decodeExceptionPort_valid = ((decode_arbitration_isValid && decode_INSTRUCTION_READY) && (! decode_LEGAL_INSTRUCTION));
-  assign decodeExceptionPort_payload_code = (4'b0010);
-  assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION;
-  assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15];
-  assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20];
-  assign decode_RegFilePlugin_rs1Data = _zz_246_;
-  assign decode_RegFilePlugin_rs2Data = _zz_247_;
-  assign _zz_57_ = decode_RegFilePlugin_rs1Data;
-  assign _zz_56_ = decode_RegFilePlugin_rs2Data;
-  always @ (*) begin
-    lastStageRegFileWrite_valid = (_zz_54_ && writeBack_arbitration_isFiring);
-    if(_zz_159_)begin
-      lastStageRegFileWrite_valid = 1'b1;
-    end
-  end
-
-  assign lastStageRegFileWrite_payload_address = _zz_53_[11 : 7];
-  assign lastStageRegFileWrite_payload_data = _zz_87_;
-  always @ (*) begin
-    case(execute_ALU_BITWISE_CTRL)
-      `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin
-        execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2);
-      end
-      `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin
-        execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2);
-      end
-      default : begin
-        execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2);
-      end
-    endcase
-  end
-
-  always @ (*) begin
-    case(execute_ALU_CTRL)
-      `AluCtrlEnum_defaultEncoding_BITWISE : begin
-        _zz_160_ = execute_IntAluPlugin_bitwise;
-      end
-      `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin
-        _zz_160_ = {31'd0, _zz_367_};
-      end
-      default : begin
-        _zz_160_ = execute_SRC_ADD_SUB;
-      end
-    endcase
-  end
-
-  assign _zz_51_ = _zz_160_;
-  assign _zz_49_ = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS));
-  always @ (*) begin
-    case(execute_SRC1_CTRL)
-      `Src1CtrlEnum_defaultEncoding_RS : begin
-        _zz_161_ = execute_RS1;
-      end
-      `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin
-        _zz_161_ = {29'd0, _zz_368_};
-      end
-      `Src1CtrlEnum_defaultEncoding_IMU : begin
-        _zz_161_ = {execute_INSTRUCTION[31 : 12],(12'b000000000000)};
-      end
-      default : begin
-        _zz_161_ = {27'd0, _zz_369_};
-      end
-    endcase
-  end
-
-  assign _zz_48_ = _zz_161_;
-  assign _zz_162_ = _zz_370_[11];
-  always @ (*) begin
-    _zz_163_[19] = _zz_162_;
-    _zz_163_[18] = _zz_162_;
-    _zz_163_[17] = _zz_162_;
-    _zz_163_[16] = _zz_162_;
-    _zz_163_[15] = _zz_162_;
-    _zz_163_[14] = _zz_162_;
-    _zz_163_[13] = _zz_162_;
-    _zz_163_[12] = _zz_162_;
-    _zz_163_[11] = _zz_162_;
-    _zz_163_[10] = _zz_162_;
-    _zz_163_[9] = _zz_162_;
-    _zz_163_[8] = _zz_162_;
-    _zz_163_[7] = _zz_162_;
-    _zz_163_[6] = _zz_162_;
-    _zz_163_[5] = _zz_162_;
-    _zz_163_[4] = _zz_162_;
-    _zz_163_[3] = _zz_162_;
-    _zz_163_[2] = _zz_162_;
-    _zz_163_[1] = _zz_162_;
-    _zz_163_[0] = _zz_162_;
-  end
-
-  assign _zz_164_ = _zz_371_[11];
-  always @ (*) begin
-    _zz_165_[19] = _zz_164_;
-    _zz_165_[18] = _zz_164_;
-    _zz_165_[17] = _zz_164_;
-    _zz_165_[16] = _zz_164_;
-    _zz_165_[15] = _zz_164_;
-    _zz_165_[14] = _zz_164_;
-    _zz_165_[13] = _zz_164_;
-    _zz_165_[12] = _zz_164_;
-    _zz_165_[11] = _zz_164_;
-    _zz_165_[10] = _zz_164_;
-    _zz_165_[9] = _zz_164_;
-    _zz_165_[8] = _zz_164_;
-    _zz_165_[7] = _zz_164_;
-    _zz_165_[6] = _zz_164_;
-    _zz_165_[5] = _zz_164_;
-    _zz_165_[4] = _zz_164_;
-    _zz_165_[3] = _zz_164_;
-    _zz_165_[2] = _zz_164_;
-    _zz_165_[1] = _zz_164_;
-    _zz_165_[0] = _zz_164_;
-  end
-
-  always @ (*) begin
-    case(execute_SRC2_CTRL)
-      `Src2CtrlEnum_defaultEncoding_RS : begin
-        _zz_166_ = execute_RS2;
-      end
-      `Src2CtrlEnum_defaultEncoding_IMI : begin
-        _zz_166_ = {_zz_163_,execute_INSTRUCTION[31 : 20]};
-      end
-      `Src2CtrlEnum_defaultEncoding_IMS : begin
-        _zz_166_ = {_zz_165_,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}};
-      end
-      default : begin
-        _zz_166_ = _zz_44_;
-      end
-    endcase
-  end
-
-  assign _zz_46_ = _zz_166_;
-  always @ (*) begin
-    execute_SrcPlugin_addSub = _zz_372_;
-    if(execute_SRC2_FORCE_ZERO)begin
-      execute_SrcPlugin_addSub = execute_SRC1;
-    end
-  end
-
-  assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31]));
-  assign _zz_43_ = execute_SrcPlugin_addSub;
-  assign _zz_42_ = execute_SrcPlugin_addSub;
-  assign _zz_41_ = execute_SrcPlugin_less;
-  assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0];
-  always @ (*) begin
-    _zz_167_[0] = execute_SRC1[31];
-    _zz_167_[1] = execute_SRC1[30];
-    _zz_167_[2] = execute_SRC1[29];
-    _zz_167_[3] = execute_SRC1[28];
-    _zz_167_[4] = execute_SRC1[27];
-    _zz_167_[5] = execute_SRC1[26];
-    _zz_167_[6] = execute_SRC1[25];
-    _zz_167_[7] = execute_SRC1[24];
-    _zz_167_[8] = execute_SRC1[23];
-    _zz_167_[9] = execute_SRC1[22];
-    _zz_167_[10] = execute_SRC1[21];
-    _zz_167_[11] = execute_SRC1[20];
-    _zz_167_[12] = execute_SRC1[19];
-    _zz_167_[13] = execute_SRC1[18];
-    _zz_167_[14] = execute_SRC1[17];
-    _zz_167_[15] = execute_SRC1[16];
-    _zz_167_[16] = execute_SRC1[15];
-    _zz_167_[17] = execute_SRC1[14];
-    _zz_167_[18] = execute_SRC1[13];
-    _zz_167_[19] = execute_SRC1[12];
-    _zz_167_[20] = execute_SRC1[11];
-    _zz_167_[21] = execute_SRC1[10];
-    _zz_167_[22] = execute_SRC1[9];
-    _zz_167_[23] = execute_SRC1[8];
-    _zz_167_[24] = execute_SRC1[7];
-    _zz_167_[25] = execute_SRC1[6];
-    _zz_167_[26] = execute_SRC1[5];
-    _zz_167_[27] = execute_SRC1[4];
-    _zz_167_[28] = execute_SRC1[3];
-    _zz_167_[29] = execute_SRC1[2];
-    _zz_167_[30] = execute_SRC1[1];
-    _zz_167_[31] = execute_SRC1[0];
-  end
-
-  assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_167_ : execute_SRC1);
-  assign _zz_39_ = _zz_380_;
-  always @ (*) begin
-    _zz_168_[0] = memory_SHIFT_RIGHT[31];
-    _zz_168_[1] = memory_SHIFT_RIGHT[30];
-    _zz_168_[2] = memory_SHIFT_RIGHT[29];
-    _zz_168_[3] = memory_SHIFT_RIGHT[28];
-    _zz_168_[4] = memory_SHIFT_RIGHT[27];
-    _zz_168_[5] = memory_SHIFT_RIGHT[26];
-    _zz_168_[6] = memory_SHIFT_RIGHT[25];
-    _zz_168_[7] = memory_SHIFT_RIGHT[24];
-    _zz_168_[8] = memory_SHIFT_RIGHT[23];
-    _zz_168_[9] = memory_SHIFT_RIGHT[22];
-    _zz_168_[10] = memory_SHIFT_RIGHT[21];
-    _zz_168_[11] = memory_SHIFT_RIGHT[20];
-    _zz_168_[12] = memory_SHIFT_RIGHT[19];
-    _zz_168_[13] = memory_SHIFT_RIGHT[18];
-    _zz_168_[14] = memory_SHIFT_RIGHT[17];
-    _zz_168_[15] = memory_SHIFT_RIGHT[16];
-    _zz_168_[16] = memory_SHIFT_RIGHT[15];
-    _zz_168_[17] = memory_SHIFT_RIGHT[14];
-    _zz_168_[18] = memory_SHIFT_RIGHT[13];
-    _zz_168_[19] = memory_SHIFT_RIGHT[12];
-    _zz_168_[20] = memory_SHIFT_RIGHT[11];
-    _zz_168_[21] = memory_SHIFT_RIGHT[10];
-    _zz_168_[22] = memory_SHIFT_RIGHT[9];
-    _zz_168_[23] = memory_SHIFT_RIGHT[8];
-    _zz_168_[24] = memory_SHIFT_RIGHT[7];
-    _zz_168_[25] = memory_SHIFT_RIGHT[6];
-    _zz_168_[26] = memory_SHIFT_RIGHT[5];
-    _zz_168_[27] = memory_SHIFT_RIGHT[4];
-    _zz_168_[28] = memory_SHIFT_RIGHT[3];
-    _zz_168_[29] = memory_SHIFT_RIGHT[2];
-    _zz_168_[30] = memory_SHIFT_RIGHT[1];
-    _zz_168_[31] = memory_SHIFT_RIGHT[0];
-  end
-
-  always @ (*) begin
-    _zz_169_ = 1'b0;
-    if(_zz_296_)begin
-      if(_zz_297_)begin
-        if(_zz_175_)begin
-          _zz_169_ = 1'b1;
-        end
-      end
-    end
-    if(_zz_298_)begin
-      if(_zz_299_)begin
-        if(_zz_177_)begin
-          _zz_169_ = 1'b1;
-        end
-      end
-    end
-    if(_zz_300_)begin
-      if(_zz_301_)begin
-        if(_zz_179_)begin
-          _zz_169_ = 1'b1;
-        end
-      end
-    end
-    if((! decode_RS1_USE))begin
-      _zz_169_ = 1'b0;
-    end
-  end
-
-  always @ (*) begin
-    _zz_170_ = 1'b0;
-    if(_zz_296_)begin
-      if(_zz_297_)begin
-        if(_zz_176_)begin
-          _zz_170_ = 1'b1;
-        end
-      end
-    end
-    if(_zz_298_)begin
-      if(_zz_299_)begin
-        if(_zz_178_)begin
-          _zz_170_ = 1'b1;
-        end
-      end
-    end
-    if(_zz_300_)begin
-      if(_zz_301_)begin
-        if(_zz_180_)begin
-          _zz_170_ = 1'b1;
-        end
-      end
-    end
-    if((! decode_RS2_USE))begin
-      _zz_170_ = 1'b0;
-    end
-  end
-
-  assign _zz_171_ = (_zz_54_ && writeBack_arbitration_isFiring);
-  assign _zz_175_ = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]);
-  assign _zz_176_ = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]);
-  assign _zz_177_ = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]);
-  assign _zz_178_ = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]);
-  assign _zz_179_ = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]);
-  assign _zz_180_ = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]);
-  assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2);
-  assign _zz_181_ = execute_INSTRUCTION[14 : 12];
-  always @ (*) begin
-    if((_zz_181_ == (3'b000))) begin
-        _zz_182_ = execute_BranchPlugin_eq;
-    end else if((_zz_181_ == (3'b001))) begin
-        _zz_182_ = (! execute_BranchPlugin_eq);
-    end else if((((_zz_181_ & (3'b101)) == (3'b101)))) begin
-        _zz_182_ = (! execute_SRC_LESS);
-    end else begin
-        _zz_182_ = execute_SRC_LESS;
-    end
-  end
-
-  always @ (*) begin
-    case(execute_BRANCH_CTRL)
-      `BranchCtrlEnum_defaultEncoding_INC : begin
-        _zz_183_ = 1'b0;
-      end
-      `BranchCtrlEnum_defaultEncoding_JAL : begin
-        _zz_183_ = 1'b1;
-      end
-      `BranchCtrlEnum_defaultEncoding_JALR : begin
-        _zz_183_ = 1'b1;
-      end
-      default : begin
-        _zz_183_ = _zz_182_;
-      end
-    endcase
-  end
-
-  assign _zz_35_ = _zz_183_;
-  assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JALR) ? execute_RS1 : execute_PC);
-  assign _zz_184_ = _zz_382_[19];
-  always @ (*) begin
-    _zz_185_[10] = _zz_184_;
-    _zz_185_[9] = _zz_184_;
-    _zz_185_[8] = _zz_184_;
-    _zz_185_[7] = _zz_184_;
-    _zz_185_[6] = _zz_184_;
-    _zz_185_[5] = _zz_184_;
-    _zz_185_[4] = _zz_184_;
-    _zz_185_[3] = _zz_184_;
-    _zz_185_[2] = _zz_184_;
-    _zz_185_[1] = _zz_184_;
-    _zz_185_[0] = _zz_184_;
-  end
-
-  assign _zz_186_ = _zz_383_[11];
-  always @ (*) begin
-    _zz_187_[19] = _zz_186_;
-    _zz_187_[18] = _zz_186_;
-    _zz_187_[17] = _zz_186_;
-    _zz_187_[16] = _zz_186_;
-    _zz_187_[15] = _zz_186_;
-    _zz_187_[14] = _zz_186_;
-    _zz_187_[13] = _zz_186_;
-    _zz_187_[12] = _zz_186_;
-    _zz_187_[11] = _zz_186_;
-    _zz_187_[10] = _zz_186_;
-    _zz_187_[9] = _zz_186_;
-    _zz_187_[8] = _zz_186_;
-    _zz_187_[7] = _zz_186_;
-    _zz_187_[6] = _zz_186_;
-    _zz_187_[5] = _zz_186_;
-    _zz_187_[4] = _zz_186_;
-    _zz_187_[3] = _zz_186_;
-    _zz_187_[2] = _zz_186_;
-    _zz_187_[1] = _zz_186_;
-    _zz_187_[0] = _zz_186_;
-  end
-
-  assign _zz_188_ = _zz_384_[11];
-  always @ (*) begin
-    _zz_189_[18] = _zz_188_;
-    _zz_189_[17] = _zz_188_;
-    _zz_189_[16] = _zz_188_;
-    _zz_189_[15] = _zz_188_;
-    _zz_189_[14] = _zz_188_;
-    _zz_189_[13] = _zz_188_;
-    _zz_189_[12] = _zz_188_;
-    _zz_189_[11] = _zz_188_;
-    _zz_189_[10] = _zz_188_;
-    _zz_189_[9] = _zz_188_;
-    _zz_189_[8] = _zz_188_;
-    _zz_189_[7] = _zz_188_;
-    _zz_189_[6] = _zz_188_;
-    _zz_189_[5] = _zz_188_;
-    _zz_189_[4] = _zz_188_;
-    _zz_189_[3] = _zz_188_;
-    _zz_189_[2] = _zz_188_;
-    _zz_189_[1] = _zz_188_;
-    _zz_189_[0] = _zz_188_;
-  end
-
-  always @ (*) begin
-    case(execute_BRANCH_CTRL)
-      `BranchCtrlEnum_defaultEncoding_JAL : begin
-        _zz_190_ = {{_zz_185_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0};
-      end
-      `BranchCtrlEnum_defaultEncoding_JALR : begin
-        _zz_190_ = {_zz_187_,execute_INSTRUCTION[31 : 20]};
-      end
-      default : begin
-        _zz_190_ = {{_zz_189_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0};
-      end
-    endcase
-  end
-
-  assign execute_BranchPlugin_branch_src2 = _zz_190_;
-  assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2);
-  assign _zz_33_ = {execute_BranchPlugin_branchAdder[31 : 1],(1'b0)};
-  assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0));
-  assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC;
-  assign BranchPlugin_branchExceptionPort_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && BranchPlugin_jumpInterface_payload[1]);
-  assign BranchPlugin_branchExceptionPort_payload_code = (4'b0000);
-  assign BranchPlugin_branchExceptionPort_payload_badAddr = BranchPlugin_jumpInterface_payload;
-  always @ (*) begin
-    CsrPlugin_privilege = _zz_191_;
-    if(CsrPlugin_forceMachineWire)begin
-      CsrPlugin_privilege = (2'b11);
-    end
-  end
-
-  assign CsrPlugin_misa_base = (2'b01);
-  assign CsrPlugin_misa_extensions = (26'b00000000000000000000000000);
-  assign CsrPlugin_sip_SEIP_OR = (CsrPlugin_sip_SEIP_SOFT || CsrPlugin_sip_SEIP_INPUT);
-  assign _zz_192_ = (CsrPlugin_sip_STIP && CsrPlugin_sie_STIE);
-  assign _zz_193_ = (CsrPlugin_sip_SSIP && CsrPlugin_sie_SSIE);
-  assign _zz_194_ = (CsrPlugin_sip_SEIP_OR && CsrPlugin_sie_SEIE);
-  assign _zz_195_ = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE);
-  assign _zz_196_ = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE);
-  assign _zz_197_ = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE);
-  always @ (*) begin
-    CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b11);
-    case(CsrPlugin_exceptionPortCtrl_exceptionContext_code)
-      4'b1000 : begin
-        if(((1'b1 && CsrPlugin_medeleg_EU) && (! 1'b0)))begin
-          CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b01);
-        end
-      end
-      4'b0010 : begin
-        if(((1'b1 && CsrPlugin_medeleg_II) && (! 1'b0)))begin
-          CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b01);
-        end
-      end
-      4'b0101 : begin
-        if(((1'b1 && CsrPlugin_medeleg_LAF) && (! 1'b0)))begin
-          CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b01);
-        end
-      end
-      4'b1101 : begin
-        if(((1'b1 && CsrPlugin_medeleg_LPF) && (! 1'b0)))begin
-          CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b01);
-        end
-      end
-      4'b0100 : begin
-        if(((1'b1 && CsrPlugin_medeleg_LAM) && (! 1'b0)))begin
-          CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b01);
-        end
-      end
-      4'b0111 : begin
-        if(((1'b1 && CsrPlugin_medeleg_SAF) && (! 1'b0)))begin
-          CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b01);
-        end
-      end
-      4'b0001 : begin
-        if(((1'b1 && CsrPlugin_medeleg_IAF) && (! 1'b0)))begin
-          CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b01);
-        end
-      end
-      4'b1001 : begin
-        if(((1'b1 && CsrPlugin_medeleg_ES) && (! 1'b0)))begin
-          CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b01);
-        end
-      end
-      4'b1100 : begin
-        if(((1'b1 && CsrPlugin_medeleg_IPF) && (! 1'b0)))begin
-          CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b01);
-        end
-      end
-      4'b1111 : begin
-        if(((1'b1 && CsrPlugin_medeleg_SPF) && (! 1'b0)))begin
-          CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b01);
-        end
-      end
-      4'b0110 : begin
-        if(((1'b1 && CsrPlugin_medeleg_SAM) && (! 1'b0)))begin
-          CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b01);
-        end
-      end
-      4'b0000 : begin
-        if(((1'b1 && CsrPlugin_medeleg_IAM) && (! 1'b0)))begin
-          CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b01);
-        end
-      end
-      default : begin
-      end
-    endcase
-  end
-
-  assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege);
-  assign _zz_198_ = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid};
-  assign _zz_199_ = _zz_385_[0];
-  always @ (*) begin
-    CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
-    if(_zz_282_)begin
-      CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1;
-    end
-    if(decode_arbitration_isFlushed)begin
-      CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0;
-    end
-  end
-
-  always @ (*) begin
-    CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
-    if(CsrPlugin_selfException_valid)begin
-      CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1;
-    end
-    if(execute_arbitration_isFlushed)begin
-      CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0;
-    end
-  end
-
-  always @ (*) begin
-    CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory;
-    if(BranchPlugin_branchExceptionPort_valid)begin
-      CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1;
-    end
-    if(memory_arbitration_isFlushed)begin
-      CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0;
-    end
-  end
-
-  always @ (*) begin
-    CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack;
-    if(DBusCachedPlugin_exceptionBus_valid)begin
-      CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1;
-    end
-    if(writeBack_arbitration_isFlushed)begin
-      CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0;
-    end
-  end
-
-  assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
-  assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
-  assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory;
-  assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack;
-  assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException);
-  always @ (*) begin
-    CsrPlugin_pipelineLiberator_done = ((! ({writeBack_arbitration_isValid,{memory_arbitration_isValid,execute_arbitration_isValid}} != (3'b000))) && IBusCachedPlugin_pcValids_3);
-    if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != (3'b000)))begin
-      CsrPlugin_pipelineLiberator_done = 1'b0;
-    end
-    if(CsrPlugin_hadException)begin
-      CsrPlugin_pipelineLiberator_done = 1'b0;
-    end
-  end
-
-  assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts);
-  always @ (*) begin
-    CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege;
-    if(CsrPlugin_hadException)begin
-      CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege;
-    end
-  end
-
-  always @ (*) begin
-    CsrPlugin_trapCause = CsrPlugin_interrupt_code;
-    if(CsrPlugin_hadException)begin
-      CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code;
-    end
-  end
-
-  always @ (*) begin
-    CsrPlugin_xtvec_mode = (2'bxx);
-    case(CsrPlugin_targetPrivilege)
-      2'b01 : begin
-        CsrPlugin_xtvec_mode = CsrPlugin_stvec_mode;
-      end
-      2'b11 : begin
-        CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode;
-      end
-      default : begin
-      end
-    endcase
-  end
-
-  always @ (*) begin
-    CsrPlugin_xtvec_base = (30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx);
-    case(CsrPlugin_targetPrivilege)
-      2'b01 : begin
-        CsrPlugin_xtvec_base = CsrPlugin_stvec_base;
-      end
-      2'b11 : begin
-        CsrPlugin_xtvec_base = CsrPlugin_mtvec_base;
-      end
-      default : begin
-      end
-    endcase
-  end
-
-  assign contextSwitching = CsrPlugin_jumpInterface_valid;
-  assign _zz_31_ = (! (((decode_INSTRUCTION[14 : 13] == (2'b01)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))) || ((decode_INSTRUCTION[14 : 13] == (2'b11)) && (decode_INSTRUCTION[19 : 15] == (5'b00000)))));
-  assign _zz_30_ = (decode_INSTRUCTION[13 : 7] != (7'b0100000));
-  always @ (*) begin
-    execute_CsrPlugin_inWfi = 1'b0;
-    if(_zz_283_)begin
-      execute_CsrPlugin_inWfi = 1'b1;
-    end
-  end
-
-  assign execute_CsrPlugin_blockedBySideEffects = ({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00));
-  always @ (*) begin
-    execute_CsrPlugin_illegalAccess = 1'b1;
-    case(execute_CsrPlugin_csrAddress)
-      12'b101111000000 : begin
-        execute_CsrPlugin_illegalAccess = 1'b0;
-      end
-      12'b001100000000 : begin
-        execute_CsrPlugin_illegalAccess = 1'b0;
-      end
-      12'b001100000011 : begin
-        if(execute_CSR_WRITE_OPCODE)begin
-          execute_CsrPlugin_illegalAccess = 1'b0;
-        end
-      end
-      12'b111100010001 : begin
-        if(execute_CSR_READ_OPCODE)begin
-          execute_CsrPlugin_illegalAccess = 1'b0;
-        end
-      end
-      12'b000101000010 : begin
-        execute_CsrPlugin_illegalAccess = 1'b0;
-      end
-      12'b111100010100 : begin
-        if(execute_CSR_READ_OPCODE)begin
-          execute_CsrPlugin_illegalAccess = 1'b0;
-        end
-      end
-      12'b100111000000 : begin
-        execute_CsrPlugin_illegalAccess = 1'b0;
-      end
-      12'b000100000000 : begin
-        execute_CsrPlugin_illegalAccess = 1'b0;
-      end
-      12'b001100000010 : begin
-        if(execute_CSR_WRITE_OPCODE)begin
-          execute_CsrPlugin_illegalAccess = 1'b0;
-        end
-      end
-      12'b001101000001 : begin
-        execute_CsrPlugin_illegalAccess = 1'b0;
-      end
-      12'b001101000100 : begin
-        execute_CsrPlugin_illegalAccess = 1'b0;
-      end
-      12'b001100000101 : begin
-        if(execute_CSR_WRITE_OPCODE)begin
-          execute_CsrPlugin_illegalAccess = 1'b0;
-        end
-      end
-      12'b000110000000 : begin
-        execute_CsrPlugin_illegalAccess = 1'b0;
-      end
-      12'b110011000000 : begin
-        if(execute_CSR_READ_OPCODE)begin
-          execute_CsrPlugin_illegalAccess = 1'b0;
-        end
-      end
-      12'b000101000001 : begin
-        execute_CsrPlugin_illegalAccess = 1'b0;
-      end
-      12'b111100010011 : begin
-        if(execute_CSR_READ_OPCODE)begin
-          execute_CsrPlugin_illegalAccess = 1'b0;
-        end
-      end
-      12'b000101000100 : begin
-        execute_CsrPlugin_illegalAccess = 1'b0;
-      end
-      12'b001101000011 : begin
-        if(execute_CSR_READ_OPCODE)begin
-          execute_CsrPlugin_illegalAccess = 1'b0;
-        end
-      end
-      12'b000100000101 : begin
-        execute_CsrPlugin_illegalAccess = 1'b0;
-      end
-      12'b111111000000 : begin
-        if(execute_CSR_READ_OPCODE)begin
-          execute_CsrPlugin_illegalAccess = 1'b0;
-        end
-      end
-      12'b001101000000 : begin
-        execute_CsrPlugin_illegalAccess = 1'b0;
-      end
-      12'b001100000100 : begin
-        execute_CsrPlugin_illegalAccess = 1'b0;
-      end
-      12'b111100010010 : begin
-        if(execute_CSR_READ_OPCODE)begin
-          execute_CsrPlugin_illegalAccess = 1'b0;
-        end
-      end
-      12'b000101000011 : begin
-        execute_CsrPlugin_illegalAccess = 1'b0;
-      end
-      12'b110111000000 : begin
-        if(execute_CSR_READ_OPCODE)begin
-          execute_CsrPlugin_illegalAccess = 1'b0;
-        end
-      end
-      12'b000101000000 : begin
-        execute_CsrPlugin_illegalAccess = 1'b0;
-      end
-      12'b001101000010 : begin
-        if(execute_CSR_READ_OPCODE)begin
-          execute_CsrPlugin_illegalAccess = 1'b0;
-        end
-      end
-      12'b000100000100 : begin
-        execute_CsrPlugin_illegalAccess = 1'b0;
-      end
-      default : begin
-      end
-    endcase
-    if((CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]))begin
-      execute_CsrPlugin_illegalAccess = 1'b1;
-    end
-    if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin
-      execute_CsrPlugin_illegalAccess = 1'b0;
-    end
-  end
-
-  always @ (*) begin
-    execute_CsrPlugin_illegalInstruction = 1'b0;
-    if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin
-      if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin
-        execute_CsrPlugin_illegalInstruction = 1'b1;
-      end
-    end
-  end
-
-  always @ (*) begin
-    CsrPlugin_selfException_valid = 1'b0;
-    if(_zz_302_)begin
-      CsrPlugin_selfException_valid = 1'b1;
-    end
-    if(_zz_303_)begin
-      CsrPlugin_selfException_valid = 1'b1;
-    end
-  end
-
-  always @ (*) begin
-    CsrPlugin_selfException_payload_code = (4'bxxxx);
-    if(_zz_302_)begin
-      CsrPlugin_selfException_payload_code = (4'b0010);
-    end
-    if(_zz_303_)begin
-      case(CsrPlugin_privilege)
-        2'b00 : begin
-          CsrPlugin_selfException_payload_code = (4'b1000);
-        end
-        2'b01 : begin
-          CsrPlugin_selfException_payload_code = (4'b1001);
-        end
-        default : begin
-          CsrPlugin_selfException_payload_code = (4'b1011);
-        end
-      endcase
-    end
-  end
-
-  assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION;
-  always @ (*) begin
-    execute_CsrPlugin_readData = (32'b00000000000000000000000000000000);
-    case(execute_CsrPlugin_csrAddress)
-      12'b101111000000 : begin
-        execute_CsrPlugin_readData[31 : 0] = _zz_207_;
-      end
-      12'b001100000000 : begin
-        execute_CsrPlugin_readData[19 : 19] = MmuPlugin_status_mxr;
-        execute_CsrPlugin_readData[18 : 18] = MmuPlugin_status_sum;
-        execute_CsrPlugin_readData[17 : 17] = MmuPlugin_status_mprv;
-        execute_CsrPlugin_readData[12 : 11] = CsrPlugin_mstatus_MPP;
-        execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mstatus_MPIE;
-        execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mstatus_MIE;
-        execute_CsrPlugin_readData[8 : 8] = CsrPlugin_sstatus_SPP;
-        execute_CsrPlugin_readData[5 : 5] = CsrPlugin_sstatus_SPIE;
-        execute_CsrPlugin_readData[1 : 1] = CsrPlugin_sstatus_SIE;
-      end
-      12'b001100000011 : begin
-      end
-      12'b111100010001 : begin
-        execute_CsrPlugin_readData[0 : 0] = (1'b1);
-      end
-      12'b000101000010 : begin
-        execute_CsrPlugin_readData[31 : 31] = CsrPlugin_scause_interrupt;
-        execute_CsrPlugin_readData[3 : 0] = CsrPlugin_scause_exceptionCode;
-      end
-      12'b111100010100 : begin
-      end
-      12'b100111000000 : begin
-        execute_CsrPlugin_readData[31 : 0] = _zz_209_;
-      end
-      12'b000100000000 : begin
-        execute_CsrPlugin_readData[19 : 19] = MmuPlugin_status_mxr;
-        execute_CsrPlugin_readData[18 : 18] = MmuPlugin_status_sum;
-        execute_CsrPlugin_readData[17 : 17] = MmuPlugin_status_mprv;
-        execute_CsrPlugin_readData[8 : 8] = CsrPlugin_sstatus_SPP;
-        execute_CsrPlugin_readData[5 : 5] = CsrPlugin_sstatus_SPIE;
-        execute_CsrPlugin_readData[1 : 1] = CsrPlugin_sstatus_SIE;
-      end
-      12'b001100000010 : begin
-      end
-      12'b001101000001 : begin
-        execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mepc;
-      end
-      12'b001101000100 : begin
-        execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mip_MEIP;
-        execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mip_MTIP;
-        execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mip_MSIP;
-        execute_CsrPlugin_readData[5 : 5] = CsrPlugin_sip_STIP;
-        execute_CsrPlugin_readData[1 : 1] = CsrPlugin_sip_SSIP;
-        execute_CsrPlugin_readData[9 : 9] = CsrPlugin_sip_SEIP_OR;
-      end
-      12'b001100000101 : begin
-      end
-      12'b000110000000 : begin
-        execute_CsrPlugin_readData[31 : 31] = MmuPlugin_satp_mode;
-        execute_CsrPlugin_readData[19 : 0] = MmuPlugin_satp_ppn;
-      end
-      12'b110011000000 : begin
-        execute_CsrPlugin_readData[12 : 0] = (13'b1000000000000);
-        execute_CsrPlugin_readData[25 : 20] = (6'b100000);
-      end
-      12'b000101000001 : begin
-        execute_CsrPlugin_readData[31 : 0] = CsrPlugin_sepc;
-      end
-      12'b111100010011 : begin
-        execute_CsrPlugin_readData[1 : 0] = (2'b11);
-      end
-      12'b000101000100 : begin
-        execute_CsrPlugin_readData[5 : 5] = CsrPlugin_sip_STIP;
-        execute_CsrPlugin_readData[1 : 1] = CsrPlugin_sip_SSIP;
-        execute_CsrPlugin_readData[9 : 9] = CsrPlugin_sip_SEIP_OR;
-      end
-      12'b001101000011 : begin
-        execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mtval;
-      end
-      12'b000100000101 : begin
-        execute_CsrPlugin_readData[31 : 2] = CsrPlugin_stvec_base;
-        execute_CsrPlugin_readData[1 : 0] = CsrPlugin_stvec_mode;
-      end
-      12'b111111000000 : begin
-        execute_CsrPlugin_readData[31 : 0] = _zz_208_;
-      end
-      12'b001101000000 : begin
-        execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mscratch;
-      end
-      12'b001100000100 : begin
-        execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mie_MEIE;
-        execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mie_MTIE;
-        execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mie_MSIE;
-        execute_CsrPlugin_readData[9 : 9] = CsrPlugin_sie_SEIE;
-        execute_CsrPlugin_readData[5 : 5] = CsrPlugin_sie_STIE;
-        execute_CsrPlugin_readData[1 : 1] = CsrPlugin_sie_SSIE;
-      end
-      12'b111100010010 : begin
-        execute_CsrPlugin_readData[1 : 0] = (2'b10);
-      end
-      12'b000101000011 : begin
-        execute_CsrPlugin_readData[31 : 0] = CsrPlugin_stval;
-      end
-      12'b110111000000 : begin
-        execute_CsrPlugin_readData[31 : 0] = _zz_210_;
-      end
-      12'b000101000000 : begin
-        execute_CsrPlugin_readData[31 : 0] = CsrPlugin_sscratch;
-      end
-      12'b001101000010 : begin
-        execute_CsrPlugin_readData[31 : 31] = CsrPlugin_mcause_interrupt;
-        execute_CsrPlugin_readData[3 : 0] = CsrPlugin_mcause_exceptionCode;
-      end
-      12'b000100000100 : begin
-        execute_CsrPlugin_readData[9 : 9] = CsrPlugin_sie_SEIE;
-        execute_CsrPlugin_readData[5 : 5] = CsrPlugin_sie_STIE;
-        execute_CsrPlugin_readData[1 : 1] = CsrPlugin_sie_SSIE;
-      end
-      default : begin
-      end
-    endcase
-  end
-
-  assign execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE);
-  assign execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE);
-  assign execute_CsrPlugin_writeEnable = ((execute_CsrPlugin_writeInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers));
-  assign execute_CsrPlugin_readEnable = ((execute_CsrPlugin_readInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers));
-  always @ (*) begin
-    execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData;
-    case(execute_CsrPlugin_csrAddress)
-      12'b001101000100 : begin
-        execute_CsrPlugin_readToWriteData[9 : 9] = CsrPlugin_sip_SEIP_SOFT;
-      end
-      12'b000101000100 : begin
-        execute_CsrPlugin_readToWriteData[9 : 9] = CsrPlugin_sip_SEIP_SOFT;
-      end
-      default : begin
-      end
-    endcase
-  end
-
-  always @ (*) begin
-    case(_zz_329_)
-      1'b0 : begin
-        execute_CsrPlugin_writeData = execute_SRC1;
-      end
-      default : begin
-        execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1));
-      end
-    endcase
-  end
-
-  assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20];
-  always @ (*) begin
-    memory_MulDivIterativePlugin_mul_counter_willIncrement = 1'b0;
-    if(_zz_276_)begin
-      if(_zz_284_)begin
-        memory_MulDivIterativePlugin_mul_counter_willIncrement = 1'b1;
-      end
-    end
-  end
-
-  always @ (*) begin
-    memory_MulDivIterativePlugin_mul_counter_willClear = 1'b0;
-    if((! memory_arbitration_isStuck))begin
-      memory_MulDivIterativePlugin_mul_counter_willClear = 1'b1;
-    end
-  end
-
-  assign memory_MulDivIterativePlugin_mul_willOverflowIfInc = (memory_MulDivIterativePlugin_mul_counter_value == (6'b100000));
-  assign memory_MulDivIterativePlugin_mul_counter_willOverflow = (memory_MulDivIterativePlugin_mul_willOverflowIfInc && memory_MulDivIterativePlugin_mul_counter_willIncrement);
-  always @ (*) begin
-    if(memory_MulDivIterativePlugin_mul_counter_willOverflow)begin
-      memory_MulDivIterativePlugin_mul_counter_valueNext = (6'b000000);
-    end else begin
-      memory_MulDivIterativePlugin_mul_counter_valueNext = (memory_MulDivIterativePlugin_mul_counter_value + _zz_388_);
-    end
-    if(memory_MulDivIterativePlugin_mul_counter_willClear)begin
-      memory_MulDivIterativePlugin_mul_counter_valueNext = (6'b000000);
-    end
-  end
-
-  always @ (*) begin
-    memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b0;
-    if(_zz_277_)begin
-      if(_zz_285_)begin
-        memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b1;
-      end
-    end
-  end
-
-  always @ (*) begin
-    memory_MulDivIterativePlugin_div_counter_willClear = 1'b0;
-    if(_zz_304_)begin
-      memory_MulDivIterativePlugin_div_counter_willClear = 1'b1;
-    end
-  end
-
-  assign memory_MulDivIterativePlugin_div_counter_willOverflowIfInc = (memory_MulDivIterativePlugin_div_counter_value == (6'b100001));
-  assign memory_MulDivIterativePlugin_div_counter_willOverflow = (memory_MulDivIterativePlugin_div_counter_willOverflowIfInc && memory_MulDivIterativePlugin_div_counter_willIncrement);
-  always @ (*) begin
-    if(memory_MulDivIterativePlugin_div_counter_willOverflow)begin
-      memory_MulDivIterativePlugin_div_counter_valueNext = (6'b000000);
-    end else begin
-      memory_MulDivIterativePlugin_div_counter_valueNext = (memory_MulDivIterativePlugin_div_counter_value + _zz_396_);
-    end
-    if(memory_MulDivIterativePlugin_div_counter_willClear)begin
-      memory_MulDivIterativePlugin_div_counter_valueNext = (6'b000000);
-    end
-  end
-
-  assign _zz_200_ = memory_MulDivIterativePlugin_rs1[31 : 0];
-  assign _zz_201_ = {memory_MulDivIterativePlugin_accumulator[31 : 0],_zz_200_[31]};
-  assign _zz_202_ = (_zz_201_ - _zz_397_);
-  assign _zz_203_ = (memory_INSTRUCTION[13] ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_rs1[31 : 0]);
-  assign _zz_204_ = (execute_RS2[31] && execute_IS_RS2_SIGNED);
-  assign _zz_205_ = ((execute_IS_MUL && _zz_204_) || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED));
-  always @ (*) begin
-    _zz_206_[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]);
-    _zz_206_[31 : 0] = execute_RS1;
-  end
-
-  assign _zz_208_ = (_zz_207_ & externalInterruptArray_regNext);
-  assign externalInterrupt = (_zz_208_ != (32'b00000000000000000000000000000000));
-  assign _zz_210_ = (_zz_209_ & externalInterruptArray_regNext);
-  assign externalInterruptS = (_zz_210_ != (32'b00000000000000000000000000000000));
-  assign _zz_27_ = decode_SHIFT_CTRL;
-  assign _zz_24_ = execute_SHIFT_CTRL;
-  assign _zz_25_ = _zz_82_;
-  assign _zz_40_ = decode_to_execute_SHIFT_CTRL;
-  assign _zz_38_ = execute_to_memory_SHIFT_CTRL;
-  assign _zz_22_ = decode_ALU_CTRL;
-  assign _zz_20_ = _zz_81_;
-  assign _zz_50_ = decode_to_execute_ALU_CTRL;
-  assign _zz_19_ = decode_ENV_CTRL;
-  assign _zz_16_ = execute_ENV_CTRL;
-  assign _zz_14_ = memory_ENV_CTRL;
-  assign _zz_17_ = _zz_78_;
-  assign _zz_29_ = decode_to_execute_ENV_CTRL;
-  assign _zz_28_ = execute_to_memory_ENV_CTRL;
-  assign _zz_32_ = memory_to_writeBack_ENV_CTRL;
-  assign _zz_12_ = decode_SRC2_CTRL;
-  assign _zz_10_ = _zz_63_;
-  assign _zz_45_ = decode_to_execute_SRC2_CTRL;
-  assign _zz_9_ = decode_SRC1_CTRL;
-  assign _zz_7_ = _zz_62_;
-  assign _zz_47_ = decode_to_execute_SRC1_CTRL;
-  assign _zz_6_ = decode_ALU_BITWISE_CTRL;
-  assign _zz_4_ = _zz_70_;
-  assign _zz_52_ = decode_to_execute_ALU_BITWISE_CTRL;
-  assign _zz_3_ = decode_BRANCH_CTRL;
-  assign _zz_1_ = _zz_66_;
-  assign _zz_34_ = decode_to_execute_BRANCH_CTRL;
-  assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != (3'b000)) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != (4'b0000)));
-  assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != (2'b00)) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != (3'b000)));
-  assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != (1'b0)) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != (2'b00)));
-  assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != (1'b0)));
-  assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck));
-  assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers);
-  assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt));
-  assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt));
-  assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck));
-  assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers);
-  assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt));
-  assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt));
-  assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck));
-  assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers);
-  assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt));
-  assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt));
-  assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0);
-  assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers);
-  assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt));
-  assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt));
-  assign iBusWishbone_ADR = {_zz_455_,_zz_211_};
-  assign iBusWishbone_CTI = ((_zz_211_ == (3'b111)) ? (3'b111) : (3'b010));
-  assign iBusWishbone_BTE = (2'b00);
-  assign iBusWishbone_SEL = (4'b1111);
-  assign iBusWishbone_WE = 1'b0;
-  assign iBusWishbone_DAT_MOSI = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx);
-  always @ (*) begin
-    iBusWishbone_CYC = 1'b0;
-    if(_zz_305_)begin
-      iBusWishbone_CYC = 1'b1;
-    end
-  end
-
-  always @ (*) begin
-    iBusWishbone_STB = 1'b0;
-    if(_zz_305_)begin
-      iBusWishbone_STB = 1'b1;
-    end
-  end
-
-  assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK);
-  assign iBus_rsp_valid = _zz_212_;
-  assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext;
-  assign iBus_rsp_payload_error = 1'b0;
-  assign _zz_218_ = (dBus_cmd_payload_length != (3'b000));
-  assign _zz_214_ = dBus_cmd_valid;
-  assign _zz_216_ = dBus_cmd_payload_wr;
-  assign _zz_217_ = (_zz_213_ == dBus_cmd_payload_length);
-  assign dBus_cmd_ready = (_zz_215_ && (_zz_216_ || _zz_217_));
-  assign dBusWishbone_ADR = ((_zz_218_ ? {{dBus_cmd_payload_address[31 : 5],_zz_213_},(2'b00)} : {dBus_cmd_payload_address[31 : 2],(2'b00)}) >>> 2);
-  assign dBusWishbone_CTI = (_zz_218_ ? (_zz_217_ ? (3'b111) : (3'b010)) : (3'b000));
-  assign dBusWishbone_BTE = (2'b00);
-  assign dBusWishbone_SEL = (_zz_216_ ? dBus_cmd_payload_mask : (4'b1111));
-  assign dBusWishbone_WE = _zz_216_;
-  assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data;
-  assign _zz_215_ = (_zz_214_ && dBusWishbone_ACK);
-  assign dBusWishbone_CYC = _zz_214_;
-  assign dBusWishbone_STB = _zz_214_;
-  assign dBus_rsp_valid = _zz_219_;
-  assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext;
-  assign dBus_rsp_payload_error = 1'b0;
-  always @ (posedge clk) begin
-    if(reset) begin
-      IBusCachedPlugin_fetchPc_pcReg <= externalResetVector;
-      IBusCachedPlugin_fetchPc_booted <= 1'b0;
-      IBusCachedPlugin_fetchPc_inc <= 1'b0;
-      _zz_109_ <= 1'b0;
-      _zz_111_ <= 1'b0;
-      _zz_114_ <= 1'b0;
-      IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0;
-      IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0;
-      IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0;
-      IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0;
-      IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0;
-      IBusCachedPlugin_injector_nextPcCalc_valids_5 <= 1'b0;
-      IBusCachedPlugin_injector_decodeRemoved <= 1'b0;
-      IBusCachedPlugin_rspCounter <= _zz_116_;
-      IBusCachedPlugin_rspCounter <= (32'b00000000000000000000000000000000);
-      _zz_117_ <= 1'b0;
-      _zz_124_ <= 1'b0;
-      DBusCachedPlugin_rspCounter <= _zz_131_;
-      DBusCachedPlugin_rspCounter <= (32'b00000000000000000000000000000000);
-      MmuPlugin_status_sum <= 1'b0;
-      MmuPlugin_status_mxr <= 1'b0;
-      MmuPlugin_status_mprv <= 1'b0;
-      MmuPlugin_satp_mode <= 1'b0;
-      MmuPlugin_ports_0_cache_0_valid <= 1'b0;
-      MmuPlugin_ports_0_cache_1_valid <= 1'b0;
-      MmuPlugin_ports_0_cache_2_valid <= 1'b0;
-      MmuPlugin_ports_0_cache_3_valid <= 1'b0;
-      MmuPlugin_ports_0_entryToReplace_value <= (2'b00);
-      MmuPlugin_ports_1_cache_0_valid <= 1'b0;
-      MmuPlugin_ports_1_cache_1_valid <= 1'b0;
-      MmuPlugin_ports_1_cache_2_valid <= 1'b0;
-      MmuPlugin_ports_1_cache_3_valid <= 1'b0;
-      MmuPlugin_ports_1_entryToReplace_value <= (2'b00);
-      MmuPlugin_shared_state_1_ <= `MmuPlugin_shared_State_defaultEncoding_IDLE;
-      _zz_159_ <= 1'b1;
-      _zz_172_ <= 1'b0;
-      _zz_191_ <= (2'b11);
-      CsrPlugin_mstatus_MIE <= 1'b0;
-      CsrPlugin_mstatus_MPIE <= 1'b0;
-      CsrPlugin_mstatus_MPP <= (2'b11);
-      CsrPlugin_mie_MEIE <= 1'b0;
-      CsrPlugin_mie_MTIE <= 1'b0;
-      CsrPlugin_mie_MSIE <= 1'b0;
-      CsrPlugin_medeleg_IAM <= 1'b0;
-      CsrPlugin_medeleg_IAF <= 1'b0;
-      CsrPlugin_medeleg_II <= 1'b0;
-      CsrPlugin_medeleg_LAM <= 1'b0;
-      CsrPlugin_medeleg_LAF <= 1'b0;
-      CsrPlugin_medeleg_SAM <= 1'b0;
-      CsrPlugin_medeleg_SAF <= 1'b0;
-      CsrPlugin_medeleg_EU <= 1'b0;
-      CsrPlugin_medeleg_ES <= 1'b0;
-      CsrPlugin_medeleg_IPF <= 1'b0;
-      CsrPlugin_medeleg_LPF <= 1'b0;
-      CsrPlugin_medeleg_SPF <= 1'b0;
-      CsrPlugin_mideleg_ST <= 1'b0;
-      CsrPlugin_mideleg_SE <= 1'b0;
-      CsrPlugin_mideleg_SS <= 1'b0;
-      CsrPlugin_sstatus_SIE <= 1'b0;
-      CsrPlugin_sstatus_SPIE <= 1'b0;
-      CsrPlugin_sstatus_SPP <= (1'b1);
-      CsrPlugin_sip_SEIP_SOFT <= 1'b0;
-      CsrPlugin_sip_STIP <= 1'b0;
-      CsrPlugin_sip_SSIP <= 1'b0;
-      CsrPlugin_sie_SEIE <= 1'b0;
-      CsrPlugin_sie_STIE <= 1'b0;
-      CsrPlugin_sie_SSIE <= 1'b0;
-      CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0;
-      CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0;
-      CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0;
-      CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0;
-      CsrPlugin_interrupt_valid <= 1'b0;
-      CsrPlugin_lastStageWasWfi <= 1'b0;
-      CsrPlugin_hadException <= 1'b0;
-      execute_CsrPlugin_wfiWake <= 1'b0;
-      memory_MulDivIterativePlugin_mul_counter_value <= (6'b000000);
-      memory_MulDivIterativePlugin_div_counter_value <= (6'b000000);
-      _zz_207_ <= (32'b00000000000000000000000000000000);
-      _zz_209_ <= (32'b00000000000000000000000000000000);
-      execute_arbitration_isValid <= 1'b0;
-      memory_arbitration_isValid <= 1'b0;
-      writeBack_arbitration_isValid <= 1'b0;
-      execute_to_memory_IS_DBUS_SHARING <= 1'b0;
-      memory_to_writeBack_IS_DBUS_SHARING <= 1'b0;
-      memory_to_writeBack_REGFILE_WRITE_DATA <= (32'b00000000000000000000000000000000);
-      memory_to_writeBack_INSTRUCTION <= (32'b00000000000000000000000000000000);
-      _zz_211_ <= (3'b000);
-      _zz_212_ <= 1'b0;
-      _zz_213_ <= (3'b000);
-      _zz_219_ <= 1'b0;
-    end else begin
-      IBusCachedPlugin_fetchPc_booted <= 1'b1;
-      if((IBusCachedPlugin_fetchPc_corrected || IBusCachedPlugin_fetchPc_pcRegPropagate))begin
-        IBusCachedPlugin_fetchPc_inc <= 1'b0;
-      end
-      if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin
-        IBusCachedPlugin_fetchPc_inc <= 1'b1;
-      end
-      if(((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready))begin
-        IBusCachedPlugin_fetchPc_inc <= 1'b0;
-      end
-      if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetcherflushIt) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin
-        IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc;
-      end
-      if(IBusCachedPlugin_fetcherflushIt)begin
-        _zz_109_ <= 1'b0;
-      end
-      if(_zz_107_)begin
-        _zz_109_ <= IBusCachedPlugin_iBusRsp_stages_0_output_valid;
-      end
-      if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin
-        _zz_111_ <= IBusCachedPlugin_iBusRsp_stages_1_output_valid;
-      end
-      if(IBusCachedPlugin_fetcherflushIt)begin
-        _zz_111_ <= 1'b0;
-      end
-      if(IBusCachedPlugin_iBusRsp_stages_2_output_ready)begin
-        _zz_114_ <= IBusCachedPlugin_iBusRsp_stages_2_output_valid;
-      end
-      if(IBusCachedPlugin_fetcherflushIt)begin
-        _zz_114_ <= 1'b0;
-      end
-      if(IBusCachedPlugin_fetcherflushIt)begin
-        IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0;
-      end
-      if((! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)))begin
-        IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1;
-      end
-      if(IBusCachedPlugin_fetcherflushIt)begin
-        IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0;
-      end
-      if((! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)))begin
-        IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0;
-      end
-      if(IBusCachedPlugin_fetcherflushIt)begin
-        IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0;
-      end
-      if(IBusCachedPlugin_fetcherflushIt)begin
-        IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0;
-      end
-      if((! (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)))begin
-        IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1;
-      end
-      if(IBusCachedPlugin_fetcherflushIt)begin
-        IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0;
-      end
-      if(IBusCachedPlugin_fetcherflushIt)begin
-        IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0;
-      end
-      if((! execute_arbitration_isStuck))begin
-        IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2;
-      end
-      if(IBusCachedPlugin_fetcherflushIt)begin
-        IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0;
-      end
-      if(IBusCachedPlugin_fetcherflushIt)begin
-        IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0;
-      end
-      if((! memory_arbitration_isStuck))begin
-        IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3;
-      end
-      if(IBusCachedPlugin_fetcherflushIt)begin
-        IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0;
-      end
-      if(IBusCachedPlugin_fetcherflushIt)begin
-        IBusCachedPlugin_injector_nextPcCalc_valids_5 <= 1'b0;
-      end
-      if((! writeBack_arbitration_isStuck))begin
-        IBusCachedPlugin_injector_nextPcCalc_valids_5 <= IBusCachedPlugin_injector_nextPcCalc_valids_4;
-      end
-      if(IBusCachedPlugin_fetcherflushIt)begin
-        IBusCachedPlugin_injector_nextPcCalc_valids_5 <= 1'b0;
-      end
-      if(decode_arbitration_removeIt)begin
-        IBusCachedPlugin_injector_decodeRemoved <= 1'b1;
-      end
-      if(IBusCachedPlugin_fetcherflushIt)begin
-        IBusCachedPlugin_injector_decodeRemoved <= 1'b0;
-      end
-      if(iBus_rsp_valid)begin
-        IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + (32'b00000000000000000000000000000001));
-      end
-      if(dataCache_1__io_mem_cmd_s2mPipe_ready)begin
-        _zz_117_ <= 1'b0;
-      end
-      if(_zz_306_)begin
-        _zz_117_ <= dataCache_1__io_mem_cmd_valid;
-      end
-      if(dataCache_1__io_mem_cmd_s2mPipe_ready)begin
-        _zz_124_ <= dataCache_1__io_mem_cmd_s2mPipe_valid;
-      end
-      if(dBus_rsp_valid)begin
-        DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + (32'b00000000000000000000000000000001));
-      end
-      MmuPlugin_ports_0_entryToReplace_value <= MmuPlugin_ports_0_entryToReplace_valueNext;
-      if(contextSwitching)begin
-        if(MmuPlugin_ports_0_cache_0_exception)begin
-          MmuPlugin_ports_0_cache_0_valid <= 1'b0;
-        end
-        if(MmuPlugin_ports_0_cache_1_exception)begin
-          MmuPlugin_ports_0_cache_1_valid <= 1'b0;
-        end
-        if(MmuPlugin_ports_0_cache_2_exception)begin
-          MmuPlugin_ports_0_cache_2_valid <= 1'b0;
-        end
-        if(MmuPlugin_ports_0_cache_3_exception)begin
-          MmuPlugin_ports_0_cache_3_valid <= 1'b0;
-        end
-      end
-      MmuPlugin_ports_1_entryToReplace_value <= MmuPlugin_ports_1_entryToReplace_valueNext;
-      if(contextSwitching)begin
-        if(MmuPlugin_ports_1_cache_0_exception)begin
-          MmuPlugin_ports_1_cache_0_valid <= 1'b0;
-        end
-        if(MmuPlugin_ports_1_cache_1_exception)begin
-          MmuPlugin_ports_1_cache_1_valid <= 1'b0;
-        end
-        if(MmuPlugin_ports_1_cache_2_exception)begin
-          MmuPlugin_ports_1_cache_2_valid <= 1'b0;
-        end
-        if(MmuPlugin_ports_1_cache_3_exception)begin
-          MmuPlugin_ports_1_cache_3_valid <= 1'b0;
-        end
-      end
-      case(MmuPlugin_shared_state_1_)
-        `MmuPlugin_shared_State_defaultEncoding_IDLE : begin
-          if(_zz_307_)begin
-            MmuPlugin_shared_state_1_ <= `MmuPlugin_shared_State_defaultEncoding_L1_CMD;
-          end
-          if(_zz_308_)begin
-            MmuPlugin_shared_state_1_ <= `MmuPlugin_shared_State_defaultEncoding_L1_CMD;
-          end
-        end
-        `MmuPlugin_shared_State_defaultEncoding_L1_CMD : begin
-          if(MmuPlugin_dBusAccess_cmd_ready)begin
-            MmuPlugin_shared_state_1_ <= `MmuPlugin_shared_State_defaultEncoding_L1_RSP;
-          end
-        end
-        `MmuPlugin_shared_State_defaultEncoding_L1_RSP : begin
-          if(MmuPlugin_dBusAccess_rsp_valid)begin
-            MmuPlugin_shared_state_1_ <= `MmuPlugin_shared_State_defaultEncoding_L0_CMD;
-            if((MmuPlugin_shared_dBusRsp_leaf || MmuPlugin_shared_dBusRsp_exception))begin
-              MmuPlugin_shared_state_1_ <= `MmuPlugin_shared_State_defaultEncoding_IDLE;
-            end
-            if(MmuPlugin_dBusAccess_rsp_payload_redo)begin
-              MmuPlugin_shared_state_1_ <= `MmuPlugin_shared_State_defaultEncoding_L1_CMD;
-            end
-          end
-        end
-        `MmuPlugin_shared_State_defaultEncoding_L0_CMD : begin
-          if(MmuPlugin_dBusAccess_cmd_ready)begin
-            MmuPlugin_shared_state_1_ <= `MmuPlugin_shared_State_defaultEncoding_L0_RSP;
-          end
-        end
-        default : begin
-          if(MmuPlugin_dBusAccess_rsp_valid)begin
-            MmuPlugin_shared_state_1_ <= `MmuPlugin_shared_State_defaultEncoding_IDLE;
-            if(MmuPlugin_dBusAccess_rsp_payload_redo)begin
-              MmuPlugin_shared_state_1_ <= `MmuPlugin_shared_State_defaultEncoding_L0_CMD;
-            end
-          end
-        end
-      endcase
-      if(_zz_293_)begin
-        if(_zz_294_)begin
-          if(_zz_309_)begin
-            MmuPlugin_ports_0_cache_0_valid <= 1'b1;
-          end
-          if(_zz_310_)begin
-            MmuPlugin_ports_0_cache_1_valid <= 1'b1;
-          end
-          if(_zz_311_)begin
-            MmuPlugin_ports_0_cache_2_valid <= 1'b1;
-          end
-          if(_zz_312_)begin
-            MmuPlugin_ports_0_cache_3_valid <= 1'b1;
-          end
-        end
-        if(_zz_295_)begin
-          if(_zz_313_)begin
-            MmuPlugin_ports_1_cache_0_valid <= 1'b1;
-          end
-          if(_zz_314_)begin
-            MmuPlugin_ports_1_cache_1_valid <= 1'b1;
-          end
-          if(_zz_315_)begin
-            MmuPlugin_ports_1_cache_2_valid <= 1'b1;
-          end
-          if(_zz_316_)begin
-            MmuPlugin_ports_1_cache_3_valid <= 1'b1;
-          end
-        end
-      end
-      if((writeBack_arbitration_isValid && writeBack_IS_SFENCE_VMA))begin
-        MmuPlugin_ports_0_cache_0_valid <= 1'b0;
-        MmuPlugin_ports_0_cache_1_valid <= 1'b0;
-        MmuPlugin_ports_0_cache_2_valid <= 1'b0;
-        MmuPlugin_ports_0_cache_3_valid <= 1'b0;
-        MmuPlugin_ports_1_cache_0_valid <= 1'b0;
-        MmuPlugin_ports_1_cache_1_valid <= 1'b0;
-        MmuPlugin_ports_1_cache_2_valid <= 1'b0;
-        MmuPlugin_ports_1_cache_3_valid <= 1'b0;
-      end
-      _zz_159_ <= 1'b0;
-      _zz_172_ <= _zz_171_;
-      if((! decode_arbitration_isStuck))begin
-        CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0;
-      end else begin
-        CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode;
-      end
-      if((! execute_arbitration_isStuck))begin
-        CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck));
-      end else begin
-        CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute;
-      end
-      if((! memory_arbitration_isStuck))begin
-        CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck));
-      end else begin
-        CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory;
-      end
-      if((! writeBack_arbitration_isStuck))begin
-        CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck));
-      end else begin
-        CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0;
-      end
-      CsrPlugin_interrupt_valid <= 1'b0;
-      if(_zz_317_)begin
-        if(_zz_318_)begin
-          CsrPlugin_interrupt_valid <= 1'b1;
-        end
-        if(_zz_319_)begin
-          CsrPlugin_interrupt_valid <= 1'b1;
-        end
-        if(_zz_320_)begin
-          CsrPlugin_interrupt_valid <= 1'b1;
-        end
-      end
-      if(_zz_321_)begin
-        if(_zz_322_)begin
-          CsrPlugin_interrupt_valid <= 1'b1;
-        end
-        if(_zz_323_)begin
-          CsrPlugin_interrupt_valid <= 1'b1;
-        end
-        if(_zz_324_)begin
-          CsrPlugin_interrupt_valid <= 1'b1;
-        end
-        if(_zz_325_)begin
-          CsrPlugin_interrupt_valid <= 1'b1;
-        end
-        if(_zz_326_)begin
-          CsrPlugin_interrupt_valid <= 1'b1;
-        end
-        if(_zz_327_)begin
-          CsrPlugin_interrupt_valid <= 1'b1;
-        end
-      end
-      CsrPlugin_lastStageWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI));
-      CsrPlugin_hadException <= CsrPlugin_exception;
-      if(_zz_286_)begin
-        _zz_191_ <= CsrPlugin_targetPrivilege;
-        case(CsrPlugin_targetPrivilege)
-          2'b01 : begin
-            CsrPlugin_sstatus_SIE <= 1'b0;
-            CsrPlugin_sstatus_SPIE <= CsrPlugin_sstatus_SIE;
-            CsrPlugin_sstatus_SPP <= CsrPlugin_privilege[0 : 0];
-          end
-          2'b11 : begin
-            CsrPlugin_mstatus_MIE <= 1'b0;
-            CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE;
-            CsrPlugin_mstatus_MPP <= CsrPlugin_privilege;
-          end
-          default : begin
-          end
-        endcase
-      end
-      if(_zz_287_)begin
-        case(_zz_288_)
-          2'b11 : begin
-            CsrPlugin_mstatus_MPP <= (2'b00);
-            CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE;
-            CsrPlugin_mstatus_MPIE <= 1'b1;
-            _zz_191_ <= CsrPlugin_mstatus_MPP;
-          end
-          2'b01 : begin
-            CsrPlugin_sstatus_SPP <= (1'b0);
-            CsrPlugin_sstatus_SIE <= CsrPlugin_sstatus_SPIE;
-            CsrPlugin_sstatus_SPIE <= 1'b1;
-            _zz_191_ <= {(1'b0),CsrPlugin_sstatus_SPP};
-          end
-          default : begin
-          end
-        endcase
-      end
-      execute_CsrPlugin_wfiWake <= ({_zz_197_,{_zz_196_,{_zz_195_,{_zz_194_,{_zz_193_,_zz_192_}}}}} != (6'b000000));
-      memory_MulDivIterativePlugin_mul_counter_value <= memory_MulDivIterativePlugin_mul_counter_valueNext;
-      memory_MulDivIterativePlugin_div_counter_value <= memory_MulDivIterativePlugin_div_counter_valueNext;
-      if((! writeBack_arbitration_isStuck))begin
-        memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION;
-      end
-      if((! memory_arbitration_isStuck))begin
-        execute_to_memory_IS_DBUS_SHARING <= execute_IS_DBUS_SHARING;
-      end
-      if((! writeBack_arbitration_isStuck))begin
-        memory_to_writeBack_IS_DBUS_SHARING <= memory_IS_DBUS_SHARING;
-      end
-      if((! writeBack_arbitration_isStuck))begin
-        memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_37_;
-      end
-      if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin
-        execute_arbitration_isValid <= 1'b0;
-      end
-      if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin
-        execute_arbitration_isValid <= decode_arbitration_isValid;
-      end
-      if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin
-        memory_arbitration_isValid <= 1'b0;
-      end
-      if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin
-        memory_arbitration_isValid <= execute_arbitration_isValid;
-      end
-      if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin
-        writeBack_arbitration_isValid <= 1'b0;
-      end
-      if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin
-        writeBack_arbitration_isValid <= memory_arbitration_isValid;
-      end
-      if(MmuPlugin_dBusAccess_rsp_valid)begin
-        memory_to_writeBack_IS_DBUS_SHARING <= 1'b0;
-      end
-      case(execute_CsrPlugin_csrAddress)
-        12'b101111000000 : begin
-          if(execute_CsrPlugin_writeEnable)begin
-            _zz_207_ <= execute_CsrPlugin_writeData[31 : 0];
-          end
-        end
-        12'b001100000000 : begin
-          if(execute_CsrPlugin_writeEnable)begin
-            MmuPlugin_status_mxr <= _zz_410_[0];
-            MmuPlugin_status_sum <= _zz_411_[0];
-            MmuPlugin_status_mprv <= _zz_412_[0];
-            CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11];
-            CsrPlugin_mstatus_MPIE <= _zz_413_[0];
-            CsrPlugin_mstatus_MIE <= _zz_414_[0];
-            CsrPlugin_sstatus_SPP <= execute_CsrPlugin_writeData[8 : 8];
-            CsrPlugin_sstatus_SPIE <= _zz_415_[0];
-            CsrPlugin_sstatus_SIE <= _zz_416_[0];
-          end
-        end
-        12'b001100000011 : begin
-          if(execute_CsrPlugin_writeEnable)begin
-            CsrPlugin_mideleg_SE <= _zz_417_[0];
-            CsrPlugin_mideleg_ST <= _zz_418_[0];
-            CsrPlugin_mideleg_SS <= _zz_419_[0];
-          end
-        end
-        12'b111100010001 : begin
-        end
-        12'b000101000010 : begin
-        end
-        12'b111100010100 : begin
-        end
-        12'b100111000000 : begin
-          if(execute_CsrPlugin_writeEnable)begin
-            _zz_209_ <= execute_CsrPlugin_writeData[31 : 0];
-          end
-        end
-        12'b000100000000 : begin
-          if(execute_CsrPlugin_writeEnable)begin
-            MmuPlugin_status_mxr <= _zz_421_[0];
-            MmuPlugin_status_sum <= _zz_422_[0];
-            MmuPlugin_status_mprv <= _zz_423_[0];
-            CsrPlugin_sstatus_SPP <= execute_CsrPlugin_writeData[8 : 8];
-            CsrPlugin_sstatus_SPIE <= _zz_424_[0];
-            CsrPlugin_sstatus_SIE <= _zz_425_[0];
-          end
-        end
-        12'b001100000010 : begin
-          if(execute_CsrPlugin_writeEnable)begin
-            CsrPlugin_medeleg_EU <= _zz_426_[0];
-            CsrPlugin_medeleg_II <= _zz_427_[0];
-            CsrPlugin_medeleg_LAF <= _zz_428_[0];
-            CsrPlugin_medeleg_LPF <= _zz_429_[0];
-            CsrPlugin_medeleg_LAM <= _zz_430_[0];
-            CsrPlugin_medeleg_SAF <= _zz_431_[0];
-            CsrPlugin_medeleg_IAF <= _zz_432_[0];
-            CsrPlugin_medeleg_ES <= _zz_433_[0];
-            CsrPlugin_medeleg_IPF <= _zz_434_[0];
-            CsrPlugin_medeleg_SPF <= _zz_435_[0];
-            CsrPlugin_medeleg_SAM <= _zz_436_[0];
-            CsrPlugin_medeleg_IAM <= _zz_437_[0];
-          end
-        end
-        12'b001101000001 : begin
-        end
-        12'b001101000100 : begin
-          if(execute_CsrPlugin_writeEnable)begin
-            CsrPlugin_sip_STIP <= _zz_439_[0];
-            CsrPlugin_sip_SSIP <= _zz_440_[0];
-            CsrPlugin_sip_SEIP_SOFT <= _zz_441_[0];
-          end
-        end
-        12'b001100000101 : begin
-        end
-        12'b000110000000 : begin
-          if(execute_CsrPlugin_writeEnable)begin
-            MmuPlugin_satp_mode <= _zz_442_[0];
-          end
-        end
-        12'b110011000000 : begin
-        end
-        12'b000101000001 : begin
-        end
-        12'b111100010011 : begin
-        end
-        12'b000101000100 : begin
-          if(execute_CsrPlugin_writeEnable)begin
-            CsrPlugin_sip_STIP <= _zz_443_[0];
-            CsrPlugin_sip_SSIP <= _zz_444_[0];
-            CsrPlugin_sip_SEIP_SOFT <= _zz_445_[0];
-          end
-        end
-        12'b001101000011 : begin
-        end
-        12'b000100000101 : begin
-        end
-        12'b111111000000 : begin
-        end
-        12'b001101000000 : begin
-        end
-        12'b001100000100 : begin
-          if(execute_CsrPlugin_writeEnable)begin
-            CsrPlugin_mie_MEIE <= _zz_446_[0];
-            CsrPlugin_mie_MTIE <= _zz_447_[0];
-            CsrPlugin_mie_MSIE <= _zz_448_[0];
-            CsrPlugin_sie_SEIE <= _zz_449_[0];
-            CsrPlugin_sie_STIE <= _zz_450_[0];
-            CsrPlugin_sie_SSIE <= _zz_451_[0];
-          end
-        end
-        12'b111100010010 : begin
-        end
-        12'b000101000011 : begin
-        end
-        12'b110111000000 : begin
-        end
-        12'b000101000000 : begin
-        end
-        12'b001101000010 : begin
-        end
-        12'b000100000100 : begin
-          if(execute_CsrPlugin_writeEnable)begin
-            CsrPlugin_sie_SEIE <= _zz_452_[0];
-            CsrPlugin_sie_STIE <= _zz_453_[0];
-            CsrPlugin_sie_SSIE <= _zz_454_[0];
-          end
-        end
-        default : begin
-        end
-      endcase
-      if(_zz_305_)begin
-        if(iBusWishbone_ACK)begin
-          _zz_211_ <= (_zz_211_ + (3'b001));
-        end
-      end
-      _zz_212_ <= (iBusWishbone_CYC && iBusWishbone_ACK);
-      if((_zz_214_ && _zz_215_))begin
-        _zz_213_ <= (_zz_213_ + (3'b001));
-        if(_zz_217_)begin
-          _zz_213_ <= (3'b000);
-        end
-      end
-      _zz_219_ <= ((_zz_214_ && (! dBusWishbone_WE)) && dBusWishbone_ACK);
-    end
-  end
-
-  always @ (posedge clk) begin
-    if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin
-      _zz_112_ <= IBusCachedPlugin_iBusRsp_stages_1_output_payload;
-    end
-    if(IBusCachedPlugin_iBusRsp_stages_2_output_ready)begin
-      _zz_115_ <= IBusCachedPlugin_iBusRsp_stages_2_output_payload;
-    end
-    if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin
-      IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit;
-    end
-    if(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)begin
-      IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit;
-    end
-    if(_zz_306_)begin
-      _zz_118_ <= dataCache_1__io_mem_cmd_payload_wr;
-      _zz_119_ <= dataCache_1__io_mem_cmd_payload_address;
-      _zz_120_ <= dataCache_1__io_mem_cmd_payload_data;
-      _zz_121_ <= dataCache_1__io_mem_cmd_payload_mask;
-      _zz_122_ <= dataCache_1__io_mem_cmd_payload_length;
-      _zz_123_ <= dataCache_1__io_mem_cmd_payload_last;
-    end
-    if(dataCache_1__io_mem_cmd_s2mPipe_ready)begin
-      _zz_125_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_wr;
-      _zz_126_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_address;
-      _zz_127_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_data;
-      _zz_128_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_mask;
-      _zz_129_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_length;
-      _zz_130_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_last;
-    end
-    if((MmuPlugin_dBusAccess_rsp_valid && (! MmuPlugin_dBusAccess_rsp_payload_redo)))begin
-      MmuPlugin_shared_pteBuffer_V <= MmuPlugin_shared_dBusRsp_pte_V;
-      MmuPlugin_shared_pteBuffer_R <= MmuPlugin_shared_dBusRsp_pte_R;
-      MmuPlugin_shared_pteBuffer_W <= MmuPlugin_shared_dBusRsp_pte_W;
-      MmuPlugin_shared_pteBuffer_X <= MmuPlugin_shared_dBusRsp_pte_X;
-      MmuPlugin_shared_pteBuffer_U <= MmuPlugin_shared_dBusRsp_pte_U;
-      MmuPlugin_shared_pteBuffer_G <= MmuPlugin_shared_dBusRsp_pte_G;
-      MmuPlugin_shared_pteBuffer_A <= MmuPlugin_shared_dBusRsp_pte_A;
-      MmuPlugin_shared_pteBuffer_D <= MmuPlugin_shared_dBusRsp_pte_D;
-      MmuPlugin_shared_pteBuffer_RSW <= MmuPlugin_shared_dBusRsp_pte_RSW;
-      MmuPlugin_shared_pteBuffer_PPN0 <= MmuPlugin_shared_dBusRsp_pte_PPN0;
-      MmuPlugin_shared_pteBuffer_PPN1 <= MmuPlugin_shared_dBusRsp_pte_PPN1;
-    end
-    case(MmuPlugin_shared_state_1_)
-      `MmuPlugin_shared_State_defaultEncoding_IDLE : begin
-        if(_zz_307_)begin
-          MmuPlugin_shared_vpn_1 <= IBusCachedPlugin_mmuBus_cmd_virtualAddress[31 : 22];
-          MmuPlugin_shared_vpn_0 <= IBusCachedPlugin_mmuBus_cmd_virtualAddress[21 : 12];
-          MmuPlugin_shared_portId <= (1'b0);
-        end
-        if(_zz_308_)begin
-          MmuPlugin_shared_vpn_1 <= DBusCachedPlugin_mmuBus_cmd_virtualAddress[31 : 22];
-          MmuPlugin_shared_vpn_0 <= DBusCachedPlugin_mmuBus_cmd_virtualAddress[21 : 12];
-          MmuPlugin_shared_portId <= (1'b1);
-        end
-      end
-      `MmuPlugin_shared_State_defaultEncoding_L1_CMD : begin
-      end
-      `MmuPlugin_shared_State_defaultEncoding_L1_RSP : begin
-      end
-      `MmuPlugin_shared_State_defaultEncoding_L0_CMD : begin
-      end
-      default : begin
-      end
-    endcase
-    if(_zz_293_)begin
-      if(_zz_294_)begin
-        if(_zz_309_)begin
-          MmuPlugin_ports_0_cache_0_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != (10'b0000000000))));
-          MmuPlugin_ports_0_cache_0_virtualAddress_0 <= MmuPlugin_shared_vpn_0;
-          MmuPlugin_ports_0_cache_0_virtualAddress_1 <= MmuPlugin_shared_vpn_1;
-          MmuPlugin_ports_0_cache_0_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0;
-          MmuPlugin_ports_0_cache_0_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0];
-          MmuPlugin_ports_0_cache_0_allowRead <= MmuPlugin_shared_dBusRsp_pte_R;
-          MmuPlugin_ports_0_cache_0_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W;
-          MmuPlugin_ports_0_cache_0_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X;
-          MmuPlugin_ports_0_cache_0_allowUser <= MmuPlugin_shared_dBusRsp_pte_U;
-          MmuPlugin_ports_0_cache_0_superPage <= (MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP);
-        end
-        if(_zz_310_)begin
-          MmuPlugin_ports_0_cache_1_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != (10'b0000000000))));
-          MmuPlugin_ports_0_cache_1_virtualAddress_0 <= MmuPlugin_shared_vpn_0;
-          MmuPlugin_ports_0_cache_1_virtualAddress_1 <= MmuPlugin_shared_vpn_1;
-          MmuPlugin_ports_0_cache_1_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0;
-          MmuPlugin_ports_0_cache_1_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0];
-          MmuPlugin_ports_0_cache_1_allowRead <= MmuPlugin_shared_dBusRsp_pte_R;
-          MmuPlugin_ports_0_cache_1_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W;
-          MmuPlugin_ports_0_cache_1_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X;
-          MmuPlugin_ports_0_cache_1_allowUser <= MmuPlugin_shared_dBusRsp_pte_U;
-          MmuPlugin_ports_0_cache_1_superPage <= (MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP);
-        end
-        if(_zz_311_)begin
-          MmuPlugin_ports_0_cache_2_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != (10'b0000000000))));
-          MmuPlugin_ports_0_cache_2_virtualAddress_0 <= MmuPlugin_shared_vpn_0;
-          MmuPlugin_ports_0_cache_2_virtualAddress_1 <= MmuPlugin_shared_vpn_1;
-          MmuPlugin_ports_0_cache_2_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0;
-          MmuPlugin_ports_0_cache_2_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0];
-          MmuPlugin_ports_0_cache_2_allowRead <= MmuPlugin_shared_dBusRsp_pte_R;
-          MmuPlugin_ports_0_cache_2_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W;
-          MmuPlugin_ports_0_cache_2_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X;
-          MmuPlugin_ports_0_cache_2_allowUser <= MmuPlugin_shared_dBusRsp_pte_U;
-          MmuPlugin_ports_0_cache_2_superPage <= (MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP);
-        end
-        if(_zz_312_)begin
-          MmuPlugin_ports_0_cache_3_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != (10'b0000000000))));
-          MmuPlugin_ports_0_cache_3_virtualAddress_0 <= MmuPlugin_shared_vpn_0;
-          MmuPlugin_ports_0_cache_3_virtualAddress_1 <= MmuPlugin_shared_vpn_1;
-          MmuPlugin_ports_0_cache_3_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0;
-          MmuPlugin_ports_0_cache_3_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0];
-          MmuPlugin_ports_0_cache_3_allowRead <= MmuPlugin_shared_dBusRsp_pte_R;
-          MmuPlugin_ports_0_cache_3_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W;
-          MmuPlugin_ports_0_cache_3_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X;
-          MmuPlugin_ports_0_cache_3_allowUser <= MmuPlugin_shared_dBusRsp_pte_U;
-          MmuPlugin_ports_0_cache_3_superPage <= (MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP);
-        end
-      end
-      if(_zz_295_)begin
-        if(_zz_313_)begin
-          MmuPlugin_ports_1_cache_0_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != (10'b0000000000))));
-          MmuPlugin_ports_1_cache_0_virtualAddress_0 <= MmuPlugin_shared_vpn_0;
-          MmuPlugin_ports_1_cache_0_virtualAddress_1 <= MmuPlugin_shared_vpn_1;
-          MmuPlugin_ports_1_cache_0_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0;
-          MmuPlugin_ports_1_cache_0_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0];
-          MmuPlugin_ports_1_cache_0_allowRead <= MmuPlugin_shared_dBusRsp_pte_R;
-          MmuPlugin_ports_1_cache_0_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W;
-          MmuPlugin_ports_1_cache_0_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X;
-          MmuPlugin_ports_1_cache_0_allowUser <= MmuPlugin_shared_dBusRsp_pte_U;
-          MmuPlugin_ports_1_cache_0_superPage <= (MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP);
-        end
-        if(_zz_314_)begin
-          MmuPlugin_ports_1_cache_1_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != (10'b0000000000))));
-          MmuPlugin_ports_1_cache_1_virtualAddress_0 <= MmuPlugin_shared_vpn_0;
-          MmuPlugin_ports_1_cache_1_virtualAddress_1 <= MmuPlugin_shared_vpn_1;
-          MmuPlugin_ports_1_cache_1_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0;
-          MmuPlugin_ports_1_cache_1_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0];
-          MmuPlugin_ports_1_cache_1_allowRead <= MmuPlugin_shared_dBusRsp_pte_R;
-          MmuPlugin_ports_1_cache_1_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W;
-          MmuPlugin_ports_1_cache_1_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X;
-          MmuPlugin_ports_1_cache_1_allowUser <= MmuPlugin_shared_dBusRsp_pte_U;
-          MmuPlugin_ports_1_cache_1_superPage <= (MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP);
-        end
-        if(_zz_315_)begin
-          MmuPlugin_ports_1_cache_2_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != (10'b0000000000))));
-          MmuPlugin_ports_1_cache_2_virtualAddress_0 <= MmuPlugin_shared_vpn_0;
-          MmuPlugin_ports_1_cache_2_virtualAddress_1 <= MmuPlugin_shared_vpn_1;
-          MmuPlugin_ports_1_cache_2_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0;
-          MmuPlugin_ports_1_cache_2_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0];
-          MmuPlugin_ports_1_cache_2_allowRead <= MmuPlugin_shared_dBusRsp_pte_R;
-          MmuPlugin_ports_1_cache_2_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W;
-          MmuPlugin_ports_1_cache_2_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X;
-          MmuPlugin_ports_1_cache_2_allowUser <= MmuPlugin_shared_dBusRsp_pte_U;
-          MmuPlugin_ports_1_cache_2_superPage <= (MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP);
-        end
-        if(_zz_316_)begin
-          MmuPlugin_ports_1_cache_3_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != (10'b0000000000))));
-          MmuPlugin_ports_1_cache_3_virtualAddress_0 <= MmuPlugin_shared_vpn_0;
-          MmuPlugin_ports_1_cache_3_virtualAddress_1 <= MmuPlugin_shared_vpn_1;
-          MmuPlugin_ports_1_cache_3_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0;
-          MmuPlugin_ports_1_cache_3_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0];
-          MmuPlugin_ports_1_cache_3_allowRead <= MmuPlugin_shared_dBusRsp_pte_R;
-          MmuPlugin_ports_1_cache_3_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W;
-          MmuPlugin_ports_1_cache_3_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X;
-          MmuPlugin_ports_1_cache_3_allowUser <= MmuPlugin_shared_dBusRsp_pte_U;
-          MmuPlugin_ports_1_cache_3_superPage <= (MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP);
-        end
-      end
-    end
-    if(_zz_171_)begin
-      _zz_173_ <= _zz_53_[11 : 7];
-      _zz_174_ <= _zz_87_;
-    end
-    CsrPlugin_mip_MEIP <= externalInterrupt;
-    CsrPlugin_mip_MTIP <= timerInterrupt;
-    CsrPlugin_mip_MSIP <= softwareInterrupt;
-    CsrPlugin_sip_SEIP_INPUT <= externalInterruptS;
-    CsrPlugin_mcycle <= (CsrPlugin_mcycle + (64'b0000000000000000000000000000000000000000000000000000000000000001));
-    if(writeBack_arbitration_isFiring)begin
-      CsrPlugin_minstret <= (CsrPlugin_minstret + (64'b0000000000000000000000000000000000000000000000000000000000000001));
-    end
-    if(_zz_282_)begin
-      CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_199_ ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code);
-      CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_199_ ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr);
-    end
-    if(CsrPlugin_selfException_valid)begin
-      CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code;
-      CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr;
-    end
-    if(BranchPlugin_branchExceptionPort_valid)begin
-      CsrPlugin_exceptionPortCtrl_exceptionContext_code <= BranchPlugin_branchExceptionPort_payload_code;
-      CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= BranchPlugin_branchExceptionPort_payload_badAddr;
-    end
-    if(DBusCachedPlugin_exceptionBus_valid)begin
-      CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code;
-      CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr;
-    end
-    if(_zz_317_)begin
-      if(_zz_318_)begin
-        CsrPlugin_interrupt_code <= (4'b0101);
-        CsrPlugin_interrupt_targetPrivilege <= (2'b01);
-      end
-      if(_zz_319_)begin
-        CsrPlugin_interrupt_code <= (4'b0001);
-        CsrPlugin_interrupt_targetPrivilege <= (2'b01);
-      end
-      if(_zz_320_)begin
-        CsrPlugin_interrupt_code <= (4'b1001);
-        CsrPlugin_interrupt_targetPrivilege <= (2'b01);
-      end
-    end
-    if(_zz_321_)begin
-      if(_zz_322_)begin
-        CsrPlugin_interrupt_code <= (4'b0101);
-        CsrPlugin_interrupt_targetPrivilege <= (2'b11);
-      end
-      if(_zz_323_)begin
-        CsrPlugin_interrupt_code <= (4'b0001);
-        CsrPlugin_interrupt_targetPrivilege <= (2'b11);
-      end
-      if(_zz_324_)begin
-        CsrPlugin_interrupt_code <= (4'b1001);
-        CsrPlugin_interrupt_targetPrivilege <= (2'b11);
-      end
-      if(_zz_325_)begin
-        CsrPlugin_interrupt_code <= (4'b0111);
-        CsrPlugin_interrupt_targetPrivilege <= (2'b11);
-      end
-      if(_zz_326_)begin
-        CsrPlugin_interrupt_code <= (4'b0011);
-        CsrPlugin_interrupt_targetPrivilege <= (2'b11);
-      end
-      if(_zz_327_)begin
-        CsrPlugin_interrupt_code <= (4'b1011);
-        CsrPlugin_interrupt_targetPrivilege <= (2'b11);
-      end
-    end
-    if(_zz_286_)begin
-      case(CsrPlugin_targetPrivilege)
-        2'b01 : begin
-          CsrPlugin_scause_interrupt <= (! CsrPlugin_hadException);
-          CsrPlugin_scause_exceptionCode <= CsrPlugin_trapCause;
-          CsrPlugin_sepc <= writeBack_PC;
-          if(CsrPlugin_hadException)begin
-            CsrPlugin_stval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr;
-          end
-        end
-        2'b11 : begin
-          CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException);
-          CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause;
-          CsrPlugin_mepc <= writeBack_PC;
-          if(CsrPlugin_hadException)begin
-            CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr;
-          end
-        end
-        default : begin
-        end
-      endcase
-    end
-    if(_zz_276_)begin
-      if(_zz_284_)begin
-        memory_MulDivIterativePlugin_rs2 <= (memory_MulDivIterativePlugin_rs2 >>> 1);
-        memory_MulDivIterativePlugin_accumulator <= ({_zz_389_,memory_MulDivIterativePlugin_accumulator[31 : 0]} >>> 1);
-      end
-    end
-    if((memory_MulDivIterativePlugin_div_counter_value == (6'b100000)))begin
-      memory_MulDivIterativePlugin_div_done <= 1'b1;
-    end
-    if((! memory_arbitration_isStuck))begin
-      memory_MulDivIterativePlugin_div_done <= 1'b0;
-    end
-    if(_zz_277_)begin
-      if(_zz_285_)begin
-        memory_MulDivIterativePlugin_rs1[31 : 0] <= _zz_398_[31:0];
-        memory_MulDivIterativePlugin_accumulator[31 : 0] <= ((! _zz_202_[32]) ? _zz_399_ : _zz_400_);
-        if((memory_MulDivIterativePlugin_div_counter_value == (6'b100000)))begin
-          memory_MulDivIterativePlugin_div_result <= _zz_401_[31:0];
-        end
-      end
-    end
-    if(_zz_304_)begin
-      memory_MulDivIterativePlugin_accumulator <= (65'b00000000000000000000000000000000000000000000000000000000000000000);
-      memory_MulDivIterativePlugin_rs1 <= ((_zz_205_ ? (~ _zz_206_) : _zz_206_) + _zz_407_);
-      memory_MulDivIterativePlugin_rs2 <= ((_zz_204_ ? (~ execute_RS2) : execute_RS2) + _zz_409_);
-      memory_MulDivIterativePlugin_div_needRevert <= ((_zz_205_ ^ (_zz_204_ && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == (32'b00000000000000000000000000000000)) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13]))));
-    end
-    externalInterruptArray_regNext <= externalInterruptArray;
-    if((! memory_arbitration_isStuck))begin
-      execute_to_memory_BRANCH_DO <= execute_BRANCH_DO;
-    end
-    if((! execute_arbitration_isStuck))begin
-      decode_to_execute_MEMORY_LRSC <= decode_MEMORY_LRSC;
-    end
-    if((! execute_arbitration_isStuck))begin
-      decode_to_execute_RS2 <= decode_RS2;
-    end
-    if((! execute_arbitration_isStuck))begin
-      decode_to_execute_SHIFT_CTRL <= _zz_26_;
-    end
-    if((! memory_arbitration_isStuck))begin
-      execute_to_memory_SHIFT_CTRL <= _zz_23_;
-    end
-    if((! execute_arbitration_isStuck))begin
-      decode_to_execute_INSTRUCTION <= decode_INSTRUCTION;
-    end
-    if((! memory_arbitration_isStuck))begin
-      execute_to_memory_INSTRUCTION <= execute_INSTRUCTION;
-    end
-    if((! execute_arbitration_isStuck))begin
-      decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT;
-    end
-    if((! execute_arbitration_isStuck))begin
-      decode_to_execute_IS_MUL <= decode_IS_MUL;
-    end
-    if((! memory_arbitration_isStuck))begin
-      execute_to_memory_IS_MUL <= execute_IS_MUL;
-    end
-    if((! execute_arbitration_isStuck))begin
-      decode_to_execute_IS_CSR <= decode_IS_CSR;
-    end
-    if((! memory_arbitration_isStuck))begin
-      execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT;
-    end
-    if((! execute_arbitration_isStuck))begin
-      decode_to_execute_ALU_CTRL <= _zz_21_;
-    end
-    if((! execute_arbitration_isStuck))begin
-      decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED;
-    end
-    if((! execute_arbitration_isStuck))begin
-      decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID;
-    end
-    if((! memory_arbitration_isStuck))begin
-      execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID;
-    end
-    if((! writeBack_arbitration_isStuck))begin
-      memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID;
-    end
-    if((! execute_arbitration_isStuck))begin
-      decode_to_execute_ENV_CTRL <= _zz_18_;
-    end
-    if((! memory_arbitration_isStuck))begin
-      execute_to_memory_ENV_CTRL <= _zz_15_;
-    end
-    if((! writeBack_arbitration_isStuck))begin
-      memory_to_writeBack_ENV_CTRL <= _zz_13_;
-    end
-    if((! execute_arbitration_isStuck))begin
-      decode_to_execute_PC <= decode_PC;
-    end
-    if((! memory_arbitration_isStuck))begin
-      execute_to_memory_PC <= _zz_44_;
-    end
-    if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin
-      memory_to_writeBack_PC <= memory_PC;
-    end
-    if((! execute_arbitration_isStuck))begin
-      decode_to_execute_SRC2_CTRL <= _zz_11_;
-    end
-    if((! execute_arbitration_isStuck))begin
-      decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE;
-    end
-    if((! memory_arbitration_isStuck))begin
-      execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE;
-    end
-    if((! execute_arbitration_isStuck))begin
-      decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS;
-    end
-    if((! execute_arbitration_isStuck))begin
-      decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE;
-    end
-    if((! execute_arbitration_isStuck))begin
-      decode_to_execute_MEMORY_AMO <= decode_MEMORY_AMO;
-    end
-    if((! execute_arbitration_isStuck))begin
-      decode_to_execute_FORMAL_PC_NEXT <= _zz_94_;
-    end
-    if((! memory_arbitration_isStuck))begin
-      execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT;
-    end
-    if((! writeBack_arbitration_isStuck))begin
-      memory_to_writeBack_FORMAL_PC_NEXT <= _zz_93_;
-    end
-    if((! execute_arbitration_isStuck))begin
-      decode_to_execute_MEMORY_WR <= decode_MEMORY_WR;
-    end
-    if((! memory_arbitration_isStuck))begin
-      execute_to_memory_MEMORY_WR <= execute_MEMORY_WR;
-    end
-    if((! writeBack_arbitration_isStuck))begin
-      memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR;
-    end
-    if((! execute_arbitration_isStuck))begin
-      decode_to_execute_SRC1_CTRL <= _zz_8_;
-    end
-    if((! execute_arbitration_isStuck))begin
-      decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED;
-    end
-    if((! execute_arbitration_isStuck))begin
-      decode_to_execute_IS_DIV <= decode_IS_DIV;
-    end
-    if((! memory_arbitration_isStuck))begin
-      execute_to_memory_IS_DIV <= execute_IS_DIV;
-    end
-    if((! memory_arbitration_isStuck))begin
-      execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW;
-    end
-    if((! writeBack_arbitration_isStuck))begin
-      memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW;
-    end
-    if((! execute_arbitration_isStuck))begin
-      decode_to_execute_ALU_BITWISE_CTRL <= _zz_5_;
-    end
-    if((! execute_arbitration_isStuck))begin
-      decode_to_execute_IS_SFENCE_VMA <= decode_IS_SFENCE_VMA;
-    end
-    if((! memory_arbitration_isStuck))begin
-      execute_to_memory_IS_SFENCE_VMA <= execute_IS_SFENCE_VMA;
-    end
-    if((! writeBack_arbitration_isStuck))begin
-      memory_to_writeBack_IS_SFENCE_VMA <= memory_IS_SFENCE_VMA;
-    end
-    if((! execute_arbitration_isStuck))begin
-      decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE;
-    end
-    if((! memory_arbitration_isStuck))begin
-      execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE;
-    end
-    if((! writeBack_arbitration_isStuck))begin
-      memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE;
-    end
-    if((! memory_arbitration_isStuck))begin
-      execute_to_memory_REGFILE_WRITE_DATA <= _zz_36_;
-    end
-    if((! execute_arbitration_isStuck))begin
-      decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE;
-    end
-    if((! execute_arbitration_isStuck))begin
-      decode_to_execute_BRANCH_CTRL <= _zz_2_;
-    end
-    if((! execute_arbitration_isStuck))begin
-      decode_to_execute_RS1 <= decode_RS1;
-    end
-    if((! memory_arbitration_isStuck))begin
-      execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC;
-    end
-    if((! execute_arbitration_isStuck))begin
-      decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED;
-    end
-    if((! execute_arbitration_isStuck))begin
-      decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE;
-    end
-    if((! execute_arbitration_isStuck))begin
-      decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO;
-    end
-    case(execute_CsrPlugin_csrAddress)
-      12'b101111000000 : begin
-      end
-      12'b001100000000 : begin
-      end
-      12'b001100000011 : begin
-      end
-      12'b111100010001 : begin
-      end
-      12'b000101000010 : begin
-        if(execute_CsrPlugin_writeEnable)begin
-          CsrPlugin_scause_interrupt <= _zz_420_[0];
-          CsrPlugin_scause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0];
-        end
-      end
-      12'b111100010100 : begin
-      end
-      12'b100111000000 : begin
-      end
-      12'b000100000000 : begin
-      end
-      12'b001100000010 : begin
-      end
-      12'b001101000001 : begin
-        if(execute_CsrPlugin_writeEnable)begin
-          CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0];
-        end
-      end
-      12'b001101000100 : begin
-        if(execute_CsrPlugin_writeEnable)begin
-          CsrPlugin_mip_MSIP <= _zz_438_[0];
-        end
-      end
-      12'b001100000101 : begin
-        if(execute_CsrPlugin_writeEnable)begin
-          CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2];
-          CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0];
-        end
-      end
-      12'b000110000000 : begin
-        if(execute_CsrPlugin_writeEnable)begin
-          MmuPlugin_satp_ppn <= execute_CsrPlugin_writeData[19 : 0];
-        end
-      end
-      12'b110011000000 : begin
-      end
-      12'b000101000001 : begin
-        if(execute_CsrPlugin_writeEnable)begin
-          CsrPlugin_sepc <= execute_CsrPlugin_writeData[31 : 0];
-        end
-      end
-      12'b111100010011 : begin
-      end
-      12'b000101000100 : begin
-      end
-      12'b001101000011 : begin
-      end
-      12'b000100000101 : begin
-        if(execute_CsrPlugin_writeEnable)begin
-          CsrPlugin_stvec_base <= execute_CsrPlugin_writeData[31 : 2];
-          CsrPlugin_stvec_mode <= execute_CsrPlugin_writeData[1 : 0];
-        end
-      end
-      12'b111111000000 : begin
-      end
-      12'b001101000000 : begin
-        if(execute_CsrPlugin_writeEnable)begin
-          CsrPlugin_mscratch <= execute_CsrPlugin_writeData[31 : 0];
-        end
-      end
-      12'b001100000100 : begin
-      end
-      12'b111100010010 : begin
-      end
-      12'b000101000011 : begin
-        if(execute_CsrPlugin_writeEnable)begin
-          CsrPlugin_stval <= execute_CsrPlugin_writeData[31 : 0];
-        end
-      end
-      12'b110111000000 : begin
-      end
-      12'b000101000000 : begin
-        if(execute_CsrPlugin_writeEnable)begin
-          CsrPlugin_sscratch <= execute_CsrPlugin_writeData[31 : 0];
-        end
-      end
-      12'b001101000010 : begin
-      end
-      12'b000100000100 : begin
-      end
-      default : begin
-      end
-    endcase
-    iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO;
-    dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO;
-  end
-
-endmodule
-
diff --git a/sdc-plugin/tests/base_litex/base_litex.sdc b/sdc-plugin/tests/base_litex/base_litex.sdc
deleted file mode 100644
index 7ce1f0d..0000000
--- a/sdc-plugin/tests/base_litex/base_litex.sdc
+++ /dev/null
@@ -1,59 +0,0 @@
-create_clock -name clk100 -period 10.0 clk100
-
-# Input clock 100 MHz
-create_clock -period 10 clk100_ibuf -waveform {0.000 5.000}
-
-# Input clock BUFG 100 MHz
-create_clock -period 10 soc_clk100bg -waveform {0.000 5.000}
-
-# PLL feedback loop 100 MHz
-create_clock -period 10 soc_pll_fb -waveform {0.000 5.000}
-
-# PLL CLKOUT0 60 MHz
-create_clock -period 16.666 soc_pll_sys -waveform {0.000 8.333}
-
-# BUFG CLKOUT0 60 MHz
-create_clock -period 16.666 sys_clk -waveform {0.000 8.333}
-
-# PLL CLKOUT1 240 MHz
-create_clock -period 4.166 soc_pll_sys4x  -waveform {0.000 2.083}
-
-# BUFG CLKOUT1 240 MHz
-create_clock -period 4.166 sys4x_clk -waveform {0.000 2.083}
-
-# PLL CLKOUT2 240 MHz
-create_clock -period 4.166 soc_pll_sys4x_dqs -waveform {1.041 3.124}
-
-# BUFG CLKOUT2 240 MHz
-create_clock -period 4.166 sys4x_dqs_clk -waveform {1.041 3.124}
-
-# PLL CLKOUT3 200 MHz
-create_clock -period 5 soc_pll_clk200 -waveform {0.000 2.500}
-
-# BUFG CLKOUT3 200 MHz
-create_clock -period 5 clk200_clk -waveform {0.000 2.500}
-
-# PLL CLKOUT4 25 MHz
-create_clock -period 40 soc_pll_clk100 -waveform {0.000 20.000}
-
-# BUFG CLKOUT4 25 MHz
-create_clock -period 40 eth_ref_clk_obuf -waveform {0.000 20.000}
-
-set_clock_groups -exclusive -group {clk100 soc_clk100bg soc_pll_fb} -group {soc_pll_sys sys_clk} -group {soc_pll_sys4x soc_pll_sys4x_dqs} -group {soc_pll_clk200 clk200_clk}
-#create_clock -name sys_clk -period 16.666 [get_nets sys_clk]
-#
-#create_clock -name eth_rx_clk -period 40.0 [get_nets eth_rx_clk]
-#
-#create_clock -name eth_tx_clk -period 40.0 [get_nets eth_tx_clk]
-#
-#set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets sys_clk]] -group [get_clocks -include_generated_clocks -of [get_nets eth_rx_clk]] -asynchronous
-#
-#set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets sys_clk]] -group [get_clocks -include_generated_clocks -of [get_nets eth_tx_clk]] -asynchronous
-#
-#set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets eth_rx_clk]] -group [get_clocks -include_generated_clocks -of [get_nets eth_tx_clk]] -asynchronous
-#
-#set_false_path -quiet -to [get_nets -quiet -filter {mr_ff == TRUE}]
-#
-#set_false_path -quiet -to [get_pins -quiet -filter {REF_PIN_NAME == PRE} -of [get_cells -quiet -filter {ars_ff1 == TRUE || ars_ff2 == TRUE}]]
-#
-#set_max_delay 2 -quiet -from [get_pins -quiet -filter {REF_PIN_NAME == Q} -of [get_cells -quiet -filter {ars_ff1 == TRUE}]] -to [get_pins -quiet -filter {REF_PIN_NAME == D} -of [get_cells -quiet -filter {ars_ff2 == TRUE}]]
diff --git a/sdc-plugin/tests/base_litex/base_litex.tcl b/sdc-plugin/tests/base_litex/base_litex.tcl
deleted file mode 100644
index efee8f4..0000000
--- a/sdc-plugin/tests/base_litex/base_litex.tcl
+++ /dev/null
@@ -1,38 +0,0 @@
-yosys -import
-plugin -i xdc
-plugin -i sdc
-# Import the commands from the plugins to the tcl interpreter
-yosys -import
-
-read_verilog base_litex.v
-read_verilog VexRiscv_Linux.v
-read_verilog -specify -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v
-read_verilog -lib +/xilinx/cells_xtra.v
-hierarchy -check -auto-top
-
-# Start flow after library reading
-synth_xilinx -vpr -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check
-
-write_json $::env(OUT_JSON)
-return
-#Read the design timing constraints
-read_sdc $::env(INPUT_SDC_FILE)
-
-#Read the design constraints
-read_xdc -part_json $::env(PART_JSON) $::env(INPUT_XDC_FILE)
-
-# Map Xilinx tech library to 7-series VPR tech library.
-read_verilog -lib ../techmaps/cells_sim.v
-techmap -map  ../techmaps/cells_map.v
-
-# opt_expr -undriven makes sure all nets are driven, if only by the $undef
-# net.
-opt_expr -undriven
-opt_clean
-
-setundef -zero -params
-stat
-
-# Write the design in JSON format.
-write_json $::env(OUT_JSON)
-write_blif -attr -param -cname -conn $::env(OUT_EBLIF)
diff --git a/sdc-plugin/tests/base_litex/base_litex.v b/sdc-plugin/tests/base_litex/base_litex.v
deleted file mode 100644
index 1689eda..0000000
--- a/sdc-plugin/tests/base_litex/base_litex.v
+++ /dev/null
@@ -1,15844 +0,0 @@
-//--------------------------------------------------------------------------------
-// Auto-generated by Migen (d11565a) & LiteX (02bfda5e) on 2020-02-19 17:32:00
-//--------------------------------------------------------------------------------
-module top(
-	output reg serial_tx,
-	input serial_rx,
-	input clk100,
-	input cpu_reset,
-	output eth_ref_clk,
-	output [13:0] ddram_a,
-	output [2:0] ddram_ba,
-	output ddram_ras_n,
-	output ddram_cas_n,
-	output ddram_we_n,
-	output ddram_cs_n,
-	output [1:0] ddram_dm,
-	inout [15:0] ddram_dq,
-	output [1:0] ddram_dqs_p,
-	output [1:0] ddram_dqs_n,
-	output ddram_clk_p,
-	output ddram_clk_n,
-	output ddram_cke,
-	output ddram_odt,
-	output ddram_reset_n,
-	input eth_clocks_tx,
-	input eth_clocks_rx,
-	output eth_rst_n,
-	inout eth_mdio,
-	output eth_mdc,
-	input eth_rx_dv,
-	input eth_rx_er,
-	input [3:0] eth_rx_data,
-	output reg eth_tx_en,
-	output reg [3:0] eth_tx_data,
-	input eth_col,
-	input eth_crs,
-	output [3:0] led
-);
-
-wire [3:0] led;
-
-assign led[0] = idelayctl_rdy;
-assign led[1] = soc_pll_locked;
-assign led[2] = 0;
-assign led[3] = 0;
-
-// Manually inserted OBUFs
-wire [13:0] ddram_a;
-wire [ 2:0] ddram_ba;
-wire        ddram_ras_n;
-wire        ddram_cas_n;
-wire        ddram_we_n;
-wire        ddram_cs_n;
-wire [ 1:0] ddram_dm;
-wire        ddram_cke;
-wire        ddram_odt;
-wire        ddram_reset_n;
-
-// End manually inserted OBUFs
-
-wire eth_ref_clk_obuf;
-wire idelayctl_rdy;
-wire soc_netsoc_ctrl_reset_reset_re;
-wire soc_netsoc_ctrl_reset_reset_r;
-wire soc_netsoc_ctrl_reset_reset_we;
-reg soc_netsoc_ctrl_reset_reset_w = 1'd0;
-reg [31:0] soc_netsoc_ctrl_storage = 32'd305419896;
-reg soc_netsoc_ctrl_re = 1'd0;
-wire [31:0] soc_netsoc_ctrl_bus_errors_status;
-wire soc_netsoc_ctrl_bus_errors_we;
-wire soc_netsoc_ctrl_reset;
-wire soc_netsoc_ctrl_bus_error;
-reg [31:0] soc_netsoc_ctrl_bus_errors = 32'd0;
-wire soc_netsoc_cpu_reset;
-wire [29:0] soc_netsoc_cpu_ibus_adr;
-wire [31:0] soc_netsoc_cpu_ibus_dat_w;
-wire [31:0] soc_netsoc_cpu_ibus_dat_r;
-wire [3:0] soc_netsoc_cpu_ibus_sel;
-wire soc_netsoc_cpu_ibus_cyc;
-wire soc_netsoc_cpu_ibus_stb;
-wire soc_netsoc_cpu_ibus_ack;
-wire soc_netsoc_cpu_ibus_we;
-wire [2:0] soc_netsoc_cpu_ibus_cti;
-wire [1:0] soc_netsoc_cpu_ibus_bte;
-wire soc_netsoc_cpu_ibus_err;
-wire [29:0] soc_netsoc_cpu_dbus_adr;
-wire [31:0] soc_netsoc_cpu_dbus_dat_w;
-wire [31:0] soc_netsoc_cpu_dbus_dat_r;
-wire [3:0] soc_netsoc_cpu_dbus_sel;
-wire soc_netsoc_cpu_dbus_cyc;
-wire soc_netsoc_cpu_dbus_stb;
-wire soc_netsoc_cpu_dbus_ack;
-wire soc_netsoc_cpu_dbus_we;
-wire [2:0] soc_netsoc_cpu_dbus_cti;
-wire [1:0] soc_netsoc_cpu_dbus_bte;
-wire soc_netsoc_cpu_dbus_err;
-reg [31:0] soc_netsoc_cpu_interrupt0 = 32'd0;
-wire soc_netsoc_cpu_latch_re;
-wire soc_netsoc_cpu_latch_r;
-wire soc_netsoc_cpu_latch_we;
-reg soc_netsoc_cpu_latch_w = 1'd0;
-reg [63:0] soc_netsoc_cpu_time_status = 64'd0;
-wire soc_netsoc_cpu_time_we;
-reg [63:0] soc_netsoc_cpu_time_cmp_storage = 64'd18446744073709551615;
-reg soc_netsoc_cpu_time_cmp_re = 1'd0;
-wire soc_netsoc_cpu_interrupt1;
-reg [63:0] soc_netsoc_cpu_time = 64'd0;
-reg [63:0] soc_netsoc_cpu_time_cmp = 64'd18446744073709551615;
-wire [29:0] soc_netsoc_interface0_soc_bus_adr;
-wire [31:0] soc_netsoc_interface0_soc_bus_dat_w;
-wire [31:0] soc_netsoc_interface0_soc_bus_dat_r;
-wire [3:0] soc_netsoc_interface0_soc_bus_sel;
-wire soc_netsoc_interface0_soc_bus_cyc;
-wire soc_netsoc_interface0_soc_bus_stb;
-wire soc_netsoc_interface0_soc_bus_ack;
-wire soc_netsoc_interface0_soc_bus_we;
-wire [2:0] soc_netsoc_interface0_soc_bus_cti;
-wire [1:0] soc_netsoc_interface0_soc_bus_bte;
-wire soc_netsoc_interface0_soc_bus_err;
-wire [29:0] soc_netsoc_interface1_soc_bus_adr;
-wire [31:0] soc_netsoc_interface1_soc_bus_dat_w;
-wire [31:0] soc_netsoc_interface1_soc_bus_dat_r;
-wire [3:0] soc_netsoc_interface1_soc_bus_sel;
-wire soc_netsoc_interface1_soc_bus_cyc;
-wire soc_netsoc_interface1_soc_bus_stb;
-wire soc_netsoc_interface1_soc_bus_ack;
-wire soc_netsoc_interface1_soc_bus_we;
-wire [2:0] soc_netsoc_interface1_soc_bus_cti;
-wire [1:0] soc_netsoc_interface1_soc_bus_bte;
-wire soc_netsoc_interface1_soc_bus_err;
-wire [29:0] soc_netsoc_rom_bus_adr;
-wire [31:0] soc_netsoc_rom_bus_dat_w;
-wire [31:0] soc_netsoc_rom_bus_dat_r;
-wire [3:0] soc_netsoc_rom_bus_sel;
-wire soc_netsoc_rom_bus_cyc;
-wire soc_netsoc_rom_bus_stb;
-reg soc_netsoc_rom_bus_ack = 1'd0;
-wire soc_netsoc_rom_bus_we;
-wire [2:0] soc_netsoc_rom_bus_cti;
-wire [1:0] soc_netsoc_rom_bus_bte;
-reg soc_netsoc_rom_bus_err = 1'd0;
-wire [13:0] soc_netsoc_rom_adr;
-wire [31:0] soc_netsoc_rom_dat_r;
-wire [29:0] soc_netsoc_sram_bus_adr;
-wire [31:0] soc_netsoc_sram_bus_dat_w;
-wire [31:0] soc_netsoc_sram_bus_dat_r;
-wire [3:0] soc_netsoc_sram_bus_sel;
-wire soc_netsoc_sram_bus_cyc;
-wire soc_netsoc_sram_bus_stb;
-reg soc_netsoc_sram_bus_ack = 1'd0;
-wire soc_netsoc_sram_bus_we;
-wire [2:0] soc_netsoc_sram_bus_cti;
-wire [1:0] soc_netsoc_sram_bus_bte;
-reg soc_netsoc_sram_bus_err = 1'd0;
-wire [12:0] soc_netsoc_sram_adr;
-wire [31:0] soc_netsoc_sram_dat_r;
-reg [3:0] soc_netsoc_sram_we = 4'd0;
-wire [31:0] soc_netsoc_sram_dat_w;
-reg [31:0] soc_netsoc_uart_phy_storage = 32'd8246337;
-reg soc_netsoc_uart_phy_re = 1'd0;
-wire soc_netsoc_uart_phy_sink_valid;
-reg soc_netsoc_uart_phy_sink_ready = 1'd0;
-wire soc_netsoc_uart_phy_sink_first;
-wire soc_netsoc_uart_phy_sink_last;
-wire [7:0] soc_netsoc_uart_phy_sink_payload_data;
-reg soc_netsoc_uart_phy_uart_clk_txen = 1'd0;
-reg [31:0] soc_netsoc_uart_phy_phase_accumulator_tx = 32'd0;
-reg [7:0] soc_netsoc_uart_phy_tx_reg = 8'd0;
-reg [3:0] soc_netsoc_uart_phy_tx_bitcount = 4'd0;
-reg soc_netsoc_uart_phy_tx_busy = 1'd0;
-reg soc_netsoc_uart_phy_source_valid = 1'd0;
-wire soc_netsoc_uart_phy_source_ready;
-reg soc_netsoc_uart_phy_source_first = 1'd0;
-reg soc_netsoc_uart_phy_source_last = 1'd0;
-reg [7:0] soc_netsoc_uart_phy_source_payload_data = 8'd0;
-reg soc_netsoc_uart_phy_uart_clk_rxen = 1'd0;
-reg [31:0] soc_netsoc_uart_phy_phase_accumulator_rx = 32'd0;
-wire soc_netsoc_uart_phy_rx;
-reg soc_netsoc_uart_phy_rx_r = 1'd0;
-reg [7:0] soc_netsoc_uart_phy_rx_reg = 8'd0;
-reg [3:0] soc_netsoc_uart_phy_rx_bitcount = 4'd0;
-reg soc_netsoc_uart_phy_rx_busy = 1'd0;
-wire soc_netsoc_uart_rxtx_re;
-wire [7:0] soc_netsoc_uart_rxtx_r;
-wire soc_netsoc_uart_rxtx_we;
-wire [7:0] soc_netsoc_uart_rxtx_w;
-wire soc_netsoc_uart_txfull_status;
-wire soc_netsoc_uart_txfull_we;
-wire soc_netsoc_uart_rxempty_status;
-wire soc_netsoc_uart_rxempty_we;
-wire soc_netsoc_uart_irq;
-wire soc_netsoc_uart_tx_status;
-reg soc_netsoc_uart_tx_pending = 1'd0;
-wire soc_netsoc_uart_tx_trigger;
-reg soc_netsoc_uart_tx_clear = 1'd0;
-reg soc_netsoc_uart_tx_old_trigger = 1'd0;
-wire soc_netsoc_uart_rx_status;
-reg soc_netsoc_uart_rx_pending = 1'd0;
-wire soc_netsoc_uart_rx_trigger;
-reg soc_netsoc_uart_rx_clear = 1'd0;
-reg soc_netsoc_uart_rx_old_trigger = 1'd0;
-wire soc_netsoc_uart_eventmanager_status_re;
-wire [1:0] soc_netsoc_uart_eventmanager_status_r;
-wire soc_netsoc_uart_eventmanager_status_we;
-reg [1:0] soc_netsoc_uart_eventmanager_status_w = 2'd0;
-wire soc_netsoc_uart_eventmanager_pending_re;
-wire [1:0] soc_netsoc_uart_eventmanager_pending_r;
-wire soc_netsoc_uart_eventmanager_pending_we;
-reg [1:0] soc_netsoc_uart_eventmanager_pending_w = 2'd0;
-reg [1:0] soc_netsoc_uart_eventmanager_storage = 2'd0;
-reg soc_netsoc_uart_eventmanager_re = 1'd0;
-wire soc_netsoc_uart_tx_fifo_sink_valid;
-wire soc_netsoc_uart_tx_fifo_sink_ready;
-reg soc_netsoc_uart_tx_fifo_sink_first = 1'd0;
-reg soc_netsoc_uart_tx_fifo_sink_last = 1'd0;
-wire [7:0] soc_netsoc_uart_tx_fifo_sink_payload_data;
-wire soc_netsoc_uart_tx_fifo_source_valid;
-wire soc_netsoc_uart_tx_fifo_source_ready;
-wire soc_netsoc_uart_tx_fifo_source_first;
-wire soc_netsoc_uart_tx_fifo_source_last;
-wire [7:0] soc_netsoc_uart_tx_fifo_source_payload_data;
-wire soc_netsoc_uart_tx_fifo_re;
-reg soc_netsoc_uart_tx_fifo_readable = 1'd0;
-wire soc_netsoc_uart_tx_fifo_syncfifo_we;
-wire soc_netsoc_uart_tx_fifo_syncfifo_writable;
-wire soc_netsoc_uart_tx_fifo_syncfifo_re;
-wire soc_netsoc_uart_tx_fifo_syncfifo_readable;
-wire [9:0] soc_netsoc_uart_tx_fifo_syncfifo_din;
-wire [9:0] soc_netsoc_uart_tx_fifo_syncfifo_dout;
-reg [4:0] soc_netsoc_uart_tx_fifo_level0 = 5'd0;
-reg soc_netsoc_uart_tx_fifo_replace = 1'd0;
-reg [3:0] soc_netsoc_uart_tx_fifo_produce = 4'd0;
-reg [3:0] soc_netsoc_uart_tx_fifo_consume = 4'd0;
-reg [3:0] soc_netsoc_uart_tx_fifo_wrport_adr = 4'd0;
-wire [9:0] soc_netsoc_uart_tx_fifo_wrport_dat_r;
-wire soc_netsoc_uart_tx_fifo_wrport_we;
-wire [9:0] soc_netsoc_uart_tx_fifo_wrport_dat_w;
-wire soc_netsoc_uart_tx_fifo_do_read;
-wire [3:0] soc_netsoc_uart_tx_fifo_rdport_adr;
-wire [9:0] soc_netsoc_uart_tx_fifo_rdport_dat_r;
-wire soc_netsoc_uart_tx_fifo_rdport_re;
-wire [4:0] soc_netsoc_uart_tx_fifo_level1;
-wire [7:0] soc_netsoc_uart_tx_fifo_fifo_in_payload_data;
-wire soc_netsoc_uart_tx_fifo_fifo_in_first;
-wire soc_netsoc_uart_tx_fifo_fifo_in_last;
-wire [7:0] soc_netsoc_uart_tx_fifo_fifo_out_payload_data;
-wire soc_netsoc_uart_tx_fifo_fifo_out_first;
-wire soc_netsoc_uart_tx_fifo_fifo_out_last;
-wire soc_netsoc_uart_rx_fifo_sink_valid;
-wire soc_netsoc_uart_rx_fifo_sink_ready;
-wire soc_netsoc_uart_rx_fifo_sink_first;
-wire soc_netsoc_uart_rx_fifo_sink_last;
-wire [7:0] soc_netsoc_uart_rx_fifo_sink_payload_data;
-wire soc_netsoc_uart_rx_fifo_source_valid;
-wire soc_netsoc_uart_rx_fifo_source_ready;
-wire soc_netsoc_uart_rx_fifo_source_first;
-wire soc_netsoc_uart_rx_fifo_source_last;
-wire [7:0] soc_netsoc_uart_rx_fifo_source_payload_data;
-wire soc_netsoc_uart_rx_fifo_re;
-reg soc_netsoc_uart_rx_fifo_readable = 1'd0;
-wire soc_netsoc_uart_rx_fifo_syncfifo_we;
-wire soc_netsoc_uart_rx_fifo_syncfifo_writable;
-wire soc_netsoc_uart_rx_fifo_syncfifo_re;
-wire soc_netsoc_uart_rx_fifo_syncfifo_readable;
-wire [9:0] soc_netsoc_uart_rx_fifo_syncfifo_din;
-wire [9:0] soc_netsoc_uart_rx_fifo_syncfifo_dout;
-reg [4:0] soc_netsoc_uart_rx_fifo_level0 = 5'd0;
-reg soc_netsoc_uart_rx_fifo_replace = 1'd0;
-reg [3:0] soc_netsoc_uart_rx_fifo_produce = 4'd0;
-reg [3:0] soc_netsoc_uart_rx_fifo_consume = 4'd0;
-reg [3:0] soc_netsoc_uart_rx_fifo_wrport_adr = 4'd0;
-wire [9:0] soc_netsoc_uart_rx_fifo_wrport_dat_r;
-wire soc_netsoc_uart_rx_fifo_wrport_we;
-wire [9:0] soc_netsoc_uart_rx_fifo_wrport_dat_w;
-wire soc_netsoc_uart_rx_fifo_do_read;
-wire [3:0] soc_netsoc_uart_rx_fifo_rdport_adr;
-wire [9:0] soc_netsoc_uart_rx_fifo_rdport_dat_r;
-wire soc_netsoc_uart_rx_fifo_rdport_re;
-wire [4:0] soc_netsoc_uart_rx_fifo_level1;
-wire [7:0] soc_netsoc_uart_rx_fifo_fifo_in_payload_data;
-wire soc_netsoc_uart_rx_fifo_fifo_in_first;
-wire soc_netsoc_uart_rx_fifo_fifo_in_last;
-wire [7:0] soc_netsoc_uart_rx_fifo_fifo_out_payload_data;
-wire soc_netsoc_uart_rx_fifo_fifo_out_first;
-wire soc_netsoc_uart_rx_fifo_fifo_out_last;
-reg soc_netsoc_uart_reset = 1'd0;
-reg [31:0] soc_netsoc_timer0_load_storage = 32'd0;
-reg soc_netsoc_timer0_load_re = 1'd0;
-reg [31:0] soc_netsoc_timer0_reload_storage = 32'd0;
-reg soc_netsoc_timer0_reload_re = 1'd0;
-reg soc_netsoc_timer0_en_storage = 1'd0;
-reg soc_netsoc_timer0_en_re = 1'd0;
-reg soc_netsoc_timer0_update_value_storage = 1'd0;
-reg soc_netsoc_timer0_update_value_re = 1'd0;
-reg [31:0] soc_netsoc_timer0_value_status = 32'd0;
-wire soc_netsoc_timer0_value_we;
-wire soc_netsoc_timer0_irq;
-wire soc_netsoc_timer0_zero_status;
-reg soc_netsoc_timer0_zero_pending = 1'd0;
-wire soc_netsoc_timer0_zero_trigger;
-reg soc_netsoc_timer0_zero_clear = 1'd0;
-reg soc_netsoc_timer0_zero_old_trigger = 1'd0;
-wire soc_netsoc_timer0_eventmanager_status_re;
-wire soc_netsoc_timer0_eventmanager_status_r;
-wire soc_netsoc_timer0_eventmanager_status_we;
-wire soc_netsoc_timer0_eventmanager_status_w;
-wire soc_netsoc_timer0_eventmanager_pending_re;
-wire soc_netsoc_timer0_eventmanager_pending_r;
-wire soc_netsoc_timer0_eventmanager_pending_we;
-wire soc_netsoc_timer0_eventmanager_pending_w;
-reg soc_netsoc_timer0_eventmanager_storage = 1'd0;
-reg soc_netsoc_timer0_eventmanager_re = 1'd0;
-reg [31:0] soc_netsoc_timer0_value = 32'd0;
-reg [13:0] soc_netsoc_interface_adr = 14'd0;
-reg soc_netsoc_interface_we = 1'd0;
-wire [7:0] soc_netsoc_interface_dat_w;
-wire [7:0] soc_netsoc_interface_dat_r;
-wire [29:0] soc_netsoc_bus_wishbone_adr;
-wire [31:0] soc_netsoc_bus_wishbone_dat_w;
-wire [31:0] soc_netsoc_bus_wishbone_dat_r;
-wire [3:0] soc_netsoc_bus_wishbone_sel;
-wire soc_netsoc_bus_wishbone_cyc;
-wire soc_netsoc_bus_wishbone_stb;
-reg soc_netsoc_bus_wishbone_ack = 1'd0;
-wire soc_netsoc_bus_wishbone_we;
-wire [2:0] soc_netsoc_bus_wishbone_cti;
-wire [1:0] soc_netsoc_bus_wishbone_bte;
-reg soc_netsoc_bus_wishbone_err = 1'd0;
-wire [29:0] soc_netsoc_interface0_wb_sdram_adr;
-wire [31:0] soc_netsoc_interface0_wb_sdram_dat_w;
-reg [31:0] soc_netsoc_interface0_wb_sdram_dat_r = 32'd0;
-wire [3:0] soc_netsoc_interface0_wb_sdram_sel;
-wire soc_netsoc_interface0_wb_sdram_cyc;
-wire soc_netsoc_interface0_wb_sdram_stb;
-reg soc_netsoc_interface0_wb_sdram_ack = 1'd0;
-wire soc_netsoc_interface0_wb_sdram_we;
-wire [2:0] soc_netsoc_interface0_wb_sdram_cti;
-wire [1:0] soc_netsoc_interface0_wb_sdram_bte;
-reg soc_netsoc_interface0_wb_sdram_err = 1'd0;
-(* dont_touch = "true" *) wire sys_clk;
-wire sys_rst;
-wire sys4x_clk;
-wire sys4x_dqs_clk;
-wire clk200_clk;
-wire clk200_rst;
-wire soc_pll_locked;
-wire soc_pll_fb;
-reg [3:0] soc_reset_counter = 4'd15;
-reg soc_ic_reset = 1'd1;
-wire [29:0] soc_emulator_ram_bus_adr;
-wire [31:0] soc_emulator_ram_bus_dat_w;
-wire [31:0] soc_emulator_ram_bus_dat_r;
-wire [3:0] soc_emulator_ram_bus_sel;
-wire soc_emulator_ram_bus_cyc;
-wire soc_emulator_ram_bus_stb;
-reg soc_emulator_ram_bus_ack = 1'd0;
-wire soc_emulator_ram_bus_we;
-wire [2:0] soc_emulator_ram_bus_cti;
-wire [1:0] soc_emulator_ram_bus_bte;
-reg soc_emulator_ram_bus_err = 1'd0;
-wire [11:0] soc_emulator_ram_adr;
-wire [31:0] soc_emulator_ram_dat_r;
-reg [3:0] soc_emulator_ram_we = 4'd0;
-wire [31:0] soc_emulator_ram_dat_w;
-reg [4:0] soc_a7ddrphy_half_sys8x_taps_storage = 5'd8;
-reg soc_a7ddrphy_half_sys8x_taps_re = 1'd0;
-wire soc_a7ddrphy_cdly_rst_re;
-wire soc_a7ddrphy_cdly_rst_r;
-wire soc_a7ddrphy_cdly_rst_we;
-reg soc_a7ddrphy_cdly_rst_w = 1'd0;
-wire soc_a7ddrphy_cdly_inc_re;
-wire soc_a7ddrphy_cdly_inc_r;
-wire soc_a7ddrphy_cdly_inc_we;
-reg soc_a7ddrphy_cdly_inc_w = 1'd0;
-reg [1:0] soc_a7ddrphy_dly_sel_storage = 2'd0;
-reg soc_a7ddrphy_dly_sel_re = 1'd0;
-wire soc_a7ddrphy_rdly_dq_rst_re;
-wire soc_a7ddrphy_rdly_dq_rst_r;
-wire soc_a7ddrphy_rdly_dq_rst_we;
-reg soc_a7ddrphy_rdly_dq_rst_w = 1'd0;
-wire soc_a7ddrphy_rdly_dq_inc_re;
-wire soc_a7ddrphy_rdly_dq_inc_r;
-wire soc_a7ddrphy_rdly_dq_inc_we;
-reg soc_a7ddrphy_rdly_dq_inc_w = 1'd0;
-wire soc_a7ddrphy_rdly_dq_bitslip_rst_re;
-wire soc_a7ddrphy_rdly_dq_bitslip_rst_r;
-wire soc_a7ddrphy_rdly_dq_bitslip_rst_we;
-reg soc_a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
-wire soc_a7ddrphy_rdly_dq_bitslip_re;
-wire soc_a7ddrphy_rdly_dq_bitslip_r;
-wire soc_a7ddrphy_rdly_dq_bitslip_we;
-reg soc_a7ddrphy_rdly_dq_bitslip_w = 1'd0;
-wire [13:0] soc_a7ddrphy_dfi_p0_address;
-wire [2:0] soc_a7ddrphy_dfi_p0_bank;
-wire soc_a7ddrphy_dfi_p0_cas_n;
-wire soc_a7ddrphy_dfi_p0_cs_n;
-wire soc_a7ddrphy_dfi_p0_ras_n;
-wire soc_a7ddrphy_dfi_p0_we_n;
-wire soc_a7ddrphy_dfi_p0_cke;
-wire soc_a7ddrphy_dfi_p0_odt;
-wire soc_a7ddrphy_dfi_p0_reset_n;
-wire soc_a7ddrphy_dfi_p0_act_n;
-wire [31:0] soc_a7ddrphy_dfi_p0_wrdata;
-wire soc_a7ddrphy_dfi_p0_wrdata_en;
-wire [3:0] soc_a7ddrphy_dfi_p0_wrdata_mask;
-wire soc_a7ddrphy_dfi_p0_rddata_en;
-reg [31:0] soc_a7ddrphy_dfi_p0_rddata = 32'd0;
-reg soc_a7ddrphy_dfi_p0_rddata_valid = 1'd0;
-wire [13:0] soc_a7ddrphy_dfi_p1_address;
-wire [2:0] soc_a7ddrphy_dfi_p1_bank;
-wire soc_a7ddrphy_dfi_p1_cas_n;
-wire soc_a7ddrphy_dfi_p1_cs_n;
-wire soc_a7ddrphy_dfi_p1_ras_n;
-wire soc_a7ddrphy_dfi_p1_we_n;
-wire soc_a7ddrphy_dfi_p1_cke;
-wire soc_a7ddrphy_dfi_p1_odt;
-wire soc_a7ddrphy_dfi_p1_reset_n;
-wire soc_a7ddrphy_dfi_p1_act_n;
-wire [31:0] soc_a7ddrphy_dfi_p1_wrdata;
-wire soc_a7ddrphy_dfi_p1_wrdata_en;
-wire [3:0] soc_a7ddrphy_dfi_p1_wrdata_mask;
-wire soc_a7ddrphy_dfi_p1_rddata_en;
-reg [31:0] soc_a7ddrphy_dfi_p1_rddata = 32'd0;
-reg soc_a7ddrphy_dfi_p1_rddata_valid = 1'd0;
-wire [13:0] soc_a7ddrphy_dfi_p2_address;
-wire [2:0] soc_a7ddrphy_dfi_p2_bank;
-wire soc_a7ddrphy_dfi_p2_cas_n;
-wire soc_a7ddrphy_dfi_p2_cs_n;
-wire soc_a7ddrphy_dfi_p2_ras_n;
-wire soc_a7ddrphy_dfi_p2_we_n;
-wire soc_a7ddrphy_dfi_p2_cke;
-wire soc_a7ddrphy_dfi_p2_odt;
-wire soc_a7ddrphy_dfi_p2_reset_n;
-wire soc_a7ddrphy_dfi_p2_act_n;
-wire [31:0] soc_a7ddrphy_dfi_p2_wrdata;
-wire soc_a7ddrphy_dfi_p2_wrdata_en;
-wire [3:0] soc_a7ddrphy_dfi_p2_wrdata_mask;
-wire soc_a7ddrphy_dfi_p2_rddata_en;
-reg [31:0] soc_a7ddrphy_dfi_p2_rddata = 32'd0;
-reg soc_a7ddrphy_dfi_p2_rddata_valid = 1'd0;
-wire [13:0] soc_a7ddrphy_dfi_p3_address;
-wire [2:0] soc_a7ddrphy_dfi_p3_bank;
-wire soc_a7ddrphy_dfi_p3_cas_n;
-wire soc_a7ddrphy_dfi_p3_cs_n;
-wire soc_a7ddrphy_dfi_p3_ras_n;
-wire soc_a7ddrphy_dfi_p3_we_n;
-wire soc_a7ddrphy_dfi_p3_cke;
-wire soc_a7ddrphy_dfi_p3_odt;
-wire soc_a7ddrphy_dfi_p3_reset_n;
-wire soc_a7ddrphy_dfi_p3_act_n;
-wire [31:0] soc_a7ddrphy_dfi_p3_wrdata;
-wire soc_a7ddrphy_dfi_p3_wrdata_en;
-wire [3:0] soc_a7ddrphy_dfi_p3_wrdata_mask;
-wire soc_a7ddrphy_dfi_p3_rddata_en;
-reg [31:0] soc_a7ddrphy_dfi_p3_rddata = 32'd0;
-reg soc_a7ddrphy_dfi_p3_rddata_valid = 1'd0;
-wire soc_a7ddrphy_sd_clk_se_nodelay;
-reg soc_a7ddrphy_oe_dqs = 1'd0;
-wire soc_a7ddrphy_dqs_preamble;
-wire soc_a7ddrphy_dqs_postamble;
-reg [7:0] soc_a7ddrphy_dqs_serdes_pattern = 8'd85;
-wire soc_a7ddrphy_dqs_nodelay0;
-wire soc_a7ddrphy_dqs_t0;
-wire soc_a7ddrphy0;
-wire soc_a7ddrphy_dqs_nodelay1;
-wire soc_a7ddrphy_dqs_t1;
-wire soc_a7ddrphy1;
-reg soc_a7ddrphy_oe_dq = 1'd0;
-wire soc_a7ddrphy_dq_o_nodelay0;
-wire soc_a7ddrphy_dq_i_nodelay0;
-wire soc_a7ddrphy_dq_i_delayed0;
-wire soc_a7ddrphy_dq_t0;
-wire [7:0] soc_a7ddrphy_dq_i_data0;
-wire [7:0] soc_a7ddrphy_bitslip0_i;
-reg [7:0] soc_a7ddrphy_bitslip0_o = 8'd0;
-reg [2:0] soc_a7ddrphy_bitslip0_value = 3'd0;
-reg [15:0] soc_a7ddrphy_bitslip0_r = 16'd0;
-wire soc_a7ddrphy_dq_o_nodelay1;
-wire soc_a7ddrphy_dq_i_nodelay1;
-wire soc_a7ddrphy_dq_i_delayed1;
-wire soc_a7ddrphy_dq_t1;
-wire [7:0] soc_a7ddrphy_dq_i_data1;
-wire [7:0] soc_a7ddrphy_bitslip1_i;
-reg [7:0] soc_a7ddrphy_bitslip1_o = 8'd0;
-reg [2:0] soc_a7ddrphy_bitslip1_value = 3'd0;
-reg [15:0] soc_a7ddrphy_bitslip1_r = 16'd0;
-wire soc_a7ddrphy_dq_o_nodelay2;
-wire soc_a7ddrphy_dq_i_nodelay2;
-wire soc_a7ddrphy_dq_i_delayed2;
-wire soc_a7ddrphy_dq_t2;
-wire [7:0] soc_a7ddrphy_dq_i_data2;
-wire [7:0] soc_a7ddrphy_bitslip2_i;
-reg [7:0] soc_a7ddrphy_bitslip2_o = 8'd0;
-reg [2:0] soc_a7ddrphy_bitslip2_value = 3'd0;
-reg [15:0] soc_a7ddrphy_bitslip2_r = 16'd0;
-wire soc_a7ddrphy_dq_o_nodelay3;
-wire soc_a7ddrphy_dq_i_nodelay3;
-wire soc_a7ddrphy_dq_i_delayed3;
-wire soc_a7ddrphy_dq_t3;
-wire [7:0] soc_a7ddrphy_dq_i_data3;
-wire [7:0] soc_a7ddrphy_bitslip3_i;
-reg [7:0] soc_a7ddrphy_bitslip3_o = 8'd0;
-reg [2:0] soc_a7ddrphy_bitslip3_value = 3'd0;
-reg [15:0] soc_a7ddrphy_bitslip3_r = 16'd0;
-wire soc_a7ddrphy_dq_o_nodelay4;
-wire soc_a7ddrphy_dq_i_nodelay4;
-wire soc_a7ddrphy_dq_i_delayed4;
-wire soc_a7ddrphy_dq_t4;
-wire [7:0] soc_a7ddrphy_dq_i_data4;
-wire [7:0] soc_a7ddrphy_bitslip4_i;
-reg [7:0] soc_a7ddrphy_bitslip4_o = 8'd0;
-reg [2:0] soc_a7ddrphy_bitslip4_value = 3'd0;
-reg [15:0] soc_a7ddrphy_bitslip4_r = 16'd0;
-wire soc_a7ddrphy_dq_o_nodelay5;
-wire soc_a7ddrphy_dq_i_nodelay5;
-wire soc_a7ddrphy_dq_i_delayed5;
-wire soc_a7ddrphy_dq_t5;
-wire [7:0] soc_a7ddrphy_dq_i_data5;
-wire [7:0] soc_a7ddrphy_bitslip5_i;
-reg [7:0] soc_a7ddrphy_bitslip5_o = 8'd0;
-reg [2:0] soc_a7ddrphy_bitslip5_value = 3'd0;
-reg [15:0] soc_a7ddrphy_bitslip5_r = 16'd0;
-wire soc_a7ddrphy_dq_o_nodelay6;
-wire soc_a7ddrphy_dq_i_nodelay6;
-wire soc_a7ddrphy_dq_i_delayed6;
-wire soc_a7ddrphy_dq_t6;
-wire [7:0] soc_a7ddrphy_dq_i_data6;
-wire [7:0] soc_a7ddrphy_bitslip6_i;
-reg [7:0] soc_a7ddrphy_bitslip6_o = 8'd0;
-reg [2:0] soc_a7ddrphy_bitslip6_value = 3'd0;
-reg [15:0] soc_a7ddrphy_bitslip6_r = 16'd0;
-wire soc_a7ddrphy_dq_o_nodelay7;
-wire soc_a7ddrphy_dq_i_nodelay7;
-wire soc_a7ddrphy_dq_i_delayed7;
-wire soc_a7ddrphy_dq_t7;
-wire [7:0] soc_a7ddrphy_dq_i_data7;
-wire [7:0] soc_a7ddrphy_bitslip7_i;
-reg [7:0] soc_a7ddrphy_bitslip7_o = 8'd0;
-reg [2:0] soc_a7ddrphy_bitslip7_value = 3'd0;
-reg [15:0] soc_a7ddrphy_bitslip7_r = 16'd0;
-wire soc_a7ddrphy_dq_o_nodelay8;
-wire soc_a7ddrphy_dq_i_nodelay8;
-wire soc_a7ddrphy_dq_i_delayed8;
-wire soc_a7ddrphy_dq_t8;
-wire [7:0] soc_a7ddrphy_dq_i_data8;
-wire [7:0] soc_a7ddrphy_bitslip8_i;
-reg [7:0] soc_a7ddrphy_bitslip8_o = 8'd0;
-reg [2:0] soc_a7ddrphy_bitslip8_value = 3'd0;
-reg [15:0] soc_a7ddrphy_bitslip8_r = 16'd0;
-wire soc_a7ddrphy_dq_o_nodelay9;
-wire soc_a7ddrphy_dq_i_nodelay9;
-wire soc_a7ddrphy_dq_i_delayed9;
-wire soc_a7ddrphy_dq_t9;
-wire [7:0] soc_a7ddrphy_dq_i_data9;
-wire [7:0] soc_a7ddrphy_bitslip9_i;
-reg [7:0] soc_a7ddrphy_bitslip9_o = 8'd0;
-reg [2:0] soc_a7ddrphy_bitslip9_value = 3'd0;
-reg [15:0] soc_a7ddrphy_bitslip9_r = 16'd0;
-wire soc_a7ddrphy_dq_o_nodelay10;
-wire soc_a7ddrphy_dq_i_nodelay10;
-wire soc_a7ddrphy_dq_i_delayed10;
-wire soc_a7ddrphy_dq_t10;
-wire [7:0] soc_a7ddrphy_dq_i_data10;
-wire [7:0] soc_a7ddrphy_bitslip10_i;
-reg [7:0] soc_a7ddrphy_bitslip10_o = 8'd0;
-reg [2:0] soc_a7ddrphy_bitslip10_value = 3'd0;
-reg [15:0] soc_a7ddrphy_bitslip10_r = 16'd0;
-wire soc_a7ddrphy_dq_o_nodelay11;
-wire soc_a7ddrphy_dq_i_nodelay11;
-wire soc_a7ddrphy_dq_i_delayed11;
-wire soc_a7ddrphy_dq_t11;
-wire [7:0] soc_a7ddrphy_dq_i_data11;
-wire [7:0] soc_a7ddrphy_bitslip11_i;
-reg [7:0] soc_a7ddrphy_bitslip11_o = 8'd0;
-reg [2:0] soc_a7ddrphy_bitslip11_value = 3'd0;
-reg [15:0] soc_a7ddrphy_bitslip11_r = 16'd0;
-wire soc_a7ddrphy_dq_o_nodelay12;
-wire soc_a7ddrphy_dq_i_nodelay12;
-wire soc_a7ddrphy_dq_i_delayed12;
-wire soc_a7ddrphy_dq_t12;
-wire [7:0] soc_a7ddrphy_dq_i_data12;
-wire [7:0] soc_a7ddrphy_bitslip12_i;
-reg [7:0] soc_a7ddrphy_bitslip12_o = 8'd0;
-reg [2:0] soc_a7ddrphy_bitslip12_value = 3'd0;
-reg [15:0] soc_a7ddrphy_bitslip12_r = 16'd0;
-wire soc_a7ddrphy_dq_o_nodelay13;
-wire soc_a7ddrphy_dq_i_nodelay13;
-wire soc_a7ddrphy_dq_i_delayed13;
-wire soc_a7ddrphy_dq_t13;
-wire [7:0] soc_a7ddrphy_dq_i_data13;
-wire [7:0] soc_a7ddrphy_bitslip13_i;
-reg [7:0] soc_a7ddrphy_bitslip13_o = 8'd0;
-reg [2:0] soc_a7ddrphy_bitslip13_value = 3'd0;
-reg [15:0] soc_a7ddrphy_bitslip13_r = 16'd0;
-wire soc_a7ddrphy_dq_o_nodelay14;
-wire soc_a7ddrphy_dq_i_nodelay14;
-wire soc_a7ddrphy_dq_i_delayed14;
-wire soc_a7ddrphy_dq_t14;
-wire [7:0] soc_a7ddrphy_dq_i_data14;
-wire [7:0] soc_a7ddrphy_bitslip14_i;
-reg [7:0] soc_a7ddrphy_bitslip14_o = 8'd0;
-reg [2:0] soc_a7ddrphy_bitslip14_value = 3'd0;
-reg [15:0] soc_a7ddrphy_bitslip14_r = 16'd0;
-wire soc_a7ddrphy_dq_o_nodelay15;
-wire soc_a7ddrphy_dq_i_nodelay15;
-wire soc_a7ddrphy_dq_i_delayed15;
-wire soc_a7ddrphy_dq_t15;
-wire [7:0] soc_a7ddrphy_dq_i_data15;
-wire [7:0] soc_a7ddrphy_bitslip15_i;
-reg [7:0] soc_a7ddrphy_bitslip15_o = 8'd0;
-reg [2:0] soc_a7ddrphy_bitslip15_value = 3'd0;
-reg [15:0] soc_a7ddrphy_bitslip15_r = 16'd0;
-reg soc_a7ddrphy_n_rddata_en0 = 1'd0;
-reg soc_a7ddrphy_n_rddata_en1 = 1'd0;
-reg soc_a7ddrphy_n_rddata_en2 = 1'd0;
-reg soc_a7ddrphy_n_rddata_en3 = 1'd0;
-reg soc_a7ddrphy_n_rddata_en4 = 1'd0;
-reg soc_a7ddrphy_n_rddata_en5 = 1'd0;
-reg soc_a7ddrphy_n_rddata_en6 = 1'd0;
-reg soc_a7ddrphy_n_rddata_en7 = 1'd0;
-wire soc_a7ddrphy_oe;
-reg [3:0] soc_a7ddrphy_last_wrdata_en = 4'd0;
-wire [13:0] soc_netsoc_sdram_inti_p0_address;
-wire [2:0] soc_netsoc_sdram_inti_p0_bank;
-reg soc_netsoc_sdram_inti_p0_cas_n = 1'd1;
-reg soc_netsoc_sdram_inti_p0_cs_n = 1'd1;
-reg soc_netsoc_sdram_inti_p0_ras_n = 1'd1;
-reg soc_netsoc_sdram_inti_p0_we_n = 1'd1;
-wire soc_netsoc_sdram_inti_p0_cke;
-wire soc_netsoc_sdram_inti_p0_odt;
-wire soc_netsoc_sdram_inti_p0_reset_n;
-reg soc_netsoc_sdram_inti_p0_act_n = 1'd1;
-wire [31:0] soc_netsoc_sdram_inti_p0_wrdata;
-wire soc_netsoc_sdram_inti_p0_wrdata_en;
-wire [3:0] soc_netsoc_sdram_inti_p0_wrdata_mask;
-wire soc_netsoc_sdram_inti_p0_rddata_en;
-reg [31:0] soc_netsoc_sdram_inti_p0_rddata = 32'd0;
-reg soc_netsoc_sdram_inti_p0_rddata_valid = 1'd0;
-wire [13:0] soc_netsoc_sdram_inti_p1_address;
-wire [2:0] soc_netsoc_sdram_inti_p1_bank;
-reg soc_netsoc_sdram_inti_p1_cas_n = 1'd1;
-reg soc_netsoc_sdram_inti_p1_cs_n = 1'd1;
-reg soc_netsoc_sdram_inti_p1_ras_n = 1'd1;
-reg soc_netsoc_sdram_inti_p1_we_n = 1'd1;
-wire soc_netsoc_sdram_inti_p1_cke;
-wire soc_netsoc_sdram_inti_p1_odt;
-wire soc_netsoc_sdram_inti_p1_reset_n;
-reg soc_netsoc_sdram_inti_p1_act_n = 1'd1;
-wire [31:0] soc_netsoc_sdram_inti_p1_wrdata;
-wire soc_netsoc_sdram_inti_p1_wrdata_en;
-wire [3:0] soc_netsoc_sdram_inti_p1_wrdata_mask;
-wire soc_netsoc_sdram_inti_p1_rddata_en;
-reg [31:0] soc_netsoc_sdram_inti_p1_rddata = 32'd0;
-reg soc_netsoc_sdram_inti_p1_rddata_valid = 1'd0;
-wire [13:0] soc_netsoc_sdram_inti_p2_address;
-wire [2:0] soc_netsoc_sdram_inti_p2_bank;
-reg soc_netsoc_sdram_inti_p2_cas_n = 1'd1;
-reg soc_netsoc_sdram_inti_p2_cs_n = 1'd1;
-reg soc_netsoc_sdram_inti_p2_ras_n = 1'd1;
-reg soc_netsoc_sdram_inti_p2_we_n = 1'd1;
-wire soc_netsoc_sdram_inti_p2_cke;
-wire soc_netsoc_sdram_inti_p2_odt;
-wire soc_netsoc_sdram_inti_p2_reset_n;
-reg soc_netsoc_sdram_inti_p2_act_n = 1'd1;
-wire [31:0] soc_netsoc_sdram_inti_p2_wrdata;
-wire soc_netsoc_sdram_inti_p2_wrdata_en;
-wire [3:0] soc_netsoc_sdram_inti_p2_wrdata_mask;
-wire soc_netsoc_sdram_inti_p2_rddata_en;
-reg [31:0] soc_netsoc_sdram_inti_p2_rddata = 32'd0;
-reg soc_netsoc_sdram_inti_p2_rddata_valid = 1'd0;
-wire [13:0] soc_netsoc_sdram_inti_p3_address;
-wire [2:0] soc_netsoc_sdram_inti_p3_bank;
-reg soc_netsoc_sdram_inti_p3_cas_n = 1'd1;
-reg soc_netsoc_sdram_inti_p3_cs_n = 1'd1;
-reg soc_netsoc_sdram_inti_p3_ras_n = 1'd1;
-reg soc_netsoc_sdram_inti_p3_we_n = 1'd1;
-wire soc_netsoc_sdram_inti_p3_cke;
-wire soc_netsoc_sdram_inti_p3_odt;
-wire soc_netsoc_sdram_inti_p3_reset_n;
-reg soc_netsoc_sdram_inti_p3_act_n = 1'd1;
-wire [31:0] soc_netsoc_sdram_inti_p3_wrdata;
-wire soc_netsoc_sdram_inti_p3_wrdata_en;
-wire [3:0] soc_netsoc_sdram_inti_p3_wrdata_mask;
-wire soc_netsoc_sdram_inti_p3_rddata_en;
-reg [31:0] soc_netsoc_sdram_inti_p3_rddata = 32'd0;
-reg soc_netsoc_sdram_inti_p3_rddata_valid = 1'd0;
-wire [13:0] soc_netsoc_sdram_slave_p0_address;
-wire [2:0] soc_netsoc_sdram_slave_p0_bank;
-wire soc_netsoc_sdram_slave_p0_cas_n;
-wire soc_netsoc_sdram_slave_p0_cs_n;
-wire soc_netsoc_sdram_slave_p0_ras_n;
-wire soc_netsoc_sdram_slave_p0_we_n;
-wire soc_netsoc_sdram_slave_p0_cke;
-wire soc_netsoc_sdram_slave_p0_odt;
-wire soc_netsoc_sdram_slave_p0_reset_n;
-wire soc_netsoc_sdram_slave_p0_act_n;
-wire [31:0] soc_netsoc_sdram_slave_p0_wrdata;
-wire soc_netsoc_sdram_slave_p0_wrdata_en;
-wire [3:0] soc_netsoc_sdram_slave_p0_wrdata_mask;
-wire soc_netsoc_sdram_slave_p0_rddata_en;
-reg [31:0] soc_netsoc_sdram_slave_p0_rddata = 32'd0;
-reg soc_netsoc_sdram_slave_p0_rddata_valid = 1'd0;
-wire [13:0] soc_netsoc_sdram_slave_p1_address;
-wire [2:0] soc_netsoc_sdram_slave_p1_bank;
-wire soc_netsoc_sdram_slave_p1_cas_n;
-wire soc_netsoc_sdram_slave_p1_cs_n;
-wire soc_netsoc_sdram_slave_p1_ras_n;
-wire soc_netsoc_sdram_slave_p1_we_n;
-wire soc_netsoc_sdram_slave_p1_cke;
-wire soc_netsoc_sdram_slave_p1_odt;
-wire soc_netsoc_sdram_slave_p1_reset_n;
-wire soc_netsoc_sdram_slave_p1_act_n;
-wire [31:0] soc_netsoc_sdram_slave_p1_wrdata;
-wire soc_netsoc_sdram_slave_p1_wrdata_en;
-wire [3:0] soc_netsoc_sdram_slave_p1_wrdata_mask;
-wire soc_netsoc_sdram_slave_p1_rddata_en;
-reg [31:0] soc_netsoc_sdram_slave_p1_rddata = 32'd0;
-reg soc_netsoc_sdram_slave_p1_rddata_valid = 1'd0;
-wire [13:0] soc_netsoc_sdram_slave_p2_address;
-wire [2:0] soc_netsoc_sdram_slave_p2_bank;
-wire soc_netsoc_sdram_slave_p2_cas_n;
-wire soc_netsoc_sdram_slave_p2_cs_n;
-wire soc_netsoc_sdram_slave_p2_ras_n;
-wire soc_netsoc_sdram_slave_p2_we_n;
-wire soc_netsoc_sdram_slave_p2_cke;
-wire soc_netsoc_sdram_slave_p2_odt;
-wire soc_netsoc_sdram_slave_p2_reset_n;
-wire soc_netsoc_sdram_slave_p2_act_n;
-wire [31:0] soc_netsoc_sdram_slave_p2_wrdata;
-wire soc_netsoc_sdram_slave_p2_wrdata_en;
-wire [3:0] soc_netsoc_sdram_slave_p2_wrdata_mask;
-wire soc_netsoc_sdram_slave_p2_rddata_en;
-reg [31:0] soc_netsoc_sdram_slave_p2_rddata = 32'd0;
-reg soc_netsoc_sdram_slave_p2_rddata_valid = 1'd0;
-wire [13:0] soc_netsoc_sdram_slave_p3_address;
-wire [2:0] soc_netsoc_sdram_slave_p3_bank;
-wire soc_netsoc_sdram_slave_p3_cas_n;
-wire soc_netsoc_sdram_slave_p3_cs_n;
-wire soc_netsoc_sdram_slave_p3_ras_n;
-wire soc_netsoc_sdram_slave_p3_we_n;
-wire soc_netsoc_sdram_slave_p3_cke;
-wire soc_netsoc_sdram_slave_p3_odt;
-wire soc_netsoc_sdram_slave_p3_reset_n;
-wire soc_netsoc_sdram_slave_p3_act_n;
-wire [31:0] soc_netsoc_sdram_slave_p3_wrdata;
-wire soc_netsoc_sdram_slave_p3_wrdata_en;
-wire [3:0] soc_netsoc_sdram_slave_p3_wrdata_mask;
-wire soc_netsoc_sdram_slave_p3_rddata_en;
-reg [31:0] soc_netsoc_sdram_slave_p3_rddata = 32'd0;
-reg soc_netsoc_sdram_slave_p3_rddata_valid = 1'd0;
-reg [13:0] soc_netsoc_sdram_master_p0_address = 14'd0;
-reg [2:0] soc_netsoc_sdram_master_p0_bank = 3'd0;
-reg soc_netsoc_sdram_master_p0_cas_n = 1'd1;
-reg soc_netsoc_sdram_master_p0_cs_n = 1'd1;
-reg soc_netsoc_sdram_master_p0_ras_n = 1'd1;
-reg soc_netsoc_sdram_master_p0_we_n = 1'd1;
-reg soc_netsoc_sdram_master_p0_cke = 1'd0;
-reg soc_netsoc_sdram_master_p0_odt = 1'd0;
-reg soc_netsoc_sdram_master_p0_reset_n = 1'd0;
-reg soc_netsoc_sdram_master_p0_act_n = 1'd1;
-reg [31:0] soc_netsoc_sdram_master_p0_wrdata = 32'd0;
-reg soc_netsoc_sdram_master_p0_wrdata_en = 1'd0;
-reg [3:0] soc_netsoc_sdram_master_p0_wrdata_mask = 4'd0;
-reg soc_netsoc_sdram_master_p0_rddata_en = 1'd0;
-wire [31:0] soc_netsoc_sdram_master_p0_rddata;
-wire soc_netsoc_sdram_master_p0_rddata_valid;
-reg [13:0] soc_netsoc_sdram_master_p1_address = 14'd0;
-reg [2:0] soc_netsoc_sdram_master_p1_bank = 3'd0;
-reg soc_netsoc_sdram_master_p1_cas_n = 1'd1;
-reg soc_netsoc_sdram_master_p1_cs_n = 1'd1;
-reg soc_netsoc_sdram_master_p1_ras_n = 1'd1;
-reg soc_netsoc_sdram_master_p1_we_n = 1'd1;
-reg soc_netsoc_sdram_master_p1_cke = 1'd0;
-reg soc_netsoc_sdram_master_p1_odt = 1'd0;
-reg soc_netsoc_sdram_master_p1_reset_n = 1'd0;
-reg soc_netsoc_sdram_master_p1_act_n = 1'd1;
-reg [31:0] soc_netsoc_sdram_master_p1_wrdata = 32'd0;
-reg soc_netsoc_sdram_master_p1_wrdata_en = 1'd0;
-reg [3:0] soc_netsoc_sdram_master_p1_wrdata_mask = 4'd0;
-reg soc_netsoc_sdram_master_p1_rddata_en = 1'd0;
-wire [31:0] soc_netsoc_sdram_master_p1_rddata;
-wire soc_netsoc_sdram_master_p1_rddata_valid;
-reg [13:0] soc_netsoc_sdram_master_p2_address = 14'd0;
-reg [2:0] soc_netsoc_sdram_master_p2_bank = 3'd0;
-reg soc_netsoc_sdram_master_p2_cas_n = 1'd1;
-reg soc_netsoc_sdram_master_p2_cs_n = 1'd1;
-reg soc_netsoc_sdram_master_p2_ras_n = 1'd1;
-reg soc_netsoc_sdram_master_p2_we_n = 1'd1;
-reg soc_netsoc_sdram_master_p2_cke = 1'd0;
-reg soc_netsoc_sdram_master_p2_odt = 1'd0;
-reg soc_netsoc_sdram_master_p2_reset_n = 1'd0;
-reg soc_netsoc_sdram_master_p2_act_n = 1'd1;
-reg [31:0] soc_netsoc_sdram_master_p2_wrdata = 32'd0;
-reg soc_netsoc_sdram_master_p2_wrdata_en = 1'd0;
-reg [3:0] soc_netsoc_sdram_master_p2_wrdata_mask = 4'd0;
-reg soc_netsoc_sdram_master_p2_rddata_en = 1'd0;
-wire [31:0] soc_netsoc_sdram_master_p2_rddata;
-wire soc_netsoc_sdram_master_p2_rddata_valid;
-reg [13:0] soc_netsoc_sdram_master_p3_address = 14'd0;
-reg [2:0] soc_netsoc_sdram_master_p3_bank = 3'd0;
-reg soc_netsoc_sdram_master_p3_cas_n = 1'd1;
-reg soc_netsoc_sdram_master_p3_cs_n = 1'd1;
-reg soc_netsoc_sdram_master_p3_ras_n = 1'd1;
-reg soc_netsoc_sdram_master_p3_we_n = 1'd1;
-reg soc_netsoc_sdram_master_p3_cke = 1'd0;
-reg soc_netsoc_sdram_master_p3_odt = 1'd0;
-reg soc_netsoc_sdram_master_p3_reset_n = 1'd0;
-reg soc_netsoc_sdram_master_p3_act_n = 1'd1;
-reg [31:0] soc_netsoc_sdram_master_p3_wrdata = 32'd0;
-reg soc_netsoc_sdram_master_p3_wrdata_en = 1'd0;
-reg [3:0] soc_netsoc_sdram_master_p3_wrdata_mask = 4'd0;
-reg soc_netsoc_sdram_master_p3_rddata_en = 1'd0;
-wire [31:0] soc_netsoc_sdram_master_p3_rddata;
-wire soc_netsoc_sdram_master_p3_rddata_valid;
-reg [3:0] soc_netsoc_sdram_storage = 4'd0;
-reg soc_netsoc_sdram_re = 1'd0;
-reg [5:0] soc_netsoc_sdram_phaseinjector0_command_storage = 6'd0;
-reg soc_netsoc_sdram_phaseinjector0_command_re = 1'd0;
-wire soc_netsoc_sdram_phaseinjector0_command_issue_re;
-wire soc_netsoc_sdram_phaseinjector0_command_issue_r;
-wire soc_netsoc_sdram_phaseinjector0_command_issue_we;
-reg soc_netsoc_sdram_phaseinjector0_command_issue_w = 1'd0;
-reg [13:0] soc_netsoc_sdram_phaseinjector0_address_storage = 14'd0;
-reg soc_netsoc_sdram_phaseinjector0_address_re = 1'd0;
-reg [2:0] soc_netsoc_sdram_phaseinjector0_baddress_storage = 3'd0;
-reg soc_netsoc_sdram_phaseinjector0_baddress_re = 1'd0;
-reg [31:0] soc_netsoc_sdram_phaseinjector0_wrdata_storage = 32'd0;
-reg soc_netsoc_sdram_phaseinjector0_wrdata_re = 1'd0;
-reg [31:0] soc_netsoc_sdram_phaseinjector0_status = 32'd0;
-wire soc_netsoc_sdram_phaseinjector0_we;
-reg [5:0] soc_netsoc_sdram_phaseinjector1_command_storage = 6'd0;
-reg soc_netsoc_sdram_phaseinjector1_command_re = 1'd0;
-wire soc_netsoc_sdram_phaseinjector1_command_issue_re;
-wire soc_netsoc_sdram_phaseinjector1_command_issue_r;
-wire soc_netsoc_sdram_phaseinjector1_command_issue_we;
-reg soc_netsoc_sdram_phaseinjector1_command_issue_w = 1'd0;
-reg [13:0] soc_netsoc_sdram_phaseinjector1_address_storage = 14'd0;
-reg soc_netsoc_sdram_phaseinjector1_address_re = 1'd0;
-reg [2:0] soc_netsoc_sdram_phaseinjector1_baddress_storage = 3'd0;
-reg soc_netsoc_sdram_phaseinjector1_baddress_re = 1'd0;
-reg [31:0] soc_netsoc_sdram_phaseinjector1_wrdata_storage = 32'd0;
-reg soc_netsoc_sdram_phaseinjector1_wrdata_re = 1'd0;
-reg [31:0] soc_netsoc_sdram_phaseinjector1_status = 32'd0;
-wire soc_netsoc_sdram_phaseinjector1_we;
-reg [5:0] soc_netsoc_sdram_phaseinjector2_command_storage = 6'd0;
-reg soc_netsoc_sdram_phaseinjector2_command_re = 1'd0;
-wire soc_netsoc_sdram_phaseinjector2_command_issue_re;
-wire soc_netsoc_sdram_phaseinjector2_command_issue_r;
-wire soc_netsoc_sdram_phaseinjector2_command_issue_we;
-reg soc_netsoc_sdram_phaseinjector2_command_issue_w = 1'd0;
-reg [13:0] soc_netsoc_sdram_phaseinjector2_address_storage = 14'd0;
-reg soc_netsoc_sdram_phaseinjector2_address_re = 1'd0;
-reg [2:0] soc_netsoc_sdram_phaseinjector2_baddress_storage = 3'd0;
-reg soc_netsoc_sdram_phaseinjector2_baddress_re = 1'd0;
-reg [31:0] soc_netsoc_sdram_phaseinjector2_wrdata_storage = 32'd0;
-reg soc_netsoc_sdram_phaseinjector2_wrdata_re = 1'd0;
-reg [31:0] soc_netsoc_sdram_phaseinjector2_status = 32'd0;
-wire soc_netsoc_sdram_phaseinjector2_we;
-reg [5:0] soc_netsoc_sdram_phaseinjector3_command_storage = 6'd0;
-reg soc_netsoc_sdram_phaseinjector3_command_re = 1'd0;
-wire soc_netsoc_sdram_phaseinjector3_command_issue_re;
-wire soc_netsoc_sdram_phaseinjector3_command_issue_r;
-wire soc_netsoc_sdram_phaseinjector3_command_issue_we;
-reg soc_netsoc_sdram_phaseinjector3_command_issue_w = 1'd0;
-reg [13:0] soc_netsoc_sdram_phaseinjector3_address_storage = 14'd0;
-reg soc_netsoc_sdram_phaseinjector3_address_re = 1'd0;
-reg [2:0] soc_netsoc_sdram_phaseinjector3_baddress_storage = 3'd0;
-reg soc_netsoc_sdram_phaseinjector3_baddress_re = 1'd0;
-reg [31:0] soc_netsoc_sdram_phaseinjector3_wrdata_storage = 32'd0;
-reg soc_netsoc_sdram_phaseinjector3_wrdata_re = 1'd0;
-reg [31:0] soc_netsoc_sdram_phaseinjector3_status = 32'd0;
-wire soc_netsoc_sdram_phaseinjector3_we;
-wire soc_netsoc_sdram_interface_bank0_valid;
-wire soc_netsoc_sdram_interface_bank0_ready;
-wire soc_netsoc_sdram_interface_bank0_we;
-wire [20:0] soc_netsoc_sdram_interface_bank0_addr;
-wire soc_netsoc_sdram_interface_bank0_lock;
-wire soc_netsoc_sdram_interface_bank0_wdata_ready;
-wire soc_netsoc_sdram_interface_bank0_rdata_valid;
-wire soc_netsoc_sdram_interface_bank1_valid;
-wire soc_netsoc_sdram_interface_bank1_ready;
-wire soc_netsoc_sdram_interface_bank1_we;
-wire [20:0] soc_netsoc_sdram_interface_bank1_addr;
-wire soc_netsoc_sdram_interface_bank1_lock;
-wire soc_netsoc_sdram_interface_bank1_wdata_ready;
-wire soc_netsoc_sdram_interface_bank1_rdata_valid;
-wire soc_netsoc_sdram_interface_bank2_valid;
-wire soc_netsoc_sdram_interface_bank2_ready;
-wire soc_netsoc_sdram_interface_bank2_we;
-wire [20:0] soc_netsoc_sdram_interface_bank2_addr;
-wire soc_netsoc_sdram_interface_bank2_lock;
-wire soc_netsoc_sdram_interface_bank2_wdata_ready;
-wire soc_netsoc_sdram_interface_bank2_rdata_valid;
-wire soc_netsoc_sdram_interface_bank3_valid;
-wire soc_netsoc_sdram_interface_bank3_ready;
-wire soc_netsoc_sdram_interface_bank3_we;
-wire [20:0] soc_netsoc_sdram_interface_bank3_addr;
-wire soc_netsoc_sdram_interface_bank3_lock;
-wire soc_netsoc_sdram_interface_bank3_wdata_ready;
-wire soc_netsoc_sdram_interface_bank3_rdata_valid;
-wire soc_netsoc_sdram_interface_bank4_valid;
-wire soc_netsoc_sdram_interface_bank4_ready;
-wire soc_netsoc_sdram_interface_bank4_we;
-wire [20:0] soc_netsoc_sdram_interface_bank4_addr;
-wire soc_netsoc_sdram_interface_bank4_lock;
-wire soc_netsoc_sdram_interface_bank4_wdata_ready;
-wire soc_netsoc_sdram_interface_bank4_rdata_valid;
-wire soc_netsoc_sdram_interface_bank5_valid;
-wire soc_netsoc_sdram_interface_bank5_ready;
-wire soc_netsoc_sdram_interface_bank5_we;
-wire [20:0] soc_netsoc_sdram_interface_bank5_addr;
-wire soc_netsoc_sdram_interface_bank5_lock;
-wire soc_netsoc_sdram_interface_bank5_wdata_ready;
-wire soc_netsoc_sdram_interface_bank5_rdata_valid;
-wire soc_netsoc_sdram_interface_bank6_valid;
-wire soc_netsoc_sdram_interface_bank6_ready;
-wire soc_netsoc_sdram_interface_bank6_we;
-wire [20:0] soc_netsoc_sdram_interface_bank6_addr;
-wire soc_netsoc_sdram_interface_bank6_lock;
-wire soc_netsoc_sdram_interface_bank6_wdata_ready;
-wire soc_netsoc_sdram_interface_bank6_rdata_valid;
-wire soc_netsoc_sdram_interface_bank7_valid;
-wire soc_netsoc_sdram_interface_bank7_ready;
-wire soc_netsoc_sdram_interface_bank7_we;
-wire [20:0] soc_netsoc_sdram_interface_bank7_addr;
-wire soc_netsoc_sdram_interface_bank7_lock;
-wire soc_netsoc_sdram_interface_bank7_wdata_ready;
-wire soc_netsoc_sdram_interface_bank7_rdata_valid;
-reg [127:0] soc_netsoc_sdram_interface_wdata = 128'd0;
-reg [15:0] soc_netsoc_sdram_interface_wdata_we = 16'd0;
-wire [127:0] soc_netsoc_sdram_interface_rdata;
-reg [13:0] soc_netsoc_sdram_dfi_p0_address = 14'd0;
-reg [2:0] soc_netsoc_sdram_dfi_p0_bank = 3'd0;
-reg soc_netsoc_sdram_dfi_p0_cas_n = 1'd1;
-reg soc_netsoc_sdram_dfi_p0_cs_n = 1'd1;
-reg soc_netsoc_sdram_dfi_p0_ras_n = 1'd1;
-reg soc_netsoc_sdram_dfi_p0_we_n = 1'd1;
-wire soc_netsoc_sdram_dfi_p0_cke;
-wire soc_netsoc_sdram_dfi_p0_odt;
-wire soc_netsoc_sdram_dfi_p0_reset_n;
-reg soc_netsoc_sdram_dfi_p0_act_n = 1'd1;
-wire [31:0] soc_netsoc_sdram_dfi_p0_wrdata;
-reg soc_netsoc_sdram_dfi_p0_wrdata_en = 1'd0;
-wire [3:0] soc_netsoc_sdram_dfi_p0_wrdata_mask;
-reg soc_netsoc_sdram_dfi_p0_rddata_en = 1'd0;
-wire [31:0] soc_netsoc_sdram_dfi_p0_rddata;
-wire soc_netsoc_sdram_dfi_p0_rddata_valid;
-reg [13:0] soc_netsoc_sdram_dfi_p1_address = 14'd0;
-reg [2:0] soc_netsoc_sdram_dfi_p1_bank = 3'd0;
-reg soc_netsoc_sdram_dfi_p1_cas_n = 1'd1;
-reg soc_netsoc_sdram_dfi_p1_cs_n = 1'd1;
-reg soc_netsoc_sdram_dfi_p1_ras_n = 1'd1;
-reg soc_netsoc_sdram_dfi_p1_we_n = 1'd1;
-wire soc_netsoc_sdram_dfi_p1_cke;
-wire soc_netsoc_sdram_dfi_p1_odt;
-wire soc_netsoc_sdram_dfi_p1_reset_n;
-reg soc_netsoc_sdram_dfi_p1_act_n = 1'd1;
-wire [31:0] soc_netsoc_sdram_dfi_p1_wrdata;
-reg soc_netsoc_sdram_dfi_p1_wrdata_en = 1'd0;
-wire [3:0] soc_netsoc_sdram_dfi_p1_wrdata_mask;
-reg soc_netsoc_sdram_dfi_p1_rddata_en = 1'd0;
-wire [31:0] soc_netsoc_sdram_dfi_p1_rddata;
-wire soc_netsoc_sdram_dfi_p1_rddata_valid;
-reg [13:0] soc_netsoc_sdram_dfi_p2_address = 14'd0;
-reg [2:0] soc_netsoc_sdram_dfi_p2_bank = 3'd0;
-reg soc_netsoc_sdram_dfi_p2_cas_n = 1'd1;
-reg soc_netsoc_sdram_dfi_p2_cs_n = 1'd1;
-reg soc_netsoc_sdram_dfi_p2_ras_n = 1'd1;
-reg soc_netsoc_sdram_dfi_p2_we_n = 1'd1;
-wire soc_netsoc_sdram_dfi_p2_cke;
-wire soc_netsoc_sdram_dfi_p2_odt;
-wire soc_netsoc_sdram_dfi_p2_reset_n;
-reg soc_netsoc_sdram_dfi_p2_act_n = 1'd1;
-wire [31:0] soc_netsoc_sdram_dfi_p2_wrdata;
-reg soc_netsoc_sdram_dfi_p2_wrdata_en = 1'd0;
-wire [3:0] soc_netsoc_sdram_dfi_p2_wrdata_mask;
-reg soc_netsoc_sdram_dfi_p2_rddata_en = 1'd0;
-wire [31:0] soc_netsoc_sdram_dfi_p2_rddata;
-wire soc_netsoc_sdram_dfi_p2_rddata_valid;
-reg [13:0] soc_netsoc_sdram_dfi_p3_address = 14'd0;
-reg [2:0] soc_netsoc_sdram_dfi_p3_bank = 3'd0;
-reg soc_netsoc_sdram_dfi_p3_cas_n = 1'd1;
-reg soc_netsoc_sdram_dfi_p3_cs_n = 1'd1;
-reg soc_netsoc_sdram_dfi_p3_ras_n = 1'd1;
-reg soc_netsoc_sdram_dfi_p3_we_n = 1'd1;
-wire soc_netsoc_sdram_dfi_p3_cke;
-wire soc_netsoc_sdram_dfi_p3_odt;
-wire soc_netsoc_sdram_dfi_p3_reset_n;
-reg soc_netsoc_sdram_dfi_p3_act_n = 1'd1;
-wire [31:0] soc_netsoc_sdram_dfi_p3_wrdata;
-reg soc_netsoc_sdram_dfi_p3_wrdata_en = 1'd0;
-wire [3:0] soc_netsoc_sdram_dfi_p3_wrdata_mask;
-reg soc_netsoc_sdram_dfi_p3_rddata_en = 1'd0;
-wire [31:0] soc_netsoc_sdram_dfi_p3_rddata;
-wire soc_netsoc_sdram_dfi_p3_rddata_valid;
-reg soc_netsoc_sdram_cmd_valid = 1'd0;
-reg soc_netsoc_sdram_cmd_ready = 1'd0;
-reg soc_netsoc_sdram_cmd_last = 1'd0;
-reg [13:0] soc_netsoc_sdram_cmd_payload_a = 14'd0;
-reg [2:0] soc_netsoc_sdram_cmd_payload_ba = 3'd0;
-reg soc_netsoc_sdram_cmd_payload_cas = 1'd0;
-reg soc_netsoc_sdram_cmd_payload_ras = 1'd0;
-reg soc_netsoc_sdram_cmd_payload_we = 1'd0;
-reg soc_netsoc_sdram_cmd_payload_is_read = 1'd0;
-reg soc_netsoc_sdram_cmd_payload_is_write = 1'd0;
-wire soc_netsoc_sdram_wants_refresh;
-wire soc_netsoc_sdram_wants_zqcs;
-wire soc_netsoc_sdram_timer_wait;
-wire soc_netsoc_sdram_timer_done0;
-wire [8:0] soc_netsoc_sdram_timer_count0;
-wire soc_netsoc_sdram_timer_done1;
-reg [8:0] soc_netsoc_sdram_timer_count1 = 9'd468;
-wire soc_netsoc_sdram_postponer_req_i;
-reg soc_netsoc_sdram_postponer_req_o = 1'd0;
-reg soc_netsoc_sdram_postponer_count = 1'd0;
-reg soc_netsoc_sdram_sequencer_start0 = 1'd0;
-wire soc_netsoc_sdram_sequencer_done0;
-wire soc_netsoc_sdram_sequencer_start1;
-reg soc_netsoc_sdram_sequencer_done1 = 1'd0;
-reg [5:0] soc_netsoc_sdram_sequencer_counter = 6'd0;
-reg soc_netsoc_sdram_sequencer_count = 1'd0;
-wire soc_netsoc_sdram_zqcs_timer_wait;
-wire soc_netsoc_sdram_zqcs_timer_done0;
-wire [25:0] soc_netsoc_sdram_zqcs_timer_count0;
-wire soc_netsoc_sdram_zqcs_timer_done1;
-reg [25:0] soc_netsoc_sdram_zqcs_timer_count1 = 26'd59999999;
-reg soc_netsoc_sdram_zqcs_executer_start = 1'd0;
-reg soc_netsoc_sdram_zqcs_executer_done = 1'd0;
-reg [4:0] soc_netsoc_sdram_zqcs_executer_counter = 5'd0;
-wire soc_netsoc_sdram_bankmachine0_req_valid;
-wire soc_netsoc_sdram_bankmachine0_req_ready;
-wire soc_netsoc_sdram_bankmachine0_req_we;
-wire [20:0] soc_netsoc_sdram_bankmachine0_req_addr;
-wire soc_netsoc_sdram_bankmachine0_req_lock;
-reg soc_netsoc_sdram_bankmachine0_req_wdata_ready = 1'd0;
-reg soc_netsoc_sdram_bankmachine0_req_rdata_valid = 1'd0;
-wire soc_netsoc_sdram_bankmachine0_refresh_req;
-reg soc_netsoc_sdram_bankmachine0_refresh_gnt = 1'd0;
-reg soc_netsoc_sdram_bankmachine0_cmd_valid = 1'd0;
-reg soc_netsoc_sdram_bankmachine0_cmd_ready = 1'd0;
-reg [13:0] soc_netsoc_sdram_bankmachine0_cmd_payload_a = 14'd0;
-wire [2:0] soc_netsoc_sdram_bankmachine0_cmd_payload_ba;
-reg soc_netsoc_sdram_bankmachine0_cmd_payload_cas = 1'd0;
-reg soc_netsoc_sdram_bankmachine0_cmd_payload_ras = 1'd0;
-reg soc_netsoc_sdram_bankmachine0_cmd_payload_we = 1'd0;
-reg soc_netsoc_sdram_bankmachine0_cmd_payload_is_cmd = 1'd0;
-reg soc_netsoc_sdram_bankmachine0_cmd_payload_is_read = 1'd0;
-reg soc_netsoc_sdram_bankmachine0_cmd_payload_is_write = 1'd0;
-reg soc_netsoc_sdram_bankmachine0_auto_precharge = 1'd0;
-wire soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid;
-wire soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready;
-reg soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0;
-reg soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0;
-wire soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
-wire soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_source_valid;
-wire soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_source_ready;
-wire soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_source_first;
-wire soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_source_last;
-wire soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
-wire soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we;
-wire soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
-wire soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re;
-wire soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
-wire [23:0] soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
-wire [23:0] soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-reg [3:0] soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_level = 4'd0;
-reg soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_replace = 1'd0;
-reg [2:0] soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_produce = 3'd0;
-reg [2:0] soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_consume = 3'd0;
-reg [2:0] soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr = 3'd0;
-wire [23:0] soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r;
-wire soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we;
-wire [23:0] soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
-wire soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_do_read;
-wire [2:0] soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
-wire soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first;
-wire soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last;
-wire soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
-wire soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
-wire soc_netsoc_sdram_bankmachine0_cmd_buffer_sink_valid;
-wire soc_netsoc_sdram_bankmachine0_cmd_buffer_sink_ready;
-wire soc_netsoc_sdram_bankmachine0_cmd_buffer_sink_first;
-wire soc_netsoc_sdram_bankmachine0_cmd_buffer_sink_last;
-wire soc_netsoc_sdram_bankmachine0_cmd_buffer_sink_payload_we;
-wire [20:0] soc_netsoc_sdram_bankmachine0_cmd_buffer_sink_payload_addr;
-wire soc_netsoc_sdram_bankmachine0_cmd_buffer_source_valid;
-wire soc_netsoc_sdram_bankmachine0_cmd_buffer_source_ready;
-wire soc_netsoc_sdram_bankmachine0_cmd_buffer_source_first;
-wire soc_netsoc_sdram_bankmachine0_cmd_buffer_source_last;
-reg soc_netsoc_sdram_bankmachine0_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] soc_netsoc_sdram_bankmachine0_cmd_buffer_source_payload_addr = 21'd0;
-wire soc_netsoc_sdram_bankmachine0_cmd_buffer_pipe_ce;
-wire soc_netsoc_sdram_bankmachine0_cmd_buffer_busy;
-reg soc_netsoc_sdram_bankmachine0_cmd_buffer_valid_n = 1'd0;
-reg soc_netsoc_sdram_bankmachine0_cmd_buffer_first_n = 1'd0;
-reg soc_netsoc_sdram_bankmachine0_cmd_buffer_last_n = 1'd0;
-reg [13:0] soc_netsoc_sdram_bankmachine0_row = 14'd0;
-reg soc_netsoc_sdram_bankmachine0_row_opened = 1'd0;
-wire soc_netsoc_sdram_bankmachine0_row_hit;
-reg soc_netsoc_sdram_bankmachine0_row_open = 1'd0;
-reg soc_netsoc_sdram_bankmachine0_row_close = 1'd0;
-reg soc_netsoc_sdram_bankmachine0_row_col_n_addr_sel = 1'd0;
-wire soc_netsoc_sdram_bankmachine0_twtpcon_valid;
-(* dont_touch = "true" *) reg soc_netsoc_sdram_bankmachine0_twtpcon_ready = 1'd1;
-reg [2:0] soc_netsoc_sdram_bankmachine0_twtpcon_count = 3'd0;
-wire soc_netsoc_sdram_bankmachine0_trccon_valid;
-(* dont_touch = "true" *) reg soc_netsoc_sdram_bankmachine0_trccon_ready = 1'd1;
-reg [1:0] soc_netsoc_sdram_bankmachine0_trccon_count = 2'd0;
-wire soc_netsoc_sdram_bankmachine0_trascon_valid;
-(* dont_touch = "true" *) reg soc_netsoc_sdram_bankmachine0_trascon_ready = 1'd1;
-reg [1:0] soc_netsoc_sdram_bankmachine0_trascon_count = 2'd0;
-wire soc_netsoc_sdram_bankmachine1_req_valid;
-wire soc_netsoc_sdram_bankmachine1_req_ready;
-wire soc_netsoc_sdram_bankmachine1_req_we;
-wire [20:0] soc_netsoc_sdram_bankmachine1_req_addr;
-wire soc_netsoc_sdram_bankmachine1_req_lock;
-reg soc_netsoc_sdram_bankmachine1_req_wdata_ready = 1'd0;
-reg soc_netsoc_sdram_bankmachine1_req_rdata_valid = 1'd0;
-wire soc_netsoc_sdram_bankmachine1_refresh_req;
-reg soc_netsoc_sdram_bankmachine1_refresh_gnt = 1'd0;
-reg soc_netsoc_sdram_bankmachine1_cmd_valid = 1'd0;
-reg soc_netsoc_sdram_bankmachine1_cmd_ready = 1'd0;
-reg [13:0] soc_netsoc_sdram_bankmachine1_cmd_payload_a = 14'd0;
-wire [2:0] soc_netsoc_sdram_bankmachine1_cmd_payload_ba;
-reg soc_netsoc_sdram_bankmachine1_cmd_payload_cas = 1'd0;
-reg soc_netsoc_sdram_bankmachine1_cmd_payload_ras = 1'd0;
-reg soc_netsoc_sdram_bankmachine1_cmd_payload_we = 1'd0;
-reg soc_netsoc_sdram_bankmachine1_cmd_payload_is_cmd = 1'd0;
-reg soc_netsoc_sdram_bankmachine1_cmd_payload_is_read = 1'd0;
-reg soc_netsoc_sdram_bankmachine1_cmd_payload_is_write = 1'd0;
-reg soc_netsoc_sdram_bankmachine1_auto_precharge = 1'd0;
-wire soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid;
-wire soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready;
-reg soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0;
-reg soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0;
-wire soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
-wire soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_source_valid;
-wire soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_source_ready;
-wire soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_source_first;
-wire soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_source_last;
-wire soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
-wire soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we;
-wire soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
-wire soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re;
-wire soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
-wire [23:0] soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
-wire [23:0] soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-reg [3:0] soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_level = 4'd0;
-reg soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_replace = 1'd0;
-reg [2:0] soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_produce = 3'd0;
-reg [2:0] soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_consume = 3'd0;
-reg [2:0] soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr = 3'd0;
-wire [23:0] soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r;
-wire soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we;
-wire [23:0] soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
-wire soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_do_read;
-wire [2:0] soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
-wire soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first;
-wire soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last;
-wire soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
-wire soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
-wire soc_netsoc_sdram_bankmachine1_cmd_buffer_sink_valid;
-wire soc_netsoc_sdram_bankmachine1_cmd_buffer_sink_ready;
-wire soc_netsoc_sdram_bankmachine1_cmd_buffer_sink_first;
-wire soc_netsoc_sdram_bankmachine1_cmd_buffer_sink_last;
-wire soc_netsoc_sdram_bankmachine1_cmd_buffer_sink_payload_we;
-wire [20:0] soc_netsoc_sdram_bankmachine1_cmd_buffer_sink_payload_addr;
-wire soc_netsoc_sdram_bankmachine1_cmd_buffer_source_valid;
-wire soc_netsoc_sdram_bankmachine1_cmd_buffer_source_ready;
-wire soc_netsoc_sdram_bankmachine1_cmd_buffer_source_first;
-wire soc_netsoc_sdram_bankmachine1_cmd_buffer_source_last;
-reg soc_netsoc_sdram_bankmachine1_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] soc_netsoc_sdram_bankmachine1_cmd_buffer_source_payload_addr = 21'd0;
-wire soc_netsoc_sdram_bankmachine1_cmd_buffer_pipe_ce;
-wire soc_netsoc_sdram_bankmachine1_cmd_buffer_busy;
-reg soc_netsoc_sdram_bankmachine1_cmd_buffer_valid_n = 1'd0;
-reg soc_netsoc_sdram_bankmachine1_cmd_buffer_first_n = 1'd0;
-reg soc_netsoc_sdram_bankmachine1_cmd_buffer_last_n = 1'd0;
-reg [13:0] soc_netsoc_sdram_bankmachine1_row = 14'd0;
-reg soc_netsoc_sdram_bankmachine1_row_opened = 1'd0;
-wire soc_netsoc_sdram_bankmachine1_row_hit;
-reg soc_netsoc_sdram_bankmachine1_row_open = 1'd0;
-reg soc_netsoc_sdram_bankmachine1_row_close = 1'd0;
-reg soc_netsoc_sdram_bankmachine1_row_col_n_addr_sel = 1'd0;
-wire soc_netsoc_sdram_bankmachine1_twtpcon_valid;
-(* dont_touch = "true" *) reg soc_netsoc_sdram_bankmachine1_twtpcon_ready = 1'd1;
-reg [2:0] soc_netsoc_sdram_bankmachine1_twtpcon_count = 3'd0;
-wire soc_netsoc_sdram_bankmachine1_trccon_valid;
-(* dont_touch = "true" *) reg soc_netsoc_sdram_bankmachine1_trccon_ready = 1'd1;
-reg [1:0] soc_netsoc_sdram_bankmachine1_trccon_count = 2'd0;
-wire soc_netsoc_sdram_bankmachine1_trascon_valid;
-(* dont_touch = "true" *) reg soc_netsoc_sdram_bankmachine1_trascon_ready = 1'd1;
-reg [1:0] soc_netsoc_sdram_bankmachine1_trascon_count = 2'd0;
-wire soc_netsoc_sdram_bankmachine2_req_valid;
-wire soc_netsoc_sdram_bankmachine2_req_ready;
-wire soc_netsoc_sdram_bankmachine2_req_we;
-wire [20:0] soc_netsoc_sdram_bankmachine2_req_addr;
-wire soc_netsoc_sdram_bankmachine2_req_lock;
-reg soc_netsoc_sdram_bankmachine2_req_wdata_ready = 1'd0;
-reg soc_netsoc_sdram_bankmachine2_req_rdata_valid = 1'd0;
-wire soc_netsoc_sdram_bankmachine2_refresh_req;
-reg soc_netsoc_sdram_bankmachine2_refresh_gnt = 1'd0;
-reg soc_netsoc_sdram_bankmachine2_cmd_valid = 1'd0;
-reg soc_netsoc_sdram_bankmachine2_cmd_ready = 1'd0;
-reg [13:0] soc_netsoc_sdram_bankmachine2_cmd_payload_a = 14'd0;
-wire [2:0] soc_netsoc_sdram_bankmachine2_cmd_payload_ba;
-reg soc_netsoc_sdram_bankmachine2_cmd_payload_cas = 1'd0;
-reg soc_netsoc_sdram_bankmachine2_cmd_payload_ras = 1'd0;
-reg soc_netsoc_sdram_bankmachine2_cmd_payload_we = 1'd0;
-reg soc_netsoc_sdram_bankmachine2_cmd_payload_is_cmd = 1'd0;
-reg soc_netsoc_sdram_bankmachine2_cmd_payload_is_read = 1'd0;
-reg soc_netsoc_sdram_bankmachine2_cmd_payload_is_write = 1'd0;
-reg soc_netsoc_sdram_bankmachine2_auto_precharge = 1'd0;
-wire soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid;
-wire soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready;
-reg soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0;
-reg soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0;
-wire soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
-wire soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_source_valid;
-wire soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_source_ready;
-wire soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_source_first;
-wire soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_source_last;
-wire soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
-wire soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we;
-wire soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
-wire soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re;
-wire soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
-wire [23:0] soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
-wire [23:0] soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-reg [3:0] soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_level = 4'd0;
-reg soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_replace = 1'd0;
-reg [2:0] soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_produce = 3'd0;
-reg [2:0] soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_consume = 3'd0;
-reg [2:0] soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr = 3'd0;
-wire [23:0] soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r;
-wire soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we;
-wire [23:0] soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
-wire soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_do_read;
-wire [2:0] soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
-wire soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first;
-wire soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last;
-wire soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
-wire soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
-wire soc_netsoc_sdram_bankmachine2_cmd_buffer_sink_valid;
-wire soc_netsoc_sdram_bankmachine2_cmd_buffer_sink_ready;
-wire soc_netsoc_sdram_bankmachine2_cmd_buffer_sink_first;
-wire soc_netsoc_sdram_bankmachine2_cmd_buffer_sink_last;
-wire soc_netsoc_sdram_bankmachine2_cmd_buffer_sink_payload_we;
-wire [20:0] soc_netsoc_sdram_bankmachine2_cmd_buffer_sink_payload_addr;
-wire soc_netsoc_sdram_bankmachine2_cmd_buffer_source_valid;
-wire soc_netsoc_sdram_bankmachine2_cmd_buffer_source_ready;
-wire soc_netsoc_sdram_bankmachine2_cmd_buffer_source_first;
-wire soc_netsoc_sdram_bankmachine2_cmd_buffer_source_last;
-reg soc_netsoc_sdram_bankmachine2_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] soc_netsoc_sdram_bankmachine2_cmd_buffer_source_payload_addr = 21'd0;
-wire soc_netsoc_sdram_bankmachine2_cmd_buffer_pipe_ce;
-wire soc_netsoc_sdram_bankmachine2_cmd_buffer_busy;
-reg soc_netsoc_sdram_bankmachine2_cmd_buffer_valid_n = 1'd0;
-reg soc_netsoc_sdram_bankmachine2_cmd_buffer_first_n = 1'd0;
-reg soc_netsoc_sdram_bankmachine2_cmd_buffer_last_n = 1'd0;
-reg [13:0] soc_netsoc_sdram_bankmachine2_row = 14'd0;
-reg soc_netsoc_sdram_bankmachine2_row_opened = 1'd0;
-wire soc_netsoc_sdram_bankmachine2_row_hit;
-reg soc_netsoc_sdram_bankmachine2_row_open = 1'd0;
-reg soc_netsoc_sdram_bankmachine2_row_close = 1'd0;
-reg soc_netsoc_sdram_bankmachine2_row_col_n_addr_sel = 1'd0;
-wire soc_netsoc_sdram_bankmachine2_twtpcon_valid;
-(* dont_touch = "true" *) reg soc_netsoc_sdram_bankmachine2_twtpcon_ready = 1'd1;
-reg [2:0] soc_netsoc_sdram_bankmachine2_twtpcon_count = 3'd0;
-wire soc_netsoc_sdram_bankmachine2_trccon_valid;
-(* dont_touch = "true" *) reg soc_netsoc_sdram_bankmachine2_trccon_ready = 1'd1;
-reg [1:0] soc_netsoc_sdram_bankmachine2_trccon_count = 2'd0;
-wire soc_netsoc_sdram_bankmachine2_trascon_valid;
-(* dont_touch = "true" *) reg soc_netsoc_sdram_bankmachine2_trascon_ready = 1'd1;
-reg [1:0] soc_netsoc_sdram_bankmachine2_trascon_count = 2'd0;
-wire soc_netsoc_sdram_bankmachine3_req_valid;
-wire soc_netsoc_sdram_bankmachine3_req_ready;
-wire soc_netsoc_sdram_bankmachine3_req_we;
-wire [20:0] soc_netsoc_sdram_bankmachine3_req_addr;
-wire soc_netsoc_sdram_bankmachine3_req_lock;
-reg soc_netsoc_sdram_bankmachine3_req_wdata_ready = 1'd0;
-reg soc_netsoc_sdram_bankmachine3_req_rdata_valid = 1'd0;
-wire soc_netsoc_sdram_bankmachine3_refresh_req;
-reg soc_netsoc_sdram_bankmachine3_refresh_gnt = 1'd0;
-reg soc_netsoc_sdram_bankmachine3_cmd_valid = 1'd0;
-reg soc_netsoc_sdram_bankmachine3_cmd_ready = 1'd0;
-reg [13:0] soc_netsoc_sdram_bankmachine3_cmd_payload_a = 14'd0;
-wire [2:0] soc_netsoc_sdram_bankmachine3_cmd_payload_ba;
-reg soc_netsoc_sdram_bankmachine3_cmd_payload_cas = 1'd0;
-reg soc_netsoc_sdram_bankmachine3_cmd_payload_ras = 1'd0;
-reg soc_netsoc_sdram_bankmachine3_cmd_payload_we = 1'd0;
-reg soc_netsoc_sdram_bankmachine3_cmd_payload_is_cmd = 1'd0;
-reg soc_netsoc_sdram_bankmachine3_cmd_payload_is_read = 1'd0;
-reg soc_netsoc_sdram_bankmachine3_cmd_payload_is_write = 1'd0;
-reg soc_netsoc_sdram_bankmachine3_auto_precharge = 1'd0;
-wire soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid;
-wire soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready;
-reg soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0;
-reg soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0;
-wire soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
-wire soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_source_valid;
-wire soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_source_ready;
-wire soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_source_first;
-wire soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_source_last;
-wire soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
-wire soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we;
-wire soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
-wire soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re;
-wire soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
-wire [23:0] soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
-wire [23:0] soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-reg [3:0] soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_level = 4'd0;
-reg soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_replace = 1'd0;
-reg [2:0] soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_produce = 3'd0;
-reg [2:0] soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_consume = 3'd0;
-reg [2:0] soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr = 3'd0;
-wire [23:0] soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r;
-wire soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we;
-wire [23:0] soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
-wire soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_do_read;
-wire [2:0] soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
-wire soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first;
-wire soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last;
-wire soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
-wire soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
-wire soc_netsoc_sdram_bankmachine3_cmd_buffer_sink_valid;
-wire soc_netsoc_sdram_bankmachine3_cmd_buffer_sink_ready;
-wire soc_netsoc_sdram_bankmachine3_cmd_buffer_sink_first;
-wire soc_netsoc_sdram_bankmachine3_cmd_buffer_sink_last;
-wire soc_netsoc_sdram_bankmachine3_cmd_buffer_sink_payload_we;
-wire [20:0] soc_netsoc_sdram_bankmachine3_cmd_buffer_sink_payload_addr;
-wire soc_netsoc_sdram_bankmachine3_cmd_buffer_source_valid;
-wire soc_netsoc_sdram_bankmachine3_cmd_buffer_source_ready;
-wire soc_netsoc_sdram_bankmachine3_cmd_buffer_source_first;
-wire soc_netsoc_sdram_bankmachine3_cmd_buffer_source_last;
-reg soc_netsoc_sdram_bankmachine3_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] soc_netsoc_sdram_bankmachine3_cmd_buffer_source_payload_addr = 21'd0;
-wire soc_netsoc_sdram_bankmachine3_cmd_buffer_pipe_ce;
-wire soc_netsoc_sdram_bankmachine3_cmd_buffer_busy;
-reg soc_netsoc_sdram_bankmachine3_cmd_buffer_valid_n = 1'd0;
-reg soc_netsoc_sdram_bankmachine3_cmd_buffer_first_n = 1'd0;
-reg soc_netsoc_sdram_bankmachine3_cmd_buffer_last_n = 1'd0;
-reg [13:0] soc_netsoc_sdram_bankmachine3_row = 14'd0;
-reg soc_netsoc_sdram_bankmachine3_row_opened = 1'd0;
-wire soc_netsoc_sdram_bankmachine3_row_hit;
-reg soc_netsoc_sdram_bankmachine3_row_open = 1'd0;
-reg soc_netsoc_sdram_bankmachine3_row_close = 1'd0;
-reg soc_netsoc_sdram_bankmachine3_row_col_n_addr_sel = 1'd0;
-wire soc_netsoc_sdram_bankmachine3_twtpcon_valid;
-(* dont_touch = "true" *) reg soc_netsoc_sdram_bankmachine3_twtpcon_ready = 1'd1;
-reg [2:0] soc_netsoc_sdram_bankmachine3_twtpcon_count = 3'd0;
-wire soc_netsoc_sdram_bankmachine3_trccon_valid;
-(* dont_touch = "true" *) reg soc_netsoc_sdram_bankmachine3_trccon_ready = 1'd1;
-reg [1:0] soc_netsoc_sdram_bankmachine3_trccon_count = 2'd0;
-wire soc_netsoc_sdram_bankmachine3_trascon_valid;
-(* dont_touch = "true" *) reg soc_netsoc_sdram_bankmachine3_trascon_ready = 1'd1;
-reg [1:0] soc_netsoc_sdram_bankmachine3_trascon_count = 2'd0;
-wire soc_netsoc_sdram_bankmachine4_req_valid;
-wire soc_netsoc_sdram_bankmachine4_req_ready;
-wire soc_netsoc_sdram_bankmachine4_req_we;
-wire [20:0] soc_netsoc_sdram_bankmachine4_req_addr;
-wire soc_netsoc_sdram_bankmachine4_req_lock;
-reg soc_netsoc_sdram_bankmachine4_req_wdata_ready = 1'd0;
-reg soc_netsoc_sdram_bankmachine4_req_rdata_valid = 1'd0;
-wire soc_netsoc_sdram_bankmachine4_refresh_req;
-reg soc_netsoc_sdram_bankmachine4_refresh_gnt = 1'd0;
-reg soc_netsoc_sdram_bankmachine4_cmd_valid = 1'd0;
-reg soc_netsoc_sdram_bankmachine4_cmd_ready = 1'd0;
-reg [13:0] soc_netsoc_sdram_bankmachine4_cmd_payload_a = 14'd0;
-wire [2:0] soc_netsoc_sdram_bankmachine4_cmd_payload_ba;
-reg soc_netsoc_sdram_bankmachine4_cmd_payload_cas = 1'd0;
-reg soc_netsoc_sdram_bankmachine4_cmd_payload_ras = 1'd0;
-reg soc_netsoc_sdram_bankmachine4_cmd_payload_we = 1'd0;
-reg soc_netsoc_sdram_bankmachine4_cmd_payload_is_cmd = 1'd0;
-reg soc_netsoc_sdram_bankmachine4_cmd_payload_is_read = 1'd0;
-reg soc_netsoc_sdram_bankmachine4_cmd_payload_is_write = 1'd0;
-reg soc_netsoc_sdram_bankmachine4_auto_precharge = 1'd0;
-wire soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_sink_valid;
-wire soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_sink_ready;
-reg soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0;
-reg soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0;
-wire soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
-wire soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_source_valid;
-wire soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_source_ready;
-wire soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_source_first;
-wire soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_source_last;
-wire soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
-wire soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we;
-wire soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
-wire soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_re;
-wire soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
-wire [23:0] soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
-wire [23:0] soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-reg [3:0] soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_level = 4'd0;
-reg soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_replace = 1'd0;
-reg [2:0] soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_produce = 3'd0;
-reg [2:0] soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_consume = 3'd0;
-reg [2:0] soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr = 3'd0;
-wire [23:0] soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_r;
-wire soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_we;
-wire [23:0] soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
-wire soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_do_read;
-wire [2:0] soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
-wire soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_first;
-wire soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_last;
-wire soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
-wire soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
-wire soc_netsoc_sdram_bankmachine4_cmd_buffer_sink_valid;
-wire soc_netsoc_sdram_bankmachine4_cmd_buffer_sink_ready;
-wire soc_netsoc_sdram_bankmachine4_cmd_buffer_sink_first;
-wire soc_netsoc_sdram_bankmachine4_cmd_buffer_sink_last;
-wire soc_netsoc_sdram_bankmachine4_cmd_buffer_sink_payload_we;
-wire [20:0] soc_netsoc_sdram_bankmachine4_cmd_buffer_sink_payload_addr;
-wire soc_netsoc_sdram_bankmachine4_cmd_buffer_source_valid;
-wire soc_netsoc_sdram_bankmachine4_cmd_buffer_source_ready;
-wire soc_netsoc_sdram_bankmachine4_cmd_buffer_source_first;
-wire soc_netsoc_sdram_bankmachine4_cmd_buffer_source_last;
-reg soc_netsoc_sdram_bankmachine4_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] soc_netsoc_sdram_bankmachine4_cmd_buffer_source_payload_addr = 21'd0;
-wire soc_netsoc_sdram_bankmachine4_cmd_buffer_pipe_ce;
-wire soc_netsoc_sdram_bankmachine4_cmd_buffer_busy;
-reg soc_netsoc_sdram_bankmachine4_cmd_buffer_valid_n = 1'd0;
-reg soc_netsoc_sdram_bankmachine4_cmd_buffer_first_n = 1'd0;
-reg soc_netsoc_sdram_bankmachine4_cmd_buffer_last_n = 1'd0;
-reg [13:0] soc_netsoc_sdram_bankmachine4_row = 14'd0;
-reg soc_netsoc_sdram_bankmachine4_row_opened = 1'd0;
-wire soc_netsoc_sdram_bankmachine4_row_hit;
-reg soc_netsoc_sdram_bankmachine4_row_open = 1'd0;
-reg soc_netsoc_sdram_bankmachine4_row_close = 1'd0;
-reg soc_netsoc_sdram_bankmachine4_row_col_n_addr_sel = 1'd0;
-wire soc_netsoc_sdram_bankmachine4_twtpcon_valid;
-(* dont_touch = "true" *) reg soc_netsoc_sdram_bankmachine4_twtpcon_ready = 1'd1;
-reg [2:0] soc_netsoc_sdram_bankmachine4_twtpcon_count = 3'd0;
-wire soc_netsoc_sdram_bankmachine4_trccon_valid;
-(* dont_touch = "true" *) reg soc_netsoc_sdram_bankmachine4_trccon_ready = 1'd1;
-reg [1:0] soc_netsoc_sdram_bankmachine4_trccon_count = 2'd0;
-wire soc_netsoc_sdram_bankmachine4_trascon_valid;
-(* dont_touch = "true" *) reg soc_netsoc_sdram_bankmachine4_trascon_ready = 1'd1;
-reg [1:0] soc_netsoc_sdram_bankmachine4_trascon_count = 2'd0;
-wire soc_netsoc_sdram_bankmachine5_req_valid;
-wire soc_netsoc_sdram_bankmachine5_req_ready;
-wire soc_netsoc_sdram_bankmachine5_req_we;
-wire [20:0] soc_netsoc_sdram_bankmachine5_req_addr;
-wire soc_netsoc_sdram_bankmachine5_req_lock;
-reg soc_netsoc_sdram_bankmachine5_req_wdata_ready = 1'd0;
-reg soc_netsoc_sdram_bankmachine5_req_rdata_valid = 1'd0;
-wire soc_netsoc_sdram_bankmachine5_refresh_req;
-reg soc_netsoc_sdram_bankmachine5_refresh_gnt = 1'd0;
-reg soc_netsoc_sdram_bankmachine5_cmd_valid = 1'd0;
-reg soc_netsoc_sdram_bankmachine5_cmd_ready = 1'd0;
-reg [13:0] soc_netsoc_sdram_bankmachine5_cmd_payload_a = 14'd0;
-wire [2:0] soc_netsoc_sdram_bankmachine5_cmd_payload_ba;
-reg soc_netsoc_sdram_bankmachine5_cmd_payload_cas = 1'd0;
-reg soc_netsoc_sdram_bankmachine5_cmd_payload_ras = 1'd0;
-reg soc_netsoc_sdram_bankmachine5_cmd_payload_we = 1'd0;
-reg soc_netsoc_sdram_bankmachine5_cmd_payload_is_cmd = 1'd0;
-reg soc_netsoc_sdram_bankmachine5_cmd_payload_is_read = 1'd0;
-reg soc_netsoc_sdram_bankmachine5_cmd_payload_is_write = 1'd0;
-reg soc_netsoc_sdram_bankmachine5_auto_precharge = 1'd0;
-wire soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_sink_valid;
-wire soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_sink_ready;
-reg soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0;
-reg soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0;
-wire soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
-wire soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_source_valid;
-wire soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_source_ready;
-wire soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_source_first;
-wire soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_source_last;
-wire soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
-wire soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we;
-wire soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
-wire soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_re;
-wire soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
-wire [23:0] soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
-wire [23:0] soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-reg [3:0] soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_level = 4'd0;
-reg soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_replace = 1'd0;
-reg [2:0] soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_produce = 3'd0;
-reg [2:0] soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_consume = 3'd0;
-reg [2:0] soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr = 3'd0;
-wire [23:0] soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_r;
-wire soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_we;
-wire [23:0] soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
-wire soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_do_read;
-wire [2:0] soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
-wire soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_first;
-wire soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_last;
-wire soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
-wire soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
-wire soc_netsoc_sdram_bankmachine5_cmd_buffer_sink_valid;
-wire soc_netsoc_sdram_bankmachine5_cmd_buffer_sink_ready;
-wire soc_netsoc_sdram_bankmachine5_cmd_buffer_sink_first;
-wire soc_netsoc_sdram_bankmachine5_cmd_buffer_sink_last;
-wire soc_netsoc_sdram_bankmachine5_cmd_buffer_sink_payload_we;
-wire [20:0] soc_netsoc_sdram_bankmachine5_cmd_buffer_sink_payload_addr;
-wire soc_netsoc_sdram_bankmachine5_cmd_buffer_source_valid;
-wire soc_netsoc_sdram_bankmachine5_cmd_buffer_source_ready;
-wire soc_netsoc_sdram_bankmachine5_cmd_buffer_source_first;
-wire soc_netsoc_sdram_bankmachine5_cmd_buffer_source_last;
-reg soc_netsoc_sdram_bankmachine5_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] soc_netsoc_sdram_bankmachine5_cmd_buffer_source_payload_addr = 21'd0;
-wire soc_netsoc_sdram_bankmachine5_cmd_buffer_pipe_ce;
-wire soc_netsoc_sdram_bankmachine5_cmd_buffer_busy;
-reg soc_netsoc_sdram_bankmachine5_cmd_buffer_valid_n = 1'd0;
-reg soc_netsoc_sdram_bankmachine5_cmd_buffer_first_n = 1'd0;
-reg soc_netsoc_sdram_bankmachine5_cmd_buffer_last_n = 1'd0;
-reg [13:0] soc_netsoc_sdram_bankmachine5_row = 14'd0;
-reg soc_netsoc_sdram_bankmachine5_row_opened = 1'd0;
-wire soc_netsoc_sdram_bankmachine5_row_hit;
-reg soc_netsoc_sdram_bankmachine5_row_open = 1'd0;
-reg soc_netsoc_sdram_bankmachine5_row_close = 1'd0;
-reg soc_netsoc_sdram_bankmachine5_row_col_n_addr_sel = 1'd0;
-wire soc_netsoc_sdram_bankmachine5_twtpcon_valid;
-(* dont_touch = "true" *) reg soc_netsoc_sdram_bankmachine5_twtpcon_ready = 1'd1;
-reg [2:0] soc_netsoc_sdram_bankmachine5_twtpcon_count = 3'd0;
-wire soc_netsoc_sdram_bankmachine5_trccon_valid;
-(* dont_touch = "true" *) reg soc_netsoc_sdram_bankmachine5_trccon_ready = 1'd1;
-reg [1:0] soc_netsoc_sdram_bankmachine5_trccon_count = 2'd0;
-wire soc_netsoc_sdram_bankmachine5_trascon_valid;
-(* dont_touch = "true" *) reg soc_netsoc_sdram_bankmachine5_trascon_ready = 1'd1;
-reg [1:0] soc_netsoc_sdram_bankmachine5_trascon_count = 2'd0;
-wire soc_netsoc_sdram_bankmachine6_req_valid;
-wire soc_netsoc_sdram_bankmachine6_req_ready;
-wire soc_netsoc_sdram_bankmachine6_req_we;
-wire [20:0] soc_netsoc_sdram_bankmachine6_req_addr;
-wire soc_netsoc_sdram_bankmachine6_req_lock;
-reg soc_netsoc_sdram_bankmachine6_req_wdata_ready = 1'd0;
-reg soc_netsoc_sdram_bankmachine6_req_rdata_valid = 1'd0;
-wire soc_netsoc_sdram_bankmachine6_refresh_req;
-reg soc_netsoc_sdram_bankmachine6_refresh_gnt = 1'd0;
-reg soc_netsoc_sdram_bankmachine6_cmd_valid = 1'd0;
-reg soc_netsoc_sdram_bankmachine6_cmd_ready = 1'd0;
-reg [13:0] soc_netsoc_sdram_bankmachine6_cmd_payload_a = 14'd0;
-wire [2:0] soc_netsoc_sdram_bankmachine6_cmd_payload_ba;
-reg soc_netsoc_sdram_bankmachine6_cmd_payload_cas = 1'd0;
-reg soc_netsoc_sdram_bankmachine6_cmd_payload_ras = 1'd0;
-reg soc_netsoc_sdram_bankmachine6_cmd_payload_we = 1'd0;
-reg soc_netsoc_sdram_bankmachine6_cmd_payload_is_cmd = 1'd0;
-reg soc_netsoc_sdram_bankmachine6_cmd_payload_is_read = 1'd0;
-reg soc_netsoc_sdram_bankmachine6_cmd_payload_is_write = 1'd0;
-reg soc_netsoc_sdram_bankmachine6_auto_precharge = 1'd0;
-wire soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_sink_valid;
-wire soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_sink_ready;
-reg soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0;
-reg soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0;
-wire soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
-wire soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_source_valid;
-wire soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_source_ready;
-wire soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_source_first;
-wire soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_source_last;
-wire soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
-wire soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we;
-wire soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
-wire soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_re;
-wire soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
-wire [23:0] soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
-wire [23:0] soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-reg [3:0] soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_level = 4'd0;
-reg soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_replace = 1'd0;
-reg [2:0] soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_produce = 3'd0;
-reg [2:0] soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_consume = 3'd0;
-reg [2:0] soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr = 3'd0;
-wire [23:0] soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_r;
-wire soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_we;
-wire [23:0] soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
-wire soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_do_read;
-wire [2:0] soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
-wire soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_first;
-wire soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_last;
-wire soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
-wire soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
-wire soc_netsoc_sdram_bankmachine6_cmd_buffer_sink_valid;
-wire soc_netsoc_sdram_bankmachine6_cmd_buffer_sink_ready;
-wire soc_netsoc_sdram_bankmachine6_cmd_buffer_sink_first;
-wire soc_netsoc_sdram_bankmachine6_cmd_buffer_sink_last;
-wire soc_netsoc_sdram_bankmachine6_cmd_buffer_sink_payload_we;
-wire [20:0] soc_netsoc_sdram_bankmachine6_cmd_buffer_sink_payload_addr;
-wire soc_netsoc_sdram_bankmachine6_cmd_buffer_source_valid;
-wire soc_netsoc_sdram_bankmachine6_cmd_buffer_source_ready;
-wire soc_netsoc_sdram_bankmachine6_cmd_buffer_source_first;
-wire soc_netsoc_sdram_bankmachine6_cmd_buffer_source_last;
-reg soc_netsoc_sdram_bankmachine6_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] soc_netsoc_sdram_bankmachine6_cmd_buffer_source_payload_addr = 21'd0;
-wire soc_netsoc_sdram_bankmachine6_cmd_buffer_pipe_ce;
-wire soc_netsoc_sdram_bankmachine6_cmd_buffer_busy;
-reg soc_netsoc_sdram_bankmachine6_cmd_buffer_valid_n = 1'd0;
-reg soc_netsoc_sdram_bankmachine6_cmd_buffer_first_n = 1'd0;
-reg soc_netsoc_sdram_bankmachine6_cmd_buffer_last_n = 1'd0;
-reg [13:0] soc_netsoc_sdram_bankmachine6_row = 14'd0;
-reg soc_netsoc_sdram_bankmachine6_row_opened = 1'd0;
-wire soc_netsoc_sdram_bankmachine6_row_hit;
-reg soc_netsoc_sdram_bankmachine6_row_open = 1'd0;
-reg soc_netsoc_sdram_bankmachine6_row_close = 1'd0;
-reg soc_netsoc_sdram_bankmachine6_row_col_n_addr_sel = 1'd0;
-wire soc_netsoc_sdram_bankmachine6_twtpcon_valid;
-(* dont_touch = "true" *) reg soc_netsoc_sdram_bankmachine6_twtpcon_ready = 1'd1;
-reg [2:0] soc_netsoc_sdram_bankmachine6_twtpcon_count = 3'd0;
-wire soc_netsoc_sdram_bankmachine6_trccon_valid;
-(* dont_touch = "true" *) reg soc_netsoc_sdram_bankmachine6_trccon_ready = 1'd1;
-reg [1:0] soc_netsoc_sdram_bankmachine6_trccon_count = 2'd0;
-wire soc_netsoc_sdram_bankmachine6_trascon_valid;
-(* dont_touch = "true" *) reg soc_netsoc_sdram_bankmachine6_trascon_ready = 1'd1;
-reg [1:0] soc_netsoc_sdram_bankmachine6_trascon_count = 2'd0;
-wire soc_netsoc_sdram_bankmachine7_req_valid;
-wire soc_netsoc_sdram_bankmachine7_req_ready;
-wire soc_netsoc_sdram_bankmachine7_req_we;
-wire [20:0] soc_netsoc_sdram_bankmachine7_req_addr;
-wire soc_netsoc_sdram_bankmachine7_req_lock;
-reg soc_netsoc_sdram_bankmachine7_req_wdata_ready = 1'd0;
-reg soc_netsoc_sdram_bankmachine7_req_rdata_valid = 1'd0;
-wire soc_netsoc_sdram_bankmachine7_refresh_req;
-reg soc_netsoc_sdram_bankmachine7_refresh_gnt = 1'd0;
-reg soc_netsoc_sdram_bankmachine7_cmd_valid = 1'd0;
-reg soc_netsoc_sdram_bankmachine7_cmd_ready = 1'd0;
-reg [13:0] soc_netsoc_sdram_bankmachine7_cmd_payload_a = 14'd0;
-wire [2:0] soc_netsoc_sdram_bankmachine7_cmd_payload_ba;
-reg soc_netsoc_sdram_bankmachine7_cmd_payload_cas = 1'd0;
-reg soc_netsoc_sdram_bankmachine7_cmd_payload_ras = 1'd0;
-reg soc_netsoc_sdram_bankmachine7_cmd_payload_we = 1'd0;
-reg soc_netsoc_sdram_bankmachine7_cmd_payload_is_cmd = 1'd0;
-reg soc_netsoc_sdram_bankmachine7_cmd_payload_is_read = 1'd0;
-reg soc_netsoc_sdram_bankmachine7_cmd_payload_is_write = 1'd0;
-reg soc_netsoc_sdram_bankmachine7_auto_precharge = 1'd0;
-wire soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_sink_valid;
-wire soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_sink_ready;
-reg soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0;
-reg soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0;
-wire soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
-wire soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_source_valid;
-wire soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_source_ready;
-wire soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_source_first;
-wire soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_source_last;
-wire soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
-wire soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we;
-wire soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
-wire soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_re;
-wire soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
-wire [23:0] soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
-wire [23:0] soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-reg [3:0] soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_level = 4'd0;
-reg soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_replace = 1'd0;
-reg [2:0] soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_produce = 3'd0;
-reg [2:0] soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_consume = 3'd0;
-reg [2:0] soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr = 3'd0;
-wire [23:0] soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_r;
-wire soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_we;
-wire [23:0] soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
-wire soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_do_read;
-wire [2:0] soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
-wire soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_first;
-wire soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_last;
-wire soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
-wire soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
-wire soc_netsoc_sdram_bankmachine7_cmd_buffer_sink_valid;
-wire soc_netsoc_sdram_bankmachine7_cmd_buffer_sink_ready;
-wire soc_netsoc_sdram_bankmachine7_cmd_buffer_sink_first;
-wire soc_netsoc_sdram_bankmachine7_cmd_buffer_sink_last;
-wire soc_netsoc_sdram_bankmachine7_cmd_buffer_sink_payload_we;
-wire [20:0] soc_netsoc_sdram_bankmachine7_cmd_buffer_sink_payload_addr;
-wire soc_netsoc_sdram_bankmachine7_cmd_buffer_source_valid;
-wire soc_netsoc_sdram_bankmachine7_cmd_buffer_source_ready;
-wire soc_netsoc_sdram_bankmachine7_cmd_buffer_source_first;
-wire soc_netsoc_sdram_bankmachine7_cmd_buffer_source_last;
-reg soc_netsoc_sdram_bankmachine7_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] soc_netsoc_sdram_bankmachine7_cmd_buffer_source_payload_addr = 21'd0;
-wire soc_netsoc_sdram_bankmachine7_cmd_buffer_pipe_ce;
-wire soc_netsoc_sdram_bankmachine7_cmd_buffer_busy;
-reg soc_netsoc_sdram_bankmachine7_cmd_buffer_valid_n = 1'd0;
-reg soc_netsoc_sdram_bankmachine7_cmd_buffer_first_n = 1'd0;
-reg soc_netsoc_sdram_bankmachine7_cmd_buffer_last_n = 1'd0;
-reg [13:0] soc_netsoc_sdram_bankmachine7_row = 14'd0;
-reg soc_netsoc_sdram_bankmachine7_row_opened = 1'd0;
-wire soc_netsoc_sdram_bankmachine7_row_hit;
-reg soc_netsoc_sdram_bankmachine7_row_open = 1'd0;
-reg soc_netsoc_sdram_bankmachine7_row_close = 1'd0;
-reg soc_netsoc_sdram_bankmachine7_row_col_n_addr_sel = 1'd0;
-wire soc_netsoc_sdram_bankmachine7_twtpcon_valid;
-(* dont_touch = "true" *) reg soc_netsoc_sdram_bankmachine7_twtpcon_ready = 1'd1;
-reg [2:0] soc_netsoc_sdram_bankmachine7_twtpcon_count = 3'd0;
-wire soc_netsoc_sdram_bankmachine7_trccon_valid;
-(* dont_touch = "true" *) reg soc_netsoc_sdram_bankmachine7_trccon_ready = 1'd1;
-reg [1:0] soc_netsoc_sdram_bankmachine7_trccon_count = 2'd0;
-wire soc_netsoc_sdram_bankmachine7_trascon_valid;
-(* dont_touch = "true" *) reg soc_netsoc_sdram_bankmachine7_trascon_ready = 1'd1;
-reg [1:0] soc_netsoc_sdram_bankmachine7_trascon_count = 2'd0;
-wire soc_netsoc_sdram_ras_allowed;
-wire soc_netsoc_sdram_cas_allowed;
-reg soc_netsoc_sdram_choose_cmd_want_reads = 1'd0;
-reg soc_netsoc_sdram_choose_cmd_want_writes = 1'd0;
-reg soc_netsoc_sdram_choose_cmd_want_cmds = 1'd0;
-reg soc_netsoc_sdram_choose_cmd_want_activates = 1'd0;
-wire soc_netsoc_sdram_choose_cmd_cmd_valid;
-reg soc_netsoc_sdram_choose_cmd_cmd_ready = 1'd0;
-wire [13:0] soc_netsoc_sdram_choose_cmd_cmd_payload_a;
-wire [2:0] soc_netsoc_sdram_choose_cmd_cmd_payload_ba;
-reg soc_netsoc_sdram_choose_cmd_cmd_payload_cas = 1'd0;
-reg soc_netsoc_sdram_choose_cmd_cmd_payload_ras = 1'd0;
-reg soc_netsoc_sdram_choose_cmd_cmd_payload_we = 1'd0;
-wire soc_netsoc_sdram_choose_cmd_cmd_payload_is_cmd;
-wire soc_netsoc_sdram_choose_cmd_cmd_payload_is_read;
-wire soc_netsoc_sdram_choose_cmd_cmd_payload_is_write;
-reg [7:0] soc_netsoc_sdram_choose_cmd_valids = 8'd0;
-wire [7:0] soc_netsoc_sdram_choose_cmd_request;
-reg [2:0] soc_netsoc_sdram_choose_cmd_grant = 3'd0;
-wire soc_netsoc_sdram_choose_cmd_ce;
-reg soc_netsoc_sdram_choose_req_want_reads = 1'd0;
-reg soc_netsoc_sdram_choose_req_want_writes = 1'd0;
-reg soc_netsoc_sdram_choose_req_want_cmds = 1'd0;
-reg soc_netsoc_sdram_choose_req_want_activates = 1'd0;
-wire soc_netsoc_sdram_choose_req_cmd_valid;
-reg soc_netsoc_sdram_choose_req_cmd_ready = 1'd0;
-wire [13:0] soc_netsoc_sdram_choose_req_cmd_payload_a;
-wire [2:0] soc_netsoc_sdram_choose_req_cmd_payload_ba;
-reg soc_netsoc_sdram_choose_req_cmd_payload_cas = 1'd0;
-reg soc_netsoc_sdram_choose_req_cmd_payload_ras = 1'd0;
-reg soc_netsoc_sdram_choose_req_cmd_payload_we = 1'd0;
-wire soc_netsoc_sdram_choose_req_cmd_payload_is_cmd;
-wire soc_netsoc_sdram_choose_req_cmd_payload_is_read;
-wire soc_netsoc_sdram_choose_req_cmd_payload_is_write;
-reg [7:0] soc_netsoc_sdram_choose_req_valids = 8'd0;
-wire [7:0] soc_netsoc_sdram_choose_req_request;
-reg [2:0] soc_netsoc_sdram_choose_req_grant = 3'd0;
-wire soc_netsoc_sdram_choose_req_ce;
-reg [13:0] soc_netsoc_sdram_nop_a = 14'd0;
-reg [2:0] soc_netsoc_sdram_nop_ba = 3'd0;
-reg [1:0] soc_netsoc_sdram_steerer_sel0 = 2'd0;
-reg [1:0] soc_netsoc_sdram_steerer_sel1 = 2'd0;
-reg [1:0] soc_netsoc_sdram_steerer_sel2 = 2'd0;
-reg [1:0] soc_netsoc_sdram_steerer_sel3 = 2'd0;
-reg soc_netsoc_sdram_steerer0 = 1'd1;
-reg soc_netsoc_sdram_steerer1 = 1'd1;
-reg soc_netsoc_sdram_steerer2 = 1'd1;
-reg soc_netsoc_sdram_steerer3 = 1'd1;
-reg soc_netsoc_sdram_steerer4 = 1'd1;
-reg soc_netsoc_sdram_steerer5 = 1'd1;
-reg soc_netsoc_sdram_steerer6 = 1'd1;
-reg soc_netsoc_sdram_steerer7 = 1'd1;
-wire soc_netsoc_sdram_trrdcon_valid;
-(* dont_touch = "true" *) reg soc_netsoc_sdram_trrdcon_ready = 1'd1;
-reg soc_netsoc_sdram_trrdcon_count = 1'd0;
-wire soc_netsoc_sdram_tfawcon_valid;
-(* dont_touch = "true" *) reg soc_netsoc_sdram_tfawcon_ready = 1'd1;
-wire [1:0] soc_netsoc_sdram_tfawcon_count;
-reg [3:0] soc_netsoc_sdram_tfawcon_window = 4'd0;
-wire soc_netsoc_sdram_tccdcon_valid;
-(* dont_touch = "true" *) reg soc_netsoc_sdram_tccdcon_ready = 1'd1;
-reg soc_netsoc_sdram_tccdcon_count = 1'd0;
-wire soc_netsoc_sdram_twtrcon_valid;
-(* dont_touch = "true" *) reg soc_netsoc_sdram_twtrcon_ready = 1'd1;
-reg [2:0] soc_netsoc_sdram_twtrcon_count = 3'd0;
-wire soc_netsoc_sdram_read_available;
-wire soc_netsoc_sdram_write_available;
-reg soc_netsoc_sdram_en0 = 1'd0;
-wire soc_netsoc_sdram_max_time0;
-reg [4:0] soc_netsoc_sdram_time0 = 5'd0;
-reg soc_netsoc_sdram_en1 = 1'd0;
-wire soc_netsoc_sdram_max_time1;
-reg [3:0] soc_netsoc_sdram_time1 = 4'd0;
-wire soc_netsoc_sdram_go_to_refresh;
-wire soc_netsoc_sdram_bandwidth_update_re;
-wire soc_netsoc_sdram_bandwidth_update_r;
-wire soc_netsoc_sdram_bandwidth_update_we;
-reg soc_netsoc_sdram_bandwidth_update_w = 1'd0;
-reg [23:0] soc_netsoc_sdram_bandwidth_nreads_status = 24'd0;
-wire soc_netsoc_sdram_bandwidth_nreads_we;
-reg [23:0] soc_netsoc_sdram_bandwidth_nwrites_status = 24'd0;
-wire soc_netsoc_sdram_bandwidth_nwrites_we;
-reg [7:0] soc_netsoc_sdram_bandwidth_data_width_status = 8'd128;
-wire soc_netsoc_sdram_bandwidth_data_width_we;
-reg soc_netsoc_sdram_bandwidth_cmd_valid = 1'd0;
-reg soc_netsoc_sdram_bandwidth_cmd_ready = 1'd0;
-reg soc_netsoc_sdram_bandwidth_cmd_is_read = 1'd0;
-reg soc_netsoc_sdram_bandwidth_cmd_is_write = 1'd0;
-reg [23:0] soc_netsoc_sdram_bandwidth_counter = 24'd0;
-reg soc_netsoc_sdram_bandwidth_period = 1'd0;
-reg [23:0] soc_netsoc_sdram_bandwidth_nreads = 24'd0;
-reg [23:0] soc_netsoc_sdram_bandwidth_nwrites = 24'd0;
-reg [23:0] soc_netsoc_sdram_bandwidth_nreads_r = 24'd0;
-reg [23:0] soc_netsoc_sdram_bandwidth_nwrites_r = 24'd0;
-reg soc_netsoc_port_cmd_valid = 1'd0;
-wire soc_netsoc_port_cmd_ready;
-reg soc_netsoc_port_cmd_payload_we = 1'd0;
-reg [23:0] soc_netsoc_port_cmd_payload_addr = 24'd0;
-wire soc_netsoc_port_wdata_valid;
-wire soc_netsoc_port_wdata_ready;
-wire soc_netsoc_port_wdata_first;
-wire soc_netsoc_port_wdata_last;
-wire [127:0] soc_netsoc_port_wdata_payload_data;
-wire [15:0] soc_netsoc_port_wdata_payload_we;
-wire soc_netsoc_port_rdata_valid;
-wire soc_netsoc_port_rdata_ready;
-reg soc_netsoc_port_rdata_first = 1'd0;
-reg soc_netsoc_port_rdata_last = 1'd0;
-wire [127:0] soc_netsoc_port_rdata_payload_data;
-wire [29:0] soc_netsoc_interface1_wb_sdram_adr;
-wire [31:0] soc_netsoc_interface1_wb_sdram_dat_w;
-wire [31:0] soc_netsoc_interface1_wb_sdram_dat_r;
-wire [3:0] soc_netsoc_interface1_wb_sdram_sel;
-wire soc_netsoc_interface1_wb_sdram_cyc;
-wire soc_netsoc_interface1_wb_sdram_stb;
-wire soc_netsoc_interface1_wb_sdram_ack;
-wire soc_netsoc_interface1_wb_sdram_we;
-wire [2:0] soc_netsoc_interface1_wb_sdram_cti;
-wire [1:0] soc_netsoc_interface1_wb_sdram_bte;
-wire soc_netsoc_interface1_wb_sdram_err;
-wire [29:0] soc_netsoc_adr;
-wire [127:0] soc_netsoc_dat_w;
-wire [127:0] soc_netsoc_dat_r;
-wire [15:0] soc_netsoc_sel;
-reg soc_netsoc_cyc = 1'd0;
-reg soc_netsoc_stb = 1'd0;
-reg soc_netsoc_ack = 1'd0;
-reg soc_netsoc_we = 1'd0;
-wire [8:0] soc_netsoc_data_port_adr;
-wire [127:0] soc_netsoc_data_port_dat_r;
-reg [15:0] soc_netsoc_data_port_we = 16'd0;
-reg [127:0] soc_netsoc_data_port_dat_w = 128'd0;
-reg soc_netsoc_write_from_slave = 1'd0;
-reg [1:0] soc_netsoc_adr_offset_r = 2'd0;
-wire [8:0] soc_netsoc_tag_port_adr;
-wire [23:0] soc_netsoc_tag_port_dat_r;
-reg soc_netsoc_tag_port_we = 1'd0;
-wire [23:0] soc_netsoc_tag_port_dat_w;
-wire [22:0] soc_netsoc_tag_do_tag;
-wire soc_netsoc_tag_do_dirty;
-wire [22:0] soc_netsoc_tag_di_tag;
-reg soc_netsoc_tag_di_dirty = 1'd0;
-reg soc_netsoc_word_clr = 1'd0;
-reg soc_netsoc_word_inc = 1'd0;
-wire soc_netsoc_wdata_converter_sink_valid;
-wire soc_netsoc_wdata_converter_sink_ready;
-reg soc_netsoc_wdata_converter_sink_first = 1'd0;
-reg soc_netsoc_wdata_converter_sink_last = 1'd0;
-wire [127:0] soc_netsoc_wdata_converter_sink_payload_data;
-wire [15:0] soc_netsoc_wdata_converter_sink_payload_we;
-wire soc_netsoc_wdata_converter_source_valid;
-wire soc_netsoc_wdata_converter_source_ready;
-wire soc_netsoc_wdata_converter_source_first;
-wire soc_netsoc_wdata_converter_source_last;
-wire [127:0] soc_netsoc_wdata_converter_source_payload_data;
-wire [15:0] soc_netsoc_wdata_converter_source_payload_we;
-wire soc_netsoc_wdata_converter_converter_sink_valid;
-wire soc_netsoc_wdata_converter_converter_sink_ready;
-wire soc_netsoc_wdata_converter_converter_sink_first;
-wire soc_netsoc_wdata_converter_converter_sink_last;
-wire [143:0] soc_netsoc_wdata_converter_converter_sink_payload_data;
-wire soc_netsoc_wdata_converter_converter_source_valid;
-wire soc_netsoc_wdata_converter_converter_source_ready;
-wire soc_netsoc_wdata_converter_converter_source_first;
-wire soc_netsoc_wdata_converter_converter_source_last;
-wire [143:0] soc_netsoc_wdata_converter_converter_source_payload_data;
-wire soc_netsoc_wdata_converter_converter_source_payload_valid_token_count;
-wire soc_netsoc_wdata_converter_source_source_valid;
-wire soc_netsoc_wdata_converter_source_source_ready;
-wire soc_netsoc_wdata_converter_source_source_first;
-wire soc_netsoc_wdata_converter_source_source_last;
-wire [143:0] soc_netsoc_wdata_converter_source_source_payload_data;
-wire soc_netsoc_rdata_converter_sink_valid;
-wire soc_netsoc_rdata_converter_sink_ready;
-wire soc_netsoc_rdata_converter_sink_first;
-wire soc_netsoc_rdata_converter_sink_last;
-wire [127:0] soc_netsoc_rdata_converter_sink_payload_data;
-wire soc_netsoc_rdata_converter_source_valid;
-wire soc_netsoc_rdata_converter_source_ready;
-wire soc_netsoc_rdata_converter_source_first;
-wire soc_netsoc_rdata_converter_source_last;
-wire [127:0] soc_netsoc_rdata_converter_source_payload_data;
-wire soc_netsoc_rdata_converter_converter_sink_valid;
-wire soc_netsoc_rdata_converter_converter_sink_ready;
-wire soc_netsoc_rdata_converter_converter_sink_first;
-wire soc_netsoc_rdata_converter_converter_sink_last;
-wire [127:0] soc_netsoc_rdata_converter_converter_sink_payload_data;
-wire soc_netsoc_rdata_converter_converter_source_valid;
-wire soc_netsoc_rdata_converter_converter_source_ready;
-wire soc_netsoc_rdata_converter_converter_source_first;
-wire soc_netsoc_rdata_converter_converter_source_last;
-wire [127:0] soc_netsoc_rdata_converter_converter_source_payload_data;
-wire soc_netsoc_rdata_converter_converter_source_payload_valid_token_count;
-wire soc_netsoc_rdata_converter_source_source_valid;
-wire soc_netsoc_rdata_converter_source_source_ready;
-wire soc_netsoc_rdata_converter_source_source_first;
-wire soc_netsoc_rdata_converter_source_source_last;
-wire [127:0] soc_netsoc_rdata_converter_source_source_payload_data;
-reg soc_netsoc_count = 1'd0;
-reg soc_reset_storage = 1'd0;
-reg soc_reset_re = 1'd0;
-(* dont_touch = "true" *) wire eth_rx_clk;
-wire eth_rx_rst;
-(* dont_touch = "true" *) wire eth_tx_clk;
-wire eth_tx_rst;
-wire soc_reset0;
-wire soc_reset1;
-reg [8:0] soc_counter = 9'd0;
-wire soc_counter_done;
-wire soc_counter_ce;
-wire soc_liteethphymiitx_sink_sink_valid;
-wire soc_liteethphymiitx_sink_sink_ready;
-wire soc_liteethphymiitx_sink_sink_first;
-wire soc_liteethphymiitx_sink_sink_last;
-wire [7:0] soc_liteethphymiitx_sink_sink_payload_data;
-wire soc_liteethphymiitx_sink_sink_payload_last_be;
-wire soc_liteethphymiitx_sink_sink_payload_error;
-wire soc_liteethphymiitx_converter_sink_valid;
-wire soc_liteethphymiitx_converter_sink_ready;
-reg soc_liteethphymiitx_converter_sink_first = 1'd0;
-reg soc_liteethphymiitx_converter_sink_last = 1'd0;
-wire [7:0] soc_liteethphymiitx_converter_sink_payload_data;
-wire soc_liteethphymiitx_converter_source_valid;
-wire soc_liteethphymiitx_converter_source_ready;
-wire soc_liteethphymiitx_converter_source_first;
-wire soc_liteethphymiitx_converter_source_last;
-wire [3:0] soc_liteethphymiitx_converter_source_payload_data;
-wire soc_liteethphymiitx_converter_converter_sink_valid;
-wire soc_liteethphymiitx_converter_converter_sink_ready;
-wire soc_liteethphymiitx_converter_converter_sink_first;
-wire soc_liteethphymiitx_converter_converter_sink_last;
-reg [7:0] soc_liteethphymiitx_converter_converter_sink_payload_data = 8'd0;
-wire soc_liteethphymiitx_converter_converter_source_valid;
-wire soc_liteethphymiitx_converter_converter_source_ready;
-wire soc_liteethphymiitx_converter_converter_source_first;
-wire soc_liteethphymiitx_converter_converter_source_last;
-reg [3:0] soc_liteethphymiitx_converter_converter_source_payload_data = 4'd0;
-wire soc_liteethphymiitx_converter_converter_source_payload_valid_token_count;
-reg soc_liteethphymiitx_converter_converter_mux = 1'd0;
-wire soc_liteethphymiitx_converter_converter_first;
-wire soc_liteethphymiitx_converter_converter_last;
-wire soc_liteethphymiitx_converter_source_source_valid;
-wire soc_liteethphymiitx_converter_source_source_ready;
-wire soc_liteethphymiitx_converter_source_source_first;
-wire soc_liteethphymiitx_converter_source_source_last;
-wire [3:0] soc_liteethphymiitx_converter_source_source_payload_data;
-wire soc_liteethphymiirx_source_source_valid;
-wire soc_liteethphymiirx_source_source_ready;
-wire soc_liteethphymiirx_source_source_first;
-wire soc_liteethphymiirx_source_source_last;
-wire [7:0] soc_liteethphymiirx_source_source_payload_data;
-reg soc_liteethphymiirx_source_source_payload_last_be = 1'd0;
-reg soc_liteethphymiirx_source_source_payload_error = 1'd0;
-reg soc_liteethphymiirx_converter_sink_valid = 1'd0;
-wire soc_liteethphymiirx_converter_sink_ready;
-reg soc_liteethphymiirx_converter_sink_first = 1'd0;
-wire soc_liteethphymiirx_converter_sink_last;
-reg [3:0] soc_liteethphymiirx_converter_sink_payload_data = 4'd0;
-wire soc_liteethphymiirx_converter_source_valid;
-wire soc_liteethphymiirx_converter_source_ready;
-wire soc_liteethphymiirx_converter_source_first;
-wire soc_liteethphymiirx_converter_source_last;
-reg [7:0] soc_liteethphymiirx_converter_source_payload_data = 8'd0;
-wire soc_liteethphymiirx_converter_converter_sink_valid;
-wire soc_liteethphymiirx_converter_converter_sink_ready;
-wire soc_liteethphymiirx_converter_converter_sink_first;
-wire soc_liteethphymiirx_converter_converter_sink_last;
-wire [3:0] soc_liteethphymiirx_converter_converter_sink_payload_data;
-wire soc_liteethphymiirx_converter_converter_source_valid;
-wire soc_liteethphymiirx_converter_converter_source_ready;
-reg soc_liteethphymiirx_converter_converter_source_first = 1'd0;
-reg soc_liteethphymiirx_converter_converter_source_last = 1'd0;
-reg [7:0] soc_liteethphymiirx_converter_converter_source_payload_data = 8'd0;
-reg [1:0] soc_liteethphymiirx_converter_converter_source_payload_valid_token_count = 2'd0;
-reg soc_liteethphymiirx_converter_converter_demux = 1'd0;
-wire soc_liteethphymiirx_converter_converter_load_part;
-reg soc_liteethphymiirx_converter_converter_strobe_all = 1'd0;
-wire soc_liteethphymiirx_converter_source_source_valid;
-wire soc_liteethphymiirx_converter_source_source_ready;
-wire soc_liteethphymiirx_converter_source_source_first;
-wire soc_liteethphymiirx_converter_source_source_last;
-wire [7:0] soc_liteethphymiirx_converter_source_source_payload_data;
-reg soc_liteethphymiirx_converter_reset = 1'd0;
-wire soc_mdc;
-wire soc_oe;
-wire soc_w;
-reg [2:0] soc_storage = 3'd0;
-reg soc_re = 1'd0;
-reg soc_r = 1'd0;
-reg soc_status = 1'd0;
-wire soc_we;
-wire soc_data_w;
-wire soc_data_oe;
-wire soc_data_r;
-wire soc_tx_gap_inserter_sink_valid;
-reg soc_tx_gap_inserter_sink_ready = 1'd0;
-wire soc_tx_gap_inserter_sink_first;
-wire soc_tx_gap_inserter_sink_last;
-wire [7:0] soc_tx_gap_inserter_sink_payload_data;
-wire soc_tx_gap_inserter_sink_payload_last_be;
-wire soc_tx_gap_inserter_sink_payload_error;
-reg soc_tx_gap_inserter_source_valid = 1'd0;
-wire soc_tx_gap_inserter_source_ready;
-reg soc_tx_gap_inserter_source_first = 1'd0;
-reg soc_tx_gap_inserter_source_last = 1'd0;
-reg [7:0] soc_tx_gap_inserter_source_payload_data = 8'd0;
-reg soc_tx_gap_inserter_source_payload_last_be = 1'd0;
-reg soc_tx_gap_inserter_source_payload_error = 1'd0;
-reg [3:0] soc_tx_gap_inserter_counter = 4'd0;
-reg soc_tx_gap_inserter_counter_reset = 1'd0;
-reg soc_tx_gap_inserter_counter_ce = 1'd0;
-reg soc_preamble_crc_status = 1'd1;
-wire soc_preamble_crc_we;
-reg [31:0] soc_preamble_errors_status = 32'd0;
-wire soc_preamble_errors_we;
-reg [31:0] soc_crc_errors_status = 32'd0;
-wire soc_crc_errors_we;
-wire soc_preamble_inserter_sink_valid;
-reg soc_preamble_inserter_sink_ready = 1'd0;
-wire soc_preamble_inserter_sink_first;
-wire soc_preamble_inserter_sink_last;
-wire [7:0] soc_preamble_inserter_sink_payload_data;
-wire soc_preamble_inserter_sink_payload_last_be;
-wire soc_preamble_inserter_sink_payload_error;
-reg soc_preamble_inserter_source_valid = 1'd0;
-wire soc_preamble_inserter_source_ready;
-reg soc_preamble_inserter_source_first = 1'd0;
-reg soc_preamble_inserter_source_last = 1'd0;
-reg [7:0] soc_preamble_inserter_source_payload_data = 8'd0;
-wire soc_preamble_inserter_source_payload_last_be;
-reg soc_preamble_inserter_source_payload_error = 1'd0;
-reg [63:0] soc_preamble_inserter_preamble = 64'd15372286728091293013;
-reg [2:0] soc_preamble_inserter_cnt = 3'd0;
-reg soc_preamble_inserter_clr_cnt = 1'd0;
-reg soc_preamble_inserter_inc_cnt = 1'd0;
-wire soc_preamble_checker_sink_valid;
-reg soc_preamble_checker_sink_ready = 1'd0;
-wire soc_preamble_checker_sink_first;
-wire soc_preamble_checker_sink_last;
-wire [7:0] soc_preamble_checker_sink_payload_data;
-wire soc_preamble_checker_sink_payload_last_be;
-wire soc_preamble_checker_sink_payload_error;
-reg soc_preamble_checker_source_valid = 1'd0;
-wire soc_preamble_checker_source_ready;
-reg soc_preamble_checker_source_first = 1'd0;
-reg soc_preamble_checker_source_last = 1'd0;
-wire [7:0] soc_preamble_checker_source_payload_data;
-wire soc_preamble_checker_source_payload_last_be;
-reg soc_preamble_checker_source_payload_error = 1'd0;
-reg soc_preamble_checker_error = 1'd0;
-wire soc_crc32_inserter_sink_valid;
-reg soc_crc32_inserter_sink_ready = 1'd0;
-wire soc_crc32_inserter_sink_first;
-wire soc_crc32_inserter_sink_last;
-wire [7:0] soc_crc32_inserter_sink_payload_data;
-wire soc_crc32_inserter_sink_payload_last_be;
-wire soc_crc32_inserter_sink_payload_error;
-reg soc_crc32_inserter_source_valid = 1'd0;
-wire soc_crc32_inserter_source_ready;
-reg soc_crc32_inserter_source_first = 1'd0;
-reg soc_crc32_inserter_source_last = 1'd0;
-reg [7:0] soc_crc32_inserter_source_payload_data = 8'd0;
-reg soc_crc32_inserter_source_payload_last_be = 1'd0;
-reg soc_crc32_inserter_source_payload_error = 1'd0;
-reg [7:0] soc_crc32_inserter_data0 = 8'd0;
-wire [31:0] soc_crc32_inserter_value;
-wire soc_crc32_inserter_error;
-wire [7:0] soc_crc32_inserter_data1;
-wire [31:0] soc_crc32_inserter_last;
-reg [31:0] soc_crc32_inserter_next = 32'd0;
-reg [31:0] soc_crc32_inserter_reg = 32'd4294967295;
-reg soc_crc32_inserter_ce = 1'd0;
-reg soc_crc32_inserter_reset = 1'd0;
-reg [1:0] soc_crc32_inserter_cnt = 2'd3;
-wire soc_crc32_inserter_cnt_done;
-reg soc_crc32_inserter_is_ongoing0 = 1'd0;
-reg soc_crc32_inserter_is_ongoing1 = 1'd0;
-wire soc_crc32_checker_sink_sink_valid;
-reg soc_crc32_checker_sink_sink_ready = 1'd0;
-wire soc_crc32_checker_sink_sink_first;
-wire soc_crc32_checker_sink_sink_last;
-wire [7:0] soc_crc32_checker_sink_sink_payload_data;
-wire soc_crc32_checker_sink_sink_payload_last_be;
-wire soc_crc32_checker_sink_sink_payload_error;
-wire soc_crc32_checker_source_source_valid;
-wire soc_crc32_checker_source_source_ready;
-reg soc_crc32_checker_source_source_first = 1'd0;
-wire soc_crc32_checker_source_source_last;
-wire [7:0] soc_crc32_checker_source_source_payload_data;
-wire soc_crc32_checker_source_source_payload_last_be;
-reg soc_crc32_checker_source_source_payload_error = 1'd0;
-wire soc_crc32_checker_error;
-wire [7:0] soc_crc32_checker_crc_data0;
-wire [31:0] soc_crc32_checker_crc_value;
-wire soc_crc32_checker_crc_error;
-wire [7:0] soc_crc32_checker_crc_data1;
-wire [31:0] soc_crc32_checker_crc_last;
-reg [31:0] soc_crc32_checker_crc_next = 32'd0;
-reg [31:0] soc_crc32_checker_crc_reg = 32'd4294967295;
-reg soc_crc32_checker_crc_ce = 1'd0;
-reg soc_crc32_checker_crc_reset = 1'd0;
-reg soc_crc32_checker_syncfifo_sink_valid = 1'd0;
-wire soc_crc32_checker_syncfifo_sink_ready;
-wire soc_crc32_checker_syncfifo_sink_first;
-wire soc_crc32_checker_syncfifo_sink_last;
-wire [7:0] soc_crc32_checker_syncfifo_sink_payload_data;
-wire soc_crc32_checker_syncfifo_sink_payload_last_be;
-wire soc_crc32_checker_syncfifo_sink_payload_error;
-wire soc_crc32_checker_syncfifo_source_valid;
-wire soc_crc32_checker_syncfifo_source_ready;
-wire soc_crc32_checker_syncfifo_source_first;
-wire soc_crc32_checker_syncfifo_source_last;
-wire [7:0] soc_crc32_checker_syncfifo_source_payload_data;
-wire soc_crc32_checker_syncfifo_source_payload_last_be;
-wire soc_crc32_checker_syncfifo_source_payload_error;
-wire soc_crc32_checker_syncfifo_syncfifo_we;
-wire soc_crc32_checker_syncfifo_syncfifo_writable;
-wire soc_crc32_checker_syncfifo_syncfifo_re;
-wire soc_crc32_checker_syncfifo_syncfifo_readable;
-wire [11:0] soc_crc32_checker_syncfifo_syncfifo_din;
-wire [11:0] soc_crc32_checker_syncfifo_syncfifo_dout;
-reg [2:0] soc_crc32_checker_syncfifo_level = 3'd0;
-reg soc_crc32_checker_syncfifo_replace = 1'd0;
-reg [2:0] soc_crc32_checker_syncfifo_produce = 3'd0;
-reg [2:0] soc_crc32_checker_syncfifo_consume = 3'd0;
-reg [2:0] soc_crc32_checker_syncfifo_wrport_adr = 3'd0;
-wire [11:0] soc_crc32_checker_syncfifo_wrport_dat_r;
-wire soc_crc32_checker_syncfifo_wrport_we;
-wire [11:0] soc_crc32_checker_syncfifo_wrport_dat_w;
-wire soc_crc32_checker_syncfifo_do_read;
-wire [2:0] soc_crc32_checker_syncfifo_rdport_adr;
-wire [11:0] soc_crc32_checker_syncfifo_rdport_dat_r;
-wire [7:0] soc_crc32_checker_syncfifo_fifo_in_payload_data;
-wire soc_crc32_checker_syncfifo_fifo_in_payload_last_be;
-wire soc_crc32_checker_syncfifo_fifo_in_payload_error;
-wire soc_crc32_checker_syncfifo_fifo_in_first;
-wire soc_crc32_checker_syncfifo_fifo_in_last;
-wire [7:0] soc_crc32_checker_syncfifo_fifo_out_payload_data;
-wire soc_crc32_checker_syncfifo_fifo_out_payload_last_be;
-wire soc_crc32_checker_syncfifo_fifo_out_payload_error;
-wire soc_crc32_checker_syncfifo_fifo_out_first;
-wire soc_crc32_checker_syncfifo_fifo_out_last;
-reg soc_crc32_checker_fifo_reset = 1'd0;
-wire soc_crc32_checker_fifo_in;
-wire soc_crc32_checker_fifo_out;
-wire soc_crc32_checker_fifo_full;
-wire soc_ps_preamble_error_i;
-wire soc_ps_preamble_error_o;
-reg soc_ps_preamble_error_toggle_i = 1'd0;
-wire soc_ps_preamble_error_toggle_o;
-reg soc_ps_preamble_error_toggle_o_r = 1'd0;
-wire soc_ps_crc_error_i;
-wire soc_ps_crc_error_o;
-reg soc_ps_crc_error_toggle_i = 1'd0;
-wire soc_ps_crc_error_toggle_o;
-reg soc_ps_crc_error_toggle_o_r = 1'd0;
-wire soc_padding_inserter_sink_valid;
-reg soc_padding_inserter_sink_ready = 1'd0;
-wire soc_padding_inserter_sink_first;
-wire soc_padding_inserter_sink_last;
-wire [7:0] soc_padding_inserter_sink_payload_data;
-wire soc_padding_inserter_sink_payload_last_be;
-wire soc_padding_inserter_sink_payload_error;
-reg soc_padding_inserter_source_valid = 1'd0;
-wire soc_padding_inserter_source_ready;
-reg soc_padding_inserter_source_first = 1'd0;
-reg soc_padding_inserter_source_last = 1'd0;
-reg [7:0] soc_padding_inserter_source_payload_data = 8'd0;
-reg soc_padding_inserter_source_payload_last_be = 1'd0;
-reg soc_padding_inserter_source_payload_error = 1'd0;
-reg [15:0] soc_padding_inserter_counter = 16'd1;
-wire soc_padding_inserter_counter_done;
-reg soc_padding_inserter_counter_reset = 1'd0;
-reg soc_padding_inserter_counter_ce = 1'd0;
-wire soc_padding_checker_sink_valid;
-wire soc_padding_checker_sink_ready;
-wire soc_padding_checker_sink_first;
-wire soc_padding_checker_sink_last;
-wire [7:0] soc_padding_checker_sink_payload_data;
-wire soc_padding_checker_sink_payload_last_be;
-wire soc_padding_checker_sink_payload_error;
-wire soc_padding_checker_source_valid;
-wire soc_padding_checker_source_ready;
-wire soc_padding_checker_source_first;
-wire soc_padding_checker_source_last;
-wire [7:0] soc_padding_checker_source_payload_data;
-wire soc_padding_checker_source_payload_last_be;
-wire soc_padding_checker_source_payload_error;
-wire soc_tx_last_be_sink_valid;
-wire soc_tx_last_be_sink_ready;
-wire soc_tx_last_be_sink_first;
-wire soc_tx_last_be_sink_last;
-wire [7:0] soc_tx_last_be_sink_payload_data;
-wire soc_tx_last_be_sink_payload_last_be;
-wire soc_tx_last_be_sink_payload_error;
-wire soc_tx_last_be_source_valid;
-wire soc_tx_last_be_source_ready;
-reg soc_tx_last_be_source_first = 1'd0;
-wire soc_tx_last_be_source_last;
-wire [7:0] soc_tx_last_be_source_payload_data;
-reg soc_tx_last_be_source_payload_last_be = 1'd0;
-reg soc_tx_last_be_source_payload_error = 1'd0;
-reg soc_tx_last_be_ongoing = 1'd1;
-wire soc_rx_last_be_sink_valid;
-wire soc_rx_last_be_sink_ready;
-wire soc_rx_last_be_sink_first;
-wire soc_rx_last_be_sink_last;
-wire [7:0] soc_rx_last_be_sink_payload_data;
-wire soc_rx_last_be_sink_payload_last_be;
-wire soc_rx_last_be_sink_payload_error;
-wire soc_rx_last_be_source_valid;
-wire soc_rx_last_be_source_ready;
-wire soc_rx_last_be_source_first;
-wire soc_rx_last_be_source_last;
-wire [7:0] soc_rx_last_be_source_payload_data;
-reg soc_rx_last_be_source_payload_last_be = 1'd0;
-wire soc_rx_last_be_source_payload_error;
-wire soc_tx_converter_sink_valid;
-wire soc_tx_converter_sink_ready;
-wire soc_tx_converter_sink_first;
-wire soc_tx_converter_sink_last;
-wire [31:0] soc_tx_converter_sink_payload_data;
-wire [3:0] soc_tx_converter_sink_payload_last_be;
-wire [3:0] soc_tx_converter_sink_payload_error;
-wire soc_tx_converter_source_valid;
-wire soc_tx_converter_source_ready;
-wire soc_tx_converter_source_first;
-wire soc_tx_converter_source_last;
-wire [7:0] soc_tx_converter_source_payload_data;
-wire soc_tx_converter_source_payload_last_be;
-wire soc_tx_converter_source_payload_error;
-wire soc_tx_converter_converter_sink_valid;
-wire soc_tx_converter_converter_sink_ready;
-wire soc_tx_converter_converter_sink_first;
-wire soc_tx_converter_converter_sink_last;
-reg [39:0] soc_tx_converter_converter_sink_payload_data = 40'd0;
-wire soc_tx_converter_converter_source_valid;
-wire soc_tx_converter_converter_source_ready;
-wire soc_tx_converter_converter_source_first;
-wire soc_tx_converter_converter_source_last;
-reg [9:0] soc_tx_converter_converter_source_payload_data = 10'd0;
-wire soc_tx_converter_converter_source_payload_valid_token_count;
-reg [1:0] soc_tx_converter_converter_mux = 2'd0;
-wire soc_tx_converter_converter_first;
-wire soc_tx_converter_converter_last;
-wire soc_tx_converter_source_source_valid;
-wire soc_tx_converter_source_source_ready;
-wire soc_tx_converter_source_source_first;
-wire soc_tx_converter_source_source_last;
-wire [9:0] soc_tx_converter_source_source_payload_data;
-wire soc_rx_converter_sink_valid;
-wire soc_rx_converter_sink_ready;
-wire soc_rx_converter_sink_first;
-wire soc_rx_converter_sink_last;
-wire [7:0] soc_rx_converter_sink_payload_data;
-wire soc_rx_converter_sink_payload_last_be;
-wire soc_rx_converter_sink_payload_error;
-wire soc_rx_converter_source_valid;
-wire soc_rx_converter_source_ready;
-wire soc_rx_converter_source_first;
-wire soc_rx_converter_source_last;
-reg [31:0] soc_rx_converter_source_payload_data = 32'd0;
-reg [3:0] soc_rx_converter_source_payload_last_be = 4'd0;
-reg [3:0] soc_rx_converter_source_payload_error = 4'd0;
-wire soc_rx_converter_converter_sink_valid;
-wire soc_rx_converter_converter_sink_ready;
-wire soc_rx_converter_converter_sink_first;
-wire soc_rx_converter_converter_sink_last;
-wire [9:0] soc_rx_converter_converter_sink_payload_data;
-wire soc_rx_converter_converter_source_valid;
-wire soc_rx_converter_converter_source_ready;
-reg soc_rx_converter_converter_source_first = 1'd0;
-reg soc_rx_converter_converter_source_last = 1'd0;
-reg [39:0] soc_rx_converter_converter_source_payload_data = 40'd0;
-reg [2:0] soc_rx_converter_converter_source_payload_valid_token_count = 3'd0;
-reg [1:0] soc_rx_converter_converter_demux = 2'd0;
-wire soc_rx_converter_converter_load_part;
-reg soc_rx_converter_converter_strobe_all = 1'd0;
-wire soc_rx_converter_source_source_valid;
-wire soc_rx_converter_source_source_ready;
-wire soc_rx_converter_source_source_first;
-wire soc_rx_converter_source_source_last;
-wire [39:0] soc_rx_converter_source_source_payload_data;
-wire soc_tx_cdc_sink_valid;
-wire soc_tx_cdc_sink_ready;
-wire soc_tx_cdc_sink_first;
-wire soc_tx_cdc_sink_last;
-wire [31:0] soc_tx_cdc_sink_payload_data;
-wire [3:0] soc_tx_cdc_sink_payload_last_be;
-wire [3:0] soc_tx_cdc_sink_payload_error;
-wire soc_tx_cdc_source_valid;
-wire soc_tx_cdc_source_ready;
-wire soc_tx_cdc_source_first;
-wire soc_tx_cdc_source_last;
-wire [31:0] soc_tx_cdc_source_payload_data;
-wire [3:0] soc_tx_cdc_source_payload_last_be;
-wire [3:0] soc_tx_cdc_source_payload_error;
-wire soc_tx_cdc_asyncfifo_we;
-wire soc_tx_cdc_asyncfifo_writable;
-wire soc_tx_cdc_asyncfifo_re;
-wire soc_tx_cdc_asyncfifo_readable;
-wire [41:0] soc_tx_cdc_asyncfifo_din;
-wire [41:0] soc_tx_cdc_asyncfifo_dout;
-wire soc_tx_cdc_graycounter0_ce;
-(* dont_touch = "true" *) reg [6:0] soc_tx_cdc_graycounter0_q = 7'd0;
-wire [6:0] soc_tx_cdc_graycounter0_q_next;
-reg [6:0] soc_tx_cdc_graycounter0_q_binary = 7'd0;
-reg [6:0] soc_tx_cdc_graycounter0_q_next_binary = 7'd0;
-wire soc_tx_cdc_graycounter1_ce;
-(* dont_touch = "true" *) reg [6:0] soc_tx_cdc_graycounter1_q = 7'd0;
-wire [6:0] soc_tx_cdc_graycounter1_q_next;
-reg [6:0] soc_tx_cdc_graycounter1_q_binary = 7'd0;
-reg [6:0] soc_tx_cdc_graycounter1_q_next_binary = 7'd0;
-wire [6:0] soc_tx_cdc_produce_rdomain;
-wire [6:0] soc_tx_cdc_consume_wdomain;
-wire [5:0] soc_tx_cdc_wrport_adr;
-wire [41:0] soc_tx_cdc_wrport_dat_r;
-wire soc_tx_cdc_wrport_we;
-wire [41:0] soc_tx_cdc_wrport_dat_w;
-wire [5:0] soc_tx_cdc_rdport_adr;
-wire [41:0] soc_tx_cdc_rdport_dat_r;
-wire [31:0] soc_tx_cdc_fifo_in_payload_data;
-wire [3:0] soc_tx_cdc_fifo_in_payload_last_be;
-wire [3:0] soc_tx_cdc_fifo_in_payload_error;
-wire soc_tx_cdc_fifo_in_first;
-wire soc_tx_cdc_fifo_in_last;
-wire [31:0] soc_tx_cdc_fifo_out_payload_data;
-wire [3:0] soc_tx_cdc_fifo_out_payload_last_be;
-wire [3:0] soc_tx_cdc_fifo_out_payload_error;
-wire soc_tx_cdc_fifo_out_first;
-wire soc_tx_cdc_fifo_out_last;
-wire soc_rx_cdc_sink_valid;
-wire soc_rx_cdc_sink_ready;
-wire soc_rx_cdc_sink_first;
-wire soc_rx_cdc_sink_last;
-wire [31:0] soc_rx_cdc_sink_payload_data;
-wire [3:0] soc_rx_cdc_sink_payload_last_be;
-wire [3:0] soc_rx_cdc_sink_payload_error;
-wire soc_rx_cdc_source_valid;
-wire soc_rx_cdc_source_ready;
-wire soc_rx_cdc_source_first;
-wire soc_rx_cdc_source_last;
-wire [31:0] soc_rx_cdc_source_payload_data;
-wire [3:0] soc_rx_cdc_source_payload_last_be;
-wire [3:0] soc_rx_cdc_source_payload_error;
-wire soc_rx_cdc_asyncfifo_we;
-wire soc_rx_cdc_asyncfifo_writable;
-wire soc_rx_cdc_asyncfifo_re;
-wire soc_rx_cdc_asyncfifo_readable;
-wire [41:0] soc_rx_cdc_asyncfifo_din;
-wire [41:0] soc_rx_cdc_asyncfifo_dout;
-wire soc_rx_cdc_graycounter0_ce;
-(* dont_touch = "true" *) reg [6:0] soc_rx_cdc_graycounter0_q = 7'd0;
-wire [6:0] soc_rx_cdc_graycounter0_q_next;
-reg [6:0] soc_rx_cdc_graycounter0_q_binary = 7'd0;
-reg [6:0] soc_rx_cdc_graycounter0_q_next_binary = 7'd0;
-wire soc_rx_cdc_graycounter1_ce;
-(* dont_touch = "true" *) reg [6:0] soc_rx_cdc_graycounter1_q = 7'd0;
-wire [6:0] soc_rx_cdc_graycounter1_q_next;
-reg [6:0] soc_rx_cdc_graycounter1_q_binary = 7'd0;
-reg [6:0] soc_rx_cdc_graycounter1_q_next_binary = 7'd0;
-wire [6:0] soc_rx_cdc_produce_rdomain;
-wire [6:0] soc_rx_cdc_consume_wdomain;
-wire [5:0] soc_rx_cdc_wrport_adr;
-wire [41:0] soc_rx_cdc_wrport_dat_r;
-wire soc_rx_cdc_wrport_we;
-wire [41:0] soc_rx_cdc_wrport_dat_w;
-wire [5:0] soc_rx_cdc_rdport_adr;
-wire [41:0] soc_rx_cdc_rdport_dat_r;
-wire [31:0] soc_rx_cdc_fifo_in_payload_data;
-wire [3:0] soc_rx_cdc_fifo_in_payload_last_be;
-wire [3:0] soc_rx_cdc_fifo_in_payload_error;
-wire soc_rx_cdc_fifo_in_first;
-wire soc_rx_cdc_fifo_in_last;
-wire [31:0] soc_rx_cdc_fifo_out_payload_data;
-wire [3:0] soc_rx_cdc_fifo_out_payload_last_be;
-wire [3:0] soc_rx_cdc_fifo_out_payload_error;
-wire soc_rx_cdc_fifo_out_first;
-wire soc_rx_cdc_fifo_out_last;
-wire soc_sink_valid;
-wire soc_sink_ready;
-wire soc_sink_first;
-wire soc_sink_last;
-wire [31:0] soc_sink_payload_data;
-wire [3:0] soc_sink_payload_last_be;
-wire [3:0] soc_sink_payload_error;
-wire soc_source_valid;
-wire soc_source_ready;
-wire soc_source_first;
-wire soc_source_last;
-wire [31:0] soc_source_payload_data;
-wire [3:0] soc_source_payload_last_be;
-wire [3:0] soc_source_payload_error;
-wire [29:0] soc_bus_adr;
-wire [31:0] soc_bus_dat_w;
-wire [31:0] soc_bus_dat_r;
-wire [3:0] soc_bus_sel;
-wire soc_bus_cyc;
-wire soc_bus_stb;
-wire soc_bus_ack;
-wire soc_bus_we;
-wire [2:0] soc_bus_cti;
-wire [1:0] soc_bus_bte;
-wire soc_bus_err;
-wire soc_writer_sink_sink_valid;
-reg soc_writer_sink_sink_ready = 1'd1;
-wire soc_writer_sink_sink_first;
-wire soc_writer_sink_sink_last;
-wire [31:0] soc_writer_sink_sink_payload_data;
-wire [3:0] soc_writer_sink_sink_payload_last_be;
-wire [3:0] soc_writer_sink_sink_payload_error;
-wire soc_writer_slot_status;
-wire soc_writer_slot_we;
-wire [31:0] soc_writer_length_status;
-wire soc_writer_length_we;
-reg [31:0] soc_writer_errors_status = 32'd0;
-wire soc_writer_errors_we;
-wire soc_writer_irq;
-wire soc_writer_available_status;
-wire soc_writer_available_pending;
-wire soc_writer_available_trigger;
-reg soc_writer_available_clear = 1'd0;
-wire soc_writer_status_re;
-wire soc_writer_status_r;
-wire soc_writer_status_we;
-wire soc_writer_status_w;
-wire soc_writer_pending_re;
-wire soc_writer_pending_r;
-wire soc_writer_pending_we;
-wire soc_writer_pending_w;
-reg soc_writer_storage = 1'd0;
-reg soc_writer_re = 1'd0;
-reg [2:0] soc_writer_inc = 3'd0;
-reg [31:0] soc_writer_counter = 32'd0;
-reg soc_writer_counter_reset = 1'd0;
-reg soc_writer_counter_ce = 1'd0;
-reg soc_writer_slot = 1'd0;
-reg soc_writer_slot_ce = 1'd0;
-reg soc_writer_ongoing = 1'd0;
-reg soc_writer_fifo_sink_valid = 1'd0;
-wire soc_writer_fifo_sink_ready;
-reg soc_writer_fifo_sink_first = 1'd0;
-reg soc_writer_fifo_sink_last = 1'd0;
-wire soc_writer_fifo_sink_payload_slot;
-wire [31:0] soc_writer_fifo_sink_payload_length;
-wire soc_writer_fifo_source_valid;
-wire soc_writer_fifo_source_ready;
-wire soc_writer_fifo_source_first;
-wire soc_writer_fifo_source_last;
-wire soc_writer_fifo_source_payload_slot;
-wire [31:0] soc_writer_fifo_source_payload_length;
-wire soc_writer_fifo_syncfifo_we;
-wire soc_writer_fifo_syncfifo_writable;
-wire soc_writer_fifo_syncfifo_re;
-wire soc_writer_fifo_syncfifo_readable;
-wire [34:0] soc_writer_fifo_syncfifo_din;
-wire [34:0] soc_writer_fifo_syncfifo_dout;
-reg [1:0] soc_writer_fifo_level = 2'd0;
-reg soc_writer_fifo_replace = 1'd0;
-reg soc_writer_fifo_produce = 1'd0;
-reg soc_writer_fifo_consume = 1'd0;
-reg soc_writer_fifo_wrport_adr = 1'd0;
-wire [34:0] soc_writer_fifo_wrport_dat_r;
-wire soc_writer_fifo_wrport_we;
-wire [34:0] soc_writer_fifo_wrport_dat_w;
-wire soc_writer_fifo_do_read;
-wire soc_writer_fifo_rdport_adr;
-wire [34:0] soc_writer_fifo_rdport_dat_r;
-wire soc_writer_fifo_fifo_in_payload_slot;
-wire [31:0] soc_writer_fifo_fifo_in_payload_length;
-wire soc_writer_fifo_fifo_in_first;
-wire soc_writer_fifo_fifo_in_last;
-wire soc_writer_fifo_fifo_out_payload_slot;
-wire [31:0] soc_writer_fifo_fifo_out_payload_length;
-wire soc_writer_fifo_fifo_out_first;
-wire soc_writer_fifo_fifo_out_last;
-reg [8:0] soc_writer_memory0_adr = 9'd0;
-wire [31:0] soc_writer_memory0_dat_r;
-reg soc_writer_memory0_we = 1'd0;
-reg [31:0] soc_writer_memory0_dat_w = 32'd0;
-reg [8:0] soc_writer_memory1_adr = 9'd0;
-wire [31:0] soc_writer_memory1_dat_r;
-reg soc_writer_memory1_we = 1'd0;
-reg [31:0] soc_writer_memory1_dat_w = 32'd0;
-reg soc_reader_source_source_valid = 1'd0;
-wire soc_reader_source_source_ready;
-reg soc_reader_source_source_first = 1'd0;
-reg soc_reader_source_source_last = 1'd0;
-reg [31:0] soc_reader_source_source_payload_data = 32'd0;
-reg [3:0] soc_reader_source_source_payload_last_be = 4'd0;
-reg [3:0] soc_reader_source_source_payload_error = 4'd0;
-wire soc_reader_start_re;
-wire soc_reader_start_r;
-wire soc_reader_start_we;
-reg soc_reader_start_w = 1'd0;
-wire soc_reader_ready_status;
-wire soc_reader_ready_we;
-wire [1:0] soc_reader_level_status;
-wire soc_reader_level_we;
-reg soc_reader_slot_storage = 1'd0;
-reg soc_reader_slot_re = 1'd0;
-reg [10:0] soc_reader_length_storage = 11'd0;
-reg soc_reader_length_re = 1'd0;
-wire soc_reader_irq;
-wire soc_reader_done_status;
-reg soc_reader_done_pending = 1'd0;
-reg soc_reader_done_trigger = 1'd0;
-reg soc_reader_done_clear = 1'd0;
-wire soc_reader_eventmanager_status_re;
-wire soc_reader_eventmanager_status_r;
-wire soc_reader_eventmanager_status_we;
-wire soc_reader_eventmanager_status_w;
-wire soc_reader_eventmanager_pending_re;
-wire soc_reader_eventmanager_pending_r;
-wire soc_reader_eventmanager_pending_we;
-wire soc_reader_eventmanager_pending_w;
-reg soc_reader_eventmanager_storage = 1'd0;
-reg soc_reader_eventmanager_re = 1'd0;
-wire soc_reader_fifo_sink_valid;
-wire soc_reader_fifo_sink_ready;
-reg soc_reader_fifo_sink_first = 1'd0;
-reg soc_reader_fifo_sink_last = 1'd0;
-wire soc_reader_fifo_sink_payload_slot;
-wire [10:0] soc_reader_fifo_sink_payload_length;
-wire soc_reader_fifo_source_valid;
-reg soc_reader_fifo_source_ready = 1'd0;
-wire soc_reader_fifo_source_first;
-wire soc_reader_fifo_source_last;
-wire soc_reader_fifo_source_payload_slot;
-wire [10:0] soc_reader_fifo_source_payload_length;
-wire soc_reader_fifo_syncfifo_we;
-wire soc_reader_fifo_syncfifo_writable;
-wire soc_reader_fifo_syncfifo_re;
-wire soc_reader_fifo_syncfifo_readable;
-wire [13:0] soc_reader_fifo_syncfifo_din;
-wire [13:0] soc_reader_fifo_syncfifo_dout;
-reg [1:0] soc_reader_fifo_level = 2'd0;
-reg soc_reader_fifo_replace = 1'd0;
-reg soc_reader_fifo_produce = 1'd0;
-reg soc_reader_fifo_consume = 1'd0;
-reg soc_reader_fifo_wrport_adr = 1'd0;
-wire [13:0] soc_reader_fifo_wrport_dat_r;
-wire soc_reader_fifo_wrport_we;
-wire [13:0] soc_reader_fifo_wrport_dat_w;
-wire soc_reader_fifo_do_read;
-wire soc_reader_fifo_rdport_adr;
-wire [13:0] soc_reader_fifo_rdport_dat_r;
-wire soc_reader_fifo_fifo_in_payload_slot;
-wire [10:0] soc_reader_fifo_fifo_in_payload_length;
-wire soc_reader_fifo_fifo_in_first;
-wire soc_reader_fifo_fifo_in_last;
-wire soc_reader_fifo_fifo_out_payload_slot;
-wire [10:0] soc_reader_fifo_fifo_out_payload_length;
-wire soc_reader_fifo_fifo_out_first;
-wire soc_reader_fifo_fifo_out_last;
-reg [10:0] soc_reader_counter = 11'd0;
-reg soc_reader_counter_reset = 1'd0;
-reg soc_reader_counter_ce = 1'd0;
-wire soc_reader_last;
-reg soc_reader_last_d = 1'd0;
-wire [8:0] soc_reader_memory0_adr;
-wire [31:0] soc_reader_memory0_dat_r;
-wire [8:0] soc_reader_memory1_adr;
-wire [31:0] soc_reader_memory1_dat_r;
-wire soc_ev_irq;
-wire [29:0] soc_sram0_bus_adr0;
-wire [31:0] soc_sram0_bus_dat_w0;
-wire [31:0] soc_sram0_bus_dat_r0;
-wire [3:0] soc_sram0_bus_sel0;
-wire soc_sram0_bus_cyc0;
-wire soc_sram0_bus_stb0;
-reg soc_sram0_bus_ack0 = 1'd0;
-wire soc_sram0_bus_we0;
-wire [2:0] soc_sram0_bus_cti0;
-wire [1:0] soc_sram0_bus_bte0;
-reg soc_sram0_bus_err0 = 1'd0;
-wire [8:0] soc_sram0_adr0;
-wire [31:0] soc_sram0_dat_r0;
-wire [29:0] soc_sram1_bus_adr0;
-wire [31:0] soc_sram1_bus_dat_w0;
-wire [31:0] soc_sram1_bus_dat_r0;
-wire [3:0] soc_sram1_bus_sel0;
-wire soc_sram1_bus_cyc0;
-wire soc_sram1_bus_stb0;
-reg soc_sram1_bus_ack0 = 1'd0;
-wire soc_sram1_bus_we0;
-wire [2:0] soc_sram1_bus_cti0;
-wire [1:0] soc_sram1_bus_bte0;
-reg soc_sram1_bus_err0 = 1'd0;
-wire [8:0] soc_sram1_adr0;
-wire [31:0] soc_sram1_dat_r0;
-wire [29:0] soc_sram0_bus_adr1;
-wire [31:0] soc_sram0_bus_dat_w1;
-wire [31:0] soc_sram0_bus_dat_r1;
-wire [3:0] soc_sram0_bus_sel1;
-wire soc_sram0_bus_cyc1;
-wire soc_sram0_bus_stb1;
-reg soc_sram0_bus_ack1 = 1'd0;
-wire soc_sram0_bus_we1;
-wire [2:0] soc_sram0_bus_cti1;
-wire [1:0] soc_sram0_bus_bte1;
-reg soc_sram0_bus_err1 = 1'd0;
-wire [8:0] soc_sram0_adr1;
-wire [31:0] soc_sram0_dat_r1;
-reg [3:0] soc_sram0_we = 4'd0;
-wire [31:0] soc_sram0_dat_w;
-wire [29:0] soc_sram1_bus_adr1;
-wire [31:0] soc_sram1_bus_dat_w1;
-wire [31:0] soc_sram1_bus_dat_r1;
-wire [3:0] soc_sram1_bus_sel1;
-wire soc_sram1_bus_cyc1;
-wire soc_sram1_bus_stb1;
-reg soc_sram1_bus_ack1 = 1'd0;
-wire soc_sram1_bus_we1;
-wire [2:0] soc_sram1_bus_cti1;
-wire [1:0] soc_sram1_bus_bte1;
-reg soc_sram1_bus_err1 = 1'd0;
-wire [8:0] soc_sram1_adr1;
-wire [31:0] soc_sram1_dat_r1;
-reg [3:0] soc_sram1_we = 4'd0;
-wire [31:0] soc_sram1_dat_w;
-reg [3:0] soc_slave_sel = 4'd0;
-reg [3:0] soc_slave_sel_r = 4'd0;
-reg vns_wb2csr_state = 1'd0;
-reg vns_wb2csr_next_state = 1'd0;
-reg [1:0] vns_refresher_state = 2'd0;
-reg [1:0] vns_refresher_next_state = 2'd0;
-reg [2:0] vns_bankmachine0_state = 3'd0;
-reg [2:0] vns_bankmachine0_next_state = 3'd0;
-reg [2:0] vns_bankmachine1_state = 3'd0;
-reg [2:0] vns_bankmachine1_next_state = 3'd0;
-reg [2:0] vns_bankmachine2_state = 3'd0;
-reg [2:0] vns_bankmachine2_next_state = 3'd0;
-reg [2:0] vns_bankmachine3_state = 3'd0;
-reg [2:0] vns_bankmachine3_next_state = 3'd0;
-reg [2:0] vns_bankmachine4_state = 3'd0;
-reg [2:0] vns_bankmachine4_next_state = 3'd0;
-reg [2:0] vns_bankmachine5_state = 3'd0;
-reg [2:0] vns_bankmachine5_next_state = 3'd0;
-reg [2:0] vns_bankmachine6_state = 3'd0;
-reg [2:0] vns_bankmachine6_next_state = 3'd0;
-reg [2:0] vns_bankmachine7_state = 3'd0;
-reg [2:0] vns_bankmachine7_next_state = 3'd0;
-reg [3:0] vns_multiplexer_state = 4'd0;
-reg [3:0] vns_multiplexer_next_state = 4'd0;
-wire vns_roundrobin0_request;
-wire vns_roundrobin0_grant;
-wire vns_roundrobin0_ce;
-wire vns_roundrobin1_request;
-wire vns_roundrobin1_grant;
-wire vns_roundrobin1_ce;
-wire vns_roundrobin2_request;
-wire vns_roundrobin2_grant;
-wire vns_roundrobin2_ce;
-wire vns_roundrobin3_request;
-wire vns_roundrobin3_grant;
-wire vns_roundrobin3_ce;
-wire vns_roundrobin4_request;
-wire vns_roundrobin4_grant;
-wire vns_roundrobin4_ce;
-wire vns_roundrobin5_request;
-wire vns_roundrobin5_grant;
-wire vns_roundrobin5_ce;
-wire vns_roundrobin6_request;
-wire vns_roundrobin6_grant;
-wire vns_roundrobin6_ce;
-wire vns_roundrobin7_request;
-wire vns_roundrobin7_grant;
-wire vns_roundrobin7_ce;
-reg [2:0] vns_rbank = 3'd0;
-reg [2:0] vns_wbank = 3'd0;
-reg vns_locked0 = 1'd0;
-reg vns_locked1 = 1'd0;
-reg vns_locked2 = 1'd0;
-reg vns_locked3 = 1'd0;
-reg vns_locked4 = 1'd0;
-reg vns_locked5 = 1'd0;
-reg vns_locked6 = 1'd0;
-reg vns_locked7 = 1'd0;
-reg vns_new_master_wdata_ready0 = 1'd0;
-reg vns_new_master_wdata_ready1 = 1'd0;
-reg vns_new_master_wdata_ready2 = 1'd0;
-reg vns_new_master_rdata_valid0 = 1'd0;
-reg vns_new_master_rdata_valid1 = 1'd0;
-reg vns_new_master_rdata_valid2 = 1'd0;
-reg vns_new_master_rdata_valid3 = 1'd0;
-reg vns_new_master_rdata_valid4 = 1'd0;
-reg vns_new_master_rdata_valid5 = 1'd0;
-reg vns_new_master_rdata_valid6 = 1'd0;
-reg vns_new_master_rdata_valid7 = 1'd0;
-reg vns_new_master_rdata_valid8 = 1'd0;
-reg vns_new_master_rdata_valid9 = 1'd0;
-reg [2:0] vns_fullmemorywe_state = 3'd0;
-reg [2:0] vns_fullmemorywe_next_state = 3'd0;
-reg [1:0] vns_litedramwishbone2native_state = 2'd0;
-reg [1:0] vns_litedramwishbone2native_next_state = 2'd0;
-reg soc_netsoc_count_litedramwishbone2native_next_value = 1'd0;
-reg soc_netsoc_count_litedramwishbone2native_next_value_ce = 1'd0;
-reg vns_liteethmacgap_state = 1'd0;
-reg vns_liteethmacgap_next_state = 1'd0;
-reg [1:0] vns_liteethmacpreambleinserter_state = 2'd0;
-reg [1:0] vns_liteethmacpreambleinserter_next_state = 2'd0;
-reg vns_liteethmacpreamblechecker_state = 1'd0;
-reg vns_liteethmacpreamblechecker_next_state = 1'd0;
-reg [1:0] vns_liteethmaccrc32inserter_state = 2'd0;
-reg [1:0] vns_liteethmaccrc32inserter_next_state = 2'd0;
-reg [1:0] vns_liteethmaccrc32checker_state = 2'd0;
-reg [1:0] vns_liteethmaccrc32checker_next_state = 2'd0;
-reg vns_liteethmacpaddinginserter_state = 1'd0;
-reg vns_liteethmacpaddinginserter_next_state = 1'd0;
-reg [2:0] vns_liteethmacsramwriter_state = 3'd0;
-reg [2:0] vns_liteethmacsramwriter_next_state = 3'd0;
-reg [31:0] soc_writer_errors_status_liteethmac_next_value = 32'd0;
-reg soc_writer_errors_status_liteethmac_next_value_ce = 1'd0;
-reg [1:0] vns_liteethmacsramreader_state = 2'd0;
-reg [1:0] vns_liteethmacsramreader_next_state = 2'd0;
-wire vns_wb_sdram_con_request;
-wire vns_wb_sdram_con_grant;
-wire [29:0] vns_netsoc_shared_adr;
-wire [31:0] vns_netsoc_shared_dat_w;
-reg [31:0] vns_netsoc_shared_dat_r = 32'd0;
-wire [3:0] vns_netsoc_shared_sel;
-wire vns_netsoc_shared_cyc;
-wire vns_netsoc_shared_stb;
-reg vns_netsoc_shared_ack = 1'd0;
-wire vns_netsoc_shared_we;
-wire [2:0] vns_netsoc_shared_cti;
-wire [1:0] vns_netsoc_shared_bte;
-wire vns_netsoc_shared_err;
-wire [1:0] vns_netsoc_request;
-reg vns_netsoc_grant = 1'd0;
-reg [5:0] vns_netsoc_slave_sel = 6'd0;
-reg [5:0] vns_netsoc_slave_sel_r = 6'd0;
-reg vns_netsoc_error = 1'd0;
-wire vns_netsoc_wait;
-wire vns_netsoc_done;
-reg [19:0] vns_netsoc_count = 20'd1000000;
-wire [13:0] vns_netsoc_csrbankarray_interface0_bank_bus_adr;
-wire vns_netsoc_csrbankarray_interface0_bank_bus_we;
-wire [7:0] vns_netsoc_csrbankarray_interface0_bank_bus_dat_w;
-reg [7:0] vns_netsoc_csrbankarray_interface0_bank_bus_dat_r = 8'd0;
-wire vns_netsoc_csrbankarray_csrbank0_timer_time7_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time7_r;
-wire vns_netsoc_csrbankarray_csrbank0_timer_time7_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time7_w;
-wire vns_netsoc_csrbankarray_csrbank0_timer_time6_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time6_r;
-wire vns_netsoc_csrbankarray_csrbank0_timer_time6_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time6_w;
-wire vns_netsoc_csrbankarray_csrbank0_timer_time5_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time5_r;
-wire vns_netsoc_csrbankarray_csrbank0_timer_time5_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time5_w;
-wire vns_netsoc_csrbankarray_csrbank0_timer_time4_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time4_r;
-wire vns_netsoc_csrbankarray_csrbank0_timer_time4_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time4_w;
-wire vns_netsoc_csrbankarray_csrbank0_timer_time3_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time3_r;
-wire vns_netsoc_csrbankarray_csrbank0_timer_time3_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time3_w;
-wire vns_netsoc_csrbankarray_csrbank0_timer_time2_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time2_r;
-wire vns_netsoc_csrbankarray_csrbank0_timer_time2_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time2_w;
-wire vns_netsoc_csrbankarray_csrbank0_timer_time1_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time1_r;
-wire vns_netsoc_csrbankarray_csrbank0_timer_time1_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time1_w;
-wire vns_netsoc_csrbankarray_csrbank0_timer_time0_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time0_r;
-wire vns_netsoc_csrbankarray_csrbank0_timer_time0_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time0_w;
-wire vns_netsoc_csrbankarray_csrbank0_timer_time_cmp7_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time_cmp7_r;
-wire vns_netsoc_csrbankarray_csrbank0_timer_time_cmp7_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time_cmp7_w;
-wire vns_netsoc_csrbankarray_csrbank0_timer_time_cmp6_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time_cmp6_r;
-wire vns_netsoc_csrbankarray_csrbank0_timer_time_cmp6_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time_cmp6_w;
-wire vns_netsoc_csrbankarray_csrbank0_timer_time_cmp5_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time_cmp5_r;
-wire vns_netsoc_csrbankarray_csrbank0_timer_time_cmp5_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time_cmp5_w;
-wire vns_netsoc_csrbankarray_csrbank0_timer_time_cmp4_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time_cmp4_r;
-wire vns_netsoc_csrbankarray_csrbank0_timer_time_cmp4_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time_cmp4_w;
-wire vns_netsoc_csrbankarray_csrbank0_timer_time_cmp3_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time_cmp3_r;
-wire vns_netsoc_csrbankarray_csrbank0_timer_time_cmp3_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time_cmp3_w;
-wire vns_netsoc_csrbankarray_csrbank0_timer_time_cmp2_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time_cmp2_r;
-wire vns_netsoc_csrbankarray_csrbank0_timer_time_cmp2_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time_cmp2_w;
-wire vns_netsoc_csrbankarray_csrbank0_timer_time_cmp1_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time_cmp1_r;
-wire vns_netsoc_csrbankarray_csrbank0_timer_time_cmp1_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time_cmp1_w;
-wire vns_netsoc_csrbankarray_csrbank0_timer_time_cmp0_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time_cmp0_r;
-wire vns_netsoc_csrbankarray_csrbank0_timer_time_cmp0_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time_cmp0_w;
-wire vns_netsoc_csrbankarray_csrbank0_sel;
-wire [13:0] vns_netsoc_csrbankarray_interface1_bank_bus_adr;
-wire vns_netsoc_csrbankarray_interface1_bank_bus_we;
-wire [7:0] vns_netsoc_csrbankarray_interface1_bank_bus_dat_w;
-reg [7:0] vns_netsoc_csrbankarray_interface1_bank_bus_dat_r = 8'd0;
-wire vns_netsoc_csrbankarray_csrbank1_scratch3_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank1_scratch3_r;
-wire vns_netsoc_csrbankarray_csrbank1_scratch3_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank1_scratch3_w;
-wire vns_netsoc_csrbankarray_csrbank1_scratch2_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank1_scratch2_r;
-wire vns_netsoc_csrbankarray_csrbank1_scratch2_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank1_scratch2_w;
-wire vns_netsoc_csrbankarray_csrbank1_scratch1_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank1_scratch1_r;
-wire vns_netsoc_csrbankarray_csrbank1_scratch1_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank1_scratch1_w;
-wire vns_netsoc_csrbankarray_csrbank1_scratch0_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank1_scratch0_r;
-wire vns_netsoc_csrbankarray_csrbank1_scratch0_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank1_scratch0_w;
-wire vns_netsoc_csrbankarray_csrbank1_bus_errors3_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank1_bus_errors3_r;
-wire vns_netsoc_csrbankarray_csrbank1_bus_errors3_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank1_bus_errors3_w;
-wire vns_netsoc_csrbankarray_csrbank1_bus_errors2_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank1_bus_errors2_r;
-wire vns_netsoc_csrbankarray_csrbank1_bus_errors2_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank1_bus_errors2_w;
-wire vns_netsoc_csrbankarray_csrbank1_bus_errors1_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank1_bus_errors1_r;
-wire vns_netsoc_csrbankarray_csrbank1_bus_errors1_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank1_bus_errors1_w;
-wire vns_netsoc_csrbankarray_csrbank1_bus_errors0_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank1_bus_errors0_r;
-wire vns_netsoc_csrbankarray_csrbank1_bus_errors0_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank1_bus_errors0_w;
-wire vns_netsoc_csrbankarray_csrbank1_sel;
-wire [13:0] vns_netsoc_csrbankarray_interface2_bank_bus_adr;
-wire vns_netsoc_csrbankarray_interface2_bank_bus_we;
-wire [7:0] vns_netsoc_csrbankarray_interface2_bank_bus_dat_w;
-reg [7:0] vns_netsoc_csrbankarray_interface2_bank_bus_dat_r = 8'd0;
-wire vns_netsoc_csrbankarray_csrbank2_half_sys8x_taps0_re;
-wire [4:0] vns_netsoc_csrbankarray_csrbank2_half_sys8x_taps0_r;
-wire vns_netsoc_csrbankarray_csrbank2_half_sys8x_taps0_we;
-wire [4:0] vns_netsoc_csrbankarray_csrbank2_half_sys8x_taps0_w;
-wire vns_netsoc_csrbankarray_csrbank2_dly_sel0_re;
-wire [1:0] vns_netsoc_csrbankarray_csrbank2_dly_sel0_r;
-wire vns_netsoc_csrbankarray_csrbank2_dly_sel0_we;
-wire [1:0] vns_netsoc_csrbankarray_csrbank2_dly_sel0_w;
-wire vns_netsoc_csrbankarray_csrbank2_sel;
-wire [13:0] vns_netsoc_csrbankarray_interface3_bank_bus_adr;
-wire vns_netsoc_csrbankarray_interface3_bank_bus_we;
-wire [7:0] vns_netsoc_csrbankarray_interface3_bank_bus_dat_w;
-reg [7:0] vns_netsoc_csrbankarray_interface3_bank_bus_dat_r = 8'd0;
-wire vns_netsoc_csrbankarray_csrbank3_sram_writer_slot_re;
-wire vns_netsoc_csrbankarray_csrbank3_sram_writer_slot_r;
-wire vns_netsoc_csrbankarray_csrbank3_sram_writer_slot_we;
-wire vns_netsoc_csrbankarray_csrbank3_sram_writer_slot_w;
-wire vns_netsoc_csrbankarray_csrbank3_sram_writer_length3_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank3_sram_writer_length3_r;
-wire vns_netsoc_csrbankarray_csrbank3_sram_writer_length3_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank3_sram_writer_length3_w;
-wire vns_netsoc_csrbankarray_csrbank3_sram_writer_length2_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank3_sram_writer_length2_r;
-wire vns_netsoc_csrbankarray_csrbank3_sram_writer_length2_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank3_sram_writer_length2_w;
-wire vns_netsoc_csrbankarray_csrbank3_sram_writer_length1_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank3_sram_writer_length1_r;
-wire vns_netsoc_csrbankarray_csrbank3_sram_writer_length1_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank3_sram_writer_length1_w;
-wire vns_netsoc_csrbankarray_csrbank3_sram_writer_length0_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank3_sram_writer_length0_r;
-wire vns_netsoc_csrbankarray_csrbank3_sram_writer_length0_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank3_sram_writer_length0_w;
-wire vns_netsoc_csrbankarray_csrbank3_sram_writer_errors3_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank3_sram_writer_errors3_r;
-wire vns_netsoc_csrbankarray_csrbank3_sram_writer_errors3_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank3_sram_writer_errors3_w;
-wire vns_netsoc_csrbankarray_csrbank3_sram_writer_errors2_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank3_sram_writer_errors2_r;
-wire vns_netsoc_csrbankarray_csrbank3_sram_writer_errors2_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank3_sram_writer_errors2_w;
-wire vns_netsoc_csrbankarray_csrbank3_sram_writer_errors1_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank3_sram_writer_errors1_r;
-wire vns_netsoc_csrbankarray_csrbank3_sram_writer_errors1_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank3_sram_writer_errors1_w;
-wire vns_netsoc_csrbankarray_csrbank3_sram_writer_errors0_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank3_sram_writer_errors0_r;
-wire vns_netsoc_csrbankarray_csrbank3_sram_writer_errors0_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank3_sram_writer_errors0_w;
-wire vns_netsoc_csrbankarray_csrbank3_sram_writer_ev_enable0_re;
-wire vns_netsoc_csrbankarray_csrbank3_sram_writer_ev_enable0_r;
-wire vns_netsoc_csrbankarray_csrbank3_sram_writer_ev_enable0_we;
-wire vns_netsoc_csrbankarray_csrbank3_sram_writer_ev_enable0_w;
-wire vns_netsoc_csrbankarray_csrbank3_sram_reader_ready_re;
-wire vns_netsoc_csrbankarray_csrbank3_sram_reader_ready_r;
-wire vns_netsoc_csrbankarray_csrbank3_sram_reader_ready_we;
-wire vns_netsoc_csrbankarray_csrbank3_sram_reader_ready_w;
-wire vns_netsoc_csrbankarray_csrbank3_sram_reader_level_re;
-wire [1:0] vns_netsoc_csrbankarray_csrbank3_sram_reader_level_r;
-wire vns_netsoc_csrbankarray_csrbank3_sram_reader_level_we;
-wire [1:0] vns_netsoc_csrbankarray_csrbank3_sram_reader_level_w;
-wire vns_netsoc_csrbankarray_csrbank3_sram_reader_slot0_re;
-wire vns_netsoc_csrbankarray_csrbank3_sram_reader_slot0_r;
-wire vns_netsoc_csrbankarray_csrbank3_sram_reader_slot0_we;
-wire vns_netsoc_csrbankarray_csrbank3_sram_reader_slot0_w;
-wire vns_netsoc_csrbankarray_csrbank3_sram_reader_length1_re;
-wire [2:0] vns_netsoc_csrbankarray_csrbank3_sram_reader_length1_r;
-wire vns_netsoc_csrbankarray_csrbank3_sram_reader_length1_we;
-wire [2:0] vns_netsoc_csrbankarray_csrbank3_sram_reader_length1_w;
-wire vns_netsoc_csrbankarray_csrbank3_sram_reader_length0_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank3_sram_reader_length0_r;
-wire vns_netsoc_csrbankarray_csrbank3_sram_reader_length0_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank3_sram_reader_length0_w;
-wire vns_netsoc_csrbankarray_csrbank3_sram_reader_ev_enable0_re;
-wire vns_netsoc_csrbankarray_csrbank3_sram_reader_ev_enable0_r;
-wire vns_netsoc_csrbankarray_csrbank3_sram_reader_ev_enable0_we;
-wire vns_netsoc_csrbankarray_csrbank3_sram_reader_ev_enable0_w;
-wire vns_netsoc_csrbankarray_csrbank3_preamble_crc_re;
-wire vns_netsoc_csrbankarray_csrbank3_preamble_crc_r;
-wire vns_netsoc_csrbankarray_csrbank3_preamble_crc_we;
-wire vns_netsoc_csrbankarray_csrbank3_preamble_crc_w;
-wire vns_netsoc_csrbankarray_csrbank3_preamble_errors3_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank3_preamble_errors3_r;
-wire vns_netsoc_csrbankarray_csrbank3_preamble_errors3_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank3_preamble_errors3_w;
-wire vns_netsoc_csrbankarray_csrbank3_preamble_errors2_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank3_preamble_errors2_r;
-wire vns_netsoc_csrbankarray_csrbank3_preamble_errors2_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank3_preamble_errors2_w;
-wire vns_netsoc_csrbankarray_csrbank3_preamble_errors1_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank3_preamble_errors1_r;
-wire vns_netsoc_csrbankarray_csrbank3_preamble_errors1_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank3_preamble_errors1_w;
-wire vns_netsoc_csrbankarray_csrbank3_preamble_errors0_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank3_preamble_errors0_r;
-wire vns_netsoc_csrbankarray_csrbank3_preamble_errors0_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank3_preamble_errors0_w;
-wire vns_netsoc_csrbankarray_csrbank3_crc_errors3_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank3_crc_errors3_r;
-wire vns_netsoc_csrbankarray_csrbank3_crc_errors3_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank3_crc_errors3_w;
-wire vns_netsoc_csrbankarray_csrbank3_crc_errors2_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank3_crc_errors2_r;
-wire vns_netsoc_csrbankarray_csrbank3_crc_errors2_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank3_crc_errors2_w;
-wire vns_netsoc_csrbankarray_csrbank3_crc_errors1_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank3_crc_errors1_r;
-wire vns_netsoc_csrbankarray_csrbank3_crc_errors1_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank3_crc_errors1_w;
-wire vns_netsoc_csrbankarray_csrbank3_crc_errors0_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank3_crc_errors0_r;
-wire vns_netsoc_csrbankarray_csrbank3_crc_errors0_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank3_crc_errors0_w;
-wire vns_netsoc_csrbankarray_csrbank3_sel;
-wire [13:0] vns_netsoc_csrbankarray_interface4_bank_bus_adr;
-wire vns_netsoc_csrbankarray_interface4_bank_bus_we;
-wire [7:0] vns_netsoc_csrbankarray_interface4_bank_bus_dat_w;
-reg [7:0] vns_netsoc_csrbankarray_interface4_bank_bus_dat_r = 8'd0;
-wire vns_netsoc_csrbankarray_csrbank4_crg_reset0_re;
-wire vns_netsoc_csrbankarray_csrbank4_crg_reset0_r;
-wire vns_netsoc_csrbankarray_csrbank4_crg_reset0_we;
-wire vns_netsoc_csrbankarray_csrbank4_crg_reset0_w;
-wire vns_netsoc_csrbankarray_csrbank4_mdio_w0_re;
-wire [2:0] vns_netsoc_csrbankarray_csrbank4_mdio_w0_r;
-wire vns_netsoc_csrbankarray_csrbank4_mdio_w0_we;
-wire [2:0] vns_netsoc_csrbankarray_csrbank4_mdio_w0_w;
-wire vns_netsoc_csrbankarray_csrbank4_mdio_r_re;
-wire vns_netsoc_csrbankarray_csrbank4_mdio_r_r;
-wire vns_netsoc_csrbankarray_csrbank4_mdio_r_we;
-wire vns_netsoc_csrbankarray_csrbank4_mdio_r_w;
-wire vns_netsoc_csrbankarray_csrbank4_sel;
-wire [13:0] vns_netsoc_csrbankarray_sram_bus_adr;
-wire vns_netsoc_csrbankarray_sram_bus_we;
-wire [7:0] vns_netsoc_csrbankarray_sram_bus_dat_w;
-reg [7:0] vns_netsoc_csrbankarray_sram_bus_dat_r = 8'd0;
-wire [2:0] vns_netsoc_csrbankarray_adr;
-wire [7:0] vns_netsoc_csrbankarray_dat_r;
-wire vns_netsoc_csrbankarray_sel;
-reg vns_netsoc_csrbankarray_sel_r = 1'd0;
-wire [13:0] vns_netsoc_csrbankarray_interface5_bank_bus_adr;
-wire vns_netsoc_csrbankarray_interface5_bank_bus_we;
-wire [7:0] vns_netsoc_csrbankarray_interface5_bank_bus_dat_w;
-reg [7:0] vns_netsoc_csrbankarray_interface5_bank_bus_dat_r = 8'd0;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_control0_re;
-wire [3:0] vns_netsoc_csrbankarray_csrbank5_dfii_control0_r;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_control0_we;
-wire [3:0] vns_netsoc_csrbankarray_csrbank5_dfii_control0_w;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi0_command0_re;
-wire [5:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi0_command0_r;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi0_command0_we;
-wire [5:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi0_command0_w;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi0_address1_re;
-wire [5:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi0_address1_r;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi0_address1_we;
-wire [5:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi0_address1_w;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi0_address0_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi0_address0_r;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi0_address0_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi0_address0_w;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi0_baddress0_re;
-wire [2:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi0_baddress0_r;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi0_baddress0_we;
-wire [2:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi0_baddress0_w;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata3_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata3_r;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata3_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata3_w;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata2_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata2_r;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata2_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata2_w;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata1_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata1_r;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata1_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata1_w;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata0_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata0_r;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata0_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata0_w;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata3_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata3_r;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata3_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata3_w;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata2_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata2_r;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata2_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata2_w;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata1_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata1_r;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata1_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata1_w;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata0_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata0_r;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata0_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata0_w;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi1_command0_re;
-wire [5:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi1_command0_r;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi1_command0_we;
-wire [5:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi1_command0_w;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi1_address1_re;
-wire [5:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi1_address1_r;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi1_address1_we;
-wire [5:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi1_address1_w;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi1_address0_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi1_address0_r;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi1_address0_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi1_address0_w;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi1_baddress0_re;
-wire [2:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi1_baddress0_r;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi1_baddress0_we;
-wire [2:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi1_baddress0_w;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata3_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata3_r;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata3_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata3_w;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata2_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata2_r;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata2_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata2_w;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata1_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata1_r;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata1_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata1_w;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata0_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata0_r;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata0_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata0_w;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata3_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata3_r;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata3_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata3_w;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata2_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata2_r;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata2_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata2_w;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata1_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata1_r;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata1_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata1_w;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata0_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata0_r;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata0_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata0_w;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi2_command0_re;
-wire [5:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi2_command0_r;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi2_command0_we;
-wire [5:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi2_command0_w;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi2_address1_re;
-wire [5:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi2_address1_r;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi2_address1_we;
-wire [5:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi2_address1_w;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi2_address0_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi2_address0_r;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi2_address0_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi2_address0_w;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi2_baddress0_re;
-wire [2:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi2_baddress0_r;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi2_baddress0_we;
-wire [2:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi2_baddress0_w;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata3_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata3_r;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata3_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata3_w;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata2_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata2_r;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata2_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata2_w;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata1_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata1_r;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata1_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata1_w;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata0_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata0_r;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata0_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata0_w;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata3_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata3_r;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata3_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata3_w;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata2_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata2_r;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata2_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata2_w;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata1_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata1_r;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata1_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata1_w;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata0_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata0_r;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata0_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata0_w;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi3_command0_re;
-wire [5:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi3_command0_r;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi3_command0_we;
-wire [5:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi3_command0_w;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi3_address1_re;
-wire [5:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi3_address1_r;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi3_address1_we;
-wire [5:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi3_address1_w;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi3_address0_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi3_address0_r;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi3_address0_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi3_address0_w;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi3_baddress0_re;
-wire [2:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi3_baddress0_r;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi3_baddress0_we;
-wire [2:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi3_baddress0_w;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata3_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata3_r;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata3_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata3_w;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata2_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata2_r;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata2_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata2_w;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata1_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata1_r;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata1_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata1_w;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata0_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata0_r;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata0_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata0_w;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata3_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata3_r;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata3_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata3_w;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata2_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata2_r;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata2_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata2_w;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata1_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata1_r;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata1_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata1_w;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata0_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata0_r;
-wire vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata0_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata0_w;
-wire vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nreads2_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nreads2_r;
-wire vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nreads2_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nreads2_w;
-wire vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nreads1_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nreads1_r;
-wire vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nreads1_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nreads1_w;
-wire vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nreads0_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nreads0_r;
-wire vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nreads0_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nreads0_w;
-wire vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nwrites2_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nwrites2_r;
-wire vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nwrites2_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nwrites2_w;
-wire vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nwrites1_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nwrites1_r;
-wire vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nwrites1_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nwrites1_w;
-wire vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nwrites0_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nwrites0_r;
-wire vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nwrites0_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nwrites0_w;
-wire vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_data_width_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_data_width_r;
-wire vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_data_width_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_data_width_w;
-wire vns_netsoc_csrbankarray_csrbank5_sel;
-wire [13:0] vns_netsoc_csrbankarray_interface6_bank_bus_adr;
-wire vns_netsoc_csrbankarray_interface6_bank_bus_we;
-wire [7:0] vns_netsoc_csrbankarray_interface6_bank_bus_dat_w;
-reg [7:0] vns_netsoc_csrbankarray_interface6_bank_bus_dat_r = 8'd0;
-wire vns_netsoc_csrbankarray_csrbank6_load3_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank6_load3_r;
-wire vns_netsoc_csrbankarray_csrbank6_load3_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank6_load3_w;
-wire vns_netsoc_csrbankarray_csrbank6_load2_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank6_load2_r;
-wire vns_netsoc_csrbankarray_csrbank6_load2_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank6_load2_w;
-wire vns_netsoc_csrbankarray_csrbank6_load1_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank6_load1_r;
-wire vns_netsoc_csrbankarray_csrbank6_load1_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank6_load1_w;
-wire vns_netsoc_csrbankarray_csrbank6_load0_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank6_load0_r;
-wire vns_netsoc_csrbankarray_csrbank6_load0_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank6_load0_w;
-wire vns_netsoc_csrbankarray_csrbank6_reload3_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank6_reload3_r;
-wire vns_netsoc_csrbankarray_csrbank6_reload3_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank6_reload3_w;
-wire vns_netsoc_csrbankarray_csrbank6_reload2_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank6_reload2_r;
-wire vns_netsoc_csrbankarray_csrbank6_reload2_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank6_reload2_w;
-wire vns_netsoc_csrbankarray_csrbank6_reload1_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank6_reload1_r;
-wire vns_netsoc_csrbankarray_csrbank6_reload1_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank6_reload1_w;
-wire vns_netsoc_csrbankarray_csrbank6_reload0_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank6_reload0_r;
-wire vns_netsoc_csrbankarray_csrbank6_reload0_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank6_reload0_w;
-wire vns_netsoc_csrbankarray_csrbank6_en0_re;
-wire vns_netsoc_csrbankarray_csrbank6_en0_r;
-wire vns_netsoc_csrbankarray_csrbank6_en0_we;
-wire vns_netsoc_csrbankarray_csrbank6_en0_w;
-wire vns_netsoc_csrbankarray_csrbank6_update_value0_re;
-wire vns_netsoc_csrbankarray_csrbank6_update_value0_r;
-wire vns_netsoc_csrbankarray_csrbank6_update_value0_we;
-wire vns_netsoc_csrbankarray_csrbank6_update_value0_w;
-wire vns_netsoc_csrbankarray_csrbank6_value3_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank6_value3_r;
-wire vns_netsoc_csrbankarray_csrbank6_value3_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank6_value3_w;
-wire vns_netsoc_csrbankarray_csrbank6_value2_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank6_value2_r;
-wire vns_netsoc_csrbankarray_csrbank6_value2_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank6_value2_w;
-wire vns_netsoc_csrbankarray_csrbank6_value1_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank6_value1_r;
-wire vns_netsoc_csrbankarray_csrbank6_value1_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank6_value1_w;
-wire vns_netsoc_csrbankarray_csrbank6_value0_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank6_value0_r;
-wire vns_netsoc_csrbankarray_csrbank6_value0_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank6_value0_w;
-wire vns_netsoc_csrbankarray_csrbank6_ev_enable0_re;
-wire vns_netsoc_csrbankarray_csrbank6_ev_enable0_r;
-wire vns_netsoc_csrbankarray_csrbank6_ev_enable0_we;
-wire vns_netsoc_csrbankarray_csrbank6_ev_enable0_w;
-wire vns_netsoc_csrbankarray_csrbank6_sel;
-wire [13:0] vns_netsoc_csrbankarray_interface7_bank_bus_adr;
-wire vns_netsoc_csrbankarray_interface7_bank_bus_we;
-wire [7:0] vns_netsoc_csrbankarray_interface7_bank_bus_dat_w;
-reg [7:0] vns_netsoc_csrbankarray_interface7_bank_bus_dat_r = 8'd0;
-wire vns_netsoc_csrbankarray_csrbank7_txfull_re;
-wire vns_netsoc_csrbankarray_csrbank7_txfull_r;
-wire vns_netsoc_csrbankarray_csrbank7_txfull_we;
-wire vns_netsoc_csrbankarray_csrbank7_txfull_w;
-wire vns_netsoc_csrbankarray_csrbank7_rxempty_re;
-wire vns_netsoc_csrbankarray_csrbank7_rxempty_r;
-wire vns_netsoc_csrbankarray_csrbank7_rxempty_we;
-wire vns_netsoc_csrbankarray_csrbank7_rxempty_w;
-wire vns_netsoc_csrbankarray_csrbank7_ev_enable0_re;
-wire [1:0] vns_netsoc_csrbankarray_csrbank7_ev_enable0_r;
-wire vns_netsoc_csrbankarray_csrbank7_ev_enable0_we;
-wire [1:0] vns_netsoc_csrbankarray_csrbank7_ev_enable0_w;
-wire vns_netsoc_csrbankarray_csrbank7_sel;
-wire [13:0] vns_netsoc_csrbankarray_interface8_bank_bus_adr;
-wire vns_netsoc_csrbankarray_interface8_bank_bus_we;
-wire [7:0] vns_netsoc_csrbankarray_interface8_bank_bus_dat_w;
-reg [7:0] vns_netsoc_csrbankarray_interface8_bank_bus_dat_r = 8'd0;
-wire vns_netsoc_csrbankarray_csrbank8_tuning_word3_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank8_tuning_word3_r;
-wire vns_netsoc_csrbankarray_csrbank8_tuning_word3_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank8_tuning_word3_w;
-wire vns_netsoc_csrbankarray_csrbank8_tuning_word2_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank8_tuning_word2_r;
-wire vns_netsoc_csrbankarray_csrbank8_tuning_word2_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank8_tuning_word2_w;
-wire vns_netsoc_csrbankarray_csrbank8_tuning_word1_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank8_tuning_word1_r;
-wire vns_netsoc_csrbankarray_csrbank8_tuning_word1_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank8_tuning_word1_w;
-wire vns_netsoc_csrbankarray_csrbank8_tuning_word0_re;
-wire [7:0] vns_netsoc_csrbankarray_csrbank8_tuning_word0_r;
-wire vns_netsoc_csrbankarray_csrbank8_tuning_word0_we;
-wire [7:0] vns_netsoc_csrbankarray_csrbank8_tuning_word0_w;
-wire vns_netsoc_csrbankarray_csrbank8_sel;
-wire [13:0] vns_netsoc_csrcon_adr;
-wire vns_netsoc_csrcon_we;
-wire [7:0] vns_netsoc_csrcon_dat_w;
-wire [7:0] vns_netsoc_csrcon_dat_r;
-reg vns_rhs_array_muxed0 = 1'd0;
-reg [13:0] vns_rhs_array_muxed1 = 14'd0;
-reg [2:0] vns_rhs_array_muxed2 = 3'd0;
-reg vns_rhs_array_muxed3 = 1'd0;
-reg vns_rhs_array_muxed4 = 1'd0;
-reg vns_rhs_array_muxed5 = 1'd0;
-reg vns_t_array_muxed0 = 1'd0;
-reg vns_t_array_muxed1 = 1'd0;
-reg vns_t_array_muxed2 = 1'd0;
-reg vns_rhs_array_muxed6 = 1'd0;
-reg [13:0] vns_rhs_array_muxed7 = 14'd0;
-reg [2:0] vns_rhs_array_muxed8 = 3'd0;
-reg vns_rhs_array_muxed9 = 1'd0;
-reg vns_rhs_array_muxed10 = 1'd0;
-reg vns_rhs_array_muxed11 = 1'd0;
-reg vns_t_array_muxed3 = 1'd0;
-reg vns_t_array_muxed4 = 1'd0;
-reg vns_t_array_muxed5 = 1'd0;
-reg [20:0] vns_rhs_array_muxed12 = 21'd0;
-reg vns_rhs_array_muxed13 = 1'd0;
-reg vns_rhs_array_muxed14 = 1'd0;
-reg [20:0] vns_rhs_array_muxed15 = 21'd0;
-reg vns_rhs_array_muxed16 = 1'd0;
-reg vns_rhs_array_muxed17 = 1'd0;
-reg [20:0] vns_rhs_array_muxed18 = 21'd0;
-reg vns_rhs_array_muxed19 = 1'd0;
-reg vns_rhs_array_muxed20 = 1'd0;
-reg [20:0] vns_rhs_array_muxed21 = 21'd0;
-reg vns_rhs_array_muxed22 = 1'd0;
-reg vns_rhs_array_muxed23 = 1'd0;
-reg [20:0] vns_rhs_array_muxed24 = 21'd0;
-reg vns_rhs_array_muxed25 = 1'd0;
-reg vns_rhs_array_muxed26 = 1'd0;
-reg [20:0] vns_rhs_array_muxed27 = 21'd0;
-reg vns_rhs_array_muxed28 = 1'd0;
-reg vns_rhs_array_muxed29 = 1'd0;
-reg [20:0] vns_rhs_array_muxed30 = 21'd0;
-reg vns_rhs_array_muxed31 = 1'd0;
-reg vns_rhs_array_muxed32 = 1'd0;
-reg [20:0] vns_rhs_array_muxed33 = 21'd0;
-reg vns_rhs_array_muxed34 = 1'd0;
-reg vns_rhs_array_muxed35 = 1'd0;
-reg [29:0] vns_rhs_array_muxed36 = 30'd0;
-reg [31:0] vns_rhs_array_muxed37 = 32'd0;
-reg [3:0] vns_rhs_array_muxed38 = 4'd0;
-reg vns_rhs_array_muxed39 = 1'd0;
-reg vns_rhs_array_muxed40 = 1'd0;
-reg vns_rhs_array_muxed41 = 1'd0;
-reg [2:0] vns_rhs_array_muxed42 = 3'd0;
-reg [1:0] vns_rhs_array_muxed43 = 2'd0;
-reg [29:0] vns_rhs_array_muxed44 = 30'd0;
-reg [31:0] vns_rhs_array_muxed45 = 32'd0;
-reg [3:0] vns_rhs_array_muxed46 = 4'd0;
-reg vns_rhs_array_muxed47 = 1'd0;
-reg vns_rhs_array_muxed48 = 1'd0;
-reg vns_rhs_array_muxed49 = 1'd0;
-reg [2:0] vns_rhs_array_muxed50 = 3'd0;
-reg [1:0] vns_rhs_array_muxed51 = 2'd0;
-reg [2:0] vns_array_muxed0 = 3'd0;
-reg [13:0] vns_array_muxed1 = 14'd0;
-reg vns_array_muxed2 = 1'd0;
-reg vns_array_muxed3 = 1'd0;
-reg vns_array_muxed4 = 1'd0;
-reg vns_array_muxed5 = 1'd0;
-reg vns_array_muxed6 = 1'd0;
-reg [2:0] vns_array_muxed7 = 3'd0;
-reg [13:0] vns_array_muxed8 = 14'd0;
-reg vns_array_muxed9 = 1'd0;
-reg vns_array_muxed10 = 1'd0;
-reg vns_array_muxed11 = 1'd0;
-reg vns_array_muxed12 = 1'd0;
-reg vns_array_muxed13 = 1'd0;
-reg [2:0] vns_array_muxed14 = 3'd0;
-reg [13:0] vns_array_muxed15 = 14'd0;
-reg vns_array_muxed16 = 1'd0;
-reg vns_array_muxed17 = 1'd0;
-reg vns_array_muxed18 = 1'd0;
-reg vns_array_muxed19 = 1'd0;
-reg vns_array_muxed20 = 1'd0;
-reg [2:0] vns_array_muxed21 = 3'd0;
-reg [13:0] vns_array_muxed22 = 14'd0;
-reg vns_array_muxed23 = 1'd0;
-reg vns_array_muxed24 = 1'd0;
-reg vns_array_muxed25 = 1'd0;
-reg vns_array_muxed26 = 1'd0;
-reg vns_array_muxed27 = 1'd0;
-(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg vns_xilinxmultiregimpl0_regs0 = 1'd0;
-(* async_reg = "true", dont_touch = "true" *) reg vns_xilinxmultiregimpl0_regs1 = 1'd0;
-wire vns_xilinxasyncresetsynchronizerimpl0;
-wire vns_xilinxasyncresetsynchronizerimpl0_rst_meta;
-wire vns_xilinxasyncresetsynchronizerimpl1;
-wire vns_xilinxasyncresetsynchronizerimpl1_rst_meta;
-wire vns_xilinxasyncresetsynchronizerimpl2_rst_meta;
-wire vns_xilinxasyncresetsynchronizerimpl3_rst_meta;
-(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg vns_xilinxmultiregimpl1_regs0 = 1'd0;
-(* async_reg = "true", dont_touch = "true" *) reg vns_xilinxmultiregimpl1_regs1 = 1'd0;
-(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg vns_xilinxmultiregimpl2_regs0 = 1'd0;
-(* async_reg = "true", dont_touch = "true" *) reg vns_xilinxmultiregimpl2_regs1 = 1'd0;
-(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg vns_xilinxmultiregimpl3_regs0 = 1'd0;
-(* async_reg = "true", dont_touch = "true" *) reg vns_xilinxmultiregimpl3_regs1 = 1'd0;
-(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [6:0] vns_xilinxmultiregimpl4_regs0 = 7'd0;
-(* async_reg = "true", dont_touch = "true" *) reg [6:0] vns_xilinxmultiregimpl4_regs1 = 7'd0;
-(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [6:0] vns_xilinxmultiregimpl5_regs0 = 7'd0;
-(* async_reg = "true", dont_touch = "true" *) reg [6:0] vns_xilinxmultiregimpl5_regs1 = 7'd0;
-(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [6:0] vns_xilinxmultiregimpl6_regs0 = 7'd0;
-(* async_reg = "true", dont_touch = "true" *) reg [6:0] vns_xilinxmultiregimpl6_regs1 = 7'd0;
-(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [6:0] vns_xilinxmultiregimpl7_regs0 = 7'd0;
-(* async_reg = "true", dont_touch = "true" *) reg [6:0] vns_xilinxmultiregimpl7_regs1 = 7'd0;
-
-assign soc_netsoc_cpu_reset = soc_netsoc_ctrl_reset;
-assign soc_netsoc_ctrl_bus_error = vns_netsoc_error;
-always @(*) begin
-	soc_netsoc_cpu_interrupt0 <= 32'd0;
-	soc_netsoc_cpu_interrupt0[2] <= soc_ev_irq;
-	soc_netsoc_cpu_interrupt0[1] <= soc_netsoc_timer0_irq;
-	soc_netsoc_cpu_interrupt0[0] <= soc_netsoc_uart_irq;
-end
-assign soc_netsoc_ctrl_reset = soc_netsoc_ctrl_reset_reset_re;
-assign soc_netsoc_ctrl_bus_errors_status = soc_netsoc_ctrl_bus_errors;
-assign soc_netsoc_cpu_interrupt1 = (soc_netsoc_cpu_time >= soc_netsoc_cpu_time_cmp);
-assign soc_netsoc_interface0_soc_bus_adr = soc_netsoc_cpu_ibus_adr;
-assign soc_netsoc_interface0_soc_bus_dat_w = soc_netsoc_cpu_ibus_dat_w;
-assign soc_netsoc_cpu_ibus_dat_r = soc_netsoc_interface0_soc_bus_dat_r;
-assign soc_netsoc_interface0_soc_bus_sel = soc_netsoc_cpu_ibus_sel;
-assign soc_netsoc_interface0_soc_bus_cyc = soc_netsoc_cpu_ibus_cyc;
-assign soc_netsoc_interface0_soc_bus_stb = soc_netsoc_cpu_ibus_stb;
-assign soc_netsoc_cpu_ibus_ack = soc_netsoc_interface0_soc_bus_ack;
-assign soc_netsoc_interface0_soc_bus_we = soc_netsoc_cpu_ibus_we;
-assign soc_netsoc_interface0_soc_bus_cti = soc_netsoc_cpu_ibus_cti;
-assign soc_netsoc_interface0_soc_bus_bte = soc_netsoc_cpu_ibus_bte;
-assign soc_netsoc_cpu_ibus_err = soc_netsoc_interface0_soc_bus_err;
-assign soc_netsoc_interface1_soc_bus_adr = soc_netsoc_cpu_dbus_adr;
-assign soc_netsoc_interface1_soc_bus_dat_w = soc_netsoc_cpu_dbus_dat_w;
-assign soc_netsoc_cpu_dbus_dat_r = soc_netsoc_interface1_soc_bus_dat_r;
-assign soc_netsoc_interface1_soc_bus_sel = soc_netsoc_cpu_dbus_sel;
-assign soc_netsoc_interface1_soc_bus_cyc = soc_netsoc_cpu_dbus_cyc;
-assign soc_netsoc_interface1_soc_bus_stb = soc_netsoc_cpu_dbus_stb;
-assign soc_netsoc_cpu_dbus_ack = soc_netsoc_interface1_soc_bus_ack;
-assign soc_netsoc_interface1_soc_bus_we = soc_netsoc_cpu_dbus_we;
-assign soc_netsoc_interface1_soc_bus_cti = soc_netsoc_cpu_dbus_cti;
-assign soc_netsoc_interface1_soc_bus_bte = soc_netsoc_cpu_dbus_bte;
-assign soc_netsoc_cpu_dbus_err = soc_netsoc_interface1_soc_bus_err;
-assign soc_netsoc_rom_adr = soc_netsoc_rom_bus_adr[13:0];
-assign soc_netsoc_rom_bus_dat_r = soc_netsoc_rom_dat_r;
-always @(*) begin
-	soc_netsoc_sram_we <= 4'd0;
-	soc_netsoc_sram_we[0] <= (((soc_netsoc_sram_bus_cyc & soc_netsoc_sram_bus_stb) & soc_netsoc_sram_bus_we) & soc_netsoc_sram_bus_sel[0]);
-	soc_netsoc_sram_we[1] <= (((soc_netsoc_sram_bus_cyc & soc_netsoc_sram_bus_stb) & soc_netsoc_sram_bus_we) & soc_netsoc_sram_bus_sel[1]);
-	soc_netsoc_sram_we[2] <= (((soc_netsoc_sram_bus_cyc & soc_netsoc_sram_bus_stb) & soc_netsoc_sram_bus_we) & soc_netsoc_sram_bus_sel[2]);
-	soc_netsoc_sram_we[3] <= (((soc_netsoc_sram_bus_cyc & soc_netsoc_sram_bus_stb) & soc_netsoc_sram_bus_we) & soc_netsoc_sram_bus_sel[3]);
-end
-assign soc_netsoc_sram_adr = soc_netsoc_sram_bus_adr[12:0];
-assign soc_netsoc_sram_bus_dat_r = soc_netsoc_sram_dat_r;
-assign soc_netsoc_sram_dat_w = soc_netsoc_sram_bus_dat_w;
-assign soc_netsoc_uart_tx_fifo_sink_valid = soc_netsoc_uart_rxtx_re;
-assign soc_netsoc_uart_tx_fifo_sink_payload_data = soc_netsoc_uart_rxtx_r;
-assign soc_netsoc_uart_txfull_status = (~soc_netsoc_uart_tx_fifo_sink_ready);
-assign soc_netsoc_uart_phy_sink_valid = soc_netsoc_uart_tx_fifo_source_valid;
-assign soc_netsoc_uart_tx_fifo_source_ready = soc_netsoc_uart_phy_sink_ready;
-assign soc_netsoc_uart_phy_sink_first = soc_netsoc_uart_tx_fifo_source_first;
-assign soc_netsoc_uart_phy_sink_last = soc_netsoc_uart_tx_fifo_source_last;
-assign soc_netsoc_uart_phy_sink_payload_data = soc_netsoc_uart_tx_fifo_source_payload_data;
-assign soc_netsoc_uart_tx_trigger = (~soc_netsoc_uart_tx_fifo_sink_ready);
-assign soc_netsoc_uart_rx_fifo_sink_valid = soc_netsoc_uart_phy_source_valid;
-assign soc_netsoc_uart_phy_source_ready = soc_netsoc_uart_rx_fifo_sink_ready;
-assign soc_netsoc_uart_rx_fifo_sink_first = soc_netsoc_uart_phy_source_first;
-assign soc_netsoc_uart_rx_fifo_sink_last = soc_netsoc_uart_phy_source_last;
-assign soc_netsoc_uart_rx_fifo_sink_payload_data = soc_netsoc_uart_phy_source_payload_data;
-assign soc_netsoc_uart_rxempty_status = (~soc_netsoc_uart_rx_fifo_source_valid);
-assign soc_netsoc_uart_rxtx_w = soc_netsoc_uart_rx_fifo_source_payload_data;
-assign soc_netsoc_uart_rx_fifo_source_ready = soc_netsoc_uart_rx_clear;
-assign soc_netsoc_uart_rx_trigger = (~soc_netsoc_uart_rx_fifo_source_valid);
-always @(*) begin
-	soc_netsoc_uart_tx_clear <= 1'd0;
-	if ((soc_netsoc_uart_eventmanager_pending_re & soc_netsoc_uart_eventmanager_pending_r[0])) begin
-		soc_netsoc_uart_tx_clear <= 1'd1;
-	end
-end
-always @(*) begin
-	soc_netsoc_uart_eventmanager_status_w <= 2'd0;
-	soc_netsoc_uart_eventmanager_status_w[0] <= soc_netsoc_uart_tx_status;
-	soc_netsoc_uart_eventmanager_status_w[1] <= soc_netsoc_uart_rx_status;
-end
-always @(*) begin
-	soc_netsoc_uart_rx_clear <= 1'd0;
-	if ((soc_netsoc_uart_eventmanager_pending_re & soc_netsoc_uart_eventmanager_pending_r[1])) begin
-		soc_netsoc_uart_rx_clear <= 1'd1;
-	end
-end
-always @(*) begin
-	soc_netsoc_uart_eventmanager_pending_w <= 2'd0;
-	soc_netsoc_uart_eventmanager_pending_w[0] <= soc_netsoc_uart_tx_pending;
-	soc_netsoc_uart_eventmanager_pending_w[1] <= soc_netsoc_uart_rx_pending;
-end
-assign soc_netsoc_uart_irq = ((soc_netsoc_uart_eventmanager_pending_w[0] & soc_netsoc_uart_eventmanager_storage[0]) | (soc_netsoc_uart_eventmanager_pending_w[1] & soc_netsoc_uart_eventmanager_storage[1]));
-assign soc_netsoc_uart_tx_status = soc_netsoc_uart_tx_trigger;
-assign soc_netsoc_uart_rx_status = soc_netsoc_uart_rx_trigger;
-assign soc_netsoc_uart_tx_fifo_syncfifo_din = {soc_netsoc_uart_tx_fifo_fifo_in_last, soc_netsoc_uart_tx_fifo_fifo_in_first, soc_netsoc_uart_tx_fifo_fifo_in_payload_data};
-assign {soc_netsoc_uart_tx_fifo_fifo_out_last, soc_netsoc_uart_tx_fifo_fifo_out_first, soc_netsoc_uart_tx_fifo_fifo_out_payload_data} = soc_netsoc_uart_tx_fifo_syncfifo_dout;
-assign soc_netsoc_uart_tx_fifo_sink_ready = soc_netsoc_uart_tx_fifo_syncfifo_writable;
-assign soc_netsoc_uart_tx_fifo_syncfifo_we = soc_netsoc_uart_tx_fifo_sink_valid;
-assign soc_netsoc_uart_tx_fifo_fifo_in_first = soc_netsoc_uart_tx_fifo_sink_first;
-assign soc_netsoc_uart_tx_fifo_fifo_in_last = soc_netsoc_uart_tx_fifo_sink_last;
-assign soc_netsoc_uart_tx_fifo_fifo_in_payload_data = soc_netsoc_uart_tx_fifo_sink_payload_data;
-assign soc_netsoc_uart_tx_fifo_source_valid = soc_netsoc_uart_tx_fifo_readable;
-assign soc_netsoc_uart_tx_fifo_source_first = soc_netsoc_uart_tx_fifo_fifo_out_first;
-assign soc_netsoc_uart_tx_fifo_source_last = soc_netsoc_uart_tx_fifo_fifo_out_last;
-assign soc_netsoc_uart_tx_fifo_source_payload_data = soc_netsoc_uart_tx_fifo_fifo_out_payload_data;
-assign soc_netsoc_uart_tx_fifo_re = soc_netsoc_uart_tx_fifo_source_ready;
-assign soc_netsoc_uart_tx_fifo_syncfifo_re = (soc_netsoc_uart_tx_fifo_syncfifo_readable & ((~soc_netsoc_uart_tx_fifo_readable) | soc_netsoc_uart_tx_fifo_re));
-assign soc_netsoc_uart_tx_fifo_level1 = (soc_netsoc_uart_tx_fifo_level0 + soc_netsoc_uart_tx_fifo_readable);
-always @(*) begin
-	soc_netsoc_uart_tx_fifo_wrport_adr <= 4'd0;
-	if (soc_netsoc_uart_tx_fifo_replace) begin
-		soc_netsoc_uart_tx_fifo_wrport_adr <= (soc_netsoc_uart_tx_fifo_produce - 1'd1);
-	end else begin
-		soc_netsoc_uart_tx_fifo_wrport_adr <= soc_netsoc_uart_tx_fifo_produce;
-	end
-end
-assign soc_netsoc_uart_tx_fifo_wrport_dat_w = soc_netsoc_uart_tx_fifo_syncfifo_din;
-assign soc_netsoc_uart_tx_fifo_wrport_we = (soc_netsoc_uart_tx_fifo_syncfifo_we & (soc_netsoc_uart_tx_fifo_syncfifo_writable | soc_netsoc_uart_tx_fifo_replace));
-assign soc_netsoc_uart_tx_fifo_do_read = (soc_netsoc_uart_tx_fifo_syncfifo_readable & soc_netsoc_uart_tx_fifo_syncfifo_re);
-assign soc_netsoc_uart_tx_fifo_rdport_adr = soc_netsoc_uart_tx_fifo_consume;
-assign soc_netsoc_uart_tx_fifo_syncfifo_dout = soc_netsoc_uart_tx_fifo_rdport_dat_r;
-assign soc_netsoc_uart_tx_fifo_rdport_re = soc_netsoc_uart_tx_fifo_do_read;
-assign soc_netsoc_uart_tx_fifo_syncfifo_writable = (soc_netsoc_uart_tx_fifo_level0 != 5'd16);
-assign soc_netsoc_uart_tx_fifo_syncfifo_readable = (soc_netsoc_uart_tx_fifo_level0 != 1'd0);
-assign soc_netsoc_uart_rx_fifo_syncfifo_din = {soc_netsoc_uart_rx_fifo_fifo_in_last, soc_netsoc_uart_rx_fifo_fifo_in_first, soc_netsoc_uart_rx_fifo_fifo_in_payload_data};
-assign {soc_netsoc_uart_rx_fifo_fifo_out_last, soc_netsoc_uart_rx_fifo_fifo_out_first, soc_netsoc_uart_rx_fifo_fifo_out_payload_data} = soc_netsoc_uart_rx_fifo_syncfifo_dout;
-assign soc_netsoc_uart_rx_fifo_sink_ready = soc_netsoc_uart_rx_fifo_syncfifo_writable;
-assign soc_netsoc_uart_rx_fifo_syncfifo_we = soc_netsoc_uart_rx_fifo_sink_valid;
-assign soc_netsoc_uart_rx_fifo_fifo_in_first = soc_netsoc_uart_rx_fifo_sink_first;
-assign soc_netsoc_uart_rx_fifo_fifo_in_last = soc_netsoc_uart_rx_fifo_sink_last;
-assign soc_netsoc_uart_rx_fifo_fifo_in_payload_data = soc_netsoc_uart_rx_fifo_sink_payload_data;
-assign soc_netsoc_uart_rx_fifo_source_valid = soc_netsoc_uart_rx_fifo_readable;
-assign soc_netsoc_uart_rx_fifo_source_first = soc_netsoc_uart_rx_fifo_fifo_out_first;
-assign soc_netsoc_uart_rx_fifo_source_last = soc_netsoc_uart_rx_fifo_fifo_out_last;
-assign soc_netsoc_uart_rx_fifo_source_payload_data = soc_netsoc_uart_rx_fifo_fifo_out_payload_data;
-assign soc_netsoc_uart_rx_fifo_re = soc_netsoc_uart_rx_fifo_source_ready;
-assign soc_netsoc_uart_rx_fifo_syncfifo_re = (soc_netsoc_uart_rx_fifo_syncfifo_readable & ((~soc_netsoc_uart_rx_fifo_readable) | soc_netsoc_uart_rx_fifo_re));
-assign soc_netsoc_uart_rx_fifo_level1 = (soc_netsoc_uart_rx_fifo_level0 + soc_netsoc_uart_rx_fifo_readable);
-always @(*) begin
-	soc_netsoc_uart_rx_fifo_wrport_adr <= 4'd0;
-	if (soc_netsoc_uart_rx_fifo_replace) begin
-		soc_netsoc_uart_rx_fifo_wrport_adr <= (soc_netsoc_uart_rx_fifo_produce - 1'd1);
-	end else begin
-		soc_netsoc_uart_rx_fifo_wrport_adr <= soc_netsoc_uart_rx_fifo_produce;
-	end
-end
-assign soc_netsoc_uart_rx_fifo_wrport_dat_w = soc_netsoc_uart_rx_fifo_syncfifo_din;
-assign soc_netsoc_uart_rx_fifo_wrport_we = (soc_netsoc_uart_rx_fifo_syncfifo_we & (soc_netsoc_uart_rx_fifo_syncfifo_writable | soc_netsoc_uart_rx_fifo_replace));
-assign soc_netsoc_uart_rx_fifo_do_read = (soc_netsoc_uart_rx_fifo_syncfifo_readable & soc_netsoc_uart_rx_fifo_syncfifo_re);
-assign soc_netsoc_uart_rx_fifo_rdport_adr = soc_netsoc_uart_rx_fifo_consume;
-assign soc_netsoc_uart_rx_fifo_syncfifo_dout = soc_netsoc_uart_rx_fifo_rdport_dat_r;
-assign soc_netsoc_uart_rx_fifo_rdport_re = soc_netsoc_uart_rx_fifo_do_read;
-assign soc_netsoc_uart_rx_fifo_syncfifo_writable = (soc_netsoc_uart_rx_fifo_level0 != 5'd16);
-assign soc_netsoc_uart_rx_fifo_syncfifo_readable = (soc_netsoc_uart_rx_fifo_level0 != 1'd0);
-assign soc_netsoc_timer0_zero_trigger = (soc_netsoc_timer0_value != 1'd0);
-assign soc_netsoc_timer0_eventmanager_status_w = soc_netsoc_timer0_zero_status;
-always @(*) begin
-	soc_netsoc_timer0_zero_clear <= 1'd0;
-	if ((soc_netsoc_timer0_eventmanager_pending_re & soc_netsoc_timer0_eventmanager_pending_r)) begin
-		soc_netsoc_timer0_zero_clear <= 1'd1;
-	end
-end
-assign soc_netsoc_timer0_eventmanager_pending_w = soc_netsoc_timer0_zero_pending;
-assign soc_netsoc_timer0_irq = (soc_netsoc_timer0_eventmanager_pending_w & soc_netsoc_timer0_eventmanager_storage);
-assign soc_netsoc_timer0_zero_status = soc_netsoc_timer0_zero_trigger;
-assign soc_netsoc_interface_dat_w = soc_netsoc_bus_wishbone_dat_w;
-assign soc_netsoc_bus_wishbone_dat_r = soc_netsoc_interface_dat_r;
-always @(*) begin
-	soc_netsoc_interface_adr <= 14'd0;
-	vns_wb2csr_next_state <= 1'd0;
-	soc_netsoc_interface_we <= 1'd0;
-	soc_netsoc_bus_wishbone_ack <= 1'd0;
-	vns_wb2csr_next_state <= vns_wb2csr_state;
-	case (vns_wb2csr_state)
-		1'd1: begin
-			soc_netsoc_bus_wishbone_ack <= 1'd1;
-			vns_wb2csr_next_state <= 1'd0;
-		end
-		default: begin
-			if ((soc_netsoc_bus_wishbone_cyc & soc_netsoc_bus_wishbone_stb)) begin
-				soc_netsoc_interface_adr <= soc_netsoc_bus_wishbone_adr;
-				soc_netsoc_interface_we <= soc_netsoc_bus_wishbone_we;
-				vns_wb2csr_next_state <= 1'd1;
-			end
-		end
-	endcase
-end
-always @(*) begin
-	soc_emulator_ram_we <= 4'd0;
-	soc_emulator_ram_we[0] <= (((soc_emulator_ram_bus_cyc & soc_emulator_ram_bus_stb) & soc_emulator_ram_bus_we) & soc_emulator_ram_bus_sel[0]);
-	soc_emulator_ram_we[1] <= (((soc_emulator_ram_bus_cyc & soc_emulator_ram_bus_stb) & soc_emulator_ram_bus_we) & soc_emulator_ram_bus_sel[1]);
-	soc_emulator_ram_we[2] <= (((soc_emulator_ram_bus_cyc & soc_emulator_ram_bus_stb) & soc_emulator_ram_bus_we) & soc_emulator_ram_bus_sel[2]);
-	soc_emulator_ram_we[3] <= (((soc_emulator_ram_bus_cyc & soc_emulator_ram_bus_stb) & soc_emulator_ram_bus_we) & soc_emulator_ram_bus_sel[3]);
-end
-assign soc_emulator_ram_adr = soc_emulator_ram_bus_adr[11:0];
-assign soc_emulator_ram_bus_dat_r = soc_emulator_ram_dat_r;
-assign soc_emulator_ram_dat_w = soc_emulator_ram_bus_dat_w;
-always @(*) begin
-	soc_a7ddrphy_dqs_serdes_pattern <= 8'd85;
-	soc_a7ddrphy_dqs_serdes_pattern <= 7'd85;
-	if ((soc_a7ddrphy_dqs_preamble | soc_a7ddrphy_dqs_postamble)) begin
-		soc_a7ddrphy_dqs_serdes_pattern <= 1'd0;
-	end
-end
-assign soc_a7ddrphy_bitslip0_i = soc_a7ddrphy_dq_i_data0;
-assign soc_a7ddrphy_bitslip1_i = soc_a7ddrphy_dq_i_data1;
-assign soc_a7ddrphy_bitslip2_i = soc_a7ddrphy_dq_i_data2;
-assign soc_a7ddrphy_bitslip3_i = soc_a7ddrphy_dq_i_data3;
-assign soc_a7ddrphy_bitslip4_i = soc_a7ddrphy_dq_i_data4;
-assign soc_a7ddrphy_bitslip5_i = soc_a7ddrphy_dq_i_data5;
-assign soc_a7ddrphy_bitslip6_i = soc_a7ddrphy_dq_i_data6;
-assign soc_a7ddrphy_bitslip7_i = soc_a7ddrphy_dq_i_data7;
-assign soc_a7ddrphy_bitslip8_i = soc_a7ddrphy_dq_i_data8;
-assign soc_a7ddrphy_bitslip9_i = soc_a7ddrphy_dq_i_data9;
-assign soc_a7ddrphy_bitslip10_i = soc_a7ddrphy_dq_i_data10;
-assign soc_a7ddrphy_bitslip11_i = soc_a7ddrphy_dq_i_data11;
-assign soc_a7ddrphy_bitslip12_i = soc_a7ddrphy_dq_i_data12;
-assign soc_a7ddrphy_bitslip13_i = soc_a7ddrphy_dq_i_data13;
-assign soc_a7ddrphy_bitslip14_i = soc_a7ddrphy_dq_i_data14;
-assign soc_a7ddrphy_bitslip15_i = soc_a7ddrphy_dq_i_data15;
-always @(*) begin
-	soc_a7ddrphy_dfi_p0_rddata <= 32'd0;
-	soc_a7ddrphy_dfi_p0_rddata[0] <= soc_a7ddrphy_bitslip0_o[0];
-	soc_a7ddrphy_dfi_p0_rddata[16] <= soc_a7ddrphy_bitslip0_o[1];
-	soc_a7ddrphy_dfi_p0_rddata[1] <= soc_a7ddrphy_bitslip1_o[0];
-	soc_a7ddrphy_dfi_p0_rddata[17] <= soc_a7ddrphy_bitslip1_o[1];
-	soc_a7ddrphy_dfi_p0_rddata[2] <= soc_a7ddrphy_bitslip2_o[0];
-	soc_a7ddrphy_dfi_p0_rddata[18] <= soc_a7ddrphy_bitslip2_o[1];
-	soc_a7ddrphy_dfi_p0_rddata[3] <= soc_a7ddrphy_bitslip3_o[0];
-	soc_a7ddrphy_dfi_p0_rddata[19] <= soc_a7ddrphy_bitslip3_o[1];
-	soc_a7ddrphy_dfi_p0_rddata[4] <= soc_a7ddrphy_bitslip4_o[0];
-	soc_a7ddrphy_dfi_p0_rddata[20] <= soc_a7ddrphy_bitslip4_o[1];
-	soc_a7ddrphy_dfi_p0_rddata[5] <= soc_a7ddrphy_bitslip5_o[0];
-	soc_a7ddrphy_dfi_p0_rddata[21] <= soc_a7ddrphy_bitslip5_o[1];
-	soc_a7ddrphy_dfi_p0_rddata[6] <= soc_a7ddrphy_bitslip6_o[0];
-	soc_a7ddrphy_dfi_p0_rddata[22] <= soc_a7ddrphy_bitslip6_o[1];
-	soc_a7ddrphy_dfi_p0_rddata[7] <= soc_a7ddrphy_bitslip7_o[0];
-	soc_a7ddrphy_dfi_p0_rddata[23] <= soc_a7ddrphy_bitslip7_o[1];
-	soc_a7ddrphy_dfi_p0_rddata[8] <= soc_a7ddrphy_bitslip8_o[0];
-	soc_a7ddrphy_dfi_p0_rddata[24] <= soc_a7ddrphy_bitslip8_o[1];
-	soc_a7ddrphy_dfi_p0_rddata[9] <= soc_a7ddrphy_bitslip9_o[0];
-	soc_a7ddrphy_dfi_p0_rddata[25] <= soc_a7ddrphy_bitslip9_o[1];
-	soc_a7ddrphy_dfi_p0_rddata[10] <= soc_a7ddrphy_bitslip10_o[0];
-	soc_a7ddrphy_dfi_p0_rddata[26] <= soc_a7ddrphy_bitslip10_o[1];
-	soc_a7ddrphy_dfi_p0_rddata[11] <= soc_a7ddrphy_bitslip11_o[0];
-	soc_a7ddrphy_dfi_p0_rddata[27] <= soc_a7ddrphy_bitslip11_o[1];
-	soc_a7ddrphy_dfi_p0_rddata[12] <= soc_a7ddrphy_bitslip12_o[0];
-	soc_a7ddrphy_dfi_p0_rddata[28] <= soc_a7ddrphy_bitslip12_o[1];
-	soc_a7ddrphy_dfi_p0_rddata[13] <= soc_a7ddrphy_bitslip13_o[0];
-	soc_a7ddrphy_dfi_p0_rddata[29] <= soc_a7ddrphy_bitslip13_o[1];
-	soc_a7ddrphy_dfi_p0_rddata[14] <= soc_a7ddrphy_bitslip14_o[0];
-	soc_a7ddrphy_dfi_p0_rddata[30] <= soc_a7ddrphy_bitslip14_o[1];
-	soc_a7ddrphy_dfi_p0_rddata[15] <= soc_a7ddrphy_bitslip15_o[0];
-	soc_a7ddrphy_dfi_p0_rddata[31] <= soc_a7ddrphy_bitslip15_o[1];
-end
-always @(*) begin
-	soc_a7ddrphy_dfi_p1_rddata <= 32'd0;
-	soc_a7ddrphy_dfi_p1_rddata[0] <= soc_a7ddrphy_bitslip0_o[2];
-	soc_a7ddrphy_dfi_p1_rddata[16] <= soc_a7ddrphy_bitslip0_o[3];
-	soc_a7ddrphy_dfi_p1_rddata[1] <= soc_a7ddrphy_bitslip1_o[2];
-	soc_a7ddrphy_dfi_p1_rddata[17] <= soc_a7ddrphy_bitslip1_o[3];
-	soc_a7ddrphy_dfi_p1_rddata[2] <= soc_a7ddrphy_bitslip2_o[2];
-	soc_a7ddrphy_dfi_p1_rddata[18] <= soc_a7ddrphy_bitslip2_o[3];
-	soc_a7ddrphy_dfi_p1_rddata[3] <= soc_a7ddrphy_bitslip3_o[2];
-	soc_a7ddrphy_dfi_p1_rddata[19] <= soc_a7ddrphy_bitslip3_o[3];
-	soc_a7ddrphy_dfi_p1_rddata[4] <= soc_a7ddrphy_bitslip4_o[2];
-	soc_a7ddrphy_dfi_p1_rddata[20] <= soc_a7ddrphy_bitslip4_o[3];
-	soc_a7ddrphy_dfi_p1_rddata[5] <= soc_a7ddrphy_bitslip5_o[2];
-	soc_a7ddrphy_dfi_p1_rddata[21] <= soc_a7ddrphy_bitslip5_o[3];
-	soc_a7ddrphy_dfi_p1_rddata[6] <= soc_a7ddrphy_bitslip6_o[2];
-	soc_a7ddrphy_dfi_p1_rddata[22] <= soc_a7ddrphy_bitslip6_o[3];
-	soc_a7ddrphy_dfi_p1_rddata[7] <= soc_a7ddrphy_bitslip7_o[2];
-	soc_a7ddrphy_dfi_p1_rddata[23] <= soc_a7ddrphy_bitslip7_o[3];
-	soc_a7ddrphy_dfi_p1_rddata[8] <= soc_a7ddrphy_bitslip8_o[2];
-	soc_a7ddrphy_dfi_p1_rddata[24] <= soc_a7ddrphy_bitslip8_o[3];
-	soc_a7ddrphy_dfi_p1_rddata[9] <= soc_a7ddrphy_bitslip9_o[2];
-	soc_a7ddrphy_dfi_p1_rddata[25] <= soc_a7ddrphy_bitslip9_o[3];
-	soc_a7ddrphy_dfi_p1_rddata[10] <= soc_a7ddrphy_bitslip10_o[2];
-	soc_a7ddrphy_dfi_p1_rddata[26] <= soc_a7ddrphy_bitslip10_o[3];
-	soc_a7ddrphy_dfi_p1_rddata[11] <= soc_a7ddrphy_bitslip11_o[2];
-	soc_a7ddrphy_dfi_p1_rddata[27] <= soc_a7ddrphy_bitslip11_o[3];
-	soc_a7ddrphy_dfi_p1_rddata[12] <= soc_a7ddrphy_bitslip12_o[2];
-	soc_a7ddrphy_dfi_p1_rddata[28] <= soc_a7ddrphy_bitslip12_o[3];
-	soc_a7ddrphy_dfi_p1_rddata[13] <= soc_a7ddrphy_bitslip13_o[2];
-	soc_a7ddrphy_dfi_p1_rddata[29] <= soc_a7ddrphy_bitslip13_o[3];
-	soc_a7ddrphy_dfi_p1_rddata[14] <= soc_a7ddrphy_bitslip14_o[2];
-	soc_a7ddrphy_dfi_p1_rddata[30] <= soc_a7ddrphy_bitslip14_o[3];
-	soc_a7ddrphy_dfi_p1_rddata[15] <= soc_a7ddrphy_bitslip15_o[2];
-	soc_a7ddrphy_dfi_p1_rddata[31] <= soc_a7ddrphy_bitslip15_o[3];
-end
-always @(*) begin
-	soc_a7ddrphy_dfi_p2_rddata <= 32'd0;
-	soc_a7ddrphy_dfi_p2_rddata[0] <= soc_a7ddrphy_bitslip0_o[4];
-	soc_a7ddrphy_dfi_p2_rddata[16] <= soc_a7ddrphy_bitslip0_o[5];
-	soc_a7ddrphy_dfi_p2_rddata[1] <= soc_a7ddrphy_bitslip1_o[4];
-	soc_a7ddrphy_dfi_p2_rddata[17] <= soc_a7ddrphy_bitslip1_o[5];
-	soc_a7ddrphy_dfi_p2_rddata[2] <= soc_a7ddrphy_bitslip2_o[4];
-	soc_a7ddrphy_dfi_p2_rddata[18] <= soc_a7ddrphy_bitslip2_o[5];
-	soc_a7ddrphy_dfi_p2_rddata[3] <= soc_a7ddrphy_bitslip3_o[4];
-	soc_a7ddrphy_dfi_p2_rddata[19] <= soc_a7ddrphy_bitslip3_o[5];
-	soc_a7ddrphy_dfi_p2_rddata[4] <= soc_a7ddrphy_bitslip4_o[4];
-	soc_a7ddrphy_dfi_p2_rddata[20] <= soc_a7ddrphy_bitslip4_o[5];
-	soc_a7ddrphy_dfi_p2_rddata[5] <= soc_a7ddrphy_bitslip5_o[4];
-	soc_a7ddrphy_dfi_p2_rddata[21] <= soc_a7ddrphy_bitslip5_o[5];
-	soc_a7ddrphy_dfi_p2_rddata[6] <= soc_a7ddrphy_bitslip6_o[4];
-	soc_a7ddrphy_dfi_p2_rddata[22] <= soc_a7ddrphy_bitslip6_o[5];
-	soc_a7ddrphy_dfi_p2_rddata[7] <= soc_a7ddrphy_bitslip7_o[4];
-	soc_a7ddrphy_dfi_p2_rddata[23] <= soc_a7ddrphy_bitslip7_o[5];
-	soc_a7ddrphy_dfi_p2_rddata[8] <= soc_a7ddrphy_bitslip8_o[4];
-	soc_a7ddrphy_dfi_p2_rddata[24] <= soc_a7ddrphy_bitslip8_o[5];
-	soc_a7ddrphy_dfi_p2_rddata[9] <= soc_a7ddrphy_bitslip9_o[4];
-	soc_a7ddrphy_dfi_p2_rddata[25] <= soc_a7ddrphy_bitslip9_o[5];
-	soc_a7ddrphy_dfi_p2_rddata[10] <= soc_a7ddrphy_bitslip10_o[4];
-	soc_a7ddrphy_dfi_p2_rddata[26] <= soc_a7ddrphy_bitslip10_o[5];
-	soc_a7ddrphy_dfi_p2_rddata[11] <= soc_a7ddrphy_bitslip11_o[4];
-	soc_a7ddrphy_dfi_p2_rddata[27] <= soc_a7ddrphy_bitslip11_o[5];
-	soc_a7ddrphy_dfi_p2_rddata[12] <= soc_a7ddrphy_bitslip12_o[4];
-	soc_a7ddrphy_dfi_p2_rddata[28] <= soc_a7ddrphy_bitslip12_o[5];
-	soc_a7ddrphy_dfi_p2_rddata[13] <= soc_a7ddrphy_bitslip13_o[4];
-	soc_a7ddrphy_dfi_p2_rddata[29] <= soc_a7ddrphy_bitslip13_o[5];
-	soc_a7ddrphy_dfi_p2_rddata[14] <= soc_a7ddrphy_bitslip14_o[4];
-	soc_a7ddrphy_dfi_p2_rddata[30] <= soc_a7ddrphy_bitslip14_o[5];
-	soc_a7ddrphy_dfi_p2_rddata[15] <= soc_a7ddrphy_bitslip15_o[4];
-	soc_a7ddrphy_dfi_p2_rddata[31] <= soc_a7ddrphy_bitslip15_o[5];
-end
-always @(*) begin
-	soc_a7ddrphy_dfi_p3_rddata <= 32'd0;
-	soc_a7ddrphy_dfi_p3_rddata[0] <= soc_a7ddrphy_bitslip0_o[6];
-	soc_a7ddrphy_dfi_p3_rddata[16] <= soc_a7ddrphy_bitslip0_o[7];
-	soc_a7ddrphy_dfi_p3_rddata[1] <= soc_a7ddrphy_bitslip1_o[6];
-	soc_a7ddrphy_dfi_p3_rddata[17] <= soc_a7ddrphy_bitslip1_o[7];
-	soc_a7ddrphy_dfi_p3_rddata[2] <= soc_a7ddrphy_bitslip2_o[6];
-	soc_a7ddrphy_dfi_p3_rddata[18] <= soc_a7ddrphy_bitslip2_o[7];
-	soc_a7ddrphy_dfi_p3_rddata[3] <= soc_a7ddrphy_bitslip3_o[6];
-	soc_a7ddrphy_dfi_p3_rddata[19] <= soc_a7ddrphy_bitslip3_o[7];
-	soc_a7ddrphy_dfi_p3_rddata[4] <= soc_a7ddrphy_bitslip4_o[6];
-	soc_a7ddrphy_dfi_p3_rddata[20] <= soc_a7ddrphy_bitslip4_o[7];
-	soc_a7ddrphy_dfi_p3_rddata[5] <= soc_a7ddrphy_bitslip5_o[6];
-	soc_a7ddrphy_dfi_p3_rddata[21] <= soc_a7ddrphy_bitslip5_o[7];
-	soc_a7ddrphy_dfi_p3_rddata[6] <= soc_a7ddrphy_bitslip6_o[6];
-	soc_a7ddrphy_dfi_p3_rddata[22] <= soc_a7ddrphy_bitslip6_o[7];
-	soc_a7ddrphy_dfi_p3_rddata[7] <= soc_a7ddrphy_bitslip7_o[6];
-	soc_a7ddrphy_dfi_p3_rddata[23] <= soc_a7ddrphy_bitslip7_o[7];
-	soc_a7ddrphy_dfi_p3_rddata[8] <= soc_a7ddrphy_bitslip8_o[6];
-	soc_a7ddrphy_dfi_p3_rddata[24] <= soc_a7ddrphy_bitslip8_o[7];
-	soc_a7ddrphy_dfi_p3_rddata[9] <= soc_a7ddrphy_bitslip9_o[6];
-	soc_a7ddrphy_dfi_p3_rddata[25] <= soc_a7ddrphy_bitslip9_o[7];
-	soc_a7ddrphy_dfi_p3_rddata[10] <= soc_a7ddrphy_bitslip10_o[6];
-	soc_a7ddrphy_dfi_p3_rddata[26] <= soc_a7ddrphy_bitslip10_o[7];
-	soc_a7ddrphy_dfi_p3_rddata[11] <= soc_a7ddrphy_bitslip11_o[6];
-	soc_a7ddrphy_dfi_p3_rddata[27] <= soc_a7ddrphy_bitslip11_o[7];
-	soc_a7ddrphy_dfi_p3_rddata[12] <= soc_a7ddrphy_bitslip12_o[6];
-	soc_a7ddrphy_dfi_p3_rddata[28] <= soc_a7ddrphy_bitslip12_o[7];
-	soc_a7ddrphy_dfi_p3_rddata[13] <= soc_a7ddrphy_bitslip13_o[6];
-	soc_a7ddrphy_dfi_p3_rddata[29] <= soc_a7ddrphy_bitslip13_o[7];
-	soc_a7ddrphy_dfi_p3_rddata[14] <= soc_a7ddrphy_bitslip14_o[6];
-	soc_a7ddrphy_dfi_p3_rddata[30] <= soc_a7ddrphy_bitslip14_o[7];
-	soc_a7ddrphy_dfi_p3_rddata[15] <= soc_a7ddrphy_bitslip15_o[6];
-	soc_a7ddrphy_dfi_p3_rddata[31] <= soc_a7ddrphy_bitslip15_o[7];
-end
-assign soc_a7ddrphy_oe = ((soc_a7ddrphy_last_wrdata_en[1] | soc_a7ddrphy_last_wrdata_en[2]) | soc_a7ddrphy_last_wrdata_en[3]);
-assign soc_a7ddrphy_dqs_preamble = (soc_a7ddrphy_last_wrdata_en[1] & (~soc_a7ddrphy_last_wrdata_en[2]));
-assign soc_a7ddrphy_dqs_postamble = (soc_a7ddrphy_last_wrdata_en[3] & (~soc_a7ddrphy_last_wrdata_en[2]));
-assign soc_a7ddrphy_dfi_p0_address = soc_netsoc_sdram_master_p0_address;
-assign soc_a7ddrphy_dfi_p0_bank = soc_netsoc_sdram_master_p0_bank;
-assign soc_a7ddrphy_dfi_p0_cas_n = soc_netsoc_sdram_master_p0_cas_n;
-assign soc_a7ddrphy_dfi_p0_cs_n = soc_netsoc_sdram_master_p0_cs_n;
-assign soc_a7ddrphy_dfi_p0_ras_n = soc_netsoc_sdram_master_p0_ras_n;
-assign soc_a7ddrphy_dfi_p0_we_n = soc_netsoc_sdram_master_p0_we_n;
-assign soc_a7ddrphy_dfi_p0_cke = soc_netsoc_sdram_master_p0_cke;
-assign soc_a7ddrphy_dfi_p0_odt = soc_netsoc_sdram_master_p0_odt;
-assign soc_a7ddrphy_dfi_p0_reset_n = soc_netsoc_sdram_master_p0_reset_n;
-assign soc_a7ddrphy_dfi_p0_act_n = soc_netsoc_sdram_master_p0_act_n;
-assign soc_a7ddrphy_dfi_p0_wrdata = soc_netsoc_sdram_master_p0_wrdata;
-assign soc_a7ddrphy_dfi_p0_wrdata_en = soc_netsoc_sdram_master_p0_wrdata_en;
-assign soc_a7ddrphy_dfi_p0_wrdata_mask = soc_netsoc_sdram_master_p0_wrdata_mask;
-assign soc_a7ddrphy_dfi_p0_rddata_en = soc_netsoc_sdram_master_p0_rddata_en;
-assign soc_netsoc_sdram_master_p0_rddata = soc_a7ddrphy_dfi_p0_rddata;
-assign soc_netsoc_sdram_master_p0_rddata_valid = soc_a7ddrphy_dfi_p0_rddata_valid;
-assign soc_a7ddrphy_dfi_p1_address = soc_netsoc_sdram_master_p1_address;
-assign soc_a7ddrphy_dfi_p1_bank = soc_netsoc_sdram_master_p1_bank;
-assign soc_a7ddrphy_dfi_p1_cas_n = soc_netsoc_sdram_master_p1_cas_n;
-assign soc_a7ddrphy_dfi_p1_cs_n = soc_netsoc_sdram_master_p1_cs_n;
-assign soc_a7ddrphy_dfi_p1_ras_n = soc_netsoc_sdram_master_p1_ras_n;
-assign soc_a7ddrphy_dfi_p1_we_n = soc_netsoc_sdram_master_p1_we_n;
-assign soc_a7ddrphy_dfi_p1_cke = soc_netsoc_sdram_master_p1_cke;
-assign soc_a7ddrphy_dfi_p1_odt = soc_netsoc_sdram_master_p1_odt;
-assign soc_a7ddrphy_dfi_p1_reset_n = soc_netsoc_sdram_master_p1_reset_n;
-assign soc_a7ddrphy_dfi_p1_act_n = soc_netsoc_sdram_master_p1_act_n;
-assign soc_a7ddrphy_dfi_p1_wrdata = soc_netsoc_sdram_master_p1_wrdata;
-assign soc_a7ddrphy_dfi_p1_wrdata_en = soc_netsoc_sdram_master_p1_wrdata_en;
-assign soc_a7ddrphy_dfi_p1_wrdata_mask = soc_netsoc_sdram_master_p1_wrdata_mask;
-assign soc_a7ddrphy_dfi_p1_rddata_en = soc_netsoc_sdram_master_p1_rddata_en;
-assign soc_netsoc_sdram_master_p1_rddata = soc_a7ddrphy_dfi_p1_rddata;
-assign soc_netsoc_sdram_master_p1_rddata_valid = soc_a7ddrphy_dfi_p1_rddata_valid;
-assign soc_a7ddrphy_dfi_p2_address = soc_netsoc_sdram_master_p2_address;
-assign soc_a7ddrphy_dfi_p2_bank = soc_netsoc_sdram_master_p2_bank;
-assign soc_a7ddrphy_dfi_p2_cas_n = soc_netsoc_sdram_master_p2_cas_n;
-assign soc_a7ddrphy_dfi_p2_cs_n = soc_netsoc_sdram_master_p2_cs_n;
-assign soc_a7ddrphy_dfi_p2_ras_n = soc_netsoc_sdram_master_p2_ras_n;
-assign soc_a7ddrphy_dfi_p2_we_n = soc_netsoc_sdram_master_p2_we_n;
-assign soc_a7ddrphy_dfi_p2_cke = soc_netsoc_sdram_master_p2_cke;
-assign soc_a7ddrphy_dfi_p2_odt = soc_netsoc_sdram_master_p2_odt;
-assign soc_a7ddrphy_dfi_p2_reset_n = soc_netsoc_sdram_master_p2_reset_n;
-assign soc_a7ddrphy_dfi_p2_act_n = soc_netsoc_sdram_master_p2_act_n;
-assign soc_a7ddrphy_dfi_p2_wrdata = soc_netsoc_sdram_master_p2_wrdata;
-assign soc_a7ddrphy_dfi_p2_wrdata_en = soc_netsoc_sdram_master_p2_wrdata_en;
-assign soc_a7ddrphy_dfi_p2_wrdata_mask = soc_netsoc_sdram_master_p2_wrdata_mask;
-assign soc_a7ddrphy_dfi_p2_rddata_en = soc_netsoc_sdram_master_p2_rddata_en;
-assign soc_netsoc_sdram_master_p2_rddata = soc_a7ddrphy_dfi_p2_rddata;
-assign soc_netsoc_sdram_master_p2_rddata_valid = soc_a7ddrphy_dfi_p2_rddata_valid;
-assign soc_a7ddrphy_dfi_p3_address = soc_netsoc_sdram_master_p3_address;
-assign soc_a7ddrphy_dfi_p3_bank = soc_netsoc_sdram_master_p3_bank;
-assign soc_a7ddrphy_dfi_p3_cas_n = soc_netsoc_sdram_master_p3_cas_n;
-assign soc_a7ddrphy_dfi_p3_cs_n = soc_netsoc_sdram_master_p3_cs_n;
-assign soc_a7ddrphy_dfi_p3_ras_n = soc_netsoc_sdram_master_p3_ras_n;
-assign soc_a7ddrphy_dfi_p3_we_n = soc_netsoc_sdram_master_p3_we_n;
-assign soc_a7ddrphy_dfi_p3_cke = soc_netsoc_sdram_master_p3_cke;
-assign soc_a7ddrphy_dfi_p3_odt = soc_netsoc_sdram_master_p3_odt;
-assign soc_a7ddrphy_dfi_p3_reset_n = soc_netsoc_sdram_master_p3_reset_n;
-assign soc_a7ddrphy_dfi_p3_act_n = soc_netsoc_sdram_master_p3_act_n;
-assign soc_a7ddrphy_dfi_p3_wrdata = soc_netsoc_sdram_master_p3_wrdata;
-assign soc_a7ddrphy_dfi_p3_wrdata_en = soc_netsoc_sdram_master_p3_wrdata_en;
-assign soc_a7ddrphy_dfi_p3_wrdata_mask = soc_netsoc_sdram_master_p3_wrdata_mask;
-assign soc_a7ddrphy_dfi_p3_rddata_en = soc_netsoc_sdram_master_p3_rddata_en;
-assign soc_netsoc_sdram_master_p3_rddata = soc_a7ddrphy_dfi_p3_rddata;
-assign soc_netsoc_sdram_master_p3_rddata_valid = soc_a7ddrphy_dfi_p3_rddata_valid;
-assign soc_netsoc_sdram_slave_p0_address = soc_netsoc_sdram_dfi_p0_address;
-assign soc_netsoc_sdram_slave_p0_bank = soc_netsoc_sdram_dfi_p0_bank;
-assign soc_netsoc_sdram_slave_p0_cas_n = soc_netsoc_sdram_dfi_p0_cas_n;
-assign soc_netsoc_sdram_slave_p0_cs_n = soc_netsoc_sdram_dfi_p0_cs_n;
-assign soc_netsoc_sdram_slave_p0_ras_n = soc_netsoc_sdram_dfi_p0_ras_n;
-assign soc_netsoc_sdram_slave_p0_we_n = soc_netsoc_sdram_dfi_p0_we_n;
-assign soc_netsoc_sdram_slave_p0_cke = soc_netsoc_sdram_dfi_p0_cke;
-assign soc_netsoc_sdram_slave_p0_odt = soc_netsoc_sdram_dfi_p0_odt;
-assign soc_netsoc_sdram_slave_p0_reset_n = soc_netsoc_sdram_dfi_p0_reset_n;
-assign soc_netsoc_sdram_slave_p0_act_n = soc_netsoc_sdram_dfi_p0_act_n;
-assign soc_netsoc_sdram_slave_p0_wrdata = soc_netsoc_sdram_dfi_p0_wrdata;
-assign soc_netsoc_sdram_slave_p0_wrdata_en = soc_netsoc_sdram_dfi_p0_wrdata_en;
-assign soc_netsoc_sdram_slave_p0_wrdata_mask = soc_netsoc_sdram_dfi_p0_wrdata_mask;
-assign soc_netsoc_sdram_slave_p0_rddata_en = soc_netsoc_sdram_dfi_p0_rddata_en;
-assign soc_netsoc_sdram_dfi_p0_rddata = soc_netsoc_sdram_slave_p0_rddata;
-assign soc_netsoc_sdram_dfi_p0_rddata_valid = soc_netsoc_sdram_slave_p0_rddata_valid;
-assign soc_netsoc_sdram_slave_p1_address = soc_netsoc_sdram_dfi_p1_address;
-assign soc_netsoc_sdram_slave_p1_bank = soc_netsoc_sdram_dfi_p1_bank;
-assign soc_netsoc_sdram_slave_p1_cas_n = soc_netsoc_sdram_dfi_p1_cas_n;
-assign soc_netsoc_sdram_slave_p1_cs_n = soc_netsoc_sdram_dfi_p1_cs_n;
-assign soc_netsoc_sdram_slave_p1_ras_n = soc_netsoc_sdram_dfi_p1_ras_n;
-assign soc_netsoc_sdram_slave_p1_we_n = soc_netsoc_sdram_dfi_p1_we_n;
-assign soc_netsoc_sdram_slave_p1_cke = soc_netsoc_sdram_dfi_p1_cke;
-assign soc_netsoc_sdram_slave_p1_odt = soc_netsoc_sdram_dfi_p1_odt;
-assign soc_netsoc_sdram_slave_p1_reset_n = soc_netsoc_sdram_dfi_p1_reset_n;
-assign soc_netsoc_sdram_slave_p1_act_n = soc_netsoc_sdram_dfi_p1_act_n;
-assign soc_netsoc_sdram_slave_p1_wrdata = soc_netsoc_sdram_dfi_p1_wrdata;
-assign soc_netsoc_sdram_slave_p1_wrdata_en = soc_netsoc_sdram_dfi_p1_wrdata_en;
-assign soc_netsoc_sdram_slave_p1_wrdata_mask = soc_netsoc_sdram_dfi_p1_wrdata_mask;
-assign soc_netsoc_sdram_slave_p1_rddata_en = soc_netsoc_sdram_dfi_p1_rddata_en;
-assign soc_netsoc_sdram_dfi_p1_rddata = soc_netsoc_sdram_slave_p1_rddata;
-assign soc_netsoc_sdram_dfi_p1_rddata_valid = soc_netsoc_sdram_slave_p1_rddata_valid;
-assign soc_netsoc_sdram_slave_p2_address = soc_netsoc_sdram_dfi_p2_address;
-assign soc_netsoc_sdram_slave_p2_bank = soc_netsoc_sdram_dfi_p2_bank;
-assign soc_netsoc_sdram_slave_p2_cas_n = soc_netsoc_sdram_dfi_p2_cas_n;
-assign soc_netsoc_sdram_slave_p2_cs_n = soc_netsoc_sdram_dfi_p2_cs_n;
-assign soc_netsoc_sdram_slave_p2_ras_n = soc_netsoc_sdram_dfi_p2_ras_n;
-assign soc_netsoc_sdram_slave_p2_we_n = soc_netsoc_sdram_dfi_p2_we_n;
-assign soc_netsoc_sdram_slave_p2_cke = soc_netsoc_sdram_dfi_p2_cke;
-assign soc_netsoc_sdram_slave_p2_odt = soc_netsoc_sdram_dfi_p2_odt;
-assign soc_netsoc_sdram_slave_p2_reset_n = soc_netsoc_sdram_dfi_p2_reset_n;
-assign soc_netsoc_sdram_slave_p2_act_n = soc_netsoc_sdram_dfi_p2_act_n;
-assign soc_netsoc_sdram_slave_p2_wrdata = soc_netsoc_sdram_dfi_p2_wrdata;
-assign soc_netsoc_sdram_slave_p2_wrdata_en = soc_netsoc_sdram_dfi_p2_wrdata_en;
-assign soc_netsoc_sdram_slave_p2_wrdata_mask = soc_netsoc_sdram_dfi_p2_wrdata_mask;
-assign soc_netsoc_sdram_slave_p2_rddata_en = soc_netsoc_sdram_dfi_p2_rddata_en;
-assign soc_netsoc_sdram_dfi_p2_rddata = soc_netsoc_sdram_slave_p2_rddata;
-assign soc_netsoc_sdram_dfi_p2_rddata_valid = soc_netsoc_sdram_slave_p2_rddata_valid;
-assign soc_netsoc_sdram_slave_p3_address = soc_netsoc_sdram_dfi_p3_address;
-assign soc_netsoc_sdram_slave_p3_bank = soc_netsoc_sdram_dfi_p3_bank;
-assign soc_netsoc_sdram_slave_p3_cas_n = soc_netsoc_sdram_dfi_p3_cas_n;
-assign soc_netsoc_sdram_slave_p3_cs_n = soc_netsoc_sdram_dfi_p3_cs_n;
-assign soc_netsoc_sdram_slave_p3_ras_n = soc_netsoc_sdram_dfi_p3_ras_n;
-assign soc_netsoc_sdram_slave_p3_we_n = soc_netsoc_sdram_dfi_p3_we_n;
-assign soc_netsoc_sdram_slave_p3_cke = soc_netsoc_sdram_dfi_p3_cke;
-assign soc_netsoc_sdram_slave_p3_odt = soc_netsoc_sdram_dfi_p3_odt;
-assign soc_netsoc_sdram_slave_p3_reset_n = soc_netsoc_sdram_dfi_p3_reset_n;
-assign soc_netsoc_sdram_slave_p3_act_n = soc_netsoc_sdram_dfi_p3_act_n;
-assign soc_netsoc_sdram_slave_p3_wrdata = soc_netsoc_sdram_dfi_p3_wrdata;
-assign soc_netsoc_sdram_slave_p3_wrdata_en = soc_netsoc_sdram_dfi_p3_wrdata_en;
-assign soc_netsoc_sdram_slave_p3_wrdata_mask = soc_netsoc_sdram_dfi_p3_wrdata_mask;
-assign soc_netsoc_sdram_slave_p3_rddata_en = soc_netsoc_sdram_dfi_p3_rddata_en;
-assign soc_netsoc_sdram_dfi_p3_rddata = soc_netsoc_sdram_slave_p3_rddata;
-assign soc_netsoc_sdram_dfi_p3_rddata_valid = soc_netsoc_sdram_slave_p3_rddata_valid;
-always @(*) begin
-	soc_netsoc_sdram_master_p2_we_n <= 1'd1;
-	soc_netsoc_sdram_master_p2_cke <= 1'd0;
-	soc_netsoc_sdram_master_p2_odt <= 1'd0;
-	soc_netsoc_sdram_master_p2_reset_n <= 1'd0;
-	soc_netsoc_sdram_master_p2_act_n <= 1'd1;
-	soc_netsoc_sdram_master_p2_wrdata <= 32'd0;
-	soc_netsoc_sdram_inti_p3_rddata <= 32'd0;
-	soc_netsoc_sdram_master_p2_wrdata_en <= 1'd0;
-	soc_netsoc_sdram_inti_p3_rddata_valid <= 1'd0;
-	soc_netsoc_sdram_master_p2_wrdata_mask <= 4'd0;
-	soc_netsoc_sdram_master_p2_rddata_en <= 1'd0;
-	soc_netsoc_sdram_master_p3_address <= 14'd0;
-	soc_netsoc_sdram_master_p3_bank <= 3'd0;
-	soc_netsoc_sdram_master_p3_cas_n <= 1'd1;
-	soc_netsoc_sdram_master_p3_cs_n <= 1'd1;
-	soc_netsoc_sdram_master_p3_ras_n <= 1'd1;
-	soc_netsoc_sdram_master_p3_we_n <= 1'd1;
-	soc_netsoc_sdram_master_p3_cke <= 1'd0;
-	soc_netsoc_sdram_master_p3_odt <= 1'd0;
-	soc_netsoc_sdram_master_p3_reset_n <= 1'd0;
-	soc_netsoc_sdram_master_p3_act_n <= 1'd1;
-	soc_netsoc_sdram_master_p3_wrdata <= 32'd0;
-	soc_netsoc_sdram_master_p3_wrdata_en <= 1'd0;
-	soc_netsoc_sdram_master_p3_wrdata_mask <= 4'd0;
-	soc_netsoc_sdram_master_p3_rddata_en <= 1'd0;
-	soc_netsoc_sdram_slave_p0_rddata <= 32'd0;
-	soc_netsoc_sdram_slave_p0_rddata_valid <= 1'd0;
-	soc_netsoc_sdram_slave_p1_rddata <= 32'd0;
-	soc_netsoc_sdram_slave_p1_rddata_valid <= 1'd0;
-	soc_netsoc_sdram_slave_p2_rddata <= 32'd0;
-	soc_netsoc_sdram_slave_p2_rddata_valid <= 1'd0;
-	soc_netsoc_sdram_slave_p3_rddata <= 32'd0;
-	soc_netsoc_sdram_slave_p3_rddata_valid <= 1'd0;
-	soc_netsoc_sdram_inti_p0_rddata <= 32'd0;
-	soc_netsoc_sdram_inti_p0_rddata_valid <= 1'd0;
-	soc_netsoc_sdram_master_p0_address <= 14'd0;
-	soc_netsoc_sdram_master_p0_bank <= 3'd0;
-	soc_netsoc_sdram_master_p0_cas_n <= 1'd1;
-	soc_netsoc_sdram_master_p0_cs_n <= 1'd1;
-	soc_netsoc_sdram_master_p0_ras_n <= 1'd1;
-	soc_netsoc_sdram_master_p0_we_n <= 1'd1;
-	soc_netsoc_sdram_master_p0_cke <= 1'd0;
-	soc_netsoc_sdram_master_p0_odt <= 1'd0;
-	soc_netsoc_sdram_master_p0_reset_n <= 1'd0;
-	soc_netsoc_sdram_master_p0_act_n <= 1'd1;
-	soc_netsoc_sdram_master_p0_wrdata <= 32'd0;
-	soc_netsoc_sdram_inti_p1_rddata <= 32'd0;
-	soc_netsoc_sdram_master_p0_wrdata_en <= 1'd0;
-	soc_netsoc_sdram_inti_p1_rddata_valid <= 1'd0;
-	soc_netsoc_sdram_master_p0_wrdata_mask <= 4'd0;
-	soc_netsoc_sdram_master_p0_rddata_en <= 1'd0;
-	soc_netsoc_sdram_master_p1_address <= 14'd0;
-	soc_netsoc_sdram_master_p1_bank <= 3'd0;
-	soc_netsoc_sdram_master_p1_cas_n <= 1'd1;
-	soc_netsoc_sdram_master_p1_cs_n <= 1'd1;
-	soc_netsoc_sdram_master_p1_ras_n <= 1'd1;
-	soc_netsoc_sdram_master_p1_we_n <= 1'd1;
-	soc_netsoc_sdram_master_p1_cke <= 1'd0;
-	soc_netsoc_sdram_master_p1_odt <= 1'd0;
-	soc_netsoc_sdram_master_p1_reset_n <= 1'd0;
-	soc_netsoc_sdram_master_p1_act_n <= 1'd1;
-	soc_netsoc_sdram_master_p1_wrdata <= 32'd0;
-	soc_netsoc_sdram_inti_p2_rddata <= 32'd0;
-	soc_netsoc_sdram_master_p1_wrdata_en <= 1'd0;
-	soc_netsoc_sdram_inti_p2_rddata_valid <= 1'd0;
-	soc_netsoc_sdram_master_p1_wrdata_mask <= 4'd0;
-	soc_netsoc_sdram_master_p1_rddata_en <= 1'd0;
-	soc_netsoc_sdram_master_p2_address <= 14'd0;
-	soc_netsoc_sdram_master_p2_bank <= 3'd0;
-	soc_netsoc_sdram_master_p2_cas_n <= 1'd1;
-	soc_netsoc_sdram_master_p2_cs_n <= 1'd1;
-	soc_netsoc_sdram_master_p2_ras_n <= 1'd1;
-	if (soc_netsoc_sdram_storage[0]) begin
-		soc_netsoc_sdram_master_p0_address <= soc_netsoc_sdram_slave_p0_address;
-		soc_netsoc_sdram_master_p0_bank <= soc_netsoc_sdram_slave_p0_bank;
-		soc_netsoc_sdram_master_p0_cas_n <= soc_netsoc_sdram_slave_p0_cas_n;
-		soc_netsoc_sdram_master_p0_cs_n <= soc_netsoc_sdram_slave_p0_cs_n;
-		soc_netsoc_sdram_master_p0_ras_n <= soc_netsoc_sdram_slave_p0_ras_n;
-		soc_netsoc_sdram_master_p0_we_n <= soc_netsoc_sdram_slave_p0_we_n;
-		soc_netsoc_sdram_master_p0_cke <= soc_netsoc_sdram_slave_p0_cke;
-		soc_netsoc_sdram_master_p0_odt <= soc_netsoc_sdram_slave_p0_odt;
-		soc_netsoc_sdram_master_p0_reset_n <= soc_netsoc_sdram_slave_p0_reset_n;
-		soc_netsoc_sdram_master_p0_act_n <= soc_netsoc_sdram_slave_p0_act_n;
-		soc_netsoc_sdram_master_p0_wrdata <= soc_netsoc_sdram_slave_p0_wrdata;
-		soc_netsoc_sdram_master_p0_wrdata_en <= soc_netsoc_sdram_slave_p0_wrdata_en;
-		soc_netsoc_sdram_master_p0_wrdata_mask <= soc_netsoc_sdram_slave_p0_wrdata_mask;
-		soc_netsoc_sdram_master_p0_rddata_en <= soc_netsoc_sdram_slave_p0_rddata_en;
-		soc_netsoc_sdram_slave_p0_rddata <= soc_netsoc_sdram_master_p0_rddata;
-		soc_netsoc_sdram_slave_p0_rddata_valid <= soc_netsoc_sdram_master_p0_rddata_valid;
-		soc_netsoc_sdram_master_p1_address <= soc_netsoc_sdram_slave_p1_address;
-		soc_netsoc_sdram_master_p1_bank <= soc_netsoc_sdram_slave_p1_bank;
-		soc_netsoc_sdram_master_p1_cas_n <= soc_netsoc_sdram_slave_p1_cas_n;
-		soc_netsoc_sdram_master_p1_cs_n <= soc_netsoc_sdram_slave_p1_cs_n;
-		soc_netsoc_sdram_master_p1_ras_n <= soc_netsoc_sdram_slave_p1_ras_n;
-		soc_netsoc_sdram_master_p1_we_n <= soc_netsoc_sdram_slave_p1_we_n;
-		soc_netsoc_sdram_master_p1_cke <= soc_netsoc_sdram_slave_p1_cke;
-		soc_netsoc_sdram_master_p1_odt <= soc_netsoc_sdram_slave_p1_odt;
-		soc_netsoc_sdram_master_p1_reset_n <= soc_netsoc_sdram_slave_p1_reset_n;
-		soc_netsoc_sdram_master_p1_act_n <= soc_netsoc_sdram_slave_p1_act_n;
-		soc_netsoc_sdram_master_p1_wrdata <= soc_netsoc_sdram_slave_p1_wrdata;
-		soc_netsoc_sdram_master_p1_wrdata_en <= soc_netsoc_sdram_slave_p1_wrdata_en;
-		soc_netsoc_sdram_master_p1_wrdata_mask <= soc_netsoc_sdram_slave_p1_wrdata_mask;
-		soc_netsoc_sdram_master_p1_rddata_en <= soc_netsoc_sdram_slave_p1_rddata_en;
-		soc_netsoc_sdram_slave_p1_rddata <= soc_netsoc_sdram_master_p1_rddata;
-		soc_netsoc_sdram_slave_p1_rddata_valid <= soc_netsoc_sdram_master_p1_rddata_valid;
-		soc_netsoc_sdram_master_p2_address <= soc_netsoc_sdram_slave_p2_address;
-		soc_netsoc_sdram_master_p2_bank <= soc_netsoc_sdram_slave_p2_bank;
-		soc_netsoc_sdram_master_p2_cas_n <= soc_netsoc_sdram_slave_p2_cas_n;
-		soc_netsoc_sdram_master_p2_cs_n <= soc_netsoc_sdram_slave_p2_cs_n;
-		soc_netsoc_sdram_master_p2_ras_n <= soc_netsoc_sdram_slave_p2_ras_n;
-		soc_netsoc_sdram_master_p2_we_n <= soc_netsoc_sdram_slave_p2_we_n;
-		soc_netsoc_sdram_master_p2_cke <= soc_netsoc_sdram_slave_p2_cke;
-		soc_netsoc_sdram_master_p2_odt <= soc_netsoc_sdram_slave_p2_odt;
-		soc_netsoc_sdram_master_p2_reset_n <= soc_netsoc_sdram_slave_p2_reset_n;
-		soc_netsoc_sdram_master_p2_act_n <= soc_netsoc_sdram_slave_p2_act_n;
-		soc_netsoc_sdram_master_p2_wrdata <= soc_netsoc_sdram_slave_p2_wrdata;
-		soc_netsoc_sdram_master_p2_wrdata_en <= soc_netsoc_sdram_slave_p2_wrdata_en;
-		soc_netsoc_sdram_master_p2_wrdata_mask <= soc_netsoc_sdram_slave_p2_wrdata_mask;
-		soc_netsoc_sdram_master_p2_rddata_en <= soc_netsoc_sdram_slave_p2_rddata_en;
-		soc_netsoc_sdram_slave_p2_rddata <= soc_netsoc_sdram_master_p2_rddata;
-		soc_netsoc_sdram_slave_p2_rddata_valid <= soc_netsoc_sdram_master_p2_rddata_valid;
-		soc_netsoc_sdram_master_p3_address <= soc_netsoc_sdram_slave_p3_address;
-		soc_netsoc_sdram_master_p3_bank <= soc_netsoc_sdram_slave_p3_bank;
-		soc_netsoc_sdram_master_p3_cas_n <= soc_netsoc_sdram_slave_p3_cas_n;
-		soc_netsoc_sdram_master_p3_cs_n <= soc_netsoc_sdram_slave_p3_cs_n;
-		soc_netsoc_sdram_master_p3_ras_n <= soc_netsoc_sdram_slave_p3_ras_n;
-		soc_netsoc_sdram_master_p3_we_n <= soc_netsoc_sdram_slave_p3_we_n;
-		soc_netsoc_sdram_master_p3_cke <= soc_netsoc_sdram_slave_p3_cke;
-		soc_netsoc_sdram_master_p3_odt <= soc_netsoc_sdram_slave_p3_odt;
-		soc_netsoc_sdram_master_p3_reset_n <= soc_netsoc_sdram_slave_p3_reset_n;
-		soc_netsoc_sdram_master_p3_act_n <= soc_netsoc_sdram_slave_p3_act_n;
-		soc_netsoc_sdram_master_p3_wrdata <= soc_netsoc_sdram_slave_p3_wrdata;
-		soc_netsoc_sdram_master_p3_wrdata_en <= soc_netsoc_sdram_slave_p3_wrdata_en;
-		soc_netsoc_sdram_master_p3_wrdata_mask <= soc_netsoc_sdram_slave_p3_wrdata_mask;
-		soc_netsoc_sdram_master_p3_rddata_en <= soc_netsoc_sdram_slave_p3_rddata_en;
-		soc_netsoc_sdram_slave_p3_rddata <= soc_netsoc_sdram_master_p3_rddata;
-		soc_netsoc_sdram_slave_p3_rddata_valid <= soc_netsoc_sdram_master_p3_rddata_valid;
-	end else begin
-		soc_netsoc_sdram_master_p0_address <= soc_netsoc_sdram_inti_p0_address;
-		soc_netsoc_sdram_master_p0_bank <= soc_netsoc_sdram_inti_p0_bank;
-		soc_netsoc_sdram_master_p0_cas_n <= soc_netsoc_sdram_inti_p0_cas_n;
-		soc_netsoc_sdram_master_p0_cs_n <= soc_netsoc_sdram_inti_p0_cs_n;
-		soc_netsoc_sdram_master_p0_ras_n <= soc_netsoc_sdram_inti_p0_ras_n;
-		soc_netsoc_sdram_master_p0_we_n <= soc_netsoc_sdram_inti_p0_we_n;
-		soc_netsoc_sdram_master_p0_cke <= soc_netsoc_sdram_inti_p0_cke;
-		soc_netsoc_sdram_master_p0_odt <= soc_netsoc_sdram_inti_p0_odt;
-		soc_netsoc_sdram_master_p0_reset_n <= soc_netsoc_sdram_inti_p0_reset_n;
-		soc_netsoc_sdram_master_p0_act_n <= soc_netsoc_sdram_inti_p0_act_n;
-		soc_netsoc_sdram_master_p0_wrdata <= soc_netsoc_sdram_inti_p0_wrdata;
-		soc_netsoc_sdram_master_p0_wrdata_en <= soc_netsoc_sdram_inti_p0_wrdata_en;
-		soc_netsoc_sdram_master_p0_wrdata_mask <= soc_netsoc_sdram_inti_p0_wrdata_mask;
-		soc_netsoc_sdram_master_p0_rddata_en <= soc_netsoc_sdram_inti_p0_rddata_en;
-		soc_netsoc_sdram_inti_p0_rddata <= soc_netsoc_sdram_master_p0_rddata;
-		soc_netsoc_sdram_inti_p0_rddata_valid <= soc_netsoc_sdram_master_p0_rddata_valid;
-		soc_netsoc_sdram_master_p1_address <= soc_netsoc_sdram_inti_p1_address;
-		soc_netsoc_sdram_master_p1_bank <= soc_netsoc_sdram_inti_p1_bank;
-		soc_netsoc_sdram_master_p1_cas_n <= soc_netsoc_sdram_inti_p1_cas_n;
-		soc_netsoc_sdram_master_p1_cs_n <= soc_netsoc_sdram_inti_p1_cs_n;
-		soc_netsoc_sdram_master_p1_ras_n <= soc_netsoc_sdram_inti_p1_ras_n;
-		soc_netsoc_sdram_master_p1_we_n <= soc_netsoc_sdram_inti_p1_we_n;
-		soc_netsoc_sdram_master_p1_cke <= soc_netsoc_sdram_inti_p1_cke;
-		soc_netsoc_sdram_master_p1_odt <= soc_netsoc_sdram_inti_p1_odt;
-		soc_netsoc_sdram_master_p1_reset_n <= soc_netsoc_sdram_inti_p1_reset_n;
-		soc_netsoc_sdram_master_p1_act_n <= soc_netsoc_sdram_inti_p1_act_n;
-		soc_netsoc_sdram_master_p1_wrdata <= soc_netsoc_sdram_inti_p1_wrdata;
-		soc_netsoc_sdram_master_p1_wrdata_en <= soc_netsoc_sdram_inti_p1_wrdata_en;
-		soc_netsoc_sdram_master_p1_wrdata_mask <= soc_netsoc_sdram_inti_p1_wrdata_mask;
-		soc_netsoc_sdram_master_p1_rddata_en <= soc_netsoc_sdram_inti_p1_rddata_en;
-		soc_netsoc_sdram_inti_p1_rddata <= soc_netsoc_sdram_master_p1_rddata;
-		soc_netsoc_sdram_inti_p1_rddata_valid <= soc_netsoc_sdram_master_p1_rddata_valid;
-		soc_netsoc_sdram_master_p2_address <= soc_netsoc_sdram_inti_p2_address;
-		soc_netsoc_sdram_master_p2_bank <= soc_netsoc_sdram_inti_p2_bank;
-		soc_netsoc_sdram_master_p2_cas_n <= soc_netsoc_sdram_inti_p2_cas_n;
-		soc_netsoc_sdram_master_p2_cs_n <= soc_netsoc_sdram_inti_p2_cs_n;
-		soc_netsoc_sdram_master_p2_ras_n <= soc_netsoc_sdram_inti_p2_ras_n;
-		soc_netsoc_sdram_master_p2_we_n <= soc_netsoc_sdram_inti_p2_we_n;
-		soc_netsoc_sdram_master_p2_cke <= soc_netsoc_sdram_inti_p2_cke;
-		soc_netsoc_sdram_master_p2_odt <= soc_netsoc_sdram_inti_p2_odt;
-		soc_netsoc_sdram_master_p2_reset_n <= soc_netsoc_sdram_inti_p2_reset_n;
-		soc_netsoc_sdram_master_p2_act_n <= soc_netsoc_sdram_inti_p2_act_n;
-		soc_netsoc_sdram_master_p2_wrdata <= soc_netsoc_sdram_inti_p2_wrdata;
-		soc_netsoc_sdram_master_p2_wrdata_en <= soc_netsoc_sdram_inti_p2_wrdata_en;
-		soc_netsoc_sdram_master_p2_wrdata_mask <= soc_netsoc_sdram_inti_p2_wrdata_mask;
-		soc_netsoc_sdram_master_p2_rddata_en <= soc_netsoc_sdram_inti_p2_rddata_en;
-		soc_netsoc_sdram_inti_p2_rddata <= soc_netsoc_sdram_master_p2_rddata;
-		soc_netsoc_sdram_inti_p2_rddata_valid <= soc_netsoc_sdram_master_p2_rddata_valid;
-		soc_netsoc_sdram_master_p3_address <= soc_netsoc_sdram_inti_p3_address;
-		soc_netsoc_sdram_master_p3_bank <= soc_netsoc_sdram_inti_p3_bank;
-		soc_netsoc_sdram_master_p3_cas_n <= soc_netsoc_sdram_inti_p3_cas_n;
-		soc_netsoc_sdram_master_p3_cs_n <= soc_netsoc_sdram_inti_p3_cs_n;
-		soc_netsoc_sdram_master_p3_ras_n <= soc_netsoc_sdram_inti_p3_ras_n;
-		soc_netsoc_sdram_master_p3_we_n <= soc_netsoc_sdram_inti_p3_we_n;
-		soc_netsoc_sdram_master_p3_cke <= soc_netsoc_sdram_inti_p3_cke;
-		soc_netsoc_sdram_master_p3_odt <= soc_netsoc_sdram_inti_p3_odt;
-		soc_netsoc_sdram_master_p3_reset_n <= soc_netsoc_sdram_inti_p3_reset_n;
-		soc_netsoc_sdram_master_p3_act_n <= soc_netsoc_sdram_inti_p3_act_n;
-		soc_netsoc_sdram_master_p3_wrdata <= soc_netsoc_sdram_inti_p3_wrdata;
-		soc_netsoc_sdram_master_p3_wrdata_en <= soc_netsoc_sdram_inti_p3_wrdata_en;
-		soc_netsoc_sdram_master_p3_wrdata_mask <= soc_netsoc_sdram_inti_p3_wrdata_mask;
-		soc_netsoc_sdram_master_p3_rddata_en <= soc_netsoc_sdram_inti_p3_rddata_en;
-		soc_netsoc_sdram_inti_p3_rddata <= soc_netsoc_sdram_master_p3_rddata;
-		soc_netsoc_sdram_inti_p3_rddata_valid <= soc_netsoc_sdram_master_p3_rddata_valid;
-	end
-end
-assign soc_netsoc_sdram_inti_p0_cke = soc_netsoc_sdram_storage[1];
-assign soc_netsoc_sdram_inti_p1_cke = soc_netsoc_sdram_storage[1];
-assign soc_netsoc_sdram_inti_p2_cke = soc_netsoc_sdram_storage[1];
-assign soc_netsoc_sdram_inti_p3_cke = soc_netsoc_sdram_storage[1];
-assign soc_netsoc_sdram_inti_p0_odt = soc_netsoc_sdram_storage[2];
-assign soc_netsoc_sdram_inti_p1_odt = soc_netsoc_sdram_storage[2];
-assign soc_netsoc_sdram_inti_p2_odt = soc_netsoc_sdram_storage[2];
-assign soc_netsoc_sdram_inti_p3_odt = soc_netsoc_sdram_storage[2];
-assign soc_netsoc_sdram_inti_p0_reset_n = soc_netsoc_sdram_storage[3];
-assign soc_netsoc_sdram_inti_p1_reset_n = soc_netsoc_sdram_storage[3];
-assign soc_netsoc_sdram_inti_p2_reset_n = soc_netsoc_sdram_storage[3];
-assign soc_netsoc_sdram_inti_p3_reset_n = soc_netsoc_sdram_storage[3];
-always @(*) begin
-	soc_netsoc_sdram_inti_p0_we_n <= 1'd1;
-	soc_netsoc_sdram_inti_p0_cas_n <= 1'd1;
-	soc_netsoc_sdram_inti_p0_cs_n <= 1'd1;
-	soc_netsoc_sdram_inti_p0_ras_n <= 1'd1;
-	if (soc_netsoc_sdram_phaseinjector0_command_issue_re) begin
-		soc_netsoc_sdram_inti_p0_cs_n <= {1{(~soc_netsoc_sdram_phaseinjector0_command_storage[0])}};
-		soc_netsoc_sdram_inti_p0_we_n <= (~soc_netsoc_sdram_phaseinjector0_command_storage[1]);
-		soc_netsoc_sdram_inti_p0_cas_n <= (~soc_netsoc_sdram_phaseinjector0_command_storage[2]);
-		soc_netsoc_sdram_inti_p0_ras_n <= (~soc_netsoc_sdram_phaseinjector0_command_storage[3]);
-	end else begin
-		soc_netsoc_sdram_inti_p0_cs_n <= {1{1'd1}};
-		soc_netsoc_sdram_inti_p0_we_n <= 1'd1;
-		soc_netsoc_sdram_inti_p0_cas_n <= 1'd1;
-		soc_netsoc_sdram_inti_p0_ras_n <= 1'd1;
-	end
-end
-assign soc_netsoc_sdram_inti_p0_address = soc_netsoc_sdram_phaseinjector0_address_storage;
-assign soc_netsoc_sdram_inti_p0_bank = soc_netsoc_sdram_phaseinjector0_baddress_storage;
-assign soc_netsoc_sdram_inti_p0_wrdata_en = (soc_netsoc_sdram_phaseinjector0_command_issue_re & soc_netsoc_sdram_phaseinjector0_command_storage[4]);
-assign soc_netsoc_sdram_inti_p0_rddata_en = (soc_netsoc_sdram_phaseinjector0_command_issue_re & soc_netsoc_sdram_phaseinjector0_command_storage[5]);
-assign soc_netsoc_sdram_inti_p0_wrdata = soc_netsoc_sdram_phaseinjector0_wrdata_storage;
-assign soc_netsoc_sdram_inti_p0_wrdata_mask = 1'd0;
-always @(*) begin
-	soc_netsoc_sdram_inti_p1_we_n <= 1'd1;
-	soc_netsoc_sdram_inti_p1_cas_n <= 1'd1;
-	soc_netsoc_sdram_inti_p1_cs_n <= 1'd1;
-	soc_netsoc_sdram_inti_p1_ras_n <= 1'd1;
-	if (soc_netsoc_sdram_phaseinjector1_command_issue_re) begin
-		soc_netsoc_sdram_inti_p1_cs_n <= {1{(~soc_netsoc_sdram_phaseinjector1_command_storage[0])}};
-		soc_netsoc_sdram_inti_p1_we_n <= (~soc_netsoc_sdram_phaseinjector1_command_storage[1]);
-		soc_netsoc_sdram_inti_p1_cas_n <= (~soc_netsoc_sdram_phaseinjector1_command_storage[2]);
-		soc_netsoc_sdram_inti_p1_ras_n <= (~soc_netsoc_sdram_phaseinjector1_command_storage[3]);
-	end else begin
-		soc_netsoc_sdram_inti_p1_cs_n <= {1{1'd1}};
-		soc_netsoc_sdram_inti_p1_we_n <= 1'd1;
-		soc_netsoc_sdram_inti_p1_cas_n <= 1'd1;
-		soc_netsoc_sdram_inti_p1_ras_n <= 1'd1;
-	end
-end
-assign soc_netsoc_sdram_inti_p1_address = soc_netsoc_sdram_phaseinjector1_address_storage;
-assign soc_netsoc_sdram_inti_p1_bank = soc_netsoc_sdram_phaseinjector1_baddress_storage;
-assign soc_netsoc_sdram_inti_p1_wrdata_en = (soc_netsoc_sdram_phaseinjector1_command_issue_re & soc_netsoc_sdram_phaseinjector1_command_storage[4]);
-assign soc_netsoc_sdram_inti_p1_rddata_en = (soc_netsoc_sdram_phaseinjector1_command_issue_re & soc_netsoc_sdram_phaseinjector1_command_storage[5]);
-assign soc_netsoc_sdram_inti_p1_wrdata = soc_netsoc_sdram_phaseinjector1_wrdata_storage;
-assign soc_netsoc_sdram_inti_p1_wrdata_mask = 1'd0;
-always @(*) begin
-	soc_netsoc_sdram_inti_p2_we_n <= 1'd1;
-	soc_netsoc_sdram_inti_p2_cas_n <= 1'd1;
-	soc_netsoc_sdram_inti_p2_cs_n <= 1'd1;
-	soc_netsoc_sdram_inti_p2_ras_n <= 1'd1;
-	if (soc_netsoc_sdram_phaseinjector2_command_issue_re) begin
-		soc_netsoc_sdram_inti_p2_cs_n <= {1{(~soc_netsoc_sdram_phaseinjector2_command_storage[0])}};
-		soc_netsoc_sdram_inti_p2_we_n <= (~soc_netsoc_sdram_phaseinjector2_command_storage[1]);
-		soc_netsoc_sdram_inti_p2_cas_n <= (~soc_netsoc_sdram_phaseinjector2_command_storage[2]);
-		soc_netsoc_sdram_inti_p2_ras_n <= (~soc_netsoc_sdram_phaseinjector2_command_storage[3]);
-	end else begin
-		soc_netsoc_sdram_inti_p2_cs_n <= {1{1'd1}};
-		soc_netsoc_sdram_inti_p2_we_n <= 1'd1;
-		soc_netsoc_sdram_inti_p2_cas_n <= 1'd1;
-		soc_netsoc_sdram_inti_p2_ras_n <= 1'd1;
-	end
-end
-assign soc_netsoc_sdram_inti_p2_address = soc_netsoc_sdram_phaseinjector2_address_storage;
-assign soc_netsoc_sdram_inti_p2_bank = soc_netsoc_sdram_phaseinjector2_baddress_storage;
-assign soc_netsoc_sdram_inti_p2_wrdata_en = (soc_netsoc_sdram_phaseinjector2_command_issue_re & soc_netsoc_sdram_phaseinjector2_command_storage[4]);
-assign soc_netsoc_sdram_inti_p2_rddata_en = (soc_netsoc_sdram_phaseinjector2_command_issue_re & soc_netsoc_sdram_phaseinjector2_command_storage[5]);
-assign soc_netsoc_sdram_inti_p2_wrdata = soc_netsoc_sdram_phaseinjector2_wrdata_storage;
-assign soc_netsoc_sdram_inti_p2_wrdata_mask = 1'd0;
-always @(*) begin
-	soc_netsoc_sdram_inti_p3_we_n <= 1'd1;
-	soc_netsoc_sdram_inti_p3_cas_n <= 1'd1;
-	soc_netsoc_sdram_inti_p3_cs_n <= 1'd1;
-	soc_netsoc_sdram_inti_p3_ras_n <= 1'd1;
-	if (soc_netsoc_sdram_phaseinjector3_command_issue_re) begin
-		soc_netsoc_sdram_inti_p3_cs_n <= {1{(~soc_netsoc_sdram_phaseinjector3_command_storage[0])}};
-		soc_netsoc_sdram_inti_p3_we_n <= (~soc_netsoc_sdram_phaseinjector3_command_storage[1]);
-		soc_netsoc_sdram_inti_p3_cas_n <= (~soc_netsoc_sdram_phaseinjector3_command_storage[2]);
-		soc_netsoc_sdram_inti_p3_ras_n <= (~soc_netsoc_sdram_phaseinjector3_command_storage[3]);
-	end else begin
-		soc_netsoc_sdram_inti_p3_cs_n <= {1{1'd1}};
-		soc_netsoc_sdram_inti_p3_we_n <= 1'd1;
-		soc_netsoc_sdram_inti_p3_cas_n <= 1'd1;
-		soc_netsoc_sdram_inti_p3_ras_n <= 1'd1;
-	end
-end
-assign soc_netsoc_sdram_inti_p3_address = soc_netsoc_sdram_phaseinjector3_address_storage;
-assign soc_netsoc_sdram_inti_p3_bank = soc_netsoc_sdram_phaseinjector3_baddress_storage;
-assign soc_netsoc_sdram_inti_p3_wrdata_en = (soc_netsoc_sdram_phaseinjector3_command_issue_re & soc_netsoc_sdram_phaseinjector3_command_storage[4]);
-assign soc_netsoc_sdram_inti_p3_rddata_en = (soc_netsoc_sdram_phaseinjector3_command_issue_re & soc_netsoc_sdram_phaseinjector3_command_storage[5]);
-assign soc_netsoc_sdram_inti_p3_wrdata = soc_netsoc_sdram_phaseinjector3_wrdata_storage;
-assign soc_netsoc_sdram_inti_p3_wrdata_mask = 1'd0;
-assign soc_netsoc_sdram_bankmachine0_req_valid = soc_netsoc_sdram_interface_bank0_valid;
-assign soc_netsoc_sdram_interface_bank0_ready = soc_netsoc_sdram_bankmachine0_req_ready;
-assign soc_netsoc_sdram_bankmachine0_req_we = soc_netsoc_sdram_interface_bank0_we;
-assign soc_netsoc_sdram_bankmachine0_req_addr = soc_netsoc_sdram_interface_bank0_addr;
-assign soc_netsoc_sdram_interface_bank0_lock = soc_netsoc_sdram_bankmachine0_req_lock;
-assign soc_netsoc_sdram_interface_bank0_wdata_ready = soc_netsoc_sdram_bankmachine0_req_wdata_ready;
-assign soc_netsoc_sdram_interface_bank0_rdata_valid = soc_netsoc_sdram_bankmachine0_req_rdata_valid;
-assign soc_netsoc_sdram_bankmachine1_req_valid = soc_netsoc_sdram_interface_bank1_valid;
-assign soc_netsoc_sdram_interface_bank1_ready = soc_netsoc_sdram_bankmachine1_req_ready;
-assign soc_netsoc_sdram_bankmachine1_req_we = soc_netsoc_sdram_interface_bank1_we;
-assign soc_netsoc_sdram_bankmachine1_req_addr = soc_netsoc_sdram_interface_bank1_addr;
-assign soc_netsoc_sdram_interface_bank1_lock = soc_netsoc_sdram_bankmachine1_req_lock;
-assign soc_netsoc_sdram_interface_bank1_wdata_ready = soc_netsoc_sdram_bankmachine1_req_wdata_ready;
-assign soc_netsoc_sdram_interface_bank1_rdata_valid = soc_netsoc_sdram_bankmachine1_req_rdata_valid;
-assign soc_netsoc_sdram_bankmachine2_req_valid = soc_netsoc_sdram_interface_bank2_valid;
-assign soc_netsoc_sdram_interface_bank2_ready = soc_netsoc_sdram_bankmachine2_req_ready;
-assign soc_netsoc_sdram_bankmachine2_req_we = soc_netsoc_sdram_interface_bank2_we;
-assign soc_netsoc_sdram_bankmachine2_req_addr = soc_netsoc_sdram_interface_bank2_addr;
-assign soc_netsoc_sdram_interface_bank2_lock = soc_netsoc_sdram_bankmachine2_req_lock;
-assign soc_netsoc_sdram_interface_bank2_wdata_ready = soc_netsoc_sdram_bankmachine2_req_wdata_ready;
-assign soc_netsoc_sdram_interface_bank2_rdata_valid = soc_netsoc_sdram_bankmachine2_req_rdata_valid;
-assign soc_netsoc_sdram_bankmachine3_req_valid = soc_netsoc_sdram_interface_bank3_valid;
-assign soc_netsoc_sdram_interface_bank3_ready = soc_netsoc_sdram_bankmachine3_req_ready;
-assign soc_netsoc_sdram_bankmachine3_req_we = soc_netsoc_sdram_interface_bank3_we;
-assign soc_netsoc_sdram_bankmachine3_req_addr = soc_netsoc_sdram_interface_bank3_addr;
-assign soc_netsoc_sdram_interface_bank3_lock = soc_netsoc_sdram_bankmachine3_req_lock;
-assign soc_netsoc_sdram_interface_bank3_wdata_ready = soc_netsoc_sdram_bankmachine3_req_wdata_ready;
-assign soc_netsoc_sdram_interface_bank3_rdata_valid = soc_netsoc_sdram_bankmachine3_req_rdata_valid;
-assign soc_netsoc_sdram_bankmachine4_req_valid = soc_netsoc_sdram_interface_bank4_valid;
-assign soc_netsoc_sdram_interface_bank4_ready = soc_netsoc_sdram_bankmachine4_req_ready;
-assign soc_netsoc_sdram_bankmachine4_req_we = soc_netsoc_sdram_interface_bank4_we;
-assign soc_netsoc_sdram_bankmachine4_req_addr = soc_netsoc_sdram_interface_bank4_addr;
-assign soc_netsoc_sdram_interface_bank4_lock = soc_netsoc_sdram_bankmachine4_req_lock;
-assign soc_netsoc_sdram_interface_bank4_wdata_ready = soc_netsoc_sdram_bankmachine4_req_wdata_ready;
-assign soc_netsoc_sdram_interface_bank4_rdata_valid = soc_netsoc_sdram_bankmachine4_req_rdata_valid;
-assign soc_netsoc_sdram_bankmachine5_req_valid = soc_netsoc_sdram_interface_bank5_valid;
-assign soc_netsoc_sdram_interface_bank5_ready = soc_netsoc_sdram_bankmachine5_req_ready;
-assign soc_netsoc_sdram_bankmachine5_req_we = soc_netsoc_sdram_interface_bank5_we;
-assign soc_netsoc_sdram_bankmachine5_req_addr = soc_netsoc_sdram_interface_bank5_addr;
-assign soc_netsoc_sdram_interface_bank5_lock = soc_netsoc_sdram_bankmachine5_req_lock;
-assign soc_netsoc_sdram_interface_bank5_wdata_ready = soc_netsoc_sdram_bankmachine5_req_wdata_ready;
-assign soc_netsoc_sdram_interface_bank5_rdata_valid = soc_netsoc_sdram_bankmachine5_req_rdata_valid;
-assign soc_netsoc_sdram_bankmachine6_req_valid = soc_netsoc_sdram_interface_bank6_valid;
-assign soc_netsoc_sdram_interface_bank6_ready = soc_netsoc_sdram_bankmachine6_req_ready;
-assign soc_netsoc_sdram_bankmachine6_req_we = soc_netsoc_sdram_interface_bank6_we;
-assign soc_netsoc_sdram_bankmachine6_req_addr = soc_netsoc_sdram_interface_bank6_addr;
-assign soc_netsoc_sdram_interface_bank6_lock = soc_netsoc_sdram_bankmachine6_req_lock;
-assign soc_netsoc_sdram_interface_bank6_wdata_ready = soc_netsoc_sdram_bankmachine6_req_wdata_ready;
-assign soc_netsoc_sdram_interface_bank6_rdata_valid = soc_netsoc_sdram_bankmachine6_req_rdata_valid;
-assign soc_netsoc_sdram_bankmachine7_req_valid = soc_netsoc_sdram_interface_bank7_valid;
-assign soc_netsoc_sdram_interface_bank7_ready = soc_netsoc_sdram_bankmachine7_req_ready;
-assign soc_netsoc_sdram_bankmachine7_req_we = soc_netsoc_sdram_interface_bank7_we;
-assign soc_netsoc_sdram_bankmachine7_req_addr = soc_netsoc_sdram_interface_bank7_addr;
-assign soc_netsoc_sdram_interface_bank7_lock = soc_netsoc_sdram_bankmachine7_req_lock;
-assign soc_netsoc_sdram_interface_bank7_wdata_ready = soc_netsoc_sdram_bankmachine7_req_wdata_ready;
-assign soc_netsoc_sdram_interface_bank7_rdata_valid = soc_netsoc_sdram_bankmachine7_req_rdata_valid;
-assign soc_netsoc_sdram_timer_wait = (~soc_netsoc_sdram_timer_done0);
-assign soc_netsoc_sdram_postponer_req_i = soc_netsoc_sdram_timer_done0;
-assign soc_netsoc_sdram_wants_refresh = soc_netsoc_sdram_postponer_req_o;
-assign soc_netsoc_sdram_wants_zqcs = soc_netsoc_sdram_zqcs_timer_done0;
-assign soc_netsoc_sdram_zqcs_timer_wait = (~soc_netsoc_sdram_zqcs_executer_done);
-assign soc_netsoc_sdram_timer_done1 = (soc_netsoc_sdram_timer_count1 == 1'd0);
-assign soc_netsoc_sdram_timer_done0 = soc_netsoc_sdram_timer_done1;
-assign soc_netsoc_sdram_timer_count0 = soc_netsoc_sdram_timer_count1;
-assign soc_netsoc_sdram_sequencer_start1 = (soc_netsoc_sdram_sequencer_start0 | (soc_netsoc_sdram_sequencer_count != 1'd0));
-assign soc_netsoc_sdram_sequencer_done0 = (soc_netsoc_sdram_sequencer_done1 & (soc_netsoc_sdram_sequencer_count == 1'd0));
-assign soc_netsoc_sdram_zqcs_timer_done1 = (soc_netsoc_sdram_zqcs_timer_count1 == 1'd0);
-assign soc_netsoc_sdram_zqcs_timer_done0 = soc_netsoc_sdram_zqcs_timer_done1;
-assign soc_netsoc_sdram_zqcs_timer_count0 = soc_netsoc_sdram_zqcs_timer_count1;
-always @(*) begin
-	soc_netsoc_sdram_cmd_valid <= 1'd0;
-	soc_netsoc_sdram_zqcs_executer_start <= 1'd0;
-	soc_netsoc_sdram_cmd_last <= 1'd0;
-	soc_netsoc_sdram_sequencer_start0 <= 1'd0;
-	vns_refresher_next_state <= 2'd0;
-	vns_refresher_next_state <= vns_refresher_state;
-	case (vns_refresher_state)
-		1'd1: begin
-			soc_netsoc_sdram_cmd_valid <= 1'd1;
-			if (soc_netsoc_sdram_cmd_ready) begin
-				soc_netsoc_sdram_sequencer_start0 <= 1'd1;
-				vns_refresher_next_state <= 2'd2;
-			end
-		end
-		2'd2: begin
-			soc_netsoc_sdram_cmd_valid <= 1'd1;
-			if (soc_netsoc_sdram_sequencer_done0) begin
-				if (soc_netsoc_sdram_wants_zqcs) begin
-					soc_netsoc_sdram_zqcs_executer_start <= 1'd1;
-					vns_refresher_next_state <= 2'd3;
-				end else begin
-					soc_netsoc_sdram_cmd_valid <= 1'd0;
-					soc_netsoc_sdram_cmd_last <= 1'd1;
-					vns_refresher_next_state <= 1'd0;
-				end
-			end
-		end
-		2'd3: begin
-			soc_netsoc_sdram_cmd_valid <= 1'd1;
-			if (soc_netsoc_sdram_zqcs_executer_done) begin
-				soc_netsoc_sdram_cmd_valid <= 1'd0;
-				soc_netsoc_sdram_cmd_last <= 1'd1;
-				vns_refresher_next_state <= 1'd0;
-			end
-		end
-		default: begin
-			if (1'd1) begin
-				if (soc_netsoc_sdram_wants_refresh) begin
-					vns_refresher_next_state <= 1'd1;
-				end
-			end
-		end
-	endcase
-end
-assign soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid = soc_netsoc_sdram_bankmachine0_req_valid;
-assign soc_netsoc_sdram_bankmachine0_req_ready = soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready;
-assign soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we = soc_netsoc_sdram_bankmachine0_req_we;
-assign soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = soc_netsoc_sdram_bankmachine0_req_addr;
-assign soc_netsoc_sdram_bankmachine0_cmd_buffer_sink_valid = soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_source_valid;
-assign soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_source_ready = soc_netsoc_sdram_bankmachine0_cmd_buffer_sink_ready;
-assign soc_netsoc_sdram_bankmachine0_cmd_buffer_sink_first = soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_source_first;
-assign soc_netsoc_sdram_bankmachine0_cmd_buffer_sink_last = soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_source_last;
-assign soc_netsoc_sdram_bankmachine0_cmd_buffer_sink_payload_we = soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we;
-assign soc_netsoc_sdram_bankmachine0_cmd_buffer_sink_payload_addr = soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
-assign soc_netsoc_sdram_bankmachine0_cmd_buffer_source_ready = (soc_netsoc_sdram_bankmachine0_req_wdata_ready | soc_netsoc_sdram_bankmachine0_req_rdata_valid);
-assign soc_netsoc_sdram_bankmachine0_req_lock = (soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_source_valid | soc_netsoc_sdram_bankmachine0_cmd_buffer_source_valid);
-assign soc_netsoc_sdram_bankmachine0_row_hit = (soc_netsoc_sdram_bankmachine0_row == soc_netsoc_sdram_bankmachine0_cmd_buffer_source_payload_addr[20:7]);
-assign soc_netsoc_sdram_bankmachine0_cmd_payload_ba = 1'd0;
-always @(*) begin
-	soc_netsoc_sdram_bankmachine0_cmd_payload_a <= 14'd0;
-	if (soc_netsoc_sdram_bankmachine0_row_col_n_addr_sel) begin
-		soc_netsoc_sdram_bankmachine0_cmd_payload_a <= soc_netsoc_sdram_bankmachine0_cmd_buffer_source_payload_addr[20:7];
-	end else begin
-		soc_netsoc_sdram_bankmachine0_cmd_payload_a <= ((soc_netsoc_sdram_bankmachine0_auto_precharge <<< 4'd10) | {soc_netsoc_sdram_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
-	end
-end
-assign soc_netsoc_sdram_bankmachine0_twtpcon_valid = ((soc_netsoc_sdram_bankmachine0_cmd_valid & soc_netsoc_sdram_bankmachine0_cmd_ready) & soc_netsoc_sdram_bankmachine0_cmd_payload_is_write);
-assign soc_netsoc_sdram_bankmachine0_trccon_valid = ((soc_netsoc_sdram_bankmachine0_cmd_valid & soc_netsoc_sdram_bankmachine0_cmd_ready) & soc_netsoc_sdram_bankmachine0_row_open);
-assign soc_netsoc_sdram_bankmachine0_trascon_valid = ((soc_netsoc_sdram_bankmachine0_cmd_valid & soc_netsoc_sdram_bankmachine0_cmd_ready) & soc_netsoc_sdram_bankmachine0_row_open);
-always @(*) begin
-	soc_netsoc_sdram_bankmachine0_auto_precharge <= 1'd0;
-	if ((soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_source_valid & soc_netsoc_sdram_bankmachine0_cmd_buffer_source_valid)) begin
-		if ((soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_netsoc_sdram_bankmachine0_cmd_buffer_source_payload_addr[20:7])) begin
-			soc_netsoc_sdram_bankmachine0_auto_precharge <= (soc_netsoc_sdram_bankmachine0_row_close == 1'd0);
-		end
-	end
-end
-assign soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last, soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first, soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready = soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
-assign soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid;
-assign soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first = soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_sink_first;
-assign soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last = soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_sink_last;
-assign soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
-assign soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
-assign soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_source_valid = soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
-assign soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_source_first = soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
-assign soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_source_last = soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
-assign soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we = soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
-assign soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr = soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_source_ready;
-always @(*) begin
-	soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 3'd0;
-	if (soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_replace) begin
-		soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_produce - 1'd1);
-	end else begin
-		soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_produce;
-	end
-end
-assign soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
-assign soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we = (soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_replace));
-assign soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_do_read = (soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re);
-assign soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr = soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_consume;
-assign soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
-assign soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_level != 4'd8);
-assign soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_level != 1'd0);
-assign soc_netsoc_sdram_bankmachine0_cmd_buffer_pipe_ce = (soc_netsoc_sdram_bankmachine0_cmd_buffer_source_ready | (~soc_netsoc_sdram_bankmachine0_cmd_buffer_valid_n));
-assign soc_netsoc_sdram_bankmachine0_cmd_buffer_sink_ready = soc_netsoc_sdram_bankmachine0_cmd_buffer_pipe_ce;
-assign soc_netsoc_sdram_bankmachine0_cmd_buffer_source_valid = soc_netsoc_sdram_bankmachine0_cmd_buffer_valid_n;
-assign soc_netsoc_sdram_bankmachine0_cmd_buffer_busy = (1'd0 | soc_netsoc_sdram_bankmachine0_cmd_buffer_valid_n);
-assign soc_netsoc_sdram_bankmachine0_cmd_buffer_source_first = soc_netsoc_sdram_bankmachine0_cmd_buffer_first_n;
-assign soc_netsoc_sdram_bankmachine0_cmd_buffer_source_last = soc_netsoc_sdram_bankmachine0_cmd_buffer_last_n;
-always @(*) begin
-	soc_netsoc_sdram_bankmachine0_req_wdata_ready <= 1'd0;
-	soc_netsoc_sdram_bankmachine0_row_open <= 1'd0;
-	soc_netsoc_sdram_bankmachine0_req_rdata_valid <= 1'd0;
-	soc_netsoc_sdram_bankmachine0_row_col_n_addr_sel <= 1'd0;
-	soc_netsoc_sdram_bankmachine0_refresh_gnt <= 1'd0;
-	soc_netsoc_sdram_bankmachine0_cmd_valid <= 1'd0;
-	soc_netsoc_sdram_bankmachine0_cmd_payload_cas <= 1'd0;
-	soc_netsoc_sdram_bankmachine0_cmd_payload_ras <= 1'd0;
-	soc_netsoc_sdram_bankmachine0_cmd_payload_we <= 1'd0;
-	soc_netsoc_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd0;
-	vns_bankmachine0_next_state <= 3'd0;
-	soc_netsoc_sdram_bankmachine0_cmd_payload_is_read <= 1'd0;
-	soc_netsoc_sdram_bankmachine0_row_close <= 1'd0;
-	soc_netsoc_sdram_bankmachine0_cmd_payload_is_write <= 1'd0;
-	vns_bankmachine0_next_state <= vns_bankmachine0_state;
-	case (vns_bankmachine0_state)
-		1'd1: begin
-			if ((soc_netsoc_sdram_bankmachine0_twtpcon_ready & soc_netsoc_sdram_bankmachine0_trascon_ready)) begin
-				soc_netsoc_sdram_bankmachine0_cmd_valid <= 1'd1;
-				if (soc_netsoc_sdram_bankmachine0_cmd_ready) begin
-					vns_bankmachine0_next_state <= 3'd5;
-				end
-				soc_netsoc_sdram_bankmachine0_cmd_payload_ras <= 1'd1;
-				soc_netsoc_sdram_bankmachine0_cmd_payload_we <= 1'd1;
-				soc_netsoc_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1;
-			end
-			soc_netsoc_sdram_bankmachine0_row_close <= 1'd1;
-		end
-		2'd2: begin
-			if ((soc_netsoc_sdram_bankmachine0_twtpcon_ready & soc_netsoc_sdram_bankmachine0_trascon_ready)) begin
-				vns_bankmachine0_next_state <= 3'd5;
-			end
-			soc_netsoc_sdram_bankmachine0_row_close <= 1'd1;
-		end
-		2'd3: begin
-			if (soc_netsoc_sdram_bankmachine0_trccon_ready) begin
-				soc_netsoc_sdram_bankmachine0_row_col_n_addr_sel <= 1'd1;
-				soc_netsoc_sdram_bankmachine0_row_open <= 1'd1;
-				soc_netsoc_sdram_bankmachine0_cmd_valid <= 1'd1;
-				soc_netsoc_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1;
-				if (soc_netsoc_sdram_bankmachine0_cmd_ready) begin
-					vns_bankmachine0_next_state <= 3'd6;
-				end
-				soc_netsoc_sdram_bankmachine0_cmd_payload_ras <= 1'd1;
-			end
-		end
-		3'd4: begin
-			if (soc_netsoc_sdram_bankmachine0_twtpcon_ready) begin
-				soc_netsoc_sdram_bankmachine0_refresh_gnt <= 1'd1;
-			end
-			soc_netsoc_sdram_bankmachine0_row_close <= 1'd1;
-			soc_netsoc_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1;
-			if ((~soc_netsoc_sdram_bankmachine0_refresh_req)) begin
-				vns_bankmachine0_next_state <= 1'd0;
-			end
-		end
-		3'd5: begin
-			vns_bankmachine0_next_state <= 2'd3;
-		end
-		3'd6: begin
-			vns_bankmachine0_next_state <= 1'd0;
-		end
-		default: begin
-			if (soc_netsoc_sdram_bankmachine0_refresh_req) begin
-				vns_bankmachine0_next_state <= 3'd4;
-			end else begin
-				if (soc_netsoc_sdram_bankmachine0_cmd_buffer_source_valid) begin
-					if (soc_netsoc_sdram_bankmachine0_row_opened) begin
-						if (soc_netsoc_sdram_bankmachine0_row_hit) begin
-							soc_netsoc_sdram_bankmachine0_cmd_valid <= 1'd1;
-							if (soc_netsoc_sdram_bankmachine0_cmd_buffer_source_payload_we) begin
-								soc_netsoc_sdram_bankmachine0_req_wdata_ready <= soc_netsoc_sdram_bankmachine0_cmd_ready;
-								soc_netsoc_sdram_bankmachine0_cmd_payload_is_write <= 1'd1;
-								soc_netsoc_sdram_bankmachine0_cmd_payload_we <= 1'd1;
-							end else begin
-								soc_netsoc_sdram_bankmachine0_req_rdata_valid <= soc_netsoc_sdram_bankmachine0_cmd_ready;
-								soc_netsoc_sdram_bankmachine0_cmd_payload_is_read <= 1'd1;
-							end
-							soc_netsoc_sdram_bankmachine0_cmd_payload_cas <= 1'd1;
-							if ((soc_netsoc_sdram_bankmachine0_cmd_ready & soc_netsoc_sdram_bankmachine0_auto_precharge)) begin
-								vns_bankmachine0_next_state <= 2'd2;
-							end
-						end else begin
-							vns_bankmachine0_next_state <= 1'd1;
-						end
-					end else begin
-						vns_bankmachine0_next_state <= 2'd3;
-					end
-				end
-			end
-		end
-	endcase
-end
-assign soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid = soc_netsoc_sdram_bankmachine1_req_valid;
-assign soc_netsoc_sdram_bankmachine1_req_ready = soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready;
-assign soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we = soc_netsoc_sdram_bankmachine1_req_we;
-assign soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = soc_netsoc_sdram_bankmachine1_req_addr;
-assign soc_netsoc_sdram_bankmachine1_cmd_buffer_sink_valid = soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_source_valid;
-assign soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_source_ready = soc_netsoc_sdram_bankmachine1_cmd_buffer_sink_ready;
-assign soc_netsoc_sdram_bankmachine1_cmd_buffer_sink_first = soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_source_first;
-assign soc_netsoc_sdram_bankmachine1_cmd_buffer_sink_last = soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_source_last;
-assign soc_netsoc_sdram_bankmachine1_cmd_buffer_sink_payload_we = soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we;
-assign soc_netsoc_sdram_bankmachine1_cmd_buffer_sink_payload_addr = soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
-assign soc_netsoc_sdram_bankmachine1_cmd_buffer_source_ready = (soc_netsoc_sdram_bankmachine1_req_wdata_ready | soc_netsoc_sdram_bankmachine1_req_rdata_valid);
-assign soc_netsoc_sdram_bankmachine1_req_lock = (soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_source_valid | soc_netsoc_sdram_bankmachine1_cmd_buffer_source_valid);
-assign soc_netsoc_sdram_bankmachine1_row_hit = (soc_netsoc_sdram_bankmachine1_row == soc_netsoc_sdram_bankmachine1_cmd_buffer_source_payload_addr[20:7]);
-assign soc_netsoc_sdram_bankmachine1_cmd_payload_ba = 1'd1;
-always @(*) begin
-	soc_netsoc_sdram_bankmachine1_cmd_payload_a <= 14'd0;
-	if (soc_netsoc_sdram_bankmachine1_row_col_n_addr_sel) begin
-		soc_netsoc_sdram_bankmachine1_cmd_payload_a <= soc_netsoc_sdram_bankmachine1_cmd_buffer_source_payload_addr[20:7];
-	end else begin
-		soc_netsoc_sdram_bankmachine1_cmd_payload_a <= ((soc_netsoc_sdram_bankmachine1_auto_precharge <<< 4'd10) | {soc_netsoc_sdram_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
-	end
-end
-assign soc_netsoc_sdram_bankmachine1_twtpcon_valid = ((soc_netsoc_sdram_bankmachine1_cmd_valid & soc_netsoc_sdram_bankmachine1_cmd_ready) & soc_netsoc_sdram_bankmachine1_cmd_payload_is_write);
-assign soc_netsoc_sdram_bankmachine1_trccon_valid = ((soc_netsoc_sdram_bankmachine1_cmd_valid & soc_netsoc_sdram_bankmachine1_cmd_ready) & soc_netsoc_sdram_bankmachine1_row_open);
-assign soc_netsoc_sdram_bankmachine1_trascon_valid = ((soc_netsoc_sdram_bankmachine1_cmd_valid & soc_netsoc_sdram_bankmachine1_cmd_ready) & soc_netsoc_sdram_bankmachine1_row_open);
-always @(*) begin
-	soc_netsoc_sdram_bankmachine1_auto_precharge <= 1'd0;
-	if ((soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_source_valid & soc_netsoc_sdram_bankmachine1_cmd_buffer_source_valid)) begin
-		if ((soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_netsoc_sdram_bankmachine1_cmd_buffer_source_payload_addr[20:7])) begin
-			soc_netsoc_sdram_bankmachine1_auto_precharge <= (soc_netsoc_sdram_bankmachine1_row_close == 1'd0);
-		end
-	end
-end
-assign soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last, soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first, soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready = soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
-assign soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid;
-assign soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first = soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_sink_first;
-assign soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last = soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_sink_last;
-assign soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
-assign soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
-assign soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_source_valid = soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
-assign soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_source_first = soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
-assign soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_source_last = soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
-assign soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we = soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
-assign soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr = soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_source_ready;
-always @(*) begin
-	soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 3'd0;
-	if (soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_replace) begin
-		soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_produce - 1'd1);
-	end else begin
-		soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_produce;
-	end
-end
-assign soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
-assign soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we = (soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_replace));
-assign soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_do_read = (soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re);
-assign soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr = soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_consume;
-assign soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
-assign soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_level != 4'd8);
-assign soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_level != 1'd0);
-assign soc_netsoc_sdram_bankmachine1_cmd_buffer_pipe_ce = (soc_netsoc_sdram_bankmachine1_cmd_buffer_source_ready | (~soc_netsoc_sdram_bankmachine1_cmd_buffer_valid_n));
-assign soc_netsoc_sdram_bankmachine1_cmd_buffer_sink_ready = soc_netsoc_sdram_bankmachine1_cmd_buffer_pipe_ce;
-assign soc_netsoc_sdram_bankmachine1_cmd_buffer_source_valid = soc_netsoc_sdram_bankmachine1_cmd_buffer_valid_n;
-assign soc_netsoc_sdram_bankmachine1_cmd_buffer_busy = (1'd0 | soc_netsoc_sdram_bankmachine1_cmd_buffer_valid_n);
-assign soc_netsoc_sdram_bankmachine1_cmd_buffer_source_first = soc_netsoc_sdram_bankmachine1_cmd_buffer_first_n;
-assign soc_netsoc_sdram_bankmachine1_cmd_buffer_source_last = soc_netsoc_sdram_bankmachine1_cmd_buffer_last_n;
-always @(*) begin
-	soc_netsoc_sdram_bankmachine1_cmd_payload_cas <= 1'd0;
-	soc_netsoc_sdram_bankmachine1_cmd_payload_ras <= 1'd0;
-	soc_netsoc_sdram_bankmachine1_cmd_payload_we <= 1'd0;
-	soc_netsoc_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd0;
-	soc_netsoc_sdram_bankmachine1_row_open <= 1'd0;
-	soc_netsoc_sdram_bankmachine1_cmd_payload_is_read <= 1'd0;
-	soc_netsoc_sdram_bankmachine1_row_close <= 1'd0;
-	soc_netsoc_sdram_bankmachine1_cmd_payload_is_write <= 1'd0;
-	soc_netsoc_sdram_bankmachine1_req_wdata_ready <= 1'd0;
-	soc_netsoc_sdram_bankmachine1_req_rdata_valid <= 1'd0;
-	soc_netsoc_sdram_bankmachine1_row_col_n_addr_sel <= 1'd0;
-	soc_netsoc_sdram_bankmachine1_refresh_gnt <= 1'd0;
-	soc_netsoc_sdram_bankmachine1_cmd_valid <= 1'd0;
-	vns_bankmachine1_next_state <= 3'd0;
-	vns_bankmachine1_next_state <= vns_bankmachine1_state;
-	case (vns_bankmachine1_state)
-		1'd1: begin
-			if ((soc_netsoc_sdram_bankmachine1_twtpcon_ready & soc_netsoc_sdram_bankmachine1_trascon_ready)) begin
-				soc_netsoc_sdram_bankmachine1_cmd_valid <= 1'd1;
-				if (soc_netsoc_sdram_bankmachine1_cmd_ready) begin
-					vns_bankmachine1_next_state <= 3'd5;
-				end
-				soc_netsoc_sdram_bankmachine1_cmd_payload_ras <= 1'd1;
-				soc_netsoc_sdram_bankmachine1_cmd_payload_we <= 1'd1;
-				soc_netsoc_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1;
-			end
-			soc_netsoc_sdram_bankmachine1_row_close <= 1'd1;
-		end
-		2'd2: begin
-			if ((soc_netsoc_sdram_bankmachine1_twtpcon_ready & soc_netsoc_sdram_bankmachine1_trascon_ready)) begin
-				vns_bankmachine1_next_state <= 3'd5;
-			end
-			soc_netsoc_sdram_bankmachine1_row_close <= 1'd1;
-		end
-		2'd3: begin
-			if (soc_netsoc_sdram_bankmachine1_trccon_ready) begin
-				soc_netsoc_sdram_bankmachine1_row_col_n_addr_sel <= 1'd1;
-				soc_netsoc_sdram_bankmachine1_row_open <= 1'd1;
-				soc_netsoc_sdram_bankmachine1_cmd_valid <= 1'd1;
-				soc_netsoc_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1;
-				if (soc_netsoc_sdram_bankmachine1_cmd_ready) begin
-					vns_bankmachine1_next_state <= 3'd6;
-				end
-				soc_netsoc_sdram_bankmachine1_cmd_payload_ras <= 1'd1;
-			end
-		end
-		3'd4: begin
-			if (soc_netsoc_sdram_bankmachine1_twtpcon_ready) begin
-				soc_netsoc_sdram_bankmachine1_refresh_gnt <= 1'd1;
-			end
-			soc_netsoc_sdram_bankmachine1_row_close <= 1'd1;
-			soc_netsoc_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1;
-			if ((~soc_netsoc_sdram_bankmachine1_refresh_req)) begin
-				vns_bankmachine1_next_state <= 1'd0;
-			end
-		end
-		3'd5: begin
-			vns_bankmachine1_next_state <= 2'd3;
-		end
-		3'd6: begin
-			vns_bankmachine1_next_state <= 1'd0;
-		end
-		default: begin
-			if (soc_netsoc_sdram_bankmachine1_refresh_req) begin
-				vns_bankmachine1_next_state <= 3'd4;
-			end else begin
-				if (soc_netsoc_sdram_bankmachine1_cmd_buffer_source_valid) begin
-					if (soc_netsoc_sdram_bankmachine1_row_opened) begin
-						if (soc_netsoc_sdram_bankmachine1_row_hit) begin
-							soc_netsoc_sdram_bankmachine1_cmd_valid <= 1'd1;
-							if (soc_netsoc_sdram_bankmachine1_cmd_buffer_source_payload_we) begin
-								soc_netsoc_sdram_bankmachine1_req_wdata_ready <= soc_netsoc_sdram_bankmachine1_cmd_ready;
-								soc_netsoc_sdram_bankmachine1_cmd_payload_is_write <= 1'd1;
-								soc_netsoc_sdram_bankmachine1_cmd_payload_we <= 1'd1;
-							end else begin
-								soc_netsoc_sdram_bankmachine1_req_rdata_valid <= soc_netsoc_sdram_bankmachine1_cmd_ready;
-								soc_netsoc_sdram_bankmachine1_cmd_payload_is_read <= 1'd1;
-							end
-							soc_netsoc_sdram_bankmachine1_cmd_payload_cas <= 1'd1;
-							if ((soc_netsoc_sdram_bankmachine1_cmd_ready & soc_netsoc_sdram_bankmachine1_auto_precharge)) begin
-								vns_bankmachine1_next_state <= 2'd2;
-							end
-						end else begin
-							vns_bankmachine1_next_state <= 1'd1;
-						end
-					end else begin
-						vns_bankmachine1_next_state <= 2'd3;
-					end
-				end
-			end
-		end
-	endcase
-end
-assign soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid = soc_netsoc_sdram_bankmachine2_req_valid;
-assign soc_netsoc_sdram_bankmachine2_req_ready = soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready;
-assign soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we = soc_netsoc_sdram_bankmachine2_req_we;
-assign soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = soc_netsoc_sdram_bankmachine2_req_addr;
-assign soc_netsoc_sdram_bankmachine2_cmd_buffer_sink_valid = soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_source_valid;
-assign soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_source_ready = soc_netsoc_sdram_bankmachine2_cmd_buffer_sink_ready;
-assign soc_netsoc_sdram_bankmachine2_cmd_buffer_sink_first = soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_source_first;
-assign soc_netsoc_sdram_bankmachine2_cmd_buffer_sink_last = soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_source_last;
-assign soc_netsoc_sdram_bankmachine2_cmd_buffer_sink_payload_we = soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we;
-assign soc_netsoc_sdram_bankmachine2_cmd_buffer_sink_payload_addr = soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
-assign soc_netsoc_sdram_bankmachine2_cmd_buffer_source_ready = (soc_netsoc_sdram_bankmachine2_req_wdata_ready | soc_netsoc_sdram_bankmachine2_req_rdata_valid);
-assign soc_netsoc_sdram_bankmachine2_req_lock = (soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_source_valid | soc_netsoc_sdram_bankmachine2_cmd_buffer_source_valid);
-assign soc_netsoc_sdram_bankmachine2_row_hit = (soc_netsoc_sdram_bankmachine2_row == soc_netsoc_sdram_bankmachine2_cmd_buffer_source_payload_addr[20:7]);
-assign soc_netsoc_sdram_bankmachine2_cmd_payload_ba = 2'd2;
-always @(*) begin
-	soc_netsoc_sdram_bankmachine2_cmd_payload_a <= 14'd0;
-	if (soc_netsoc_sdram_bankmachine2_row_col_n_addr_sel) begin
-		soc_netsoc_sdram_bankmachine2_cmd_payload_a <= soc_netsoc_sdram_bankmachine2_cmd_buffer_source_payload_addr[20:7];
-	end else begin
-		soc_netsoc_sdram_bankmachine2_cmd_payload_a <= ((soc_netsoc_sdram_bankmachine2_auto_precharge <<< 4'd10) | {soc_netsoc_sdram_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
-	end
-end
-assign soc_netsoc_sdram_bankmachine2_twtpcon_valid = ((soc_netsoc_sdram_bankmachine2_cmd_valid & soc_netsoc_sdram_bankmachine2_cmd_ready) & soc_netsoc_sdram_bankmachine2_cmd_payload_is_write);
-assign soc_netsoc_sdram_bankmachine2_trccon_valid = ((soc_netsoc_sdram_bankmachine2_cmd_valid & soc_netsoc_sdram_bankmachine2_cmd_ready) & soc_netsoc_sdram_bankmachine2_row_open);
-assign soc_netsoc_sdram_bankmachine2_trascon_valid = ((soc_netsoc_sdram_bankmachine2_cmd_valid & soc_netsoc_sdram_bankmachine2_cmd_ready) & soc_netsoc_sdram_bankmachine2_row_open);
-always @(*) begin
-	soc_netsoc_sdram_bankmachine2_auto_precharge <= 1'd0;
-	if ((soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_source_valid & soc_netsoc_sdram_bankmachine2_cmd_buffer_source_valid)) begin
-		if ((soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_netsoc_sdram_bankmachine2_cmd_buffer_source_payload_addr[20:7])) begin
-			soc_netsoc_sdram_bankmachine2_auto_precharge <= (soc_netsoc_sdram_bankmachine2_row_close == 1'd0);
-		end
-	end
-end
-assign soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last, soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first, soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready = soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
-assign soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid;
-assign soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first = soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_sink_first;
-assign soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last = soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_sink_last;
-assign soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
-assign soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
-assign soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_source_valid = soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
-assign soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_source_first = soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
-assign soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_source_last = soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
-assign soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we = soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
-assign soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr = soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_source_ready;
-always @(*) begin
-	soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 3'd0;
-	if (soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_replace) begin
-		soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_produce - 1'd1);
-	end else begin
-		soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_produce;
-	end
-end
-assign soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
-assign soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we = (soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_replace));
-assign soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_do_read = (soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re);
-assign soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr = soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_consume;
-assign soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
-assign soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_level != 4'd8);
-assign soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_level != 1'd0);
-assign soc_netsoc_sdram_bankmachine2_cmd_buffer_pipe_ce = (soc_netsoc_sdram_bankmachine2_cmd_buffer_source_ready | (~soc_netsoc_sdram_bankmachine2_cmd_buffer_valid_n));
-assign soc_netsoc_sdram_bankmachine2_cmd_buffer_sink_ready = soc_netsoc_sdram_bankmachine2_cmd_buffer_pipe_ce;
-assign soc_netsoc_sdram_bankmachine2_cmd_buffer_source_valid = soc_netsoc_sdram_bankmachine2_cmd_buffer_valid_n;
-assign soc_netsoc_sdram_bankmachine2_cmd_buffer_busy = (1'd0 | soc_netsoc_sdram_bankmachine2_cmd_buffer_valid_n);
-assign soc_netsoc_sdram_bankmachine2_cmd_buffer_source_first = soc_netsoc_sdram_bankmachine2_cmd_buffer_first_n;
-assign soc_netsoc_sdram_bankmachine2_cmd_buffer_source_last = soc_netsoc_sdram_bankmachine2_cmd_buffer_last_n;
-always @(*) begin
-	soc_netsoc_sdram_bankmachine2_cmd_valid <= 1'd0;
-	soc_netsoc_sdram_bankmachine2_cmd_payload_cas <= 1'd0;
-	soc_netsoc_sdram_bankmachine2_cmd_payload_ras <= 1'd0;
-	soc_netsoc_sdram_bankmachine2_cmd_payload_we <= 1'd0;
-	soc_netsoc_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd0;
-	vns_bankmachine2_next_state <= 3'd0;
-	soc_netsoc_sdram_bankmachine2_cmd_payload_is_read <= 1'd0;
-	soc_netsoc_sdram_bankmachine2_row_close <= 1'd0;
-	soc_netsoc_sdram_bankmachine2_cmd_payload_is_write <= 1'd0;
-	soc_netsoc_sdram_bankmachine2_row_open <= 1'd0;
-	soc_netsoc_sdram_bankmachine2_req_wdata_ready <= 1'd0;
-	soc_netsoc_sdram_bankmachine2_req_rdata_valid <= 1'd0;
-	soc_netsoc_sdram_bankmachine2_row_col_n_addr_sel <= 1'd0;
-	soc_netsoc_sdram_bankmachine2_refresh_gnt <= 1'd0;
-	vns_bankmachine2_next_state <= vns_bankmachine2_state;
-	case (vns_bankmachine2_state)
-		1'd1: begin
-			if ((soc_netsoc_sdram_bankmachine2_twtpcon_ready & soc_netsoc_sdram_bankmachine2_trascon_ready)) begin
-				soc_netsoc_sdram_bankmachine2_cmd_valid <= 1'd1;
-				if (soc_netsoc_sdram_bankmachine2_cmd_ready) begin
-					vns_bankmachine2_next_state <= 3'd5;
-				end
-				soc_netsoc_sdram_bankmachine2_cmd_payload_ras <= 1'd1;
-				soc_netsoc_sdram_bankmachine2_cmd_payload_we <= 1'd1;
-				soc_netsoc_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1;
-			end
-			soc_netsoc_sdram_bankmachine2_row_close <= 1'd1;
-		end
-		2'd2: begin
-			if ((soc_netsoc_sdram_bankmachine2_twtpcon_ready & soc_netsoc_sdram_bankmachine2_trascon_ready)) begin
-				vns_bankmachine2_next_state <= 3'd5;
-			end
-			soc_netsoc_sdram_bankmachine2_row_close <= 1'd1;
-		end
-		2'd3: begin
-			if (soc_netsoc_sdram_bankmachine2_trccon_ready) begin
-				soc_netsoc_sdram_bankmachine2_row_col_n_addr_sel <= 1'd1;
-				soc_netsoc_sdram_bankmachine2_row_open <= 1'd1;
-				soc_netsoc_sdram_bankmachine2_cmd_valid <= 1'd1;
-				soc_netsoc_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1;
-				if (soc_netsoc_sdram_bankmachine2_cmd_ready) begin
-					vns_bankmachine2_next_state <= 3'd6;
-				end
-				soc_netsoc_sdram_bankmachine2_cmd_payload_ras <= 1'd1;
-			end
-		end
-		3'd4: begin
-			if (soc_netsoc_sdram_bankmachine2_twtpcon_ready) begin
-				soc_netsoc_sdram_bankmachine2_refresh_gnt <= 1'd1;
-			end
-			soc_netsoc_sdram_bankmachine2_row_close <= 1'd1;
-			soc_netsoc_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1;
-			if ((~soc_netsoc_sdram_bankmachine2_refresh_req)) begin
-				vns_bankmachine2_next_state <= 1'd0;
-			end
-		end
-		3'd5: begin
-			vns_bankmachine2_next_state <= 2'd3;
-		end
-		3'd6: begin
-			vns_bankmachine2_next_state <= 1'd0;
-		end
-		default: begin
-			if (soc_netsoc_sdram_bankmachine2_refresh_req) begin
-				vns_bankmachine2_next_state <= 3'd4;
-			end else begin
-				if (soc_netsoc_sdram_bankmachine2_cmd_buffer_source_valid) begin
-					if (soc_netsoc_sdram_bankmachine2_row_opened) begin
-						if (soc_netsoc_sdram_bankmachine2_row_hit) begin
-							soc_netsoc_sdram_bankmachine2_cmd_valid <= 1'd1;
-							if (soc_netsoc_sdram_bankmachine2_cmd_buffer_source_payload_we) begin
-								soc_netsoc_sdram_bankmachine2_req_wdata_ready <= soc_netsoc_sdram_bankmachine2_cmd_ready;
-								soc_netsoc_sdram_bankmachine2_cmd_payload_is_write <= 1'd1;
-								soc_netsoc_sdram_bankmachine2_cmd_payload_we <= 1'd1;
-							end else begin
-								soc_netsoc_sdram_bankmachine2_req_rdata_valid <= soc_netsoc_sdram_bankmachine2_cmd_ready;
-								soc_netsoc_sdram_bankmachine2_cmd_payload_is_read <= 1'd1;
-							end
-							soc_netsoc_sdram_bankmachine2_cmd_payload_cas <= 1'd1;
-							if ((soc_netsoc_sdram_bankmachine2_cmd_ready & soc_netsoc_sdram_bankmachine2_auto_precharge)) begin
-								vns_bankmachine2_next_state <= 2'd2;
-							end
-						end else begin
-							vns_bankmachine2_next_state <= 1'd1;
-						end
-					end else begin
-						vns_bankmachine2_next_state <= 2'd3;
-					end
-				end
-			end
-		end
-	endcase
-end
-assign soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid = soc_netsoc_sdram_bankmachine3_req_valid;
-assign soc_netsoc_sdram_bankmachine3_req_ready = soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready;
-assign soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we = soc_netsoc_sdram_bankmachine3_req_we;
-assign soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = soc_netsoc_sdram_bankmachine3_req_addr;
-assign soc_netsoc_sdram_bankmachine3_cmd_buffer_sink_valid = soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_source_valid;
-assign soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_source_ready = soc_netsoc_sdram_bankmachine3_cmd_buffer_sink_ready;
-assign soc_netsoc_sdram_bankmachine3_cmd_buffer_sink_first = soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_source_first;
-assign soc_netsoc_sdram_bankmachine3_cmd_buffer_sink_last = soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_source_last;
-assign soc_netsoc_sdram_bankmachine3_cmd_buffer_sink_payload_we = soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we;
-assign soc_netsoc_sdram_bankmachine3_cmd_buffer_sink_payload_addr = soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
-assign soc_netsoc_sdram_bankmachine3_cmd_buffer_source_ready = (soc_netsoc_sdram_bankmachine3_req_wdata_ready | soc_netsoc_sdram_bankmachine3_req_rdata_valid);
-assign soc_netsoc_sdram_bankmachine3_req_lock = (soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_source_valid | soc_netsoc_sdram_bankmachine3_cmd_buffer_source_valid);
-assign soc_netsoc_sdram_bankmachine3_row_hit = (soc_netsoc_sdram_bankmachine3_row == soc_netsoc_sdram_bankmachine3_cmd_buffer_source_payload_addr[20:7]);
-assign soc_netsoc_sdram_bankmachine3_cmd_payload_ba = 2'd3;
-always @(*) begin
-	soc_netsoc_sdram_bankmachine3_cmd_payload_a <= 14'd0;
-	if (soc_netsoc_sdram_bankmachine3_row_col_n_addr_sel) begin
-		soc_netsoc_sdram_bankmachine3_cmd_payload_a <= soc_netsoc_sdram_bankmachine3_cmd_buffer_source_payload_addr[20:7];
-	end else begin
-		soc_netsoc_sdram_bankmachine3_cmd_payload_a <= ((soc_netsoc_sdram_bankmachine3_auto_precharge <<< 4'd10) | {soc_netsoc_sdram_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
-	end
-end
-assign soc_netsoc_sdram_bankmachine3_twtpcon_valid = ((soc_netsoc_sdram_bankmachine3_cmd_valid & soc_netsoc_sdram_bankmachine3_cmd_ready) & soc_netsoc_sdram_bankmachine3_cmd_payload_is_write);
-assign soc_netsoc_sdram_bankmachine3_trccon_valid = ((soc_netsoc_sdram_bankmachine3_cmd_valid & soc_netsoc_sdram_bankmachine3_cmd_ready) & soc_netsoc_sdram_bankmachine3_row_open);
-assign soc_netsoc_sdram_bankmachine3_trascon_valid = ((soc_netsoc_sdram_bankmachine3_cmd_valid & soc_netsoc_sdram_bankmachine3_cmd_ready) & soc_netsoc_sdram_bankmachine3_row_open);
-always @(*) begin
-	soc_netsoc_sdram_bankmachine3_auto_precharge <= 1'd0;
-	if ((soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_source_valid & soc_netsoc_sdram_bankmachine3_cmd_buffer_source_valid)) begin
-		if ((soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_netsoc_sdram_bankmachine3_cmd_buffer_source_payload_addr[20:7])) begin
-			soc_netsoc_sdram_bankmachine3_auto_precharge <= (soc_netsoc_sdram_bankmachine3_row_close == 1'd0);
-		end
-	end
-end
-assign soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last, soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first, soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready = soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
-assign soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid;
-assign soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first = soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_sink_first;
-assign soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last = soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_sink_last;
-assign soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
-assign soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
-assign soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_source_valid = soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
-assign soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_source_first = soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
-assign soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_source_last = soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
-assign soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we = soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
-assign soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr = soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_source_ready;
-always @(*) begin
-	soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 3'd0;
-	if (soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_replace) begin
-		soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_produce - 1'd1);
-	end else begin
-		soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_produce;
-	end
-end
-assign soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
-assign soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we = (soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_replace));
-assign soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_do_read = (soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re);
-assign soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr = soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_consume;
-assign soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
-assign soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_level != 4'd8);
-assign soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_level != 1'd0);
-assign soc_netsoc_sdram_bankmachine3_cmd_buffer_pipe_ce = (soc_netsoc_sdram_bankmachine3_cmd_buffer_source_ready | (~soc_netsoc_sdram_bankmachine3_cmd_buffer_valid_n));
-assign soc_netsoc_sdram_bankmachine3_cmd_buffer_sink_ready = soc_netsoc_sdram_bankmachine3_cmd_buffer_pipe_ce;
-assign soc_netsoc_sdram_bankmachine3_cmd_buffer_source_valid = soc_netsoc_sdram_bankmachine3_cmd_buffer_valid_n;
-assign soc_netsoc_sdram_bankmachine3_cmd_buffer_busy = (1'd0 | soc_netsoc_sdram_bankmachine3_cmd_buffer_valid_n);
-assign soc_netsoc_sdram_bankmachine3_cmd_buffer_source_first = soc_netsoc_sdram_bankmachine3_cmd_buffer_first_n;
-assign soc_netsoc_sdram_bankmachine3_cmd_buffer_source_last = soc_netsoc_sdram_bankmachine3_cmd_buffer_last_n;
-always @(*) begin
-	soc_netsoc_sdram_bankmachine3_row_open <= 1'd0;
-	soc_netsoc_sdram_bankmachine3_cmd_payload_is_read <= 1'd0;
-	soc_netsoc_sdram_bankmachine3_row_close <= 1'd0;
-	soc_netsoc_sdram_bankmachine3_cmd_payload_is_write <= 1'd0;
-	soc_netsoc_sdram_bankmachine3_req_wdata_ready <= 1'd0;
-	soc_netsoc_sdram_bankmachine3_req_rdata_valid <= 1'd0;
-	soc_netsoc_sdram_bankmachine3_row_col_n_addr_sel <= 1'd0;
-	soc_netsoc_sdram_bankmachine3_refresh_gnt <= 1'd0;
-	soc_netsoc_sdram_bankmachine3_cmd_valid <= 1'd0;
-	vns_bankmachine3_next_state <= 3'd0;
-	soc_netsoc_sdram_bankmachine3_cmd_payload_cas <= 1'd0;
-	soc_netsoc_sdram_bankmachine3_cmd_payload_ras <= 1'd0;
-	soc_netsoc_sdram_bankmachine3_cmd_payload_we <= 1'd0;
-	soc_netsoc_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd0;
-	vns_bankmachine3_next_state <= vns_bankmachine3_state;
-	case (vns_bankmachine3_state)
-		1'd1: begin
-			if ((soc_netsoc_sdram_bankmachine3_twtpcon_ready & soc_netsoc_sdram_bankmachine3_trascon_ready)) begin
-				soc_netsoc_sdram_bankmachine3_cmd_valid <= 1'd1;
-				if (soc_netsoc_sdram_bankmachine3_cmd_ready) begin
-					vns_bankmachine3_next_state <= 3'd5;
-				end
-				soc_netsoc_sdram_bankmachine3_cmd_payload_ras <= 1'd1;
-				soc_netsoc_sdram_bankmachine3_cmd_payload_we <= 1'd1;
-				soc_netsoc_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1;
-			end
-			soc_netsoc_sdram_bankmachine3_row_close <= 1'd1;
-		end
-		2'd2: begin
-			if ((soc_netsoc_sdram_bankmachine3_twtpcon_ready & soc_netsoc_sdram_bankmachine3_trascon_ready)) begin
-				vns_bankmachine3_next_state <= 3'd5;
-			end
-			soc_netsoc_sdram_bankmachine3_row_close <= 1'd1;
-		end
-		2'd3: begin
-			if (soc_netsoc_sdram_bankmachine3_trccon_ready) begin
-				soc_netsoc_sdram_bankmachine3_row_col_n_addr_sel <= 1'd1;
-				soc_netsoc_sdram_bankmachine3_row_open <= 1'd1;
-				soc_netsoc_sdram_bankmachine3_cmd_valid <= 1'd1;
-				soc_netsoc_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1;
-				if (soc_netsoc_sdram_bankmachine3_cmd_ready) begin
-					vns_bankmachine3_next_state <= 3'd6;
-				end
-				soc_netsoc_sdram_bankmachine3_cmd_payload_ras <= 1'd1;
-			end
-		end
-		3'd4: begin
-			if (soc_netsoc_sdram_bankmachine3_twtpcon_ready) begin
-				soc_netsoc_sdram_bankmachine3_refresh_gnt <= 1'd1;
-			end
-			soc_netsoc_sdram_bankmachine3_row_close <= 1'd1;
-			soc_netsoc_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1;
-			if ((~soc_netsoc_sdram_bankmachine3_refresh_req)) begin
-				vns_bankmachine3_next_state <= 1'd0;
-			end
-		end
-		3'd5: begin
-			vns_bankmachine3_next_state <= 2'd3;
-		end
-		3'd6: begin
-			vns_bankmachine3_next_state <= 1'd0;
-		end
-		default: begin
-			if (soc_netsoc_sdram_bankmachine3_refresh_req) begin
-				vns_bankmachine3_next_state <= 3'd4;
-			end else begin
-				if (soc_netsoc_sdram_bankmachine3_cmd_buffer_source_valid) begin
-					if (soc_netsoc_sdram_bankmachine3_row_opened) begin
-						if (soc_netsoc_sdram_bankmachine3_row_hit) begin
-							soc_netsoc_sdram_bankmachine3_cmd_valid <= 1'd1;
-							if (soc_netsoc_sdram_bankmachine3_cmd_buffer_source_payload_we) begin
-								soc_netsoc_sdram_bankmachine3_req_wdata_ready <= soc_netsoc_sdram_bankmachine3_cmd_ready;
-								soc_netsoc_sdram_bankmachine3_cmd_payload_is_write <= 1'd1;
-								soc_netsoc_sdram_bankmachine3_cmd_payload_we <= 1'd1;
-							end else begin
-								soc_netsoc_sdram_bankmachine3_req_rdata_valid <= soc_netsoc_sdram_bankmachine3_cmd_ready;
-								soc_netsoc_sdram_bankmachine3_cmd_payload_is_read <= 1'd1;
-							end
-							soc_netsoc_sdram_bankmachine3_cmd_payload_cas <= 1'd1;
-							if ((soc_netsoc_sdram_bankmachine3_cmd_ready & soc_netsoc_sdram_bankmachine3_auto_precharge)) begin
-								vns_bankmachine3_next_state <= 2'd2;
-							end
-						end else begin
-							vns_bankmachine3_next_state <= 1'd1;
-						end
-					end else begin
-						vns_bankmachine3_next_state <= 2'd3;
-					end
-				end
-			end
-		end
-	endcase
-end
-assign soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_sink_valid = soc_netsoc_sdram_bankmachine4_req_valid;
-assign soc_netsoc_sdram_bankmachine4_req_ready = soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_sink_ready;
-assign soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_we = soc_netsoc_sdram_bankmachine4_req_we;
-assign soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = soc_netsoc_sdram_bankmachine4_req_addr;
-assign soc_netsoc_sdram_bankmachine4_cmd_buffer_sink_valid = soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_source_valid;
-assign soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_source_ready = soc_netsoc_sdram_bankmachine4_cmd_buffer_sink_ready;
-assign soc_netsoc_sdram_bankmachine4_cmd_buffer_sink_first = soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_source_first;
-assign soc_netsoc_sdram_bankmachine4_cmd_buffer_sink_last = soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_source_last;
-assign soc_netsoc_sdram_bankmachine4_cmd_buffer_sink_payload_we = soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_we;
-assign soc_netsoc_sdram_bankmachine4_cmd_buffer_sink_payload_addr = soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
-assign soc_netsoc_sdram_bankmachine4_cmd_buffer_source_ready = (soc_netsoc_sdram_bankmachine4_req_wdata_ready | soc_netsoc_sdram_bankmachine4_req_rdata_valid);
-assign soc_netsoc_sdram_bankmachine4_req_lock = (soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_source_valid | soc_netsoc_sdram_bankmachine4_cmd_buffer_source_valid);
-assign soc_netsoc_sdram_bankmachine4_row_hit = (soc_netsoc_sdram_bankmachine4_row == soc_netsoc_sdram_bankmachine4_cmd_buffer_source_payload_addr[20:7]);
-assign soc_netsoc_sdram_bankmachine4_cmd_payload_ba = 3'd4;
-always @(*) begin
-	soc_netsoc_sdram_bankmachine4_cmd_payload_a <= 14'd0;
-	if (soc_netsoc_sdram_bankmachine4_row_col_n_addr_sel) begin
-		soc_netsoc_sdram_bankmachine4_cmd_payload_a <= soc_netsoc_sdram_bankmachine4_cmd_buffer_source_payload_addr[20:7];
-	end else begin
-		soc_netsoc_sdram_bankmachine4_cmd_payload_a <= ((soc_netsoc_sdram_bankmachine4_auto_precharge <<< 4'd10) | {soc_netsoc_sdram_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
-	end
-end
-assign soc_netsoc_sdram_bankmachine4_twtpcon_valid = ((soc_netsoc_sdram_bankmachine4_cmd_valid & soc_netsoc_sdram_bankmachine4_cmd_ready) & soc_netsoc_sdram_bankmachine4_cmd_payload_is_write);
-assign soc_netsoc_sdram_bankmachine4_trccon_valid = ((soc_netsoc_sdram_bankmachine4_cmd_valid & soc_netsoc_sdram_bankmachine4_cmd_ready) & soc_netsoc_sdram_bankmachine4_row_open);
-assign soc_netsoc_sdram_bankmachine4_trascon_valid = ((soc_netsoc_sdram_bankmachine4_cmd_valid & soc_netsoc_sdram_bankmachine4_cmd_ready) & soc_netsoc_sdram_bankmachine4_row_open);
-always @(*) begin
-	soc_netsoc_sdram_bankmachine4_auto_precharge <= 1'd0;
-	if ((soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_source_valid & soc_netsoc_sdram_bankmachine4_cmd_buffer_source_valid)) begin
-		if ((soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_netsoc_sdram_bankmachine4_cmd_buffer_source_payload_addr[20:7])) begin
-			soc_netsoc_sdram_bankmachine4_auto_precharge <= (soc_netsoc_sdram_bankmachine4_row_close == 1'd0);
-		end
-	end
-end
-assign soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_last, soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_first, soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_sink_ready = soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
-assign soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_sink_valid;
-assign soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_first = soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_sink_first;
-assign soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_last = soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_sink_last;
-assign soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
-assign soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
-assign soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_source_valid = soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
-assign soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_source_first = soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
-assign soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_source_last = soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
-assign soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_we = soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
-assign soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr = soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_source_ready;
-always @(*) begin
-	soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 3'd0;
-	if (soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_replace) begin
-		soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_produce - 1'd1);
-	end else begin
-		soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr <= soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_produce;
-	end
-end
-assign soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
-assign soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_we = (soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_replace));
-assign soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_do_read = (soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_re);
-assign soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_adr = soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_consume;
-assign soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
-assign soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_level != 4'd8);
-assign soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_level != 1'd0);
-assign soc_netsoc_sdram_bankmachine4_cmd_buffer_pipe_ce = (soc_netsoc_sdram_bankmachine4_cmd_buffer_source_ready | (~soc_netsoc_sdram_bankmachine4_cmd_buffer_valid_n));
-assign soc_netsoc_sdram_bankmachine4_cmd_buffer_sink_ready = soc_netsoc_sdram_bankmachine4_cmd_buffer_pipe_ce;
-assign soc_netsoc_sdram_bankmachine4_cmd_buffer_source_valid = soc_netsoc_sdram_bankmachine4_cmd_buffer_valid_n;
-assign soc_netsoc_sdram_bankmachine4_cmd_buffer_busy = (1'd0 | soc_netsoc_sdram_bankmachine4_cmd_buffer_valid_n);
-assign soc_netsoc_sdram_bankmachine4_cmd_buffer_source_first = soc_netsoc_sdram_bankmachine4_cmd_buffer_first_n;
-assign soc_netsoc_sdram_bankmachine4_cmd_buffer_source_last = soc_netsoc_sdram_bankmachine4_cmd_buffer_last_n;
-always @(*) begin
-	soc_netsoc_sdram_bankmachine4_cmd_payload_cas <= 1'd0;
-	soc_netsoc_sdram_bankmachine4_cmd_payload_ras <= 1'd0;
-	soc_netsoc_sdram_bankmachine4_cmd_payload_we <= 1'd0;
-	soc_netsoc_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd0;
-	vns_bankmachine4_next_state <= 3'd0;
-	soc_netsoc_sdram_bankmachine4_cmd_payload_is_read <= 1'd0;
-	soc_netsoc_sdram_bankmachine4_row_close <= 1'd0;
-	soc_netsoc_sdram_bankmachine4_cmd_payload_is_write <= 1'd0;
-	soc_netsoc_sdram_bankmachine4_row_open <= 1'd0;
-	soc_netsoc_sdram_bankmachine4_req_wdata_ready <= 1'd0;
-	soc_netsoc_sdram_bankmachine4_req_rdata_valid <= 1'd0;
-	soc_netsoc_sdram_bankmachine4_row_col_n_addr_sel <= 1'd0;
-	soc_netsoc_sdram_bankmachine4_refresh_gnt <= 1'd0;
-	soc_netsoc_sdram_bankmachine4_cmd_valid <= 1'd0;
-	vns_bankmachine4_next_state <= vns_bankmachine4_state;
-	case (vns_bankmachine4_state)
-		1'd1: begin
-			if ((soc_netsoc_sdram_bankmachine4_twtpcon_ready & soc_netsoc_sdram_bankmachine4_trascon_ready)) begin
-				soc_netsoc_sdram_bankmachine4_cmd_valid <= 1'd1;
-				if (soc_netsoc_sdram_bankmachine4_cmd_ready) begin
-					vns_bankmachine4_next_state <= 3'd5;
-				end
-				soc_netsoc_sdram_bankmachine4_cmd_payload_ras <= 1'd1;
-				soc_netsoc_sdram_bankmachine4_cmd_payload_we <= 1'd1;
-				soc_netsoc_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd1;
-			end
-			soc_netsoc_sdram_bankmachine4_row_close <= 1'd1;
-		end
-		2'd2: begin
-			if ((soc_netsoc_sdram_bankmachine4_twtpcon_ready & soc_netsoc_sdram_bankmachine4_trascon_ready)) begin
-				vns_bankmachine4_next_state <= 3'd5;
-			end
-			soc_netsoc_sdram_bankmachine4_row_close <= 1'd1;
-		end
-		2'd3: begin
-			if (soc_netsoc_sdram_bankmachine4_trccon_ready) begin
-				soc_netsoc_sdram_bankmachine4_row_col_n_addr_sel <= 1'd1;
-				soc_netsoc_sdram_bankmachine4_row_open <= 1'd1;
-				soc_netsoc_sdram_bankmachine4_cmd_valid <= 1'd1;
-				soc_netsoc_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd1;
-				if (soc_netsoc_sdram_bankmachine4_cmd_ready) begin
-					vns_bankmachine4_next_state <= 3'd6;
-				end
-				soc_netsoc_sdram_bankmachine4_cmd_payload_ras <= 1'd1;
-			end
-		end
-		3'd4: begin
-			if (soc_netsoc_sdram_bankmachine4_twtpcon_ready) begin
-				soc_netsoc_sdram_bankmachine4_refresh_gnt <= 1'd1;
-			end
-			soc_netsoc_sdram_bankmachine4_row_close <= 1'd1;
-			soc_netsoc_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd1;
-			if ((~soc_netsoc_sdram_bankmachine4_refresh_req)) begin
-				vns_bankmachine4_next_state <= 1'd0;
-			end
-		end
-		3'd5: begin
-			vns_bankmachine4_next_state <= 2'd3;
-		end
-		3'd6: begin
-			vns_bankmachine4_next_state <= 1'd0;
-		end
-		default: begin
-			if (soc_netsoc_sdram_bankmachine4_refresh_req) begin
-				vns_bankmachine4_next_state <= 3'd4;
-			end else begin
-				if (soc_netsoc_sdram_bankmachine4_cmd_buffer_source_valid) begin
-					if (soc_netsoc_sdram_bankmachine4_row_opened) begin
-						if (soc_netsoc_sdram_bankmachine4_row_hit) begin
-							soc_netsoc_sdram_bankmachine4_cmd_valid <= 1'd1;
-							if (soc_netsoc_sdram_bankmachine4_cmd_buffer_source_payload_we) begin
-								soc_netsoc_sdram_bankmachine4_req_wdata_ready <= soc_netsoc_sdram_bankmachine4_cmd_ready;
-								soc_netsoc_sdram_bankmachine4_cmd_payload_is_write <= 1'd1;
-								soc_netsoc_sdram_bankmachine4_cmd_payload_we <= 1'd1;
-							end else begin
-								soc_netsoc_sdram_bankmachine4_req_rdata_valid <= soc_netsoc_sdram_bankmachine4_cmd_ready;
-								soc_netsoc_sdram_bankmachine4_cmd_payload_is_read <= 1'd1;
-							end
-							soc_netsoc_sdram_bankmachine4_cmd_payload_cas <= 1'd1;
-							if ((soc_netsoc_sdram_bankmachine4_cmd_ready & soc_netsoc_sdram_bankmachine4_auto_precharge)) begin
-								vns_bankmachine4_next_state <= 2'd2;
-							end
-						end else begin
-							vns_bankmachine4_next_state <= 1'd1;
-						end
-					end else begin
-						vns_bankmachine4_next_state <= 2'd3;
-					end
-				end
-			end
-		end
-	endcase
-end
-assign soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_sink_valid = soc_netsoc_sdram_bankmachine5_req_valid;
-assign soc_netsoc_sdram_bankmachine5_req_ready = soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_sink_ready;
-assign soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_we = soc_netsoc_sdram_bankmachine5_req_we;
-assign soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = soc_netsoc_sdram_bankmachine5_req_addr;
-assign soc_netsoc_sdram_bankmachine5_cmd_buffer_sink_valid = soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_source_valid;
-assign soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_source_ready = soc_netsoc_sdram_bankmachine5_cmd_buffer_sink_ready;
-assign soc_netsoc_sdram_bankmachine5_cmd_buffer_sink_first = soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_source_first;
-assign soc_netsoc_sdram_bankmachine5_cmd_buffer_sink_last = soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_source_last;
-assign soc_netsoc_sdram_bankmachine5_cmd_buffer_sink_payload_we = soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_we;
-assign soc_netsoc_sdram_bankmachine5_cmd_buffer_sink_payload_addr = soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
-assign soc_netsoc_sdram_bankmachine5_cmd_buffer_source_ready = (soc_netsoc_sdram_bankmachine5_req_wdata_ready | soc_netsoc_sdram_bankmachine5_req_rdata_valid);
-assign soc_netsoc_sdram_bankmachine5_req_lock = (soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_source_valid | soc_netsoc_sdram_bankmachine5_cmd_buffer_source_valid);
-assign soc_netsoc_sdram_bankmachine5_row_hit = (soc_netsoc_sdram_bankmachine5_row == soc_netsoc_sdram_bankmachine5_cmd_buffer_source_payload_addr[20:7]);
-assign soc_netsoc_sdram_bankmachine5_cmd_payload_ba = 3'd5;
-always @(*) begin
-	soc_netsoc_sdram_bankmachine5_cmd_payload_a <= 14'd0;
-	if (soc_netsoc_sdram_bankmachine5_row_col_n_addr_sel) begin
-		soc_netsoc_sdram_bankmachine5_cmd_payload_a <= soc_netsoc_sdram_bankmachine5_cmd_buffer_source_payload_addr[20:7];
-	end else begin
-		soc_netsoc_sdram_bankmachine5_cmd_payload_a <= ((soc_netsoc_sdram_bankmachine5_auto_precharge <<< 4'd10) | {soc_netsoc_sdram_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
-	end
-end
-assign soc_netsoc_sdram_bankmachine5_twtpcon_valid = ((soc_netsoc_sdram_bankmachine5_cmd_valid & soc_netsoc_sdram_bankmachine5_cmd_ready) & soc_netsoc_sdram_bankmachine5_cmd_payload_is_write);
-assign soc_netsoc_sdram_bankmachine5_trccon_valid = ((soc_netsoc_sdram_bankmachine5_cmd_valid & soc_netsoc_sdram_bankmachine5_cmd_ready) & soc_netsoc_sdram_bankmachine5_row_open);
-assign soc_netsoc_sdram_bankmachine5_trascon_valid = ((soc_netsoc_sdram_bankmachine5_cmd_valid & soc_netsoc_sdram_bankmachine5_cmd_ready) & soc_netsoc_sdram_bankmachine5_row_open);
-always @(*) begin
-	soc_netsoc_sdram_bankmachine5_auto_precharge <= 1'd0;
-	if ((soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_source_valid & soc_netsoc_sdram_bankmachine5_cmd_buffer_source_valid)) begin
-		if ((soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_netsoc_sdram_bankmachine5_cmd_buffer_source_payload_addr[20:7])) begin
-			soc_netsoc_sdram_bankmachine5_auto_precharge <= (soc_netsoc_sdram_bankmachine5_row_close == 1'd0);
-		end
-	end
-end
-assign soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_last, soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_first, soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_sink_ready = soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
-assign soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_sink_valid;
-assign soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_first = soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_sink_first;
-assign soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_last = soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_sink_last;
-assign soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
-assign soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
-assign soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_source_valid = soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
-assign soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_source_first = soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
-assign soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_source_last = soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
-assign soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_we = soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
-assign soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr = soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_source_ready;
-always @(*) begin
-	soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 3'd0;
-	if (soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_replace) begin
-		soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_produce - 1'd1);
-	end else begin
-		soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr <= soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_produce;
-	end
-end
-assign soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
-assign soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_we = (soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_replace));
-assign soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_do_read = (soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_re);
-assign soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_adr = soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_consume;
-assign soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
-assign soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_level != 4'd8);
-assign soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_level != 1'd0);
-assign soc_netsoc_sdram_bankmachine5_cmd_buffer_pipe_ce = (soc_netsoc_sdram_bankmachine5_cmd_buffer_source_ready | (~soc_netsoc_sdram_bankmachine5_cmd_buffer_valid_n));
-assign soc_netsoc_sdram_bankmachine5_cmd_buffer_sink_ready = soc_netsoc_sdram_bankmachine5_cmd_buffer_pipe_ce;
-assign soc_netsoc_sdram_bankmachine5_cmd_buffer_source_valid = soc_netsoc_sdram_bankmachine5_cmd_buffer_valid_n;
-assign soc_netsoc_sdram_bankmachine5_cmd_buffer_busy = (1'd0 | soc_netsoc_sdram_bankmachine5_cmd_buffer_valid_n);
-assign soc_netsoc_sdram_bankmachine5_cmd_buffer_source_first = soc_netsoc_sdram_bankmachine5_cmd_buffer_first_n;
-assign soc_netsoc_sdram_bankmachine5_cmd_buffer_source_last = soc_netsoc_sdram_bankmachine5_cmd_buffer_last_n;
-always @(*) begin
-	soc_netsoc_sdram_bankmachine5_row_col_n_addr_sel <= 1'd0;
-	soc_netsoc_sdram_bankmachine5_refresh_gnt <= 1'd0;
-	soc_netsoc_sdram_bankmachine5_cmd_valid <= 1'd0;
-	vns_bankmachine5_next_state <= 3'd0;
-	soc_netsoc_sdram_bankmachine5_cmd_payload_cas <= 1'd0;
-	soc_netsoc_sdram_bankmachine5_cmd_payload_ras <= 1'd0;
-	soc_netsoc_sdram_bankmachine5_cmd_payload_we <= 1'd0;
-	soc_netsoc_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd0;
-	soc_netsoc_sdram_bankmachine5_row_open <= 1'd0;
-	soc_netsoc_sdram_bankmachine5_cmd_payload_is_read <= 1'd0;
-	soc_netsoc_sdram_bankmachine5_row_close <= 1'd0;
-	soc_netsoc_sdram_bankmachine5_cmd_payload_is_write <= 1'd0;
-	soc_netsoc_sdram_bankmachine5_req_wdata_ready <= 1'd0;
-	soc_netsoc_sdram_bankmachine5_req_rdata_valid <= 1'd0;
-	vns_bankmachine5_next_state <= vns_bankmachine5_state;
-	case (vns_bankmachine5_state)
-		1'd1: begin
-			if ((soc_netsoc_sdram_bankmachine5_twtpcon_ready & soc_netsoc_sdram_bankmachine5_trascon_ready)) begin
-				soc_netsoc_sdram_bankmachine5_cmd_valid <= 1'd1;
-				if (soc_netsoc_sdram_bankmachine5_cmd_ready) begin
-					vns_bankmachine5_next_state <= 3'd5;
-				end
-				soc_netsoc_sdram_bankmachine5_cmd_payload_ras <= 1'd1;
-				soc_netsoc_sdram_bankmachine5_cmd_payload_we <= 1'd1;
-				soc_netsoc_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd1;
-			end
-			soc_netsoc_sdram_bankmachine5_row_close <= 1'd1;
-		end
-		2'd2: begin
-			if ((soc_netsoc_sdram_bankmachine5_twtpcon_ready & soc_netsoc_sdram_bankmachine5_trascon_ready)) begin
-				vns_bankmachine5_next_state <= 3'd5;
-			end
-			soc_netsoc_sdram_bankmachine5_row_close <= 1'd1;
-		end
-		2'd3: begin
-			if (soc_netsoc_sdram_bankmachine5_trccon_ready) begin
-				soc_netsoc_sdram_bankmachine5_row_col_n_addr_sel <= 1'd1;
-				soc_netsoc_sdram_bankmachine5_row_open <= 1'd1;
-				soc_netsoc_sdram_bankmachine5_cmd_valid <= 1'd1;
-				soc_netsoc_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd1;
-				if (soc_netsoc_sdram_bankmachine5_cmd_ready) begin
-					vns_bankmachine5_next_state <= 3'd6;
-				end
-				soc_netsoc_sdram_bankmachine5_cmd_payload_ras <= 1'd1;
-			end
-		end
-		3'd4: begin
-			if (soc_netsoc_sdram_bankmachine5_twtpcon_ready) begin
-				soc_netsoc_sdram_bankmachine5_refresh_gnt <= 1'd1;
-			end
-			soc_netsoc_sdram_bankmachine5_row_close <= 1'd1;
-			soc_netsoc_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd1;
-			if ((~soc_netsoc_sdram_bankmachine5_refresh_req)) begin
-				vns_bankmachine5_next_state <= 1'd0;
-			end
-		end
-		3'd5: begin
-			vns_bankmachine5_next_state <= 2'd3;
-		end
-		3'd6: begin
-			vns_bankmachine5_next_state <= 1'd0;
-		end
-		default: begin
-			if (soc_netsoc_sdram_bankmachine5_refresh_req) begin
-				vns_bankmachine5_next_state <= 3'd4;
-			end else begin
-				if (soc_netsoc_sdram_bankmachine5_cmd_buffer_source_valid) begin
-					if (soc_netsoc_sdram_bankmachine5_row_opened) begin
-						if (soc_netsoc_sdram_bankmachine5_row_hit) begin
-							soc_netsoc_sdram_bankmachine5_cmd_valid <= 1'd1;
-							if (soc_netsoc_sdram_bankmachine5_cmd_buffer_source_payload_we) begin
-								soc_netsoc_sdram_bankmachine5_req_wdata_ready <= soc_netsoc_sdram_bankmachine5_cmd_ready;
-								soc_netsoc_sdram_bankmachine5_cmd_payload_is_write <= 1'd1;
-								soc_netsoc_sdram_bankmachine5_cmd_payload_we <= 1'd1;
-							end else begin
-								soc_netsoc_sdram_bankmachine5_req_rdata_valid <= soc_netsoc_sdram_bankmachine5_cmd_ready;
-								soc_netsoc_sdram_bankmachine5_cmd_payload_is_read <= 1'd1;
-							end
-							soc_netsoc_sdram_bankmachine5_cmd_payload_cas <= 1'd1;
-							if ((soc_netsoc_sdram_bankmachine5_cmd_ready & soc_netsoc_sdram_bankmachine5_auto_precharge)) begin
-								vns_bankmachine5_next_state <= 2'd2;
-							end
-						end else begin
-							vns_bankmachine5_next_state <= 1'd1;
-						end
-					end else begin
-						vns_bankmachine5_next_state <= 2'd3;
-					end
-				end
-			end
-		end
-	endcase
-end
-assign soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_sink_valid = soc_netsoc_sdram_bankmachine6_req_valid;
-assign soc_netsoc_sdram_bankmachine6_req_ready = soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_sink_ready;
-assign soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_we = soc_netsoc_sdram_bankmachine6_req_we;
-assign soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = soc_netsoc_sdram_bankmachine6_req_addr;
-assign soc_netsoc_sdram_bankmachine6_cmd_buffer_sink_valid = soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_source_valid;
-assign soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_source_ready = soc_netsoc_sdram_bankmachine6_cmd_buffer_sink_ready;
-assign soc_netsoc_sdram_bankmachine6_cmd_buffer_sink_first = soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_source_first;
-assign soc_netsoc_sdram_bankmachine6_cmd_buffer_sink_last = soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_source_last;
-assign soc_netsoc_sdram_bankmachine6_cmd_buffer_sink_payload_we = soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_we;
-assign soc_netsoc_sdram_bankmachine6_cmd_buffer_sink_payload_addr = soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
-assign soc_netsoc_sdram_bankmachine6_cmd_buffer_source_ready = (soc_netsoc_sdram_bankmachine6_req_wdata_ready | soc_netsoc_sdram_bankmachine6_req_rdata_valid);
-assign soc_netsoc_sdram_bankmachine6_req_lock = (soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_source_valid | soc_netsoc_sdram_bankmachine6_cmd_buffer_source_valid);
-assign soc_netsoc_sdram_bankmachine6_row_hit = (soc_netsoc_sdram_bankmachine6_row == soc_netsoc_sdram_bankmachine6_cmd_buffer_source_payload_addr[20:7]);
-assign soc_netsoc_sdram_bankmachine6_cmd_payload_ba = 3'd6;
-always @(*) begin
-	soc_netsoc_sdram_bankmachine6_cmd_payload_a <= 14'd0;
-	if (soc_netsoc_sdram_bankmachine6_row_col_n_addr_sel) begin
-		soc_netsoc_sdram_bankmachine6_cmd_payload_a <= soc_netsoc_sdram_bankmachine6_cmd_buffer_source_payload_addr[20:7];
-	end else begin
-		soc_netsoc_sdram_bankmachine6_cmd_payload_a <= ((soc_netsoc_sdram_bankmachine6_auto_precharge <<< 4'd10) | {soc_netsoc_sdram_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
-	end
-end
-assign soc_netsoc_sdram_bankmachine6_twtpcon_valid = ((soc_netsoc_sdram_bankmachine6_cmd_valid & soc_netsoc_sdram_bankmachine6_cmd_ready) & soc_netsoc_sdram_bankmachine6_cmd_payload_is_write);
-assign soc_netsoc_sdram_bankmachine6_trccon_valid = ((soc_netsoc_sdram_bankmachine6_cmd_valid & soc_netsoc_sdram_bankmachine6_cmd_ready) & soc_netsoc_sdram_bankmachine6_row_open);
-assign soc_netsoc_sdram_bankmachine6_trascon_valid = ((soc_netsoc_sdram_bankmachine6_cmd_valid & soc_netsoc_sdram_bankmachine6_cmd_ready) & soc_netsoc_sdram_bankmachine6_row_open);
-always @(*) begin
-	soc_netsoc_sdram_bankmachine6_auto_precharge <= 1'd0;
-	if ((soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_source_valid & soc_netsoc_sdram_bankmachine6_cmd_buffer_source_valid)) begin
-		if ((soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_netsoc_sdram_bankmachine6_cmd_buffer_source_payload_addr[20:7])) begin
-			soc_netsoc_sdram_bankmachine6_auto_precharge <= (soc_netsoc_sdram_bankmachine6_row_close == 1'd0);
-		end
-	end
-end
-assign soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_last, soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_first, soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_sink_ready = soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
-assign soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_sink_valid;
-assign soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_first = soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_sink_first;
-assign soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_last = soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_sink_last;
-assign soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
-assign soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
-assign soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_source_valid = soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
-assign soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_source_first = soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
-assign soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_source_last = soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
-assign soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_we = soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
-assign soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr = soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_source_ready;
-always @(*) begin
-	soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 3'd0;
-	if (soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_replace) begin
-		soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_produce - 1'd1);
-	end else begin
-		soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr <= soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_produce;
-	end
-end
-assign soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
-assign soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_we = (soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_replace));
-assign soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_do_read = (soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_re);
-assign soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_adr = soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_consume;
-assign soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
-assign soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_level != 4'd8);
-assign soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_level != 1'd0);
-assign soc_netsoc_sdram_bankmachine6_cmd_buffer_pipe_ce = (soc_netsoc_sdram_bankmachine6_cmd_buffer_source_ready | (~soc_netsoc_sdram_bankmachine6_cmd_buffer_valid_n));
-assign soc_netsoc_sdram_bankmachine6_cmd_buffer_sink_ready = soc_netsoc_sdram_bankmachine6_cmd_buffer_pipe_ce;
-assign soc_netsoc_sdram_bankmachine6_cmd_buffer_source_valid = soc_netsoc_sdram_bankmachine6_cmd_buffer_valid_n;
-assign soc_netsoc_sdram_bankmachine6_cmd_buffer_busy = (1'd0 | soc_netsoc_sdram_bankmachine6_cmd_buffer_valid_n);
-assign soc_netsoc_sdram_bankmachine6_cmd_buffer_source_first = soc_netsoc_sdram_bankmachine6_cmd_buffer_first_n;
-assign soc_netsoc_sdram_bankmachine6_cmd_buffer_source_last = soc_netsoc_sdram_bankmachine6_cmd_buffer_last_n;
-always @(*) begin
-	soc_netsoc_sdram_bankmachine6_cmd_payload_we <= 1'd0;
-	soc_netsoc_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd0;
-	vns_bankmachine6_next_state <= 3'd0;
-	soc_netsoc_sdram_bankmachine6_cmd_payload_is_read <= 1'd0;
-	soc_netsoc_sdram_bankmachine6_row_close <= 1'd0;
-	soc_netsoc_sdram_bankmachine6_cmd_payload_is_write <= 1'd0;
-	soc_netsoc_sdram_bankmachine6_row_open <= 1'd0;
-	soc_netsoc_sdram_bankmachine6_req_wdata_ready <= 1'd0;
-	soc_netsoc_sdram_bankmachine6_req_rdata_valid <= 1'd0;
-	soc_netsoc_sdram_bankmachine6_row_col_n_addr_sel <= 1'd0;
-	soc_netsoc_sdram_bankmachine6_refresh_gnt <= 1'd0;
-	soc_netsoc_sdram_bankmachine6_cmd_valid <= 1'd0;
-	soc_netsoc_sdram_bankmachine6_cmd_payload_cas <= 1'd0;
-	soc_netsoc_sdram_bankmachine6_cmd_payload_ras <= 1'd0;
-	vns_bankmachine6_next_state <= vns_bankmachine6_state;
-	case (vns_bankmachine6_state)
-		1'd1: begin
-			if ((soc_netsoc_sdram_bankmachine6_twtpcon_ready & soc_netsoc_sdram_bankmachine6_trascon_ready)) begin
-				soc_netsoc_sdram_bankmachine6_cmd_valid <= 1'd1;
-				if (soc_netsoc_sdram_bankmachine6_cmd_ready) begin
-					vns_bankmachine6_next_state <= 3'd5;
-				end
-				soc_netsoc_sdram_bankmachine6_cmd_payload_ras <= 1'd1;
-				soc_netsoc_sdram_bankmachine6_cmd_payload_we <= 1'd1;
-				soc_netsoc_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd1;
-			end
-			soc_netsoc_sdram_bankmachine6_row_close <= 1'd1;
-		end
-		2'd2: begin
-			if ((soc_netsoc_sdram_bankmachine6_twtpcon_ready & soc_netsoc_sdram_bankmachine6_trascon_ready)) begin
-				vns_bankmachine6_next_state <= 3'd5;
-			end
-			soc_netsoc_sdram_bankmachine6_row_close <= 1'd1;
-		end
-		2'd3: begin
-			if (soc_netsoc_sdram_bankmachine6_trccon_ready) begin
-				soc_netsoc_sdram_bankmachine6_row_col_n_addr_sel <= 1'd1;
-				soc_netsoc_sdram_bankmachine6_row_open <= 1'd1;
-				soc_netsoc_sdram_bankmachine6_cmd_valid <= 1'd1;
-				soc_netsoc_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd1;
-				if (soc_netsoc_sdram_bankmachine6_cmd_ready) begin
-					vns_bankmachine6_next_state <= 3'd6;
-				end
-				soc_netsoc_sdram_bankmachine6_cmd_payload_ras <= 1'd1;
-			end
-		end
-		3'd4: begin
-			if (soc_netsoc_sdram_bankmachine6_twtpcon_ready) begin
-				soc_netsoc_sdram_bankmachine6_refresh_gnt <= 1'd1;
-			end
-			soc_netsoc_sdram_bankmachine6_row_close <= 1'd1;
-			soc_netsoc_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd1;
-			if ((~soc_netsoc_sdram_bankmachine6_refresh_req)) begin
-				vns_bankmachine6_next_state <= 1'd0;
-			end
-		end
-		3'd5: begin
-			vns_bankmachine6_next_state <= 2'd3;
-		end
-		3'd6: begin
-			vns_bankmachine6_next_state <= 1'd0;
-		end
-		default: begin
-			if (soc_netsoc_sdram_bankmachine6_refresh_req) begin
-				vns_bankmachine6_next_state <= 3'd4;
-			end else begin
-				if (soc_netsoc_sdram_bankmachine6_cmd_buffer_source_valid) begin
-					if (soc_netsoc_sdram_bankmachine6_row_opened) begin
-						if (soc_netsoc_sdram_bankmachine6_row_hit) begin
-							soc_netsoc_sdram_bankmachine6_cmd_valid <= 1'd1;
-							if (soc_netsoc_sdram_bankmachine6_cmd_buffer_source_payload_we) begin
-								soc_netsoc_sdram_bankmachine6_req_wdata_ready <= soc_netsoc_sdram_bankmachine6_cmd_ready;
-								soc_netsoc_sdram_bankmachine6_cmd_payload_is_write <= 1'd1;
-								soc_netsoc_sdram_bankmachine6_cmd_payload_we <= 1'd1;
-							end else begin
-								soc_netsoc_sdram_bankmachine6_req_rdata_valid <= soc_netsoc_sdram_bankmachine6_cmd_ready;
-								soc_netsoc_sdram_bankmachine6_cmd_payload_is_read <= 1'd1;
-							end
-							soc_netsoc_sdram_bankmachine6_cmd_payload_cas <= 1'd1;
-							if ((soc_netsoc_sdram_bankmachine6_cmd_ready & soc_netsoc_sdram_bankmachine6_auto_precharge)) begin
-								vns_bankmachine6_next_state <= 2'd2;
-							end
-						end else begin
-							vns_bankmachine6_next_state <= 1'd1;
-						end
-					end else begin
-						vns_bankmachine6_next_state <= 2'd3;
-					end
-				end
-			end
-		end
-	endcase
-end
-assign soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_sink_valid = soc_netsoc_sdram_bankmachine7_req_valid;
-assign soc_netsoc_sdram_bankmachine7_req_ready = soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_sink_ready;
-assign soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_we = soc_netsoc_sdram_bankmachine7_req_we;
-assign soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = soc_netsoc_sdram_bankmachine7_req_addr;
-assign soc_netsoc_sdram_bankmachine7_cmd_buffer_sink_valid = soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_source_valid;
-assign soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_source_ready = soc_netsoc_sdram_bankmachine7_cmd_buffer_sink_ready;
-assign soc_netsoc_sdram_bankmachine7_cmd_buffer_sink_first = soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_source_first;
-assign soc_netsoc_sdram_bankmachine7_cmd_buffer_sink_last = soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_source_last;
-assign soc_netsoc_sdram_bankmachine7_cmd_buffer_sink_payload_we = soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_we;
-assign soc_netsoc_sdram_bankmachine7_cmd_buffer_sink_payload_addr = soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
-assign soc_netsoc_sdram_bankmachine7_cmd_buffer_source_ready = (soc_netsoc_sdram_bankmachine7_req_wdata_ready | soc_netsoc_sdram_bankmachine7_req_rdata_valid);
-assign soc_netsoc_sdram_bankmachine7_req_lock = (soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_source_valid | soc_netsoc_sdram_bankmachine7_cmd_buffer_source_valid);
-assign soc_netsoc_sdram_bankmachine7_row_hit = (soc_netsoc_sdram_bankmachine7_row == soc_netsoc_sdram_bankmachine7_cmd_buffer_source_payload_addr[20:7]);
-assign soc_netsoc_sdram_bankmachine7_cmd_payload_ba = 3'd7;
-always @(*) begin
-	soc_netsoc_sdram_bankmachine7_cmd_payload_a <= 14'd0;
-	if (soc_netsoc_sdram_bankmachine7_row_col_n_addr_sel) begin
-		soc_netsoc_sdram_bankmachine7_cmd_payload_a <= soc_netsoc_sdram_bankmachine7_cmd_buffer_source_payload_addr[20:7];
-	end else begin
-		soc_netsoc_sdram_bankmachine7_cmd_payload_a <= ((soc_netsoc_sdram_bankmachine7_auto_precharge <<< 4'd10) | {soc_netsoc_sdram_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
-	end
-end
-assign soc_netsoc_sdram_bankmachine7_twtpcon_valid = ((soc_netsoc_sdram_bankmachine7_cmd_valid & soc_netsoc_sdram_bankmachine7_cmd_ready) & soc_netsoc_sdram_bankmachine7_cmd_payload_is_write);
-assign soc_netsoc_sdram_bankmachine7_trccon_valid = ((soc_netsoc_sdram_bankmachine7_cmd_valid & soc_netsoc_sdram_bankmachine7_cmd_ready) & soc_netsoc_sdram_bankmachine7_row_open);
-assign soc_netsoc_sdram_bankmachine7_trascon_valid = ((soc_netsoc_sdram_bankmachine7_cmd_valid & soc_netsoc_sdram_bankmachine7_cmd_ready) & soc_netsoc_sdram_bankmachine7_row_open);
-always @(*) begin
-	soc_netsoc_sdram_bankmachine7_auto_precharge <= 1'd0;
-	if ((soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_source_valid & soc_netsoc_sdram_bankmachine7_cmd_buffer_source_valid)) begin
-		if ((soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_netsoc_sdram_bankmachine7_cmd_buffer_source_payload_addr[20:7])) begin
-			soc_netsoc_sdram_bankmachine7_auto_precharge <= (soc_netsoc_sdram_bankmachine7_row_close == 1'd0);
-		end
-	end
-end
-assign soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_last, soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_first, soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_sink_ready = soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
-assign soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_sink_valid;
-assign soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_first = soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_sink_first;
-assign soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_last = soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_sink_last;
-assign soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
-assign soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
-assign soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_source_valid = soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
-assign soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_source_first = soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
-assign soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_source_last = soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
-assign soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_we = soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
-assign soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr = soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_source_ready;
-always @(*) begin
-	soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 3'd0;
-	if (soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_replace) begin
-		soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_produce - 1'd1);
-	end else begin
-		soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr <= soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_produce;
-	end
-end
-assign soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
-assign soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_we = (soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_replace));
-assign soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_do_read = (soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_re);
-assign soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_adr = soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_consume;
-assign soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
-assign soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_level != 4'd8);
-assign soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_level != 1'd0);
-assign soc_netsoc_sdram_bankmachine7_cmd_buffer_pipe_ce = (soc_netsoc_sdram_bankmachine7_cmd_buffer_source_ready | (~soc_netsoc_sdram_bankmachine7_cmd_buffer_valid_n));
-assign soc_netsoc_sdram_bankmachine7_cmd_buffer_sink_ready = soc_netsoc_sdram_bankmachine7_cmd_buffer_pipe_ce;
-assign soc_netsoc_sdram_bankmachine7_cmd_buffer_source_valid = soc_netsoc_sdram_bankmachine7_cmd_buffer_valid_n;
-assign soc_netsoc_sdram_bankmachine7_cmd_buffer_busy = (1'd0 | soc_netsoc_sdram_bankmachine7_cmd_buffer_valid_n);
-assign soc_netsoc_sdram_bankmachine7_cmd_buffer_source_first = soc_netsoc_sdram_bankmachine7_cmd_buffer_first_n;
-assign soc_netsoc_sdram_bankmachine7_cmd_buffer_source_last = soc_netsoc_sdram_bankmachine7_cmd_buffer_last_n;
-always @(*) begin
-	vns_bankmachine7_next_state <= 3'd0;
-	soc_netsoc_sdram_bankmachine7_cmd_payload_cas <= 1'd0;
-	soc_netsoc_sdram_bankmachine7_cmd_payload_ras <= 1'd0;
-	soc_netsoc_sdram_bankmachine7_cmd_payload_we <= 1'd0;
-	soc_netsoc_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd0;
-	soc_netsoc_sdram_bankmachine7_row_open <= 1'd0;
-	soc_netsoc_sdram_bankmachine7_cmd_payload_is_read <= 1'd0;
-	soc_netsoc_sdram_bankmachine7_row_close <= 1'd0;
-	soc_netsoc_sdram_bankmachine7_cmd_payload_is_write <= 1'd0;
-	soc_netsoc_sdram_bankmachine7_req_wdata_ready <= 1'd0;
-	soc_netsoc_sdram_bankmachine7_req_rdata_valid <= 1'd0;
-	soc_netsoc_sdram_bankmachine7_row_col_n_addr_sel <= 1'd0;
-	soc_netsoc_sdram_bankmachine7_refresh_gnt <= 1'd0;
-	soc_netsoc_sdram_bankmachine7_cmd_valid <= 1'd0;
-	vns_bankmachine7_next_state <= vns_bankmachine7_state;
-	case (vns_bankmachine7_state)
-		1'd1: begin
-			if ((soc_netsoc_sdram_bankmachine7_twtpcon_ready & soc_netsoc_sdram_bankmachine7_trascon_ready)) begin
-				soc_netsoc_sdram_bankmachine7_cmd_valid <= 1'd1;
-				if (soc_netsoc_sdram_bankmachine7_cmd_ready) begin
-					vns_bankmachine7_next_state <= 3'd5;
-				end
-				soc_netsoc_sdram_bankmachine7_cmd_payload_ras <= 1'd1;
-				soc_netsoc_sdram_bankmachine7_cmd_payload_we <= 1'd1;
-				soc_netsoc_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd1;
-			end
-			soc_netsoc_sdram_bankmachine7_row_close <= 1'd1;
-		end
-		2'd2: begin
-			if ((soc_netsoc_sdram_bankmachine7_twtpcon_ready & soc_netsoc_sdram_bankmachine7_trascon_ready)) begin
-				vns_bankmachine7_next_state <= 3'd5;
-			end
-			soc_netsoc_sdram_bankmachine7_row_close <= 1'd1;
-		end
-		2'd3: begin
-			if (soc_netsoc_sdram_bankmachine7_trccon_ready) begin
-				soc_netsoc_sdram_bankmachine7_row_col_n_addr_sel <= 1'd1;
-				soc_netsoc_sdram_bankmachine7_row_open <= 1'd1;
-				soc_netsoc_sdram_bankmachine7_cmd_valid <= 1'd1;
-				soc_netsoc_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd1;
-				if (soc_netsoc_sdram_bankmachine7_cmd_ready) begin
-					vns_bankmachine7_next_state <= 3'd6;
-				end
-				soc_netsoc_sdram_bankmachine7_cmd_payload_ras <= 1'd1;
-			end
-		end
-		3'd4: begin
-			if (soc_netsoc_sdram_bankmachine7_twtpcon_ready) begin
-				soc_netsoc_sdram_bankmachine7_refresh_gnt <= 1'd1;
-			end
-			soc_netsoc_sdram_bankmachine7_row_close <= 1'd1;
-			soc_netsoc_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd1;
-			if ((~soc_netsoc_sdram_bankmachine7_refresh_req)) begin
-				vns_bankmachine7_next_state <= 1'd0;
-			end
-		end
-		3'd5: begin
-			vns_bankmachine7_next_state <= 2'd3;
-		end
-		3'd6: begin
-			vns_bankmachine7_next_state <= 1'd0;
-		end
-		default: begin
-			if (soc_netsoc_sdram_bankmachine7_refresh_req) begin
-				vns_bankmachine7_next_state <= 3'd4;
-			end else begin
-				if (soc_netsoc_sdram_bankmachine7_cmd_buffer_source_valid) begin
-					if (soc_netsoc_sdram_bankmachine7_row_opened) begin
-						if (soc_netsoc_sdram_bankmachine7_row_hit) begin
-							soc_netsoc_sdram_bankmachine7_cmd_valid <= 1'd1;
-							if (soc_netsoc_sdram_bankmachine7_cmd_buffer_source_payload_we) begin
-								soc_netsoc_sdram_bankmachine7_req_wdata_ready <= soc_netsoc_sdram_bankmachine7_cmd_ready;
-								soc_netsoc_sdram_bankmachine7_cmd_payload_is_write <= 1'd1;
-								soc_netsoc_sdram_bankmachine7_cmd_payload_we <= 1'd1;
-							end else begin
-								soc_netsoc_sdram_bankmachine7_req_rdata_valid <= soc_netsoc_sdram_bankmachine7_cmd_ready;
-								soc_netsoc_sdram_bankmachine7_cmd_payload_is_read <= 1'd1;
-							end
-							soc_netsoc_sdram_bankmachine7_cmd_payload_cas <= 1'd1;
-							if ((soc_netsoc_sdram_bankmachine7_cmd_ready & soc_netsoc_sdram_bankmachine7_auto_precharge)) begin
-								vns_bankmachine7_next_state <= 2'd2;
-							end
-						end else begin
-							vns_bankmachine7_next_state <= 1'd1;
-						end
-					end else begin
-						vns_bankmachine7_next_state <= 2'd3;
-					end
-				end
-			end
-		end
-	endcase
-end
-assign soc_netsoc_sdram_trrdcon_valid = ((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & ((soc_netsoc_sdram_choose_cmd_cmd_payload_ras & (~soc_netsoc_sdram_choose_cmd_cmd_payload_cas)) & (~soc_netsoc_sdram_choose_cmd_cmd_payload_we)));
-assign soc_netsoc_sdram_tfawcon_valid = ((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & ((soc_netsoc_sdram_choose_cmd_cmd_payload_ras & (~soc_netsoc_sdram_choose_cmd_cmd_payload_cas)) & (~soc_netsoc_sdram_choose_cmd_cmd_payload_we)));
-assign soc_netsoc_sdram_ras_allowed = (soc_netsoc_sdram_trrdcon_ready & soc_netsoc_sdram_tfawcon_ready);
-assign soc_netsoc_sdram_tccdcon_valid = ((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & (soc_netsoc_sdram_choose_req_cmd_payload_is_write | soc_netsoc_sdram_choose_req_cmd_payload_is_read));
-assign soc_netsoc_sdram_cas_allowed = soc_netsoc_sdram_tccdcon_ready;
-assign soc_netsoc_sdram_twtrcon_valid = ((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & soc_netsoc_sdram_choose_req_cmd_payload_is_write);
-assign soc_netsoc_sdram_read_available = ((((((((soc_netsoc_sdram_bankmachine0_cmd_valid & soc_netsoc_sdram_bankmachine0_cmd_payload_is_read) | (soc_netsoc_sdram_bankmachine1_cmd_valid & soc_netsoc_sdram_bankmachine1_cmd_payload_is_read)) | (soc_netsoc_sdram_bankmachine2_cmd_valid & soc_netsoc_sdram_bankmachine2_cmd_payload_is_read)) | (soc_netsoc_sdram_bankmachine3_cmd_valid & soc_netsoc_sdram_bankmachine3_cmd_payload_is_read)) | (soc_netsoc_sdram_bankmachine4_cmd_valid & soc_netsoc_sdram_bankmachine4_cmd_payload_is_read)) | (soc_netsoc_sdram_bankmachine5_cmd_valid & soc_netsoc_sdram_bankmachine5_cmd_payload_is_read)) | (soc_netsoc_sdram_bankmachine6_cmd_valid & soc_netsoc_sdram_bankmachine6_cmd_payload_is_read)) | (soc_netsoc_sdram_bankmachine7_cmd_valid & soc_netsoc_sdram_bankmachine7_cmd_payload_is_read));
-assign soc_netsoc_sdram_write_available = ((((((((soc_netsoc_sdram_bankmachine0_cmd_valid & soc_netsoc_sdram_bankmachine0_cmd_payload_is_write) | (soc_netsoc_sdram_bankmachine1_cmd_valid & soc_netsoc_sdram_bankmachine1_cmd_payload_is_write)) | (soc_netsoc_sdram_bankmachine2_cmd_valid & soc_netsoc_sdram_bankmachine2_cmd_payload_is_write)) | (soc_netsoc_sdram_bankmachine3_cmd_valid & soc_netsoc_sdram_bankmachine3_cmd_payload_is_write)) | (soc_netsoc_sdram_bankmachine4_cmd_valid & soc_netsoc_sdram_bankmachine4_cmd_payload_is_write)) | (soc_netsoc_sdram_bankmachine5_cmd_valid & soc_netsoc_sdram_bankmachine5_cmd_payload_is_write)) | (soc_netsoc_sdram_bankmachine6_cmd_valid & soc_netsoc_sdram_bankmachine6_cmd_payload_is_write)) | (soc_netsoc_sdram_bankmachine7_cmd_valid & soc_netsoc_sdram_bankmachine7_cmd_payload_is_write));
-assign soc_netsoc_sdram_max_time0 = (soc_netsoc_sdram_time0 == 1'd0);
-assign soc_netsoc_sdram_max_time1 = (soc_netsoc_sdram_time1 == 1'd0);
-assign soc_netsoc_sdram_bankmachine0_refresh_req = soc_netsoc_sdram_cmd_valid;
-assign soc_netsoc_sdram_bankmachine1_refresh_req = soc_netsoc_sdram_cmd_valid;
-assign soc_netsoc_sdram_bankmachine2_refresh_req = soc_netsoc_sdram_cmd_valid;
-assign soc_netsoc_sdram_bankmachine3_refresh_req = soc_netsoc_sdram_cmd_valid;
-assign soc_netsoc_sdram_bankmachine4_refresh_req = soc_netsoc_sdram_cmd_valid;
-assign soc_netsoc_sdram_bankmachine5_refresh_req = soc_netsoc_sdram_cmd_valid;
-assign soc_netsoc_sdram_bankmachine6_refresh_req = soc_netsoc_sdram_cmd_valid;
-assign soc_netsoc_sdram_bankmachine7_refresh_req = soc_netsoc_sdram_cmd_valid;
-assign soc_netsoc_sdram_go_to_refresh = (((((((soc_netsoc_sdram_bankmachine0_refresh_gnt & soc_netsoc_sdram_bankmachine1_refresh_gnt) & soc_netsoc_sdram_bankmachine2_refresh_gnt) & soc_netsoc_sdram_bankmachine3_refresh_gnt) & soc_netsoc_sdram_bankmachine4_refresh_gnt) & soc_netsoc_sdram_bankmachine5_refresh_gnt) & soc_netsoc_sdram_bankmachine6_refresh_gnt) & soc_netsoc_sdram_bankmachine7_refresh_gnt);
-assign soc_netsoc_sdram_interface_rdata = {soc_netsoc_sdram_dfi_p3_rddata, soc_netsoc_sdram_dfi_p2_rddata, soc_netsoc_sdram_dfi_p1_rddata, soc_netsoc_sdram_dfi_p0_rddata};
-assign {soc_netsoc_sdram_dfi_p3_wrdata, soc_netsoc_sdram_dfi_p2_wrdata, soc_netsoc_sdram_dfi_p1_wrdata, soc_netsoc_sdram_dfi_p0_wrdata} = soc_netsoc_sdram_interface_wdata;
-assign {soc_netsoc_sdram_dfi_p3_wrdata_mask, soc_netsoc_sdram_dfi_p2_wrdata_mask, soc_netsoc_sdram_dfi_p1_wrdata_mask, soc_netsoc_sdram_dfi_p0_wrdata_mask} = (~soc_netsoc_sdram_interface_wdata_we);
-always @(*) begin
-	soc_netsoc_sdram_choose_cmd_valids <= 8'd0;
-	soc_netsoc_sdram_choose_cmd_valids[0] <= (soc_netsoc_sdram_bankmachine0_cmd_valid & (((soc_netsoc_sdram_bankmachine0_cmd_payload_is_cmd & soc_netsoc_sdram_choose_cmd_want_cmds) & ((~((soc_netsoc_sdram_bankmachine0_cmd_payload_ras & (~soc_netsoc_sdram_bankmachine0_cmd_payload_cas)) & (~soc_netsoc_sdram_bankmachine0_cmd_payload_we))) | soc_netsoc_sdram_choose_cmd_want_activates)) | ((soc_netsoc_sdram_bankmachine0_cmd_payload_is_read == soc_netsoc_sdram_choose_cmd_want_reads) & (soc_netsoc_sdram_bankmachine0_cmd_payload_is_write == soc_netsoc_sdram_choose_cmd_want_writes))));
-	soc_netsoc_sdram_choose_cmd_valids[1] <= (soc_netsoc_sdram_bankmachine1_cmd_valid & (((soc_netsoc_sdram_bankmachine1_cmd_payload_is_cmd & soc_netsoc_sdram_choose_cmd_want_cmds) & ((~((soc_netsoc_sdram_bankmachine1_cmd_payload_ras & (~soc_netsoc_sdram_bankmachine1_cmd_payload_cas)) & (~soc_netsoc_sdram_bankmachine1_cmd_payload_we))) | soc_netsoc_sdram_choose_cmd_want_activates)) | ((soc_netsoc_sdram_bankmachine1_cmd_payload_is_read == soc_netsoc_sdram_choose_cmd_want_reads) & (soc_netsoc_sdram_bankmachine1_cmd_payload_is_write == soc_netsoc_sdram_choose_cmd_want_writes))));
-	soc_netsoc_sdram_choose_cmd_valids[2] <= (soc_netsoc_sdram_bankmachine2_cmd_valid & (((soc_netsoc_sdram_bankmachine2_cmd_payload_is_cmd & soc_netsoc_sdram_choose_cmd_want_cmds) & ((~((soc_netsoc_sdram_bankmachine2_cmd_payload_ras & (~soc_netsoc_sdram_bankmachine2_cmd_payload_cas)) & (~soc_netsoc_sdram_bankmachine2_cmd_payload_we))) | soc_netsoc_sdram_choose_cmd_want_activates)) | ((soc_netsoc_sdram_bankmachine2_cmd_payload_is_read == soc_netsoc_sdram_choose_cmd_want_reads) & (soc_netsoc_sdram_bankmachine2_cmd_payload_is_write == soc_netsoc_sdram_choose_cmd_want_writes))));
-	soc_netsoc_sdram_choose_cmd_valids[3] <= (soc_netsoc_sdram_bankmachine3_cmd_valid & (((soc_netsoc_sdram_bankmachine3_cmd_payload_is_cmd & soc_netsoc_sdram_choose_cmd_want_cmds) & ((~((soc_netsoc_sdram_bankmachine3_cmd_payload_ras & (~soc_netsoc_sdram_bankmachine3_cmd_payload_cas)) & (~soc_netsoc_sdram_bankmachine3_cmd_payload_we))) | soc_netsoc_sdram_choose_cmd_want_activates)) | ((soc_netsoc_sdram_bankmachine3_cmd_payload_is_read == soc_netsoc_sdram_choose_cmd_want_reads) & (soc_netsoc_sdram_bankmachine3_cmd_payload_is_write == soc_netsoc_sdram_choose_cmd_want_writes))));
-	soc_netsoc_sdram_choose_cmd_valids[4] <= (soc_netsoc_sdram_bankmachine4_cmd_valid & (((soc_netsoc_sdram_bankmachine4_cmd_payload_is_cmd & soc_netsoc_sdram_choose_cmd_want_cmds) & ((~((soc_netsoc_sdram_bankmachine4_cmd_payload_ras & (~soc_netsoc_sdram_bankmachine4_cmd_payload_cas)) & (~soc_netsoc_sdram_bankmachine4_cmd_payload_we))) | soc_netsoc_sdram_choose_cmd_want_activates)) | ((soc_netsoc_sdram_bankmachine4_cmd_payload_is_read == soc_netsoc_sdram_choose_cmd_want_reads) & (soc_netsoc_sdram_bankmachine4_cmd_payload_is_write == soc_netsoc_sdram_choose_cmd_want_writes))));
-	soc_netsoc_sdram_choose_cmd_valids[5] <= (soc_netsoc_sdram_bankmachine5_cmd_valid & (((soc_netsoc_sdram_bankmachine5_cmd_payload_is_cmd & soc_netsoc_sdram_choose_cmd_want_cmds) & ((~((soc_netsoc_sdram_bankmachine5_cmd_payload_ras & (~soc_netsoc_sdram_bankmachine5_cmd_payload_cas)) & (~soc_netsoc_sdram_bankmachine5_cmd_payload_we))) | soc_netsoc_sdram_choose_cmd_want_activates)) | ((soc_netsoc_sdram_bankmachine5_cmd_payload_is_read == soc_netsoc_sdram_choose_cmd_want_reads) & (soc_netsoc_sdram_bankmachine5_cmd_payload_is_write == soc_netsoc_sdram_choose_cmd_want_writes))));
-	soc_netsoc_sdram_choose_cmd_valids[6] <= (soc_netsoc_sdram_bankmachine6_cmd_valid & (((soc_netsoc_sdram_bankmachine6_cmd_payload_is_cmd & soc_netsoc_sdram_choose_cmd_want_cmds) & ((~((soc_netsoc_sdram_bankmachine6_cmd_payload_ras & (~soc_netsoc_sdram_bankmachine6_cmd_payload_cas)) & (~soc_netsoc_sdram_bankmachine6_cmd_payload_we))) | soc_netsoc_sdram_choose_cmd_want_activates)) | ((soc_netsoc_sdram_bankmachine6_cmd_payload_is_read == soc_netsoc_sdram_choose_cmd_want_reads) & (soc_netsoc_sdram_bankmachine6_cmd_payload_is_write == soc_netsoc_sdram_choose_cmd_want_writes))));
-	soc_netsoc_sdram_choose_cmd_valids[7] <= (soc_netsoc_sdram_bankmachine7_cmd_valid & (((soc_netsoc_sdram_bankmachine7_cmd_payload_is_cmd & soc_netsoc_sdram_choose_cmd_want_cmds) & ((~((soc_netsoc_sdram_bankmachine7_cmd_payload_ras & (~soc_netsoc_sdram_bankmachine7_cmd_payload_cas)) & (~soc_netsoc_sdram_bankmachine7_cmd_payload_we))) | soc_netsoc_sdram_choose_cmd_want_activates)) | ((soc_netsoc_sdram_bankmachine7_cmd_payload_is_read == soc_netsoc_sdram_choose_cmd_want_reads) & (soc_netsoc_sdram_bankmachine7_cmd_payload_is_write == soc_netsoc_sdram_choose_cmd_want_writes))));
-end
-assign soc_netsoc_sdram_choose_cmd_request = soc_netsoc_sdram_choose_cmd_valids;
-assign soc_netsoc_sdram_choose_cmd_cmd_valid = vns_rhs_array_muxed0;
-assign soc_netsoc_sdram_choose_cmd_cmd_payload_a = vns_rhs_array_muxed1;
-assign soc_netsoc_sdram_choose_cmd_cmd_payload_ba = vns_rhs_array_muxed2;
-assign soc_netsoc_sdram_choose_cmd_cmd_payload_is_read = vns_rhs_array_muxed3;
-assign soc_netsoc_sdram_choose_cmd_cmd_payload_is_write = vns_rhs_array_muxed4;
-assign soc_netsoc_sdram_choose_cmd_cmd_payload_is_cmd = vns_rhs_array_muxed5;
-always @(*) begin
-	soc_netsoc_sdram_choose_cmd_cmd_payload_cas <= 1'd0;
-	if (soc_netsoc_sdram_choose_cmd_cmd_valid) begin
-		soc_netsoc_sdram_choose_cmd_cmd_payload_cas <= vns_t_array_muxed0;
-	end
-end
-always @(*) begin
-	soc_netsoc_sdram_choose_cmd_cmd_payload_ras <= 1'd0;
-	if (soc_netsoc_sdram_choose_cmd_cmd_valid) begin
-		soc_netsoc_sdram_choose_cmd_cmd_payload_ras <= vns_t_array_muxed1;
-	end
-end
-always @(*) begin
-	soc_netsoc_sdram_choose_cmd_cmd_payload_we <= 1'd0;
-	if (soc_netsoc_sdram_choose_cmd_cmd_valid) begin
-		soc_netsoc_sdram_choose_cmd_cmd_payload_we <= vns_t_array_muxed2;
-	end
-end
-assign soc_netsoc_sdram_choose_cmd_ce = (soc_netsoc_sdram_choose_cmd_cmd_ready | (~soc_netsoc_sdram_choose_cmd_cmd_valid));
-always @(*) begin
-	soc_netsoc_sdram_choose_req_valids <= 8'd0;
-	soc_netsoc_sdram_choose_req_valids[0] <= (soc_netsoc_sdram_bankmachine0_cmd_valid & (((soc_netsoc_sdram_bankmachine0_cmd_payload_is_cmd & soc_netsoc_sdram_choose_req_want_cmds) & ((~((soc_netsoc_sdram_bankmachine0_cmd_payload_ras & (~soc_netsoc_sdram_bankmachine0_cmd_payload_cas)) & (~soc_netsoc_sdram_bankmachine0_cmd_payload_we))) | soc_netsoc_sdram_choose_req_want_activates)) | ((soc_netsoc_sdram_bankmachine0_cmd_payload_is_read == soc_netsoc_sdram_choose_req_want_reads) & (soc_netsoc_sdram_bankmachine0_cmd_payload_is_write == soc_netsoc_sdram_choose_req_want_writes))));
-	soc_netsoc_sdram_choose_req_valids[1] <= (soc_netsoc_sdram_bankmachine1_cmd_valid & (((soc_netsoc_sdram_bankmachine1_cmd_payload_is_cmd & soc_netsoc_sdram_choose_req_want_cmds) & ((~((soc_netsoc_sdram_bankmachine1_cmd_payload_ras & (~soc_netsoc_sdram_bankmachine1_cmd_payload_cas)) & (~soc_netsoc_sdram_bankmachine1_cmd_payload_we))) | soc_netsoc_sdram_choose_req_want_activates)) | ((soc_netsoc_sdram_bankmachine1_cmd_payload_is_read == soc_netsoc_sdram_choose_req_want_reads) & (soc_netsoc_sdram_bankmachine1_cmd_payload_is_write == soc_netsoc_sdram_choose_req_want_writes))));
-	soc_netsoc_sdram_choose_req_valids[2] <= (soc_netsoc_sdram_bankmachine2_cmd_valid & (((soc_netsoc_sdram_bankmachine2_cmd_payload_is_cmd & soc_netsoc_sdram_choose_req_want_cmds) & ((~((soc_netsoc_sdram_bankmachine2_cmd_payload_ras & (~soc_netsoc_sdram_bankmachine2_cmd_payload_cas)) & (~soc_netsoc_sdram_bankmachine2_cmd_payload_we))) | soc_netsoc_sdram_choose_req_want_activates)) | ((soc_netsoc_sdram_bankmachine2_cmd_payload_is_read == soc_netsoc_sdram_choose_req_want_reads) & (soc_netsoc_sdram_bankmachine2_cmd_payload_is_write == soc_netsoc_sdram_choose_req_want_writes))));
-	soc_netsoc_sdram_choose_req_valids[3] <= (soc_netsoc_sdram_bankmachine3_cmd_valid & (((soc_netsoc_sdram_bankmachine3_cmd_payload_is_cmd & soc_netsoc_sdram_choose_req_want_cmds) & ((~((soc_netsoc_sdram_bankmachine3_cmd_payload_ras & (~soc_netsoc_sdram_bankmachine3_cmd_payload_cas)) & (~soc_netsoc_sdram_bankmachine3_cmd_payload_we))) | soc_netsoc_sdram_choose_req_want_activates)) | ((soc_netsoc_sdram_bankmachine3_cmd_payload_is_read == soc_netsoc_sdram_choose_req_want_reads) & (soc_netsoc_sdram_bankmachine3_cmd_payload_is_write == soc_netsoc_sdram_choose_req_want_writes))));
-	soc_netsoc_sdram_choose_req_valids[4] <= (soc_netsoc_sdram_bankmachine4_cmd_valid & (((soc_netsoc_sdram_bankmachine4_cmd_payload_is_cmd & soc_netsoc_sdram_choose_req_want_cmds) & ((~((soc_netsoc_sdram_bankmachine4_cmd_payload_ras & (~soc_netsoc_sdram_bankmachine4_cmd_payload_cas)) & (~soc_netsoc_sdram_bankmachine4_cmd_payload_we))) | soc_netsoc_sdram_choose_req_want_activates)) | ((soc_netsoc_sdram_bankmachine4_cmd_payload_is_read == soc_netsoc_sdram_choose_req_want_reads) & (soc_netsoc_sdram_bankmachine4_cmd_payload_is_write == soc_netsoc_sdram_choose_req_want_writes))));
-	soc_netsoc_sdram_choose_req_valids[5] <= (soc_netsoc_sdram_bankmachine5_cmd_valid & (((soc_netsoc_sdram_bankmachine5_cmd_payload_is_cmd & soc_netsoc_sdram_choose_req_want_cmds) & ((~((soc_netsoc_sdram_bankmachine5_cmd_payload_ras & (~soc_netsoc_sdram_bankmachine5_cmd_payload_cas)) & (~soc_netsoc_sdram_bankmachine5_cmd_payload_we))) | soc_netsoc_sdram_choose_req_want_activates)) | ((soc_netsoc_sdram_bankmachine5_cmd_payload_is_read == soc_netsoc_sdram_choose_req_want_reads) & (soc_netsoc_sdram_bankmachine5_cmd_payload_is_write == soc_netsoc_sdram_choose_req_want_writes))));
-	soc_netsoc_sdram_choose_req_valids[6] <= (soc_netsoc_sdram_bankmachine6_cmd_valid & (((soc_netsoc_sdram_bankmachine6_cmd_payload_is_cmd & soc_netsoc_sdram_choose_req_want_cmds) & ((~((soc_netsoc_sdram_bankmachine6_cmd_payload_ras & (~soc_netsoc_sdram_bankmachine6_cmd_payload_cas)) & (~soc_netsoc_sdram_bankmachine6_cmd_payload_we))) | soc_netsoc_sdram_choose_req_want_activates)) | ((soc_netsoc_sdram_bankmachine6_cmd_payload_is_read == soc_netsoc_sdram_choose_req_want_reads) & (soc_netsoc_sdram_bankmachine6_cmd_payload_is_write == soc_netsoc_sdram_choose_req_want_writes))));
-	soc_netsoc_sdram_choose_req_valids[7] <= (soc_netsoc_sdram_bankmachine7_cmd_valid & (((soc_netsoc_sdram_bankmachine7_cmd_payload_is_cmd & soc_netsoc_sdram_choose_req_want_cmds) & ((~((soc_netsoc_sdram_bankmachine7_cmd_payload_ras & (~soc_netsoc_sdram_bankmachine7_cmd_payload_cas)) & (~soc_netsoc_sdram_bankmachine7_cmd_payload_we))) | soc_netsoc_sdram_choose_req_want_activates)) | ((soc_netsoc_sdram_bankmachine7_cmd_payload_is_read == soc_netsoc_sdram_choose_req_want_reads) & (soc_netsoc_sdram_bankmachine7_cmd_payload_is_write == soc_netsoc_sdram_choose_req_want_writes))));
-end
-assign soc_netsoc_sdram_choose_req_request = soc_netsoc_sdram_choose_req_valids;
-assign soc_netsoc_sdram_choose_req_cmd_valid = vns_rhs_array_muxed6;
-assign soc_netsoc_sdram_choose_req_cmd_payload_a = vns_rhs_array_muxed7;
-assign soc_netsoc_sdram_choose_req_cmd_payload_ba = vns_rhs_array_muxed8;
-assign soc_netsoc_sdram_choose_req_cmd_payload_is_read = vns_rhs_array_muxed9;
-assign soc_netsoc_sdram_choose_req_cmd_payload_is_write = vns_rhs_array_muxed10;
-assign soc_netsoc_sdram_choose_req_cmd_payload_is_cmd = vns_rhs_array_muxed11;
-always @(*) begin
-	soc_netsoc_sdram_choose_req_cmd_payload_cas <= 1'd0;
-	if (soc_netsoc_sdram_choose_req_cmd_valid) begin
-		soc_netsoc_sdram_choose_req_cmd_payload_cas <= vns_t_array_muxed3;
-	end
-end
-always @(*) begin
-	soc_netsoc_sdram_choose_req_cmd_payload_ras <= 1'd0;
-	if (soc_netsoc_sdram_choose_req_cmd_valid) begin
-		soc_netsoc_sdram_choose_req_cmd_payload_ras <= vns_t_array_muxed4;
-	end
-end
-always @(*) begin
-	soc_netsoc_sdram_choose_req_cmd_payload_we <= 1'd0;
-	if (soc_netsoc_sdram_choose_req_cmd_valid) begin
-		soc_netsoc_sdram_choose_req_cmd_payload_we <= vns_t_array_muxed5;
-	end
-end
-always @(*) begin
-	soc_netsoc_sdram_bankmachine0_cmd_ready <= 1'd0;
-	if (((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & (soc_netsoc_sdram_choose_cmd_grant == 1'd0))) begin
-		soc_netsoc_sdram_bankmachine0_cmd_ready <= 1'd1;
-	end
-	if (((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & (soc_netsoc_sdram_choose_req_grant == 1'd0))) begin
-		soc_netsoc_sdram_bankmachine0_cmd_ready <= 1'd1;
-	end
-end
-always @(*) begin
-	soc_netsoc_sdram_bankmachine1_cmd_ready <= 1'd0;
-	if (((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & (soc_netsoc_sdram_choose_cmd_grant == 1'd1))) begin
-		soc_netsoc_sdram_bankmachine1_cmd_ready <= 1'd1;
-	end
-	if (((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & (soc_netsoc_sdram_choose_req_grant == 1'd1))) begin
-		soc_netsoc_sdram_bankmachine1_cmd_ready <= 1'd1;
-	end
-end
-always @(*) begin
-	soc_netsoc_sdram_bankmachine2_cmd_ready <= 1'd0;
-	if (((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & (soc_netsoc_sdram_choose_cmd_grant == 2'd2))) begin
-		soc_netsoc_sdram_bankmachine2_cmd_ready <= 1'd1;
-	end
-	if (((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & (soc_netsoc_sdram_choose_req_grant == 2'd2))) begin
-		soc_netsoc_sdram_bankmachine2_cmd_ready <= 1'd1;
-	end
-end
-always @(*) begin
-	soc_netsoc_sdram_bankmachine3_cmd_ready <= 1'd0;
-	if (((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & (soc_netsoc_sdram_choose_cmd_grant == 2'd3))) begin
-		soc_netsoc_sdram_bankmachine3_cmd_ready <= 1'd1;
-	end
-	if (((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & (soc_netsoc_sdram_choose_req_grant == 2'd3))) begin
-		soc_netsoc_sdram_bankmachine3_cmd_ready <= 1'd1;
-	end
-end
-always @(*) begin
-	soc_netsoc_sdram_bankmachine4_cmd_ready <= 1'd0;
-	if (((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & (soc_netsoc_sdram_choose_cmd_grant == 3'd4))) begin
-		soc_netsoc_sdram_bankmachine4_cmd_ready <= 1'd1;
-	end
-	if (((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & (soc_netsoc_sdram_choose_req_grant == 3'd4))) begin
-		soc_netsoc_sdram_bankmachine4_cmd_ready <= 1'd1;
-	end
-end
-always @(*) begin
-	soc_netsoc_sdram_bankmachine5_cmd_ready <= 1'd0;
-	if (((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & (soc_netsoc_sdram_choose_cmd_grant == 3'd5))) begin
-		soc_netsoc_sdram_bankmachine5_cmd_ready <= 1'd1;
-	end
-	if (((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & (soc_netsoc_sdram_choose_req_grant == 3'd5))) begin
-		soc_netsoc_sdram_bankmachine5_cmd_ready <= 1'd1;
-	end
-end
-always @(*) begin
-	soc_netsoc_sdram_bankmachine6_cmd_ready <= 1'd0;
-	if (((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & (soc_netsoc_sdram_choose_cmd_grant == 3'd6))) begin
-		soc_netsoc_sdram_bankmachine6_cmd_ready <= 1'd1;
-	end
-	if (((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & (soc_netsoc_sdram_choose_req_grant == 3'd6))) begin
-		soc_netsoc_sdram_bankmachine6_cmd_ready <= 1'd1;
-	end
-end
-always @(*) begin
-	soc_netsoc_sdram_bankmachine7_cmd_ready <= 1'd0;
-	if (((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & (soc_netsoc_sdram_choose_cmd_grant == 3'd7))) begin
-		soc_netsoc_sdram_bankmachine7_cmd_ready <= 1'd1;
-	end
-	if (((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & (soc_netsoc_sdram_choose_req_grant == 3'd7))) begin
-		soc_netsoc_sdram_bankmachine7_cmd_ready <= 1'd1;
-	end
-end
-assign soc_netsoc_sdram_choose_req_ce = (soc_netsoc_sdram_choose_req_cmd_ready | (~soc_netsoc_sdram_choose_req_cmd_valid));
-assign soc_netsoc_sdram_dfi_p0_reset_n = 1'd1;
-assign soc_netsoc_sdram_dfi_p0_cke = {1{soc_netsoc_sdram_steerer0}};
-assign soc_netsoc_sdram_dfi_p0_odt = {1{soc_netsoc_sdram_steerer1}};
-assign soc_netsoc_sdram_dfi_p1_reset_n = 1'd1;
-assign soc_netsoc_sdram_dfi_p1_cke = {1{soc_netsoc_sdram_steerer2}};
-assign soc_netsoc_sdram_dfi_p1_odt = {1{soc_netsoc_sdram_steerer3}};
-assign soc_netsoc_sdram_dfi_p2_reset_n = 1'd1;
-assign soc_netsoc_sdram_dfi_p2_cke = {1{soc_netsoc_sdram_steerer4}};
-assign soc_netsoc_sdram_dfi_p2_odt = {1{soc_netsoc_sdram_steerer5}};
-assign soc_netsoc_sdram_dfi_p3_reset_n = 1'd1;
-assign soc_netsoc_sdram_dfi_p3_cke = {1{soc_netsoc_sdram_steerer6}};
-assign soc_netsoc_sdram_dfi_p3_odt = {1{soc_netsoc_sdram_steerer7}};
-assign soc_netsoc_sdram_tfawcon_count = (((soc_netsoc_sdram_tfawcon_window[0] + soc_netsoc_sdram_tfawcon_window[1]) + soc_netsoc_sdram_tfawcon_window[2]) + soc_netsoc_sdram_tfawcon_window[3]);
-always @(*) begin
-	soc_netsoc_sdram_en0 <= 1'd0;
-	soc_netsoc_sdram_choose_cmd_want_activates <= 1'd0;
-	soc_netsoc_sdram_steerer_sel3 <= 2'd0;
-	soc_netsoc_sdram_cmd_ready <= 1'd0;
-	soc_netsoc_sdram_choose_cmd_cmd_ready <= 1'd0;
-	soc_netsoc_sdram_choose_req_want_reads <= 1'd0;
-	soc_netsoc_sdram_choose_req_want_writes <= 1'd0;
-	soc_netsoc_sdram_en1 <= 1'd0;
-	soc_netsoc_sdram_choose_req_cmd_ready <= 1'd0;
-	soc_netsoc_sdram_steerer_sel0 <= 2'd0;
-	vns_multiplexer_next_state <= 4'd0;
-	soc_netsoc_sdram_steerer_sel1 <= 2'd0;
-	soc_netsoc_sdram_steerer_sel2 <= 2'd0;
-	vns_multiplexer_next_state <= vns_multiplexer_state;
-	case (vns_multiplexer_state)
-		1'd1: begin
-			soc_netsoc_sdram_en1 <= 1'd1;
-			soc_netsoc_sdram_choose_req_want_writes <= 1'd1;
-			if (1'd0) begin
-				soc_netsoc_sdram_choose_req_cmd_ready <= (soc_netsoc_sdram_cas_allowed & ((~((soc_netsoc_sdram_choose_req_cmd_payload_ras & (~soc_netsoc_sdram_choose_req_cmd_payload_cas)) & (~soc_netsoc_sdram_choose_req_cmd_payload_we))) | soc_netsoc_sdram_ras_allowed));
-			end else begin
-				soc_netsoc_sdram_choose_cmd_want_activates <= soc_netsoc_sdram_ras_allowed;
-				soc_netsoc_sdram_choose_cmd_cmd_ready <= ((~((soc_netsoc_sdram_choose_cmd_cmd_payload_ras & (~soc_netsoc_sdram_choose_cmd_cmd_payload_cas)) & (~soc_netsoc_sdram_choose_cmd_cmd_payload_we))) | soc_netsoc_sdram_ras_allowed);
-				soc_netsoc_sdram_choose_req_cmd_ready <= soc_netsoc_sdram_cas_allowed;
-			end
-			soc_netsoc_sdram_steerer_sel0 <= 1'd0;
-			soc_netsoc_sdram_steerer_sel1 <= 1'd0;
-			soc_netsoc_sdram_steerer_sel2 <= 1'd1;
-			soc_netsoc_sdram_steerer_sel3 <= 2'd2;
-			if (soc_netsoc_sdram_read_available) begin
-				if (((~soc_netsoc_sdram_write_available) | soc_netsoc_sdram_max_time1)) begin
-					vns_multiplexer_next_state <= 2'd3;
-				end
-			end
-			if (soc_netsoc_sdram_go_to_refresh) begin
-				vns_multiplexer_next_state <= 2'd2;
-			end
-		end
-		2'd2: begin
-			soc_netsoc_sdram_steerer_sel0 <= 2'd3;
-			soc_netsoc_sdram_cmd_ready <= 1'd1;
-			if (soc_netsoc_sdram_cmd_last) begin
-				vns_multiplexer_next_state <= 1'd0;
-			end
-		end
-		2'd3: begin
-			if (soc_netsoc_sdram_twtrcon_ready) begin
-				vns_multiplexer_next_state <= 1'd0;
-			end
-		end
-		3'd4: begin
-			vns_multiplexer_next_state <= 3'd5;
-		end
-		3'd5: begin
-			vns_multiplexer_next_state <= 3'd6;
-		end
-		3'd6: begin
-			vns_multiplexer_next_state <= 3'd7;
-		end
-		3'd7: begin
-			vns_multiplexer_next_state <= 4'd8;
-		end
-		4'd8: begin
-			vns_multiplexer_next_state <= 4'd9;
-		end
-		4'd9: begin
-			vns_multiplexer_next_state <= 4'd10;
-		end
-		4'd10: begin
-			vns_multiplexer_next_state <= 4'd11;
-		end
-		4'd11: begin
-			vns_multiplexer_next_state <= 1'd1;
-		end
-		default: begin
-			soc_netsoc_sdram_en0 <= 1'd1;
-			soc_netsoc_sdram_choose_req_want_reads <= 1'd1;
-			if (1'd0) begin
-				soc_netsoc_sdram_choose_req_cmd_ready <= (soc_netsoc_sdram_cas_allowed & ((~((soc_netsoc_sdram_choose_req_cmd_payload_ras & (~soc_netsoc_sdram_choose_req_cmd_payload_cas)) & (~soc_netsoc_sdram_choose_req_cmd_payload_we))) | soc_netsoc_sdram_ras_allowed));
-			end else begin
-				soc_netsoc_sdram_choose_cmd_want_activates <= soc_netsoc_sdram_ras_allowed;
-				soc_netsoc_sdram_choose_cmd_cmd_ready <= ((~((soc_netsoc_sdram_choose_cmd_cmd_payload_ras & (~soc_netsoc_sdram_choose_cmd_cmd_payload_cas)) & (~soc_netsoc_sdram_choose_cmd_cmd_payload_we))) | soc_netsoc_sdram_ras_allowed);
-				soc_netsoc_sdram_choose_req_cmd_ready <= soc_netsoc_sdram_cas_allowed;
-			end
-			soc_netsoc_sdram_steerer_sel0 <= 1'd0;
-			soc_netsoc_sdram_steerer_sel1 <= 1'd1;
-			soc_netsoc_sdram_steerer_sel2 <= 2'd2;
-			soc_netsoc_sdram_steerer_sel3 <= 1'd0;
-			if (soc_netsoc_sdram_write_available) begin
-				if (((~soc_netsoc_sdram_read_available) | soc_netsoc_sdram_max_time0)) begin
-					vns_multiplexer_next_state <= 3'd4;
-				end
-			end
-			if (soc_netsoc_sdram_go_to_refresh) begin
-				vns_multiplexer_next_state <= 2'd2;
-			end
-		end
-	endcase
-end
-assign vns_roundrobin0_request = {(((soc_netsoc_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked0 | (soc_netsoc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_netsoc_port_cmd_valid)};
-assign vns_roundrobin0_ce = ((~soc_netsoc_sdram_interface_bank0_valid) & (~soc_netsoc_sdram_interface_bank0_lock));
-assign soc_netsoc_sdram_interface_bank0_addr = vns_rhs_array_muxed12;
-assign soc_netsoc_sdram_interface_bank0_we = vns_rhs_array_muxed13;
-assign soc_netsoc_sdram_interface_bank0_valid = vns_rhs_array_muxed14;
-assign vns_roundrobin1_request = {(((soc_netsoc_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked1 | (soc_netsoc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_netsoc_port_cmd_valid)};
-assign vns_roundrobin1_ce = ((~soc_netsoc_sdram_interface_bank1_valid) & (~soc_netsoc_sdram_interface_bank1_lock));
-assign soc_netsoc_sdram_interface_bank1_addr = vns_rhs_array_muxed15;
-assign soc_netsoc_sdram_interface_bank1_we = vns_rhs_array_muxed16;
-assign soc_netsoc_sdram_interface_bank1_valid = vns_rhs_array_muxed17;
-assign vns_roundrobin2_request = {(((soc_netsoc_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked2 | (soc_netsoc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_netsoc_port_cmd_valid)};
-assign vns_roundrobin2_ce = ((~soc_netsoc_sdram_interface_bank2_valid) & (~soc_netsoc_sdram_interface_bank2_lock));
-assign soc_netsoc_sdram_interface_bank2_addr = vns_rhs_array_muxed18;
-assign soc_netsoc_sdram_interface_bank2_we = vns_rhs_array_muxed19;
-assign soc_netsoc_sdram_interface_bank2_valid = vns_rhs_array_muxed20;
-assign vns_roundrobin3_request = {(((soc_netsoc_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked3 | (soc_netsoc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_netsoc_port_cmd_valid)};
-assign vns_roundrobin3_ce = ((~soc_netsoc_sdram_interface_bank3_valid) & (~soc_netsoc_sdram_interface_bank3_lock));
-assign soc_netsoc_sdram_interface_bank3_addr = vns_rhs_array_muxed21;
-assign soc_netsoc_sdram_interface_bank3_we = vns_rhs_array_muxed22;
-assign soc_netsoc_sdram_interface_bank3_valid = vns_rhs_array_muxed23;
-assign vns_roundrobin4_request = {(((soc_netsoc_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked4 | (soc_netsoc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_netsoc_port_cmd_valid)};
-assign vns_roundrobin4_ce = ((~soc_netsoc_sdram_interface_bank4_valid) & (~soc_netsoc_sdram_interface_bank4_lock));
-assign soc_netsoc_sdram_interface_bank4_addr = vns_rhs_array_muxed24;
-assign soc_netsoc_sdram_interface_bank4_we = vns_rhs_array_muxed25;
-assign soc_netsoc_sdram_interface_bank4_valid = vns_rhs_array_muxed26;
-assign vns_roundrobin5_request = {(((soc_netsoc_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked5 | (soc_netsoc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_netsoc_port_cmd_valid)};
-assign vns_roundrobin5_ce = ((~soc_netsoc_sdram_interface_bank5_valid) & (~soc_netsoc_sdram_interface_bank5_lock));
-assign soc_netsoc_sdram_interface_bank5_addr = vns_rhs_array_muxed27;
-assign soc_netsoc_sdram_interface_bank5_we = vns_rhs_array_muxed28;
-assign soc_netsoc_sdram_interface_bank5_valid = vns_rhs_array_muxed29;
-assign vns_roundrobin6_request = {(((soc_netsoc_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked6 | (soc_netsoc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_netsoc_port_cmd_valid)};
-assign vns_roundrobin6_ce = ((~soc_netsoc_sdram_interface_bank6_valid) & (~soc_netsoc_sdram_interface_bank6_lock));
-assign soc_netsoc_sdram_interface_bank6_addr = vns_rhs_array_muxed30;
-assign soc_netsoc_sdram_interface_bank6_we = vns_rhs_array_muxed31;
-assign soc_netsoc_sdram_interface_bank6_valid = vns_rhs_array_muxed32;
-assign vns_roundrobin7_request = {(((soc_netsoc_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked7 | (soc_netsoc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))))) & soc_netsoc_port_cmd_valid)};
-assign vns_roundrobin7_ce = ((~soc_netsoc_sdram_interface_bank7_valid) & (~soc_netsoc_sdram_interface_bank7_lock));
-assign soc_netsoc_sdram_interface_bank7_addr = vns_rhs_array_muxed33;
-assign soc_netsoc_sdram_interface_bank7_we = vns_rhs_array_muxed34;
-assign soc_netsoc_sdram_interface_bank7_valid = vns_rhs_array_muxed35;
-assign soc_netsoc_port_cmd_ready = ((((((((1'd0 | (((vns_roundrobin0_grant == 1'd0) & ((soc_netsoc_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked0 | (soc_netsoc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_netsoc_sdram_interface_bank0_ready)) | (((vns_roundrobin1_grant == 1'd0) & ((soc_netsoc_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked1 | (soc_netsoc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_netsoc_sdram_interface_bank1_ready)) | (((vns_roundrobin2_grant == 1'd0) & ((soc_netsoc_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked2 | (soc_netsoc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_netsoc_sdram_interface_bank2_ready)) | (((vns_roundrobin3_grant == 1'd0) & ((soc_netsoc_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked3 | (soc_netsoc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_netsoc_sdram_interface_bank3_ready)) | (((vns_roundrobin4_grant == 1'd0) & ((soc_netsoc_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked4 | (soc_netsoc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_netsoc_sdram_interface_bank4_ready)) | (((vns_roundrobin5_grant == 1'd0) & ((soc_netsoc_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked5 | (soc_netsoc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_netsoc_sdram_interface_bank5_ready)) | (((vns_roundrobin6_grant == 1'd0) & ((soc_netsoc_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked6 | (soc_netsoc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_netsoc_sdram_interface_bank6_ready)) | (((vns_roundrobin7_grant == 1'd0) & ((soc_netsoc_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked7 | (soc_netsoc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0)))))) & soc_netsoc_sdram_interface_bank7_ready));
-assign soc_netsoc_port_wdata_ready = vns_new_master_wdata_ready2;
-assign soc_netsoc_port_rdata_valid = vns_new_master_rdata_valid9;
-always @(*) begin
-	soc_netsoc_sdram_interface_wdata <= 128'd0;
-	soc_netsoc_sdram_interface_wdata_we <= 16'd0;
-	case ({vns_new_master_wdata_ready2})
-		1'd1: begin
-			soc_netsoc_sdram_interface_wdata <= soc_netsoc_port_wdata_payload_data;
-			soc_netsoc_sdram_interface_wdata_we <= soc_netsoc_port_wdata_payload_we;
-		end
-		default: begin
-			soc_netsoc_sdram_interface_wdata <= 1'd0;
-			soc_netsoc_sdram_interface_wdata_we <= 1'd0;
-		end
-	endcase
-end
-assign soc_netsoc_port_rdata_payload_data = soc_netsoc_sdram_interface_rdata;
-assign vns_roundrobin0_grant = 1'd0;
-assign vns_roundrobin1_grant = 1'd0;
-assign vns_roundrobin2_grant = 1'd0;
-assign vns_roundrobin3_grant = 1'd0;
-assign vns_roundrobin4_grant = 1'd0;
-assign vns_roundrobin5_grant = 1'd0;
-assign vns_roundrobin6_grant = 1'd0;
-assign vns_roundrobin7_grant = 1'd0;
-assign soc_netsoc_data_port_adr = soc_netsoc_interface0_wb_sdram_adr[10:2];
-always @(*) begin
-	soc_netsoc_data_port_we <= 16'd0;
-	soc_netsoc_data_port_dat_w <= 128'd0;
-	if (soc_netsoc_write_from_slave) begin
-		soc_netsoc_data_port_dat_w <= soc_netsoc_dat_r;
-		soc_netsoc_data_port_we <= {16{1'd1}};
-	end else begin
-		soc_netsoc_data_port_dat_w <= {4{soc_netsoc_interface0_wb_sdram_dat_w}};
-		if ((((soc_netsoc_interface0_wb_sdram_cyc & soc_netsoc_interface0_wb_sdram_stb) & soc_netsoc_interface0_wb_sdram_we) & soc_netsoc_interface0_wb_sdram_ack)) begin
-			soc_netsoc_data_port_we <= {({4{(soc_netsoc_interface0_wb_sdram_adr[1:0] == 1'd0)}} & soc_netsoc_interface0_wb_sdram_sel), ({4{(soc_netsoc_interface0_wb_sdram_adr[1:0] == 1'd1)}} & soc_netsoc_interface0_wb_sdram_sel), ({4{(soc_netsoc_interface0_wb_sdram_adr[1:0] == 2'd2)}} & soc_netsoc_interface0_wb_sdram_sel), ({4{(soc_netsoc_interface0_wb_sdram_adr[1:0] == 2'd3)}} & soc_netsoc_interface0_wb_sdram_sel)};
-		end
-	end
-end
-assign soc_netsoc_dat_w = soc_netsoc_data_port_dat_r;
-assign soc_netsoc_sel = 16'd65535;
-always @(*) begin
-	soc_netsoc_interface0_wb_sdram_dat_r <= 32'd0;
-	case (soc_netsoc_adr_offset_r)
-		1'd0: begin
-			soc_netsoc_interface0_wb_sdram_dat_r <= soc_netsoc_data_port_dat_r[127:96];
-		end
-		1'd1: begin
-			soc_netsoc_interface0_wb_sdram_dat_r <= soc_netsoc_data_port_dat_r[95:64];
-		end
-		2'd2: begin
-			soc_netsoc_interface0_wb_sdram_dat_r <= soc_netsoc_data_port_dat_r[63:32];
-		end
-		default: begin
-			soc_netsoc_interface0_wb_sdram_dat_r <= soc_netsoc_data_port_dat_r[31:0];
-		end
-	endcase
-end
-assign {soc_netsoc_tag_do_dirty, soc_netsoc_tag_do_tag} = soc_netsoc_tag_port_dat_r;
-assign soc_netsoc_tag_port_dat_w = {soc_netsoc_tag_di_dirty, soc_netsoc_tag_di_tag};
-assign soc_netsoc_tag_port_adr = soc_netsoc_interface0_wb_sdram_adr[10:2];
-assign soc_netsoc_tag_di_tag = soc_netsoc_interface0_wb_sdram_adr[29:11];
-assign soc_netsoc_adr = {soc_netsoc_tag_do_tag, soc_netsoc_interface0_wb_sdram_adr[10:2]};
-always @(*) begin
-	vns_fullmemorywe_next_state <= 3'd0;
-	soc_netsoc_tag_di_dirty <= 1'd0;
-	soc_netsoc_word_clr <= 1'd0;
-	soc_netsoc_interface0_wb_sdram_ack <= 1'd0;
-	soc_netsoc_word_inc <= 1'd0;
-	soc_netsoc_write_from_slave <= 1'd0;
-	soc_netsoc_cyc <= 1'd0;
-	soc_netsoc_stb <= 1'd0;
-	soc_netsoc_tag_port_we <= 1'd0;
-	soc_netsoc_we <= 1'd0;
-	vns_fullmemorywe_next_state <= vns_fullmemorywe_state;
-	case (vns_fullmemorywe_state)
-		1'd1: begin
-			soc_netsoc_word_clr <= 1'd1;
-			if ((soc_netsoc_tag_do_tag == soc_netsoc_interface0_wb_sdram_adr[29:11])) begin
-				soc_netsoc_interface0_wb_sdram_ack <= 1'd1;
-				if (soc_netsoc_interface0_wb_sdram_we) begin
-					soc_netsoc_tag_di_dirty <= 1'd1;
-					soc_netsoc_tag_port_we <= 1'd1;
-				end
-				vns_fullmemorywe_next_state <= 1'd0;
-			end else begin
-				if (soc_netsoc_tag_do_dirty) begin
-					vns_fullmemorywe_next_state <= 2'd2;
-				end else begin
-					vns_fullmemorywe_next_state <= 2'd3;
-				end
-			end
-		end
-		2'd2: begin
-			soc_netsoc_stb <= 1'd1;
-			soc_netsoc_cyc <= 1'd1;
-			soc_netsoc_we <= 1'd1;
-			if (soc_netsoc_ack) begin
-				soc_netsoc_word_inc <= 1'd1;
-				if (1'd1) begin
-					vns_fullmemorywe_next_state <= 2'd3;
-				end
-			end
-		end
-		2'd3: begin
-			soc_netsoc_tag_port_we <= 1'd1;
-			soc_netsoc_word_clr <= 1'd1;
-			vns_fullmemorywe_next_state <= 3'd4;
-		end
-		3'd4: begin
-			soc_netsoc_stb <= 1'd1;
-			soc_netsoc_cyc <= 1'd1;
-			soc_netsoc_we <= 1'd0;
-			if (soc_netsoc_ack) begin
-				soc_netsoc_write_from_slave <= 1'd1;
-				soc_netsoc_word_inc <= 1'd1;
-				if (1'd1) begin
-					vns_fullmemorywe_next_state <= 1'd1;
-				end else begin
-					vns_fullmemorywe_next_state <= 3'd4;
-				end
-			end
-		end
-		default: begin
-			if ((soc_netsoc_interface0_wb_sdram_cyc & soc_netsoc_interface0_wb_sdram_stb)) begin
-				vns_fullmemorywe_next_state <= 1'd1;
-			end
-		end
-	endcase
-end
-assign soc_netsoc_wdata_converter_sink_valid = ((soc_netsoc_cyc & soc_netsoc_stb) & soc_netsoc_we);
-assign soc_netsoc_wdata_converter_sink_payload_data = soc_netsoc_dat_w;
-assign soc_netsoc_wdata_converter_sink_payload_we = soc_netsoc_sel;
-assign soc_netsoc_port_wdata_valid = soc_netsoc_wdata_converter_source_valid;
-assign soc_netsoc_wdata_converter_source_ready = soc_netsoc_port_wdata_ready;
-assign soc_netsoc_port_wdata_first = soc_netsoc_wdata_converter_source_first;
-assign soc_netsoc_port_wdata_last = soc_netsoc_wdata_converter_source_last;
-assign soc_netsoc_port_wdata_payload_data = soc_netsoc_wdata_converter_source_payload_data;
-assign soc_netsoc_port_wdata_payload_we = soc_netsoc_wdata_converter_source_payload_we;
-assign soc_netsoc_rdata_converter_sink_valid = soc_netsoc_port_rdata_valid;
-assign soc_netsoc_port_rdata_ready = soc_netsoc_rdata_converter_sink_ready;
-assign soc_netsoc_rdata_converter_sink_first = soc_netsoc_port_rdata_first;
-assign soc_netsoc_rdata_converter_sink_last = soc_netsoc_port_rdata_last;
-assign soc_netsoc_rdata_converter_sink_payload_data = soc_netsoc_port_rdata_payload_data;
-assign soc_netsoc_rdata_converter_source_ready = 1'd1;
-assign soc_netsoc_dat_r = soc_netsoc_rdata_converter_source_payload_data;
-assign soc_netsoc_wdata_converter_converter_sink_valid = soc_netsoc_wdata_converter_sink_valid;
-assign soc_netsoc_wdata_converter_converter_sink_first = soc_netsoc_wdata_converter_sink_first;
-assign soc_netsoc_wdata_converter_converter_sink_last = soc_netsoc_wdata_converter_sink_last;
-assign soc_netsoc_wdata_converter_sink_ready = soc_netsoc_wdata_converter_converter_sink_ready;
-assign soc_netsoc_wdata_converter_converter_sink_payload_data = {soc_netsoc_wdata_converter_sink_payload_we, soc_netsoc_wdata_converter_sink_payload_data};
-assign soc_netsoc_wdata_converter_source_valid = soc_netsoc_wdata_converter_source_source_valid;
-assign soc_netsoc_wdata_converter_source_first = soc_netsoc_wdata_converter_source_source_first;
-assign soc_netsoc_wdata_converter_source_last = soc_netsoc_wdata_converter_source_source_last;
-assign soc_netsoc_wdata_converter_source_source_ready = soc_netsoc_wdata_converter_source_ready;
-assign {soc_netsoc_wdata_converter_source_payload_we, soc_netsoc_wdata_converter_source_payload_data} = soc_netsoc_wdata_converter_source_source_payload_data;
-assign soc_netsoc_wdata_converter_source_source_valid = soc_netsoc_wdata_converter_converter_source_valid;
-assign soc_netsoc_wdata_converter_converter_source_ready = soc_netsoc_wdata_converter_source_source_ready;
-assign soc_netsoc_wdata_converter_source_source_first = soc_netsoc_wdata_converter_converter_source_first;
-assign soc_netsoc_wdata_converter_source_source_last = soc_netsoc_wdata_converter_converter_source_last;
-assign soc_netsoc_wdata_converter_source_source_payload_data = soc_netsoc_wdata_converter_converter_source_payload_data;
-assign soc_netsoc_wdata_converter_converter_source_valid = soc_netsoc_wdata_converter_converter_sink_valid;
-assign soc_netsoc_wdata_converter_converter_sink_ready = soc_netsoc_wdata_converter_converter_source_ready;
-assign soc_netsoc_wdata_converter_converter_source_first = soc_netsoc_wdata_converter_converter_sink_first;
-assign soc_netsoc_wdata_converter_converter_source_last = soc_netsoc_wdata_converter_converter_sink_last;
-assign soc_netsoc_wdata_converter_converter_source_payload_data = soc_netsoc_wdata_converter_converter_sink_payload_data;
-assign soc_netsoc_wdata_converter_converter_source_payload_valid_token_count = 1'd1;
-assign soc_netsoc_rdata_converter_converter_sink_valid = soc_netsoc_rdata_converter_sink_valid;
-assign soc_netsoc_rdata_converter_converter_sink_first = soc_netsoc_rdata_converter_sink_first;
-assign soc_netsoc_rdata_converter_converter_sink_last = soc_netsoc_rdata_converter_sink_last;
-assign soc_netsoc_rdata_converter_sink_ready = soc_netsoc_rdata_converter_converter_sink_ready;
-assign soc_netsoc_rdata_converter_converter_sink_payload_data = {soc_netsoc_rdata_converter_sink_payload_data};
-assign soc_netsoc_rdata_converter_source_valid = soc_netsoc_rdata_converter_source_source_valid;
-assign soc_netsoc_rdata_converter_source_first = soc_netsoc_rdata_converter_source_source_first;
-assign soc_netsoc_rdata_converter_source_last = soc_netsoc_rdata_converter_source_source_last;
-assign soc_netsoc_rdata_converter_source_source_ready = soc_netsoc_rdata_converter_source_ready;
-assign {soc_netsoc_rdata_converter_source_payload_data} = soc_netsoc_rdata_converter_source_source_payload_data;
-assign soc_netsoc_rdata_converter_source_source_valid = soc_netsoc_rdata_converter_converter_source_valid;
-assign soc_netsoc_rdata_converter_converter_source_ready = soc_netsoc_rdata_converter_source_source_ready;
-assign soc_netsoc_rdata_converter_source_source_first = soc_netsoc_rdata_converter_converter_source_first;
-assign soc_netsoc_rdata_converter_source_source_last = soc_netsoc_rdata_converter_converter_source_last;
-assign soc_netsoc_rdata_converter_source_source_payload_data = soc_netsoc_rdata_converter_converter_source_payload_data;
-assign soc_netsoc_rdata_converter_converter_source_valid = soc_netsoc_rdata_converter_converter_sink_valid;
-assign soc_netsoc_rdata_converter_converter_sink_ready = soc_netsoc_rdata_converter_converter_source_ready;
-assign soc_netsoc_rdata_converter_converter_source_first = soc_netsoc_rdata_converter_converter_sink_first;
-assign soc_netsoc_rdata_converter_converter_source_last = soc_netsoc_rdata_converter_converter_sink_last;
-assign soc_netsoc_rdata_converter_converter_source_payload_data = soc_netsoc_rdata_converter_converter_sink_payload_data;
-assign soc_netsoc_rdata_converter_converter_source_payload_valid_token_count = 1'd1;
-always @(*) begin
-	soc_netsoc_count_litedramwishbone2native_next_value <= 1'd0;
-	soc_netsoc_port_cmd_valid <= 1'd0;
-	soc_netsoc_count_litedramwishbone2native_next_value_ce <= 1'd0;
-	soc_netsoc_ack <= 1'd0;
-	soc_netsoc_port_cmd_payload_we <= 1'd0;
-	vns_litedramwishbone2native_next_state <= 2'd0;
-	soc_netsoc_port_cmd_payload_addr <= 24'd0;
-	vns_litedramwishbone2native_next_state <= vns_litedramwishbone2native_state;
-	case (vns_litedramwishbone2native_state)
-		1'd1: begin
-			if (soc_netsoc_wdata_converter_sink_ready) begin
-				soc_netsoc_ack <= 1'd1;
-				vns_litedramwishbone2native_next_state <= 1'd0;
-			end
-		end
-		2'd2: begin
-			if (soc_netsoc_rdata_converter_source_valid) begin
-				soc_netsoc_ack <= 1'd1;
-				vns_litedramwishbone2native_next_state <= 1'd0;
-			end
-		end
-		default: begin
-			soc_netsoc_port_cmd_valid <= (soc_netsoc_cyc & soc_netsoc_stb);
-			soc_netsoc_port_cmd_payload_we <= soc_netsoc_we;
-			soc_netsoc_port_cmd_payload_addr <= (((soc_netsoc_adr * 1'd1) + soc_netsoc_count) - 1'd0);
-			if ((soc_netsoc_port_cmd_valid & soc_netsoc_port_cmd_ready)) begin
-				soc_netsoc_count_litedramwishbone2native_next_value <= (soc_netsoc_count + 1'd1);
-				soc_netsoc_count_litedramwishbone2native_next_value_ce <= 1'd1;
-				if ((soc_netsoc_count == 1'd0)) begin
-					soc_netsoc_count_litedramwishbone2native_next_value <= 1'd0;
-					soc_netsoc_count_litedramwishbone2native_next_value_ce <= 1'd1;
-					if (soc_netsoc_we) begin
-						vns_litedramwishbone2native_next_state <= 1'd1;
-					end else begin
-						vns_litedramwishbone2native_next_state <= 2'd2;
-					end
-				end
-			end
-		end
-	endcase
-end
-assign eth_rx_clk = eth_clocks_rx;
-assign eth_tx_clk = eth_clocks_tx;
-assign soc_reset0 = (soc_reset_storage | soc_reset1);
-assign eth_rst_n = (~soc_reset0);
-assign soc_counter_done = (soc_counter == 9'd256);
-assign soc_counter_ce = (~soc_counter_done);
-assign soc_reset1 = (~soc_counter_done);
-assign soc_liteethphymiitx_converter_sink_valid = soc_liteethphymiitx_sink_sink_valid;
-assign soc_liteethphymiitx_converter_sink_payload_data = soc_liteethphymiitx_sink_sink_payload_data;
-assign soc_liteethphymiitx_sink_sink_ready = soc_liteethphymiitx_converter_sink_ready;
-assign soc_liteethphymiitx_converter_source_ready = 1'd1;
-assign soc_liteethphymiitx_converter_converter_sink_valid = soc_liteethphymiitx_converter_sink_valid;
-assign soc_liteethphymiitx_converter_converter_sink_first = soc_liteethphymiitx_converter_sink_first;
-assign soc_liteethphymiitx_converter_converter_sink_last = soc_liteethphymiitx_converter_sink_last;
-assign soc_liteethphymiitx_converter_sink_ready = soc_liteethphymiitx_converter_converter_sink_ready;
-always @(*) begin
-	soc_liteethphymiitx_converter_converter_sink_payload_data <= 8'd0;
-	soc_liteethphymiitx_converter_converter_sink_payload_data[3:0] <= soc_liteethphymiitx_converter_sink_payload_data[3:0];
-	soc_liteethphymiitx_converter_converter_sink_payload_data[7:4] <= soc_liteethphymiitx_converter_sink_payload_data[7:4];
-end
-assign soc_liteethphymiitx_converter_source_valid = soc_liteethphymiitx_converter_source_source_valid;
-assign soc_liteethphymiitx_converter_source_first = soc_liteethphymiitx_converter_source_source_first;
-assign soc_liteethphymiitx_converter_source_last = soc_liteethphymiitx_converter_source_source_last;
-assign soc_liteethphymiitx_converter_source_source_ready = soc_liteethphymiitx_converter_source_ready;
-assign {soc_liteethphymiitx_converter_source_payload_data} = soc_liteethphymiitx_converter_source_source_payload_data;
-assign soc_liteethphymiitx_converter_source_source_valid = soc_liteethphymiitx_converter_converter_source_valid;
-assign soc_liteethphymiitx_converter_converter_source_ready = soc_liteethphymiitx_converter_source_source_ready;
-assign soc_liteethphymiitx_converter_source_source_first = soc_liteethphymiitx_converter_converter_source_first;
-assign soc_liteethphymiitx_converter_source_source_last = soc_liteethphymiitx_converter_converter_source_last;
-assign soc_liteethphymiitx_converter_source_source_payload_data = soc_liteethphymiitx_converter_converter_source_payload_data;
-assign soc_liteethphymiitx_converter_converter_first = (soc_liteethphymiitx_converter_converter_mux == 1'd0);
-assign soc_liteethphymiitx_converter_converter_last = (soc_liteethphymiitx_converter_converter_mux == 1'd1);
-assign soc_liteethphymiitx_converter_converter_source_valid = soc_liteethphymiitx_converter_converter_sink_valid;
-assign soc_liteethphymiitx_converter_converter_source_first = (soc_liteethphymiitx_converter_converter_sink_first & soc_liteethphymiitx_converter_converter_first);
-assign soc_liteethphymiitx_converter_converter_source_last = (soc_liteethphymiitx_converter_converter_sink_last & soc_liteethphymiitx_converter_converter_last);
-assign soc_liteethphymiitx_converter_converter_sink_ready = (soc_liteethphymiitx_converter_converter_last & soc_liteethphymiitx_converter_converter_source_ready);
-always @(*) begin
-	soc_liteethphymiitx_converter_converter_source_payload_data <= 4'd0;
-	case (soc_liteethphymiitx_converter_converter_mux)
-		1'd0: begin
-			soc_liteethphymiitx_converter_converter_source_payload_data <= soc_liteethphymiitx_converter_converter_sink_payload_data[3:0];
-		end
-		default: begin
-			soc_liteethphymiitx_converter_converter_source_payload_data <= soc_liteethphymiitx_converter_converter_sink_payload_data[7:4];
-		end
-	endcase
-end
-assign soc_liteethphymiitx_converter_converter_source_payload_valid_token_count = soc_liteethphymiitx_converter_converter_last;
-assign soc_liteethphymiirx_converter_sink_last = (~eth_rx_dv);
-assign soc_liteethphymiirx_source_source_valid = soc_liteethphymiirx_converter_source_valid;
-assign soc_liteethphymiirx_converter_source_ready = soc_liteethphymiirx_source_source_ready;
-assign soc_liteethphymiirx_source_source_first = soc_liteethphymiirx_converter_source_first;
-assign soc_liteethphymiirx_source_source_last = soc_liteethphymiirx_converter_source_last;
-assign soc_liteethphymiirx_source_source_payload_data = soc_liteethphymiirx_converter_source_payload_data;
-assign soc_liteethphymiirx_converter_converter_sink_valid = soc_liteethphymiirx_converter_sink_valid;
-assign soc_liteethphymiirx_converter_converter_sink_first = soc_liteethphymiirx_converter_sink_first;
-assign soc_liteethphymiirx_converter_converter_sink_last = soc_liteethphymiirx_converter_sink_last;
-assign soc_liteethphymiirx_converter_sink_ready = soc_liteethphymiirx_converter_converter_sink_ready;
-assign soc_liteethphymiirx_converter_converter_sink_payload_data = {soc_liteethphymiirx_converter_sink_payload_data};
-assign soc_liteethphymiirx_converter_source_valid = soc_liteethphymiirx_converter_source_source_valid;
-assign soc_liteethphymiirx_converter_source_first = soc_liteethphymiirx_converter_source_source_first;
-assign soc_liteethphymiirx_converter_source_last = soc_liteethphymiirx_converter_source_source_last;
-assign soc_liteethphymiirx_converter_source_source_ready = soc_liteethphymiirx_converter_source_ready;
-always @(*) begin
-	soc_liteethphymiirx_converter_source_payload_data <= 8'd0;
-	soc_liteethphymiirx_converter_source_payload_data[3:0] <= soc_liteethphymiirx_converter_source_source_payload_data[3:0];
-	soc_liteethphymiirx_converter_source_payload_data[7:4] <= soc_liteethphymiirx_converter_source_source_payload_data[7:4];
-end
-assign soc_liteethphymiirx_converter_source_source_valid = soc_liteethphymiirx_converter_converter_source_valid;
-assign soc_liteethphymiirx_converter_converter_source_ready = soc_liteethphymiirx_converter_source_source_ready;
-assign soc_liteethphymiirx_converter_source_source_first = soc_liteethphymiirx_converter_converter_source_first;
-assign soc_liteethphymiirx_converter_source_source_last = soc_liteethphymiirx_converter_converter_source_last;
-assign soc_liteethphymiirx_converter_source_source_payload_data = soc_liteethphymiirx_converter_converter_source_payload_data;
-assign soc_liteethphymiirx_converter_converter_sink_ready = ((~soc_liteethphymiirx_converter_converter_strobe_all) | soc_liteethphymiirx_converter_converter_source_ready);
-assign soc_liteethphymiirx_converter_converter_source_valid = soc_liteethphymiirx_converter_converter_strobe_all;
-assign soc_liteethphymiirx_converter_converter_load_part = (soc_liteethphymiirx_converter_converter_sink_valid & soc_liteethphymiirx_converter_converter_sink_ready);
-assign eth_mdc = soc_storage[0];
-assign soc_data_oe = soc_storage[1];
-assign soc_data_w = soc_storage[2];
-assign soc_tx_cdc_sink_valid = soc_source_valid;
-assign soc_source_ready = soc_tx_cdc_sink_ready;
-assign soc_tx_cdc_sink_first = soc_source_first;
-assign soc_tx_cdc_sink_last = soc_source_last;
-assign soc_tx_cdc_sink_payload_data = soc_source_payload_data;
-assign soc_tx_cdc_sink_payload_last_be = soc_source_payload_last_be;
-assign soc_tx_cdc_sink_payload_error = soc_source_payload_error;
-assign soc_sink_valid = soc_rx_cdc_source_valid;
-assign soc_rx_cdc_source_ready = soc_sink_ready;
-assign soc_sink_first = soc_rx_cdc_source_first;
-assign soc_sink_last = soc_rx_cdc_source_last;
-assign soc_sink_payload_data = soc_rx_cdc_source_payload_data;
-assign soc_sink_payload_last_be = soc_rx_cdc_source_payload_last_be;
-assign soc_sink_payload_error = soc_rx_cdc_source_payload_error;
-assign soc_ps_preamble_error_i = soc_preamble_checker_error;
-assign soc_ps_crc_error_i = soc_crc32_checker_error;
-always @(*) begin
-	soc_tx_gap_inserter_source_first <= 1'd0;
-	soc_tx_gap_inserter_source_last <= 1'd0;
-	soc_tx_gap_inserter_source_payload_data <= 8'd0;
-	soc_tx_gap_inserter_source_payload_last_be <= 1'd0;
-	soc_tx_gap_inserter_source_payload_error <= 1'd0;
-	soc_tx_gap_inserter_counter_reset <= 1'd0;
-	soc_tx_gap_inserter_counter_ce <= 1'd0;
-	soc_tx_gap_inserter_sink_ready <= 1'd0;
-	vns_liteethmacgap_next_state <= 1'd0;
-	soc_tx_gap_inserter_source_valid <= 1'd0;
-	vns_liteethmacgap_next_state <= vns_liteethmacgap_state;
-	case (vns_liteethmacgap_state)
-		1'd1: begin
-			soc_tx_gap_inserter_counter_ce <= 1'd1;
-			if ((soc_tx_gap_inserter_counter == 4'd11)) begin
-				vns_liteethmacgap_next_state <= 1'd0;
-			end
-		end
-		default: begin
-			soc_tx_gap_inserter_counter_reset <= 1'd1;
-			soc_tx_gap_inserter_source_valid <= soc_tx_gap_inserter_sink_valid;
-			soc_tx_gap_inserter_sink_ready <= soc_tx_gap_inserter_source_ready;
-			soc_tx_gap_inserter_source_first <= soc_tx_gap_inserter_sink_first;
-			soc_tx_gap_inserter_source_last <= soc_tx_gap_inserter_sink_last;
-			soc_tx_gap_inserter_source_payload_data <= soc_tx_gap_inserter_sink_payload_data;
-			soc_tx_gap_inserter_source_payload_last_be <= soc_tx_gap_inserter_sink_payload_last_be;
-			soc_tx_gap_inserter_source_payload_error <= soc_tx_gap_inserter_sink_payload_error;
-			if (((soc_tx_gap_inserter_sink_valid & soc_tx_gap_inserter_sink_last) & soc_tx_gap_inserter_sink_ready)) begin
-				vns_liteethmacgap_next_state <= 1'd1;
-			end
-		end
-	endcase
-end
-assign soc_preamble_inserter_source_payload_last_be = soc_preamble_inserter_sink_payload_last_be;
-always @(*) begin
-	soc_preamble_inserter_source_payload_error <= 1'd0;
-	vns_liteethmacpreambleinserter_next_state <= 2'd0;
-	soc_preamble_inserter_clr_cnt <= 1'd0;
-	soc_preamble_inserter_sink_ready <= 1'd0;
-	soc_preamble_inserter_inc_cnt <= 1'd0;
-	soc_preamble_inserter_source_valid <= 1'd0;
-	soc_preamble_inserter_source_first <= 1'd0;
-	soc_preamble_inserter_source_last <= 1'd0;
-	soc_preamble_inserter_source_payload_data <= 8'd0;
-	soc_preamble_inserter_source_payload_data <= soc_preamble_inserter_sink_payload_data;
-	vns_liteethmacpreambleinserter_next_state <= vns_liteethmacpreambleinserter_state;
-	case (vns_liteethmacpreambleinserter_state)
-		1'd1: begin
-			soc_preamble_inserter_source_valid <= 1'd1;
-			case (soc_preamble_inserter_cnt)
-				1'd0: begin
-					soc_preamble_inserter_source_payload_data <= soc_preamble_inserter_preamble[7:0];
-				end
-				1'd1: begin
-					soc_preamble_inserter_source_payload_data <= soc_preamble_inserter_preamble[15:8];
-				end
-				2'd2: begin
-					soc_preamble_inserter_source_payload_data <= soc_preamble_inserter_preamble[23:16];
-				end
-				2'd3: begin
-					soc_preamble_inserter_source_payload_data <= soc_preamble_inserter_preamble[31:24];
-				end
-				3'd4: begin
-					soc_preamble_inserter_source_payload_data <= soc_preamble_inserter_preamble[39:32];
-				end
-				3'd5: begin
-					soc_preamble_inserter_source_payload_data <= soc_preamble_inserter_preamble[47:40];
-				end
-				3'd6: begin
-					soc_preamble_inserter_source_payload_data <= soc_preamble_inserter_preamble[55:48];
-				end
-				default: begin
-					soc_preamble_inserter_source_payload_data <= soc_preamble_inserter_preamble[63:56];
-				end
-			endcase
-			if ((soc_preamble_inserter_cnt == 3'd7)) begin
-				if (soc_preamble_inserter_source_ready) begin
-					vns_liteethmacpreambleinserter_next_state <= 2'd2;
-				end
-			end else begin
-				soc_preamble_inserter_inc_cnt <= soc_preamble_inserter_source_ready;
-			end
-		end
-		2'd2: begin
-			soc_preamble_inserter_source_valid <= soc_preamble_inserter_sink_valid;
-			soc_preamble_inserter_sink_ready <= soc_preamble_inserter_source_ready;
-			soc_preamble_inserter_source_first <= soc_preamble_inserter_sink_first;
-			soc_preamble_inserter_source_last <= soc_preamble_inserter_sink_last;
-			soc_preamble_inserter_source_payload_error <= soc_preamble_inserter_sink_payload_error;
-			if (((soc_preamble_inserter_sink_valid & soc_preamble_inserter_sink_last) & soc_preamble_inserter_source_ready)) begin
-				vns_liteethmacpreambleinserter_next_state <= 1'd0;
-			end
-		end
-		default: begin
-			soc_preamble_inserter_sink_ready <= 1'd1;
-			soc_preamble_inserter_clr_cnt <= 1'd1;
-			if (soc_preamble_inserter_sink_valid) begin
-				soc_preamble_inserter_sink_ready <= 1'd0;
-				vns_liteethmacpreambleinserter_next_state <= 1'd1;
-			end
-		end
-	endcase
-end
-assign soc_preamble_checker_source_payload_data = soc_preamble_checker_sink_payload_data;
-assign soc_preamble_checker_source_payload_last_be = soc_preamble_checker_sink_payload_last_be;
-always @(*) begin
-	soc_preamble_checker_source_payload_error <= 1'd0;
-	soc_preamble_checker_error <= 1'd0;
-	soc_preamble_checker_source_valid <= 1'd0;
-	soc_preamble_checker_source_first <= 1'd0;
-	soc_preamble_checker_sink_ready <= 1'd0;
-	soc_preamble_checker_source_last <= 1'd0;
-	vns_liteethmacpreamblechecker_next_state <= 1'd0;
-	vns_liteethmacpreamblechecker_next_state <= vns_liteethmacpreamblechecker_state;
-	case (vns_liteethmacpreamblechecker_state)
-		1'd1: begin
-			soc_preamble_checker_source_valid <= soc_preamble_checker_sink_valid;
-			soc_preamble_checker_sink_ready <= soc_preamble_checker_source_ready;
-			soc_preamble_checker_source_first <= soc_preamble_checker_sink_first;
-			soc_preamble_checker_source_last <= soc_preamble_checker_sink_last;
-			soc_preamble_checker_source_payload_error <= soc_preamble_checker_sink_payload_error;
-			if (((soc_preamble_checker_source_valid & soc_preamble_checker_source_last) & soc_preamble_checker_source_ready)) begin
-				vns_liteethmacpreamblechecker_next_state <= 1'd0;
-			end
-		end
-		default: begin
-			soc_preamble_checker_sink_ready <= 1'd1;
-			if (((soc_preamble_checker_sink_valid & (~soc_preamble_checker_sink_last)) & (soc_preamble_checker_sink_payload_data == 8'd213))) begin
-				vns_liteethmacpreamblechecker_next_state <= 1'd1;
-			end
-			if ((soc_preamble_checker_sink_valid & soc_preamble_checker_sink_last)) begin
-				soc_preamble_checker_error <= 1'd1;
-			end
-		end
-	endcase
-end
-assign soc_crc32_inserter_cnt_done = (soc_crc32_inserter_cnt == 1'd0);
-assign soc_crc32_inserter_data1 = soc_crc32_inserter_data0;
-assign soc_crc32_inserter_last = soc_crc32_inserter_reg;
-assign soc_crc32_inserter_value = (~{soc_crc32_inserter_reg[0], soc_crc32_inserter_reg[1], soc_crc32_inserter_reg[2], soc_crc32_inserter_reg[3], soc_crc32_inserter_reg[4], soc_crc32_inserter_reg[5], soc_crc32_inserter_reg[6], soc_crc32_inserter_reg[7], soc_crc32_inserter_reg[8], soc_crc32_inserter_reg[9], soc_crc32_inserter_reg[10], soc_crc32_inserter_reg[11], soc_crc32_inserter_reg[12], soc_crc32_inserter_reg[13], soc_crc32_inserter_reg[14], soc_crc32_inserter_reg[15], soc_crc32_inserter_reg[16], soc_crc32_inserter_reg[17], soc_crc32_inserter_reg[18], soc_crc32_inserter_reg[19], soc_crc32_inserter_reg[20], soc_crc32_inserter_reg[21], soc_crc32_inserter_reg[22], soc_crc32_inserter_reg[23], soc_crc32_inserter_reg[24], soc_crc32_inserter_reg[25], soc_crc32_inserter_reg[26], soc_crc32_inserter_reg[27], soc_crc32_inserter_reg[28], soc_crc32_inserter_reg[29], soc_crc32_inserter_reg[30], soc_crc32_inserter_reg[31]});
-assign soc_crc32_inserter_error = (soc_crc32_inserter_next != 32'd3338984827);
-always @(*) begin
-	soc_crc32_inserter_next <= 32'd0;
-	soc_crc32_inserter_next[0] <= (((soc_crc32_inserter_last[24] ^ soc_crc32_inserter_last[30]) ^ soc_crc32_inserter_data1[1]) ^ soc_crc32_inserter_data1[7]);
-	soc_crc32_inserter_next[1] <= (((((((soc_crc32_inserter_last[25] ^ soc_crc32_inserter_last[31]) ^ soc_crc32_inserter_data1[0]) ^ soc_crc32_inserter_data1[6]) ^ soc_crc32_inserter_last[24]) ^ soc_crc32_inserter_last[30]) ^ soc_crc32_inserter_data1[1]) ^ soc_crc32_inserter_data1[7]);
-	soc_crc32_inserter_next[2] <= (((((((((soc_crc32_inserter_last[26] ^ soc_crc32_inserter_data1[5]) ^ soc_crc32_inserter_last[25]) ^ soc_crc32_inserter_last[31]) ^ soc_crc32_inserter_data1[0]) ^ soc_crc32_inserter_data1[6]) ^ soc_crc32_inserter_last[24]) ^ soc_crc32_inserter_last[30]) ^ soc_crc32_inserter_data1[1]) ^ soc_crc32_inserter_data1[7]);
-	soc_crc32_inserter_next[3] <= (((((((soc_crc32_inserter_last[27] ^ soc_crc32_inserter_data1[4]) ^ soc_crc32_inserter_last[26]) ^ soc_crc32_inserter_data1[5]) ^ soc_crc32_inserter_last[25]) ^ soc_crc32_inserter_last[31]) ^ soc_crc32_inserter_data1[0]) ^ soc_crc32_inserter_data1[6]);
-	soc_crc32_inserter_next[4] <= (((((((((soc_crc32_inserter_last[28] ^ soc_crc32_inserter_data1[3]) ^ soc_crc32_inserter_last[27]) ^ soc_crc32_inserter_data1[4]) ^ soc_crc32_inserter_last[26]) ^ soc_crc32_inserter_data1[5]) ^ soc_crc32_inserter_last[24]) ^ soc_crc32_inserter_last[30]) ^ soc_crc32_inserter_data1[1]) ^ soc_crc32_inserter_data1[7]);
-	soc_crc32_inserter_next[5] <= (((((((((((((soc_crc32_inserter_last[29] ^ soc_crc32_inserter_data1[2]) ^ soc_crc32_inserter_last[28]) ^ soc_crc32_inserter_data1[3]) ^ soc_crc32_inserter_last[27]) ^ soc_crc32_inserter_data1[4]) ^ soc_crc32_inserter_last[25]) ^ soc_crc32_inserter_last[31]) ^ soc_crc32_inserter_data1[0]) ^ soc_crc32_inserter_data1[6]) ^ soc_crc32_inserter_last[24]) ^ soc_crc32_inserter_last[30]) ^ soc_crc32_inserter_data1[1]) ^ soc_crc32_inserter_data1[7]);
-	soc_crc32_inserter_next[6] <= (((((((((((soc_crc32_inserter_last[30] ^ soc_crc32_inserter_data1[1]) ^ soc_crc32_inserter_last[29]) ^ soc_crc32_inserter_data1[2]) ^ soc_crc32_inserter_last[28]) ^ soc_crc32_inserter_data1[3]) ^ soc_crc32_inserter_last[26]) ^ soc_crc32_inserter_data1[5]) ^ soc_crc32_inserter_last[25]) ^ soc_crc32_inserter_last[31]) ^ soc_crc32_inserter_data1[0]) ^ soc_crc32_inserter_data1[6]);
-	soc_crc32_inserter_next[7] <= (((((((((soc_crc32_inserter_last[31] ^ soc_crc32_inserter_data1[0]) ^ soc_crc32_inserter_last[29]) ^ soc_crc32_inserter_data1[2]) ^ soc_crc32_inserter_last[27]) ^ soc_crc32_inserter_data1[4]) ^ soc_crc32_inserter_last[26]) ^ soc_crc32_inserter_data1[5]) ^ soc_crc32_inserter_last[24]) ^ soc_crc32_inserter_data1[7]);
-	soc_crc32_inserter_next[8] <= ((((((((soc_crc32_inserter_last[0] ^ soc_crc32_inserter_last[28]) ^ soc_crc32_inserter_data1[3]) ^ soc_crc32_inserter_last[27]) ^ soc_crc32_inserter_data1[4]) ^ soc_crc32_inserter_last[25]) ^ soc_crc32_inserter_data1[6]) ^ soc_crc32_inserter_last[24]) ^ soc_crc32_inserter_data1[7]);
-	soc_crc32_inserter_next[9] <= ((((((((soc_crc32_inserter_last[1] ^ soc_crc32_inserter_last[29]) ^ soc_crc32_inserter_data1[2]) ^ soc_crc32_inserter_last[28]) ^ soc_crc32_inserter_data1[3]) ^ soc_crc32_inserter_last[26]) ^ soc_crc32_inserter_data1[5]) ^ soc_crc32_inserter_last[25]) ^ soc_crc32_inserter_data1[6]);
-	soc_crc32_inserter_next[10] <= ((((((((soc_crc32_inserter_last[2] ^ soc_crc32_inserter_last[29]) ^ soc_crc32_inserter_data1[2]) ^ soc_crc32_inserter_last[27]) ^ soc_crc32_inserter_data1[4]) ^ soc_crc32_inserter_last[26]) ^ soc_crc32_inserter_data1[5]) ^ soc_crc32_inserter_last[24]) ^ soc_crc32_inserter_data1[7]);
-	soc_crc32_inserter_next[11] <= ((((((((soc_crc32_inserter_last[3] ^ soc_crc32_inserter_last[28]) ^ soc_crc32_inserter_data1[3]) ^ soc_crc32_inserter_last[27]) ^ soc_crc32_inserter_data1[4]) ^ soc_crc32_inserter_last[25]) ^ soc_crc32_inserter_data1[6]) ^ soc_crc32_inserter_last[24]) ^ soc_crc32_inserter_data1[7]);
-	soc_crc32_inserter_next[12] <= ((((((((((((soc_crc32_inserter_last[4] ^ soc_crc32_inserter_last[29]) ^ soc_crc32_inserter_data1[2]) ^ soc_crc32_inserter_last[28]) ^ soc_crc32_inserter_data1[3]) ^ soc_crc32_inserter_last[26]) ^ soc_crc32_inserter_data1[5]) ^ soc_crc32_inserter_last[25]) ^ soc_crc32_inserter_data1[6]) ^ soc_crc32_inserter_last[24]) ^ soc_crc32_inserter_last[30]) ^ soc_crc32_inserter_data1[1]) ^ soc_crc32_inserter_data1[7]);
-	soc_crc32_inserter_next[13] <= ((((((((((((soc_crc32_inserter_last[5] ^ soc_crc32_inserter_last[30]) ^ soc_crc32_inserter_data1[1]) ^ soc_crc32_inserter_last[29]) ^ soc_crc32_inserter_data1[2]) ^ soc_crc32_inserter_last[27]) ^ soc_crc32_inserter_data1[4]) ^ soc_crc32_inserter_last[26]) ^ soc_crc32_inserter_data1[5]) ^ soc_crc32_inserter_last[25]) ^ soc_crc32_inserter_last[31]) ^ soc_crc32_inserter_data1[0]) ^ soc_crc32_inserter_data1[6]);
-	soc_crc32_inserter_next[14] <= ((((((((((soc_crc32_inserter_last[6] ^ soc_crc32_inserter_last[31]) ^ soc_crc32_inserter_data1[0]) ^ soc_crc32_inserter_last[30]) ^ soc_crc32_inserter_data1[1]) ^ soc_crc32_inserter_last[28]) ^ soc_crc32_inserter_data1[3]) ^ soc_crc32_inserter_last[27]) ^ soc_crc32_inserter_data1[4]) ^ soc_crc32_inserter_last[26]) ^ soc_crc32_inserter_data1[5]);
-	soc_crc32_inserter_next[15] <= ((((((((soc_crc32_inserter_last[7] ^ soc_crc32_inserter_last[31]) ^ soc_crc32_inserter_data1[0]) ^ soc_crc32_inserter_last[29]) ^ soc_crc32_inserter_data1[2]) ^ soc_crc32_inserter_last[28]) ^ soc_crc32_inserter_data1[3]) ^ soc_crc32_inserter_last[27]) ^ soc_crc32_inserter_data1[4]);
-	soc_crc32_inserter_next[16] <= ((((((soc_crc32_inserter_last[8] ^ soc_crc32_inserter_last[29]) ^ soc_crc32_inserter_data1[2]) ^ soc_crc32_inserter_last[28]) ^ soc_crc32_inserter_data1[3]) ^ soc_crc32_inserter_last[24]) ^ soc_crc32_inserter_data1[7]);
-	soc_crc32_inserter_next[17] <= ((((((soc_crc32_inserter_last[9] ^ soc_crc32_inserter_last[30]) ^ soc_crc32_inserter_data1[1]) ^ soc_crc32_inserter_last[29]) ^ soc_crc32_inserter_data1[2]) ^ soc_crc32_inserter_last[25]) ^ soc_crc32_inserter_data1[6]);
-	soc_crc32_inserter_next[18] <= ((((((soc_crc32_inserter_last[10] ^ soc_crc32_inserter_last[31]) ^ soc_crc32_inserter_data1[0]) ^ soc_crc32_inserter_last[30]) ^ soc_crc32_inserter_data1[1]) ^ soc_crc32_inserter_last[26]) ^ soc_crc32_inserter_data1[5]);
-	soc_crc32_inserter_next[19] <= ((((soc_crc32_inserter_last[11] ^ soc_crc32_inserter_last[31]) ^ soc_crc32_inserter_data1[0]) ^ soc_crc32_inserter_last[27]) ^ soc_crc32_inserter_data1[4]);
-	soc_crc32_inserter_next[20] <= ((soc_crc32_inserter_last[12] ^ soc_crc32_inserter_last[28]) ^ soc_crc32_inserter_data1[3]);
-	soc_crc32_inserter_next[21] <= ((soc_crc32_inserter_last[13] ^ soc_crc32_inserter_last[29]) ^ soc_crc32_inserter_data1[2]);
-	soc_crc32_inserter_next[22] <= ((soc_crc32_inserter_last[14] ^ soc_crc32_inserter_last[24]) ^ soc_crc32_inserter_data1[7]);
-	soc_crc32_inserter_next[23] <= ((((((soc_crc32_inserter_last[15] ^ soc_crc32_inserter_last[25]) ^ soc_crc32_inserter_data1[6]) ^ soc_crc32_inserter_last[24]) ^ soc_crc32_inserter_last[30]) ^ soc_crc32_inserter_data1[1]) ^ soc_crc32_inserter_data1[7]);
-	soc_crc32_inserter_next[24] <= ((((((soc_crc32_inserter_last[16] ^ soc_crc32_inserter_last[26]) ^ soc_crc32_inserter_data1[5]) ^ soc_crc32_inserter_last[25]) ^ soc_crc32_inserter_last[31]) ^ soc_crc32_inserter_data1[0]) ^ soc_crc32_inserter_data1[6]);
-	soc_crc32_inserter_next[25] <= ((((soc_crc32_inserter_last[17] ^ soc_crc32_inserter_last[27]) ^ soc_crc32_inserter_data1[4]) ^ soc_crc32_inserter_last[26]) ^ soc_crc32_inserter_data1[5]);
-	soc_crc32_inserter_next[26] <= ((((((((soc_crc32_inserter_last[18] ^ soc_crc32_inserter_last[28]) ^ soc_crc32_inserter_data1[3]) ^ soc_crc32_inserter_last[27]) ^ soc_crc32_inserter_data1[4]) ^ soc_crc32_inserter_last[24]) ^ soc_crc32_inserter_last[30]) ^ soc_crc32_inserter_data1[1]) ^ soc_crc32_inserter_data1[7]);
-	soc_crc32_inserter_next[27] <= ((((((((soc_crc32_inserter_last[19] ^ soc_crc32_inserter_last[29]) ^ soc_crc32_inserter_data1[2]) ^ soc_crc32_inserter_last[28]) ^ soc_crc32_inserter_data1[3]) ^ soc_crc32_inserter_last[25]) ^ soc_crc32_inserter_last[31]) ^ soc_crc32_inserter_data1[0]) ^ soc_crc32_inserter_data1[6]);
-	soc_crc32_inserter_next[28] <= ((((((soc_crc32_inserter_last[20] ^ soc_crc32_inserter_last[30]) ^ soc_crc32_inserter_data1[1]) ^ soc_crc32_inserter_last[29]) ^ soc_crc32_inserter_data1[2]) ^ soc_crc32_inserter_last[26]) ^ soc_crc32_inserter_data1[5]);
-	soc_crc32_inserter_next[29] <= ((((((soc_crc32_inserter_last[21] ^ soc_crc32_inserter_last[31]) ^ soc_crc32_inserter_data1[0]) ^ soc_crc32_inserter_last[30]) ^ soc_crc32_inserter_data1[1]) ^ soc_crc32_inserter_last[27]) ^ soc_crc32_inserter_data1[4]);
-	soc_crc32_inserter_next[30] <= ((((soc_crc32_inserter_last[22] ^ soc_crc32_inserter_last[31]) ^ soc_crc32_inserter_data1[0]) ^ soc_crc32_inserter_last[28]) ^ soc_crc32_inserter_data1[3]);
-	soc_crc32_inserter_next[31] <= ((soc_crc32_inserter_last[23] ^ soc_crc32_inserter_last[29]) ^ soc_crc32_inserter_data1[2]);
-end
-always @(*) begin
-	soc_crc32_inserter_source_first <= 1'd0;
-	soc_crc32_inserter_source_last <= 1'd0;
-	soc_crc32_inserter_source_payload_data <= 8'd0;
-	soc_crc32_inserter_source_payload_last_be <= 1'd0;
-	soc_crc32_inserter_source_payload_error <= 1'd0;
-	soc_crc32_inserter_data0 <= 8'd0;
-	vns_liteethmaccrc32inserter_next_state <= 2'd0;
-	soc_crc32_inserter_is_ongoing0 <= 1'd0;
-	soc_crc32_inserter_sink_ready <= 1'd0;
-	soc_crc32_inserter_is_ongoing1 <= 1'd0;
-	soc_crc32_inserter_ce <= 1'd0;
-	soc_crc32_inserter_reset <= 1'd0;
-	soc_crc32_inserter_source_valid <= 1'd0;
-	vns_liteethmaccrc32inserter_next_state <= vns_liteethmaccrc32inserter_state;
-	case (vns_liteethmaccrc32inserter_state)
-		1'd1: begin
-			soc_crc32_inserter_ce <= (soc_crc32_inserter_sink_valid & soc_crc32_inserter_source_ready);
-			soc_crc32_inserter_data0 <= soc_crc32_inserter_sink_payload_data;
-			soc_crc32_inserter_source_valid <= soc_crc32_inserter_sink_valid;
-			soc_crc32_inserter_sink_ready <= soc_crc32_inserter_source_ready;
-			soc_crc32_inserter_source_first <= soc_crc32_inserter_sink_first;
-			soc_crc32_inserter_source_last <= soc_crc32_inserter_sink_last;
-			soc_crc32_inserter_source_payload_data <= soc_crc32_inserter_sink_payload_data;
-			soc_crc32_inserter_source_payload_last_be <= soc_crc32_inserter_sink_payload_last_be;
-			soc_crc32_inserter_source_payload_error <= soc_crc32_inserter_sink_payload_error;
-			soc_crc32_inserter_source_last <= 1'd0;
-			if (((soc_crc32_inserter_sink_valid & soc_crc32_inserter_sink_last) & soc_crc32_inserter_source_ready)) begin
-				vns_liteethmaccrc32inserter_next_state <= 2'd2;
-			end
-		end
-		2'd2: begin
-			soc_crc32_inserter_source_valid <= 1'd1;
-			case (soc_crc32_inserter_cnt)
-				1'd0: begin
-					soc_crc32_inserter_source_payload_data <= soc_crc32_inserter_value[31:24];
-				end
-				1'd1: begin
-					soc_crc32_inserter_source_payload_data <= soc_crc32_inserter_value[23:16];
-				end
-				2'd2: begin
-					soc_crc32_inserter_source_payload_data <= soc_crc32_inserter_value[15:8];
-				end
-				default: begin
-					soc_crc32_inserter_source_payload_data <= soc_crc32_inserter_value[7:0];
-				end
-			endcase
-			if (soc_crc32_inserter_cnt_done) begin
-				soc_crc32_inserter_source_last <= 1'd1;
-				if (soc_crc32_inserter_source_ready) begin
-					vns_liteethmaccrc32inserter_next_state <= 1'd0;
-				end
-			end
-			soc_crc32_inserter_is_ongoing1 <= 1'd1;
-		end
-		default: begin
-			soc_crc32_inserter_reset <= 1'd1;
-			soc_crc32_inserter_sink_ready <= 1'd1;
-			if (soc_crc32_inserter_sink_valid) begin
-				soc_crc32_inserter_sink_ready <= 1'd0;
-				vns_liteethmaccrc32inserter_next_state <= 1'd1;
-			end
-			soc_crc32_inserter_is_ongoing0 <= 1'd1;
-		end
-	endcase
-end
-assign soc_crc32_checker_fifo_full = (soc_crc32_checker_syncfifo_level == 3'd4);
-assign soc_crc32_checker_fifo_in = (soc_crc32_checker_sink_sink_valid & ((~soc_crc32_checker_fifo_full) | soc_crc32_checker_fifo_out));
-assign soc_crc32_checker_fifo_out = (soc_crc32_checker_source_source_valid & soc_crc32_checker_source_source_ready);
-assign soc_crc32_checker_syncfifo_sink_first = soc_crc32_checker_sink_sink_first;
-assign soc_crc32_checker_syncfifo_sink_last = soc_crc32_checker_sink_sink_last;
-assign soc_crc32_checker_syncfifo_sink_payload_data = soc_crc32_checker_sink_sink_payload_data;
-assign soc_crc32_checker_syncfifo_sink_payload_last_be = soc_crc32_checker_sink_sink_payload_last_be;
-assign soc_crc32_checker_syncfifo_sink_payload_error = soc_crc32_checker_sink_sink_payload_error;
-always @(*) begin
-	soc_crc32_checker_syncfifo_sink_valid <= 1'd0;
-	soc_crc32_checker_syncfifo_sink_valid <= soc_crc32_checker_sink_sink_valid;
-	soc_crc32_checker_syncfifo_sink_valid <= soc_crc32_checker_fifo_in;
-end
-always @(*) begin
-	soc_crc32_checker_sink_sink_ready <= 1'd0;
-	soc_crc32_checker_sink_sink_ready <= soc_crc32_checker_syncfifo_sink_ready;
-	soc_crc32_checker_sink_sink_ready <= soc_crc32_checker_fifo_in;
-end
-assign soc_crc32_checker_source_source_valid = (soc_crc32_checker_sink_sink_valid & soc_crc32_checker_fifo_full);
-assign soc_crc32_checker_source_source_last = soc_crc32_checker_sink_sink_last;
-assign soc_crc32_checker_syncfifo_source_ready = soc_crc32_checker_fifo_out;
-assign soc_crc32_checker_source_source_payload_data = soc_crc32_checker_syncfifo_source_payload_data;
-assign soc_crc32_checker_source_source_payload_last_be = soc_crc32_checker_syncfifo_source_payload_last_be;
-always @(*) begin
-	soc_crc32_checker_source_source_payload_error <= 1'd0;
-	soc_crc32_checker_source_source_payload_error <= soc_crc32_checker_syncfifo_source_payload_error;
-	soc_crc32_checker_source_source_payload_error <= (soc_crc32_checker_sink_sink_payload_error | soc_crc32_checker_crc_error);
-end
-assign soc_crc32_checker_error = ((soc_crc32_checker_source_source_valid & soc_crc32_checker_source_source_last) & soc_crc32_checker_crc_error);
-assign soc_crc32_checker_crc_data0 = soc_crc32_checker_sink_sink_payload_data;
-assign soc_crc32_checker_crc_data1 = soc_crc32_checker_crc_data0;
-assign soc_crc32_checker_crc_last = soc_crc32_checker_crc_reg;
-assign soc_crc32_checker_crc_value = (~{soc_crc32_checker_crc_reg[0], soc_crc32_checker_crc_reg[1], soc_crc32_checker_crc_reg[2], soc_crc32_checker_crc_reg[3], soc_crc32_checker_crc_reg[4], soc_crc32_checker_crc_reg[5], soc_crc32_checker_crc_reg[6], soc_crc32_checker_crc_reg[7], soc_crc32_checker_crc_reg[8], soc_crc32_checker_crc_reg[9], soc_crc32_checker_crc_reg[10], soc_crc32_checker_crc_reg[11], soc_crc32_checker_crc_reg[12], soc_crc32_checker_crc_reg[13], soc_crc32_checker_crc_reg[14], soc_crc32_checker_crc_reg[15], soc_crc32_checker_crc_reg[16], soc_crc32_checker_crc_reg[17], soc_crc32_checker_crc_reg[18], soc_crc32_checker_crc_reg[19], soc_crc32_checker_crc_reg[20], soc_crc32_checker_crc_reg[21], soc_crc32_checker_crc_reg[22], soc_crc32_checker_crc_reg[23], soc_crc32_checker_crc_reg[24], soc_crc32_checker_crc_reg[25], soc_crc32_checker_crc_reg[26], soc_crc32_checker_crc_reg[27], soc_crc32_checker_crc_reg[28], soc_crc32_checker_crc_reg[29], soc_crc32_checker_crc_reg[30], soc_crc32_checker_crc_reg[31]});
-assign soc_crc32_checker_crc_error = (soc_crc32_checker_crc_next != 32'd3338984827);
-always @(*) begin
-	soc_crc32_checker_crc_next <= 32'd0;
-	soc_crc32_checker_crc_next[0] <= (((soc_crc32_checker_crc_last[24] ^ soc_crc32_checker_crc_last[30]) ^ soc_crc32_checker_crc_data1[1]) ^ soc_crc32_checker_crc_data1[7]);
-	soc_crc32_checker_crc_next[1] <= (((((((soc_crc32_checker_crc_last[25] ^ soc_crc32_checker_crc_last[31]) ^ soc_crc32_checker_crc_data1[0]) ^ soc_crc32_checker_crc_data1[6]) ^ soc_crc32_checker_crc_last[24]) ^ soc_crc32_checker_crc_last[30]) ^ soc_crc32_checker_crc_data1[1]) ^ soc_crc32_checker_crc_data1[7]);
-	soc_crc32_checker_crc_next[2] <= (((((((((soc_crc32_checker_crc_last[26] ^ soc_crc32_checker_crc_data1[5]) ^ soc_crc32_checker_crc_last[25]) ^ soc_crc32_checker_crc_last[31]) ^ soc_crc32_checker_crc_data1[0]) ^ soc_crc32_checker_crc_data1[6]) ^ soc_crc32_checker_crc_last[24]) ^ soc_crc32_checker_crc_last[30]) ^ soc_crc32_checker_crc_data1[1]) ^ soc_crc32_checker_crc_data1[7]);
-	soc_crc32_checker_crc_next[3] <= (((((((soc_crc32_checker_crc_last[27] ^ soc_crc32_checker_crc_data1[4]) ^ soc_crc32_checker_crc_last[26]) ^ soc_crc32_checker_crc_data1[5]) ^ soc_crc32_checker_crc_last[25]) ^ soc_crc32_checker_crc_last[31]) ^ soc_crc32_checker_crc_data1[0]) ^ soc_crc32_checker_crc_data1[6]);
-	soc_crc32_checker_crc_next[4] <= (((((((((soc_crc32_checker_crc_last[28] ^ soc_crc32_checker_crc_data1[3]) ^ soc_crc32_checker_crc_last[27]) ^ soc_crc32_checker_crc_data1[4]) ^ soc_crc32_checker_crc_last[26]) ^ soc_crc32_checker_crc_data1[5]) ^ soc_crc32_checker_crc_last[24]) ^ soc_crc32_checker_crc_last[30]) ^ soc_crc32_checker_crc_data1[1]) ^ soc_crc32_checker_crc_data1[7]);
-	soc_crc32_checker_crc_next[5] <= (((((((((((((soc_crc32_checker_crc_last[29] ^ soc_crc32_checker_crc_data1[2]) ^ soc_crc32_checker_crc_last[28]) ^ soc_crc32_checker_crc_data1[3]) ^ soc_crc32_checker_crc_last[27]) ^ soc_crc32_checker_crc_data1[4]) ^ soc_crc32_checker_crc_last[25]) ^ soc_crc32_checker_crc_last[31]) ^ soc_crc32_checker_crc_data1[0]) ^ soc_crc32_checker_crc_data1[6]) ^ soc_crc32_checker_crc_last[24]) ^ soc_crc32_checker_crc_last[30]) ^ soc_crc32_checker_crc_data1[1]) ^ soc_crc32_checker_crc_data1[7]);
-	soc_crc32_checker_crc_next[6] <= (((((((((((soc_crc32_checker_crc_last[30] ^ soc_crc32_checker_crc_data1[1]) ^ soc_crc32_checker_crc_last[29]) ^ soc_crc32_checker_crc_data1[2]) ^ soc_crc32_checker_crc_last[28]) ^ soc_crc32_checker_crc_data1[3]) ^ soc_crc32_checker_crc_last[26]) ^ soc_crc32_checker_crc_data1[5]) ^ soc_crc32_checker_crc_last[25]) ^ soc_crc32_checker_crc_last[31]) ^ soc_crc32_checker_crc_data1[0]) ^ soc_crc32_checker_crc_data1[6]);
-	soc_crc32_checker_crc_next[7] <= (((((((((soc_crc32_checker_crc_last[31] ^ soc_crc32_checker_crc_data1[0]) ^ soc_crc32_checker_crc_last[29]) ^ soc_crc32_checker_crc_data1[2]) ^ soc_crc32_checker_crc_last[27]) ^ soc_crc32_checker_crc_data1[4]) ^ soc_crc32_checker_crc_last[26]) ^ soc_crc32_checker_crc_data1[5]) ^ soc_crc32_checker_crc_last[24]) ^ soc_crc32_checker_crc_data1[7]);
-	soc_crc32_checker_crc_next[8] <= ((((((((soc_crc32_checker_crc_last[0] ^ soc_crc32_checker_crc_last[28]) ^ soc_crc32_checker_crc_data1[3]) ^ soc_crc32_checker_crc_last[27]) ^ soc_crc32_checker_crc_data1[4]) ^ soc_crc32_checker_crc_last[25]) ^ soc_crc32_checker_crc_data1[6]) ^ soc_crc32_checker_crc_last[24]) ^ soc_crc32_checker_crc_data1[7]);
-	soc_crc32_checker_crc_next[9] <= ((((((((soc_crc32_checker_crc_last[1] ^ soc_crc32_checker_crc_last[29]) ^ soc_crc32_checker_crc_data1[2]) ^ soc_crc32_checker_crc_last[28]) ^ soc_crc32_checker_crc_data1[3]) ^ soc_crc32_checker_crc_last[26]) ^ soc_crc32_checker_crc_data1[5]) ^ soc_crc32_checker_crc_last[25]) ^ soc_crc32_checker_crc_data1[6]);
-	soc_crc32_checker_crc_next[10] <= ((((((((soc_crc32_checker_crc_last[2] ^ soc_crc32_checker_crc_last[29]) ^ soc_crc32_checker_crc_data1[2]) ^ soc_crc32_checker_crc_last[27]) ^ soc_crc32_checker_crc_data1[4]) ^ soc_crc32_checker_crc_last[26]) ^ soc_crc32_checker_crc_data1[5]) ^ soc_crc32_checker_crc_last[24]) ^ soc_crc32_checker_crc_data1[7]);
-	soc_crc32_checker_crc_next[11] <= ((((((((soc_crc32_checker_crc_last[3] ^ soc_crc32_checker_crc_last[28]) ^ soc_crc32_checker_crc_data1[3]) ^ soc_crc32_checker_crc_last[27]) ^ soc_crc32_checker_crc_data1[4]) ^ soc_crc32_checker_crc_last[25]) ^ soc_crc32_checker_crc_data1[6]) ^ soc_crc32_checker_crc_last[24]) ^ soc_crc32_checker_crc_data1[7]);
-	soc_crc32_checker_crc_next[12] <= ((((((((((((soc_crc32_checker_crc_last[4] ^ soc_crc32_checker_crc_last[29]) ^ soc_crc32_checker_crc_data1[2]) ^ soc_crc32_checker_crc_last[28]) ^ soc_crc32_checker_crc_data1[3]) ^ soc_crc32_checker_crc_last[26]) ^ soc_crc32_checker_crc_data1[5]) ^ soc_crc32_checker_crc_last[25]) ^ soc_crc32_checker_crc_data1[6]) ^ soc_crc32_checker_crc_last[24]) ^ soc_crc32_checker_crc_last[30]) ^ soc_crc32_checker_crc_data1[1]) ^ soc_crc32_checker_crc_data1[7]);
-	soc_crc32_checker_crc_next[13] <= ((((((((((((soc_crc32_checker_crc_last[5] ^ soc_crc32_checker_crc_last[30]) ^ soc_crc32_checker_crc_data1[1]) ^ soc_crc32_checker_crc_last[29]) ^ soc_crc32_checker_crc_data1[2]) ^ soc_crc32_checker_crc_last[27]) ^ soc_crc32_checker_crc_data1[4]) ^ soc_crc32_checker_crc_last[26]) ^ soc_crc32_checker_crc_data1[5]) ^ soc_crc32_checker_crc_last[25]) ^ soc_crc32_checker_crc_last[31]) ^ soc_crc32_checker_crc_data1[0]) ^ soc_crc32_checker_crc_data1[6]);
-	soc_crc32_checker_crc_next[14] <= ((((((((((soc_crc32_checker_crc_last[6] ^ soc_crc32_checker_crc_last[31]) ^ soc_crc32_checker_crc_data1[0]) ^ soc_crc32_checker_crc_last[30]) ^ soc_crc32_checker_crc_data1[1]) ^ soc_crc32_checker_crc_last[28]) ^ soc_crc32_checker_crc_data1[3]) ^ soc_crc32_checker_crc_last[27]) ^ soc_crc32_checker_crc_data1[4]) ^ soc_crc32_checker_crc_last[26]) ^ soc_crc32_checker_crc_data1[5]);
-	soc_crc32_checker_crc_next[15] <= ((((((((soc_crc32_checker_crc_last[7] ^ soc_crc32_checker_crc_last[31]) ^ soc_crc32_checker_crc_data1[0]) ^ soc_crc32_checker_crc_last[29]) ^ soc_crc32_checker_crc_data1[2]) ^ soc_crc32_checker_crc_last[28]) ^ soc_crc32_checker_crc_data1[3]) ^ soc_crc32_checker_crc_last[27]) ^ soc_crc32_checker_crc_data1[4]);
-	soc_crc32_checker_crc_next[16] <= ((((((soc_crc32_checker_crc_last[8] ^ soc_crc32_checker_crc_last[29]) ^ soc_crc32_checker_crc_data1[2]) ^ soc_crc32_checker_crc_last[28]) ^ soc_crc32_checker_crc_data1[3]) ^ soc_crc32_checker_crc_last[24]) ^ soc_crc32_checker_crc_data1[7]);
-	soc_crc32_checker_crc_next[17] <= ((((((soc_crc32_checker_crc_last[9] ^ soc_crc32_checker_crc_last[30]) ^ soc_crc32_checker_crc_data1[1]) ^ soc_crc32_checker_crc_last[29]) ^ soc_crc32_checker_crc_data1[2]) ^ soc_crc32_checker_crc_last[25]) ^ soc_crc32_checker_crc_data1[6]);
-	soc_crc32_checker_crc_next[18] <= ((((((soc_crc32_checker_crc_last[10] ^ soc_crc32_checker_crc_last[31]) ^ soc_crc32_checker_crc_data1[0]) ^ soc_crc32_checker_crc_last[30]) ^ soc_crc32_checker_crc_data1[1]) ^ soc_crc32_checker_crc_last[26]) ^ soc_crc32_checker_crc_data1[5]);
-	soc_crc32_checker_crc_next[19] <= ((((soc_crc32_checker_crc_last[11] ^ soc_crc32_checker_crc_last[31]) ^ soc_crc32_checker_crc_data1[0]) ^ soc_crc32_checker_crc_last[27]) ^ soc_crc32_checker_crc_data1[4]);
-	soc_crc32_checker_crc_next[20] <= ((soc_crc32_checker_crc_last[12] ^ soc_crc32_checker_crc_last[28]) ^ soc_crc32_checker_crc_data1[3]);
-	soc_crc32_checker_crc_next[21] <= ((soc_crc32_checker_crc_last[13] ^ soc_crc32_checker_crc_last[29]) ^ soc_crc32_checker_crc_data1[2]);
-	soc_crc32_checker_crc_next[22] <= ((soc_crc32_checker_crc_last[14] ^ soc_crc32_checker_crc_last[24]) ^ soc_crc32_checker_crc_data1[7]);
-	soc_crc32_checker_crc_next[23] <= ((((((soc_crc32_checker_crc_last[15] ^ soc_crc32_checker_crc_last[25]) ^ soc_crc32_checker_crc_data1[6]) ^ soc_crc32_checker_crc_last[24]) ^ soc_crc32_checker_crc_last[30]) ^ soc_crc32_checker_crc_data1[1]) ^ soc_crc32_checker_crc_data1[7]);
-	soc_crc32_checker_crc_next[24] <= ((((((soc_crc32_checker_crc_last[16] ^ soc_crc32_checker_crc_last[26]) ^ soc_crc32_checker_crc_data1[5]) ^ soc_crc32_checker_crc_last[25]) ^ soc_crc32_checker_crc_last[31]) ^ soc_crc32_checker_crc_data1[0]) ^ soc_crc32_checker_crc_data1[6]);
-	soc_crc32_checker_crc_next[25] <= ((((soc_crc32_checker_crc_last[17] ^ soc_crc32_checker_crc_last[27]) ^ soc_crc32_checker_crc_data1[4]) ^ soc_crc32_checker_crc_last[26]) ^ soc_crc32_checker_crc_data1[5]);
-	soc_crc32_checker_crc_next[26] <= ((((((((soc_crc32_checker_crc_last[18] ^ soc_crc32_checker_crc_last[28]) ^ soc_crc32_checker_crc_data1[3]) ^ soc_crc32_checker_crc_last[27]) ^ soc_crc32_checker_crc_data1[4]) ^ soc_crc32_checker_crc_last[24]) ^ soc_crc32_checker_crc_last[30]) ^ soc_crc32_checker_crc_data1[1]) ^ soc_crc32_checker_crc_data1[7]);
-	soc_crc32_checker_crc_next[27] <= ((((((((soc_crc32_checker_crc_last[19] ^ soc_crc32_checker_crc_last[29]) ^ soc_crc32_checker_crc_data1[2]) ^ soc_crc32_checker_crc_last[28]) ^ soc_crc32_checker_crc_data1[3]) ^ soc_crc32_checker_crc_last[25]) ^ soc_crc32_checker_crc_last[31]) ^ soc_crc32_checker_crc_data1[0]) ^ soc_crc32_checker_crc_data1[6]);
-	soc_crc32_checker_crc_next[28] <= ((((((soc_crc32_checker_crc_last[20] ^ soc_crc32_checker_crc_last[30]) ^ soc_crc32_checker_crc_data1[1]) ^ soc_crc32_checker_crc_last[29]) ^ soc_crc32_checker_crc_data1[2]) ^ soc_crc32_checker_crc_last[26]) ^ soc_crc32_checker_crc_data1[5]);
-	soc_crc32_checker_crc_next[29] <= ((((((soc_crc32_checker_crc_last[21] ^ soc_crc32_checker_crc_last[31]) ^ soc_crc32_checker_crc_data1[0]) ^ soc_crc32_checker_crc_last[30]) ^ soc_crc32_checker_crc_data1[1]) ^ soc_crc32_checker_crc_last[27]) ^ soc_crc32_checker_crc_data1[4]);
-	soc_crc32_checker_crc_next[30] <= ((((soc_crc32_checker_crc_last[22] ^ soc_crc32_checker_crc_last[31]) ^ soc_crc32_checker_crc_data1[0]) ^ soc_crc32_checker_crc_last[28]) ^ soc_crc32_checker_crc_data1[3]);
-	soc_crc32_checker_crc_next[31] <= ((soc_crc32_checker_crc_last[23] ^ soc_crc32_checker_crc_last[29]) ^ soc_crc32_checker_crc_data1[2]);
-end
-assign soc_crc32_checker_syncfifo_syncfifo_din = {soc_crc32_checker_syncfifo_fifo_in_last, soc_crc32_checker_syncfifo_fifo_in_first, soc_crc32_checker_syncfifo_fifo_in_payload_error, soc_crc32_checker_syncfifo_fifo_in_payload_last_be, soc_crc32_checker_syncfifo_fifo_in_payload_data};
-assign {soc_crc32_checker_syncfifo_fifo_out_last, soc_crc32_checker_syncfifo_fifo_out_first, soc_crc32_checker_syncfifo_fifo_out_payload_error, soc_crc32_checker_syncfifo_fifo_out_payload_last_be, soc_crc32_checker_syncfifo_fifo_out_payload_data} = soc_crc32_checker_syncfifo_syncfifo_dout;
-assign soc_crc32_checker_syncfifo_sink_ready = soc_crc32_checker_syncfifo_syncfifo_writable;
-assign soc_crc32_checker_syncfifo_syncfifo_we = soc_crc32_checker_syncfifo_sink_valid;
-assign soc_crc32_checker_syncfifo_fifo_in_first = soc_crc32_checker_syncfifo_sink_first;
-assign soc_crc32_checker_syncfifo_fifo_in_last = soc_crc32_checker_syncfifo_sink_last;
-assign soc_crc32_checker_syncfifo_fifo_in_payload_data = soc_crc32_checker_syncfifo_sink_payload_data;
-assign soc_crc32_checker_syncfifo_fifo_in_payload_last_be = soc_crc32_checker_syncfifo_sink_payload_last_be;
-assign soc_crc32_checker_syncfifo_fifo_in_payload_error = soc_crc32_checker_syncfifo_sink_payload_error;
-assign soc_crc32_checker_syncfifo_source_valid = soc_crc32_checker_syncfifo_syncfifo_readable;
-assign soc_crc32_checker_syncfifo_source_first = soc_crc32_checker_syncfifo_fifo_out_first;
-assign soc_crc32_checker_syncfifo_source_last = soc_crc32_checker_syncfifo_fifo_out_last;
-assign soc_crc32_checker_syncfifo_source_payload_data = soc_crc32_checker_syncfifo_fifo_out_payload_data;
-assign soc_crc32_checker_syncfifo_source_payload_last_be = soc_crc32_checker_syncfifo_fifo_out_payload_last_be;
-assign soc_crc32_checker_syncfifo_source_payload_error = soc_crc32_checker_syncfifo_fifo_out_payload_error;
-assign soc_crc32_checker_syncfifo_syncfifo_re = soc_crc32_checker_syncfifo_source_ready;
-always @(*) begin
-	soc_crc32_checker_syncfifo_wrport_adr <= 3'd0;
-	if (soc_crc32_checker_syncfifo_replace) begin
-		soc_crc32_checker_syncfifo_wrport_adr <= (soc_crc32_checker_syncfifo_produce - 1'd1);
-	end else begin
-		soc_crc32_checker_syncfifo_wrport_adr <= soc_crc32_checker_syncfifo_produce;
-	end
-end
-assign soc_crc32_checker_syncfifo_wrport_dat_w = soc_crc32_checker_syncfifo_syncfifo_din;
-assign soc_crc32_checker_syncfifo_wrport_we = (soc_crc32_checker_syncfifo_syncfifo_we & (soc_crc32_checker_syncfifo_syncfifo_writable | soc_crc32_checker_syncfifo_replace));
-assign soc_crc32_checker_syncfifo_do_read = (soc_crc32_checker_syncfifo_syncfifo_readable & soc_crc32_checker_syncfifo_syncfifo_re);
-assign soc_crc32_checker_syncfifo_rdport_adr = soc_crc32_checker_syncfifo_consume;
-assign soc_crc32_checker_syncfifo_syncfifo_dout = soc_crc32_checker_syncfifo_rdport_dat_r;
-assign soc_crc32_checker_syncfifo_syncfifo_writable = (soc_crc32_checker_syncfifo_level != 3'd5);
-assign soc_crc32_checker_syncfifo_syncfifo_readable = (soc_crc32_checker_syncfifo_level != 1'd0);
-always @(*) begin
-	soc_crc32_checker_crc_ce <= 1'd0;
-	vns_liteethmaccrc32checker_next_state <= 2'd0;
-	soc_crc32_checker_crc_reset <= 1'd0;
-	soc_crc32_checker_fifo_reset <= 1'd0;
-	vns_liteethmaccrc32checker_next_state <= vns_liteethmaccrc32checker_state;
-	case (vns_liteethmaccrc32checker_state)
-		1'd1: begin
-			if ((soc_crc32_checker_sink_sink_valid & soc_crc32_checker_sink_sink_ready)) begin
-				soc_crc32_checker_crc_ce <= 1'd1;
-				vns_liteethmaccrc32checker_next_state <= 2'd2;
-			end
-		end
-		2'd2: begin
-			if ((soc_crc32_checker_sink_sink_valid & soc_crc32_checker_sink_sink_ready)) begin
-				soc_crc32_checker_crc_ce <= 1'd1;
-				if (soc_crc32_checker_sink_sink_last) begin
-					vns_liteethmaccrc32checker_next_state <= 1'd0;
-				end
-			end
-		end
-		default: begin
-			soc_crc32_checker_crc_reset <= 1'd1;
-			soc_crc32_checker_fifo_reset <= 1'd1;
-			vns_liteethmaccrc32checker_next_state <= 1'd1;
-		end
-	endcase
-end
-assign soc_ps_preamble_error_o = (soc_ps_preamble_error_toggle_o ^ soc_ps_preamble_error_toggle_o_r);
-assign soc_ps_crc_error_o = (soc_ps_crc_error_toggle_o ^ soc_ps_crc_error_toggle_o_r);
-assign soc_padding_inserter_counter_done = (soc_padding_inserter_counter >= 6'd59);
-always @(*) begin
-	soc_padding_inserter_source_valid <= 1'd0;
-	soc_padding_inserter_source_first <= 1'd0;
-	soc_padding_inserter_source_last <= 1'd0;
-	soc_padding_inserter_source_payload_data <= 8'd0;
-	soc_padding_inserter_source_payload_last_be <= 1'd0;
-	soc_padding_inserter_source_payload_error <= 1'd0;
-	vns_liteethmacpaddinginserter_next_state <= 1'd0;
-	soc_padding_inserter_counter_reset <= 1'd0;
-	soc_padding_inserter_sink_ready <= 1'd0;
-	soc_padding_inserter_counter_ce <= 1'd0;
-	vns_liteethmacpaddinginserter_next_state <= vns_liteethmacpaddinginserter_state;
-	case (vns_liteethmacpaddinginserter_state)
-		1'd1: begin
-			soc_padding_inserter_source_valid <= 1'd1;
-			soc_padding_inserter_source_last <= soc_padding_inserter_counter_done;
-			soc_padding_inserter_source_payload_data <= 1'd0;
-			if ((soc_padding_inserter_source_valid & soc_padding_inserter_source_ready)) begin
-				soc_padding_inserter_counter_ce <= 1'd1;
-				if (soc_padding_inserter_counter_done) begin
-					soc_padding_inserter_counter_reset <= 1'd1;
-					vns_liteethmacpaddinginserter_next_state <= 1'd0;
-				end
-			end
-		end
-		default: begin
-			soc_padding_inserter_source_valid <= soc_padding_inserter_sink_valid;
-			soc_padding_inserter_sink_ready <= soc_padding_inserter_source_ready;
-			soc_padding_inserter_source_first <= soc_padding_inserter_sink_first;
-			soc_padding_inserter_source_last <= soc_padding_inserter_sink_last;
-			soc_padding_inserter_source_payload_data <= soc_padding_inserter_sink_payload_data;
-			soc_padding_inserter_source_payload_last_be <= soc_padding_inserter_sink_payload_last_be;
-			soc_padding_inserter_source_payload_error <= soc_padding_inserter_sink_payload_error;
-			if ((soc_padding_inserter_source_valid & soc_padding_inserter_source_ready)) begin
-				soc_padding_inserter_counter_ce <= 1'd1;
-				if (soc_padding_inserter_sink_last) begin
-					if ((~soc_padding_inserter_counter_done)) begin
-						soc_padding_inserter_source_last <= 1'd0;
-						vns_liteethmacpaddinginserter_next_state <= 1'd1;
-					end else begin
-						soc_padding_inserter_counter_reset <= 1'd1;
-					end
-				end
-			end
-		end
-	endcase
-end
-assign soc_padding_checker_source_valid = soc_padding_checker_sink_valid;
-assign soc_padding_checker_sink_ready = soc_padding_checker_source_ready;
-assign soc_padding_checker_source_first = soc_padding_checker_sink_first;
-assign soc_padding_checker_source_last = soc_padding_checker_sink_last;
-assign soc_padding_checker_source_payload_data = soc_padding_checker_sink_payload_data;
-assign soc_padding_checker_source_payload_last_be = soc_padding_checker_sink_payload_last_be;
-assign soc_padding_checker_source_payload_error = soc_padding_checker_sink_payload_error;
-assign soc_tx_last_be_source_valid = (soc_tx_last_be_sink_valid & soc_tx_last_be_ongoing);
-assign soc_tx_last_be_source_last = soc_tx_last_be_sink_payload_last_be;
-assign soc_tx_last_be_source_payload_data = soc_tx_last_be_sink_payload_data;
-assign soc_tx_last_be_sink_ready = soc_tx_last_be_source_ready;
-assign soc_rx_last_be_source_valid = soc_rx_last_be_sink_valid;
-assign soc_rx_last_be_sink_ready = soc_rx_last_be_source_ready;
-assign soc_rx_last_be_source_first = soc_rx_last_be_sink_first;
-assign soc_rx_last_be_source_last = soc_rx_last_be_sink_last;
-assign soc_rx_last_be_source_payload_data = soc_rx_last_be_sink_payload_data;
-assign soc_rx_last_be_source_payload_error = soc_rx_last_be_sink_payload_error;
-always @(*) begin
-	soc_rx_last_be_source_payload_last_be <= 1'd0;
-	soc_rx_last_be_source_payload_last_be <= soc_rx_last_be_sink_payload_last_be;
-	soc_rx_last_be_source_payload_last_be <= soc_rx_last_be_sink_last;
-end
-assign soc_tx_converter_converter_sink_valid = soc_tx_converter_sink_valid;
-assign soc_tx_converter_converter_sink_first = soc_tx_converter_sink_first;
-assign soc_tx_converter_converter_sink_last = soc_tx_converter_sink_last;
-assign soc_tx_converter_sink_ready = soc_tx_converter_converter_sink_ready;
-always @(*) begin
-	soc_tx_converter_converter_sink_payload_data <= 40'd0;
-	soc_tx_converter_converter_sink_payload_data[7:0] <= soc_tx_converter_sink_payload_data[7:0];
-	soc_tx_converter_converter_sink_payload_data[8] <= soc_tx_converter_sink_payload_last_be[0];
-	soc_tx_converter_converter_sink_payload_data[9] <= soc_tx_converter_sink_payload_error[0];
-	soc_tx_converter_converter_sink_payload_data[17:10] <= soc_tx_converter_sink_payload_data[15:8];
-	soc_tx_converter_converter_sink_payload_data[18] <= soc_tx_converter_sink_payload_last_be[1];
-	soc_tx_converter_converter_sink_payload_data[19] <= soc_tx_converter_sink_payload_error[1];
-	soc_tx_converter_converter_sink_payload_data[27:20] <= soc_tx_converter_sink_payload_data[23:16];
-	soc_tx_converter_converter_sink_payload_data[28] <= soc_tx_converter_sink_payload_last_be[2];
-	soc_tx_converter_converter_sink_payload_data[29] <= soc_tx_converter_sink_payload_error[2];
-	soc_tx_converter_converter_sink_payload_data[37:30] <= soc_tx_converter_sink_payload_data[31:24];
-	soc_tx_converter_converter_sink_payload_data[38] <= soc_tx_converter_sink_payload_last_be[3];
-	soc_tx_converter_converter_sink_payload_data[39] <= soc_tx_converter_sink_payload_error[3];
-end
-assign soc_tx_converter_source_valid = soc_tx_converter_source_source_valid;
-assign soc_tx_converter_source_first = soc_tx_converter_source_source_first;
-assign soc_tx_converter_source_last = soc_tx_converter_source_source_last;
-assign soc_tx_converter_source_source_ready = soc_tx_converter_source_ready;
-assign {soc_tx_converter_source_payload_error, soc_tx_converter_source_payload_last_be, soc_tx_converter_source_payload_data} = soc_tx_converter_source_source_payload_data;
-assign soc_tx_converter_source_source_valid = soc_tx_converter_converter_source_valid;
-assign soc_tx_converter_converter_source_ready = soc_tx_converter_source_source_ready;
-assign soc_tx_converter_source_source_first = soc_tx_converter_converter_source_first;
-assign soc_tx_converter_source_source_last = soc_tx_converter_converter_source_last;
-assign soc_tx_converter_source_source_payload_data = soc_tx_converter_converter_source_payload_data;
-assign soc_tx_converter_converter_first = (soc_tx_converter_converter_mux == 1'd0);
-assign soc_tx_converter_converter_last = (soc_tx_converter_converter_mux == 2'd3);
-assign soc_tx_converter_converter_source_valid = soc_tx_converter_converter_sink_valid;
-assign soc_tx_converter_converter_source_first = (soc_tx_converter_converter_sink_first & soc_tx_converter_converter_first);
-assign soc_tx_converter_converter_source_last = (soc_tx_converter_converter_sink_last & soc_tx_converter_converter_last);
-assign soc_tx_converter_converter_sink_ready = (soc_tx_converter_converter_last & soc_tx_converter_converter_source_ready);
-always @(*) begin
-	soc_tx_converter_converter_source_payload_data <= 10'd0;
-	case (soc_tx_converter_converter_mux)
-		1'd0: begin
-			soc_tx_converter_converter_source_payload_data <= soc_tx_converter_converter_sink_payload_data[9:0];
-		end
-		1'd1: begin
-			soc_tx_converter_converter_source_payload_data <= soc_tx_converter_converter_sink_payload_data[19:10];
-		end
-		2'd2: begin
-			soc_tx_converter_converter_source_payload_data <= soc_tx_converter_converter_sink_payload_data[29:20];
-		end
-		default: begin
-			soc_tx_converter_converter_source_payload_data <= soc_tx_converter_converter_sink_payload_data[39:30];
-		end
-	endcase
-end
-assign soc_tx_converter_converter_source_payload_valid_token_count = soc_tx_converter_converter_last;
-assign soc_rx_converter_converter_sink_valid = soc_rx_converter_sink_valid;
-assign soc_rx_converter_converter_sink_first = soc_rx_converter_sink_first;
-assign soc_rx_converter_converter_sink_last = soc_rx_converter_sink_last;
-assign soc_rx_converter_sink_ready = soc_rx_converter_converter_sink_ready;
-assign soc_rx_converter_converter_sink_payload_data = {soc_rx_converter_sink_payload_error, soc_rx_converter_sink_payload_last_be, soc_rx_converter_sink_payload_data};
-assign soc_rx_converter_source_valid = soc_rx_converter_source_source_valid;
-assign soc_rx_converter_source_first = soc_rx_converter_source_source_first;
-assign soc_rx_converter_source_last = soc_rx_converter_source_source_last;
-assign soc_rx_converter_source_source_ready = soc_rx_converter_source_ready;
-always @(*) begin
-	soc_rx_converter_source_payload_data <= 32'd0;
-	soc_rx_converter_source_payload_data[7:0] <= soc_rx_converter_source_source_payload_data[7:0];
-	soc_rx_converter_source_payload_data[15:8] <= soc_rx_converter_source_source_payload_data[17:10];
-	soc_rx_converter_source_payload_data[23:16] <= soc_rx_converter_source_source_payload_data[27:20];
-	soc_rx_converter_source_payload_data[31:24] <= soc_rx_converter_source_source_payload_data[37:30];
-end
-always @(*) begin
-	soc_rx_converter_source_payload_last_be <= 4'd0;
-	soc_rx_converter_source_payload_last_be[0] <= soc_rx_converter_source_source_payload_data[8];
-	soc_rx_converter_source_payload_last_be[1] <= soc_rx_converter_source_source_payload_data[18];
-	soc_rx_converter_source_payload_last_be[2] <= soc_rx_converter_source_source_payload_data[28];
-	soc_rx_converter_source_payload_last_be[3] <= soc_rx_converter_source_source_payload_data[38];
-end
-always @(*) begin
-	soc_rx_converter_source_payload_error <= 4'd0;
-	soc_rx_converter_source_payload_error[0] <= soc_rx_converter_source_source_payload_data[9];
-	soc_rx_converter_source_payload_error[1] <= soc_rx_converter_source_source_payload_data[19];
-	soc_rx_converter_source_payload_error[2] <= soc_rx_converter_source_source_payload_data[29];
-	soc_rx_converter_source_payload_error[3] <= soc_rx_converter_source_source_payload_data[39];
-end
-assign soc_rx_converter_source_source_valid = soc_rx_converter_converter_source_valid;
-assign soc_rx_converter_converter_source_ready = soc_rx_converter_source_source_ready;
-assign soc_rx_converter_source_source_first = soc_rx_converter_converter_source_first;
-assign soc_rx_converter_source_source_last = soc_rx_converter_converter_source_last;
-assign soc_rx_converter_source_source_payload_data = soc_rx_converter_converter_source_payload_data;
-assign soc_rx_converter_converter_sink_ready = ((~soc_rx_converter_converter_strobe_all) | soc_rx_converter_converter_source_ready);
-assign soc_rx_converter_converter_source_valid = soc_rx_converter_converter_strobe_all;
-assign soc_rx_converter_converter_load_part = (soc_rx_converter_converter_sink_valid & soc_rx_converter_converter_sink_ready);
-assign soc_tx_cdc_asyncfifo_din = {soc_tx_cdc_fifo_in_last, soc_tx_cdc_fifo_in_first, soc_tx_cdc_fifo_in_payload_error, soc_tx_cdc_fifo_in_payload_last_be, soc_tx_cdc_fifo_in_payload_data};
-assign {soc_tx_cdc_fifo_out_last, soc_tx_cdc_fifo_out_first, soc_tx_cdc_fifo_out_payload_error, soc_tx_cdc_fifo_out_payload_last_be, soc_tx_cdc_fifo_out_payload_data} = soc_tx_cdc_asyncfifo_dout;
-assign soc_tx_cdc_sink_ready = soc_tx_cdc_asyncfifo_writable;
-assign soc_tx_cdc_asyncfifo_we = soc_tx_cdc_sink_valid;
-assign soc_tx_cdc_fifo_in_first = soc_tx_cdc_sink_first;
-assign soc_tx_cdc_fifo_in_last = soc_tx_cdc_sink_last;
-assign soc_tx_cdc_fifo_in_payload_data = soc_tx_cdc_sink_payload_data;
-assign soc_tx_cdc_fifo_in_payload_last_be = soc_tx_cdc_sink_payload_last_be;
-assign soc_tx_cdc_fifo_in_payload_error = soc_tx_cdc_sink_payload_error;
-assign soc_tx_cdc_source_valid = soc_tx_cdc_asyncfifo_readable;
-assign soc_tx_cdc_source_first = soc_tx_cdc_fifo_out_first;
-assign soc_tx_cdc_source_last = soc_tx_cdc_fifo_out_last;
-assign soc_tx_cdc_source_payload_data = soc_tx_cdc_fifo_out_payload_data;
-assign soc_tx_cdc_source_payload_last_be = soc_tx_cdc_fifo_out_payload_last_be;
-assign soc_tx_cdc_source_payload_error = soc_tx_cdc_fifo_out_payload_error;
-assign soc_tx_cdc_asyncfifo_re = soc_tx_cdc_source_ready;
-assign soc_tx_cdc_graycounter0_ce = (soc_tx_cdc_asyncfifo_writable & soc_tx_cdc_asyncfifo_we);
-assign soc_tx_cdc_graycounter1_ce = (soc_tx_cdc_asyncfifo_readable & soc_tx_cdc_asyncfifo_re);
-assign soc_tx_cdc_asyncfifo_writable = (((soc_tx_cdc_graycounter0_q[6] == soc_tx_cdc_consume_wdomain[6]) | (soc_tx_cdc_graycounter0_q[5] == soc_tx_cdc_consume_wdomain[5])) | (soc_tx_cdc_graycounter0_q[4:0] != soc_tx_cdc_consume_wdomain[4:0]));
-assign soc_tx_cdc_asyncfifo_readable = (soc_tx_cdc_graycounter1_q != soc_tx_cdc_produce_rdomain);
-assign soc_tx_cdc_wrport_adr = soc_tx_cdc_graycounter0_q_binary[5:0];
-assign soc_tx_cdc_wrport_dat_w = soc_tx_cdc_asyncfifo_din;
-assign soc_tx_cdc_wrport_we = soc_tx_cdc_graycounter0_ce;
-assign soc_tx_cdc_rdport_adr = soc_tx_cdc_graycounter1_q_next_binary[5:0];
-assign soc_tx_cdc_asyncfifo_dout = soc_tx_cdc_rdport_dat_r;
-always @(*) begin
-	soc_tx_cdc_graycounter0_q_next_binary <= 7'd0;
-	if (soc_tx_cdc_graycounter0_ce) begin
-		soc_tx_cdc_graycounter0_q_next_binary <= (soc_tx_cdc_graycounter0_q_binary + 1'd1);
-	end else begin
-		soc_tx_cdc_graycounter0_q_next_binary <= soc_tx_cdc_graycounter0_q_binary;
-	end
-end
-assign soc_tx_cdc_graycounter0_q_next = (soc_tx_cdc_graycounter0_q_next_binary ^ soc_tx_cdc_graycounter0_q_next_binary[6:1]);
-always @(*) begin
-	soc_tx_cdc_graycounter1_q_next_binary <= 7'd0;
-	if (soc_tx_cdc_graycounter1_ce) begin
-		soc_tx_cdc_graycounter1_q_next_binary <= (soc_tx_cdc_graycounter1_q_binary + 1'd1);
-	end else begin
-		soc_tx_cdc_graycounter1_q_next_binary <= soc_tx_cdc_graycounter1_q_binary;
-	end
-end
-assign soc_tx_cdc_graycounter1_q_next = (soc_tx_cdc_graycounter1_q_next_binary ^ soc_tx_cdc_graycounter1_q_next_binary[6:1]);
-assign soc_rx_cdc_asyncfifo_din = {soc_rx_cdc_fifo_in_last, soc_rx_cdc_fifo_in_first, soc_rx_cdc_fifo_in_payload_error, soc_rx_cdc_fifo_in_payload_last_be, soc_rx_cdc_fifo_in_payload_data};
-assign {soc_rx_cdc_fifo_out_last, soc_rx_cdc_fifo_out_first, soc_rx_cdc_fifo_out_payload_error, soc_rx_cdc_fifo_out_payload_last_be, soc_rx_cdc_fifo_out_payload_data} = soc_rx_cdc_asyncfifo_dout;
-assign soc_rx_cdc_sink_ready = soc_rx_cdc_asyncfifo_writable;
-assign soc_rx_cdc_asyncfifo_we = soc_rx_cdc_sink_valid;
-assign soc_rx_cdc_fifo_in_first = soc_rx_cdc_sink_first;
-assign soc_rx_cdc_fifo_in_last = soc_rx_cdc_sink_last;
-assign soc_rx_cdc_fifo_in_payload_data = soc_rx_cdc_sink_payload_data;
-assign soc_rx_cdc_fifo_in_payload_last_be = soc_rx_cdc_sink_payload_last_be;
-assign soc_rx_cdc_fifo_in_payload_error = soc_rx_cdc_sink_payload_error;
-assign soc_rx_cdc_source_valid = soc_rx_cdc_asyncfifo_readable;
-assign soc_rx_cdc_source_first = soc_rx_cdc_fifo_out_first;
-assign soc_rx_cdc_source_last = soc_rx_cdc_fifo_out_last;
-assign soc_rx_cdc_source_payload_data = soc_rx_cdc_fifo_out_payload_data;
-assign soc_rx_cdc_source_payload_last_be = soc_rx_cdc_fifo_out_payload_last_be;
-assign soc_rx_cdc_source_payload_error = soc_rx_cdc_fifo_out_payload_error;
-assign soc_rx_cdc_asyncfifo_re = soc_rx_cdc_source_ready;
-assign soc_rx_cdc_graycounter0_ce = (soc_rx_cdc_asyncfifo_writable & soc_rx_cdc_asyncfifo_we);
-assign soc_rx_cdc_graycounter1_ce = (soc_rx_cdc_asyncfifo_readable & soc_rx_cdc_asyncfifo_re);
-assign soc_rx_cdc_asyncfifo_writable = (((soc_rx_cdc_graycounter0_q[6] == soc_rx_cdc_consume_wdomain[6]) | (soc_rx_cdc_graycounter0_q[5] == soc_rx_cdc_consume_wdomain[5])) | (soc_rx_cdc_graycounter0_q[4:0] != soc_rx_cdc_consume_wdomain[4:0]));
-assign soc_rx_cdc_asyncfifo_readable = (soc_rx_cdc_graycounter1_q != soc_rx_cdc_produce_rdomain);
-assign soc_rx_cdc_wrport_adr = soc_rx_cdc_graycounter0_q_binary[5:0];
-assign soc_rx_cdc_wrport_dat_w = soc_rx_cdc_asyncfifo_din;
-assign soc_rx_cdc_wrport_we = soc_rx_cdc_graycounter0_ce;
-assign soc_rx_cdc_rdport_adr = soc_rx_cdc_graycounter1_q_next_binary[5:0];
-assign soc_rx_cdc_asyncfifo_dout = soc_rx_cdc_rdport_dat_r;
-always @(*) begin
-	soc_rx_cdc_graycounter0_q_next_binary <= 7'd0;
-	if (soc_rx_cdc_graycounter0_ce) begin
-		soc_rx_cdc_graycounter0_q_next_binary <= (soc_rx_cdc_graycounter0_q_binary + 1'd1);
-	end else begin
-		soc_rx_cdc_graycounter0_q_next_binary <= soc_rx_cdc_graycounter0_q_binary;
-	end
-end
-assign soc_rx_cdc_graycounter0_q_next = (soc_rx_cdc_graycounter0_q_next_binary ^ soc_rx_cdc_graycounter0_q_next_binary[6:1]);
-always @(*) begin
-	soc_rx_cdc_graycounter1_q_next_binary <= 7'd0;
-	if (soc_rx_cdc_graycounter1_ce) begin
-		soc_rx_cdc_graycounter1_q_next_binary <= (soc_rx_cdc_graycounter1_q_binary + 1'd1);
-	end else begin
-		soc_rx_cdc_graycounter1_q_next_binary <= soc_rx_cdc_graycounter1_q_binary;
-	end
-end
-assign soc_rx_cdc_graycounter1_q_next = (soc_rx_cdc_graycounter1_q_next_binary ^ soc_rx_cdc_graycounter1_q_next_binary[6:1]);
-assign soc_tx_converter_sink_valid = soc_tx_cdc_source_valid;
-assign soc_tx_cdc_source_ready = soc_tx_converter_sink_ready;
-assign soc_tx_converter_sink_first = soc_tx_cdc_source_first;
-assign soc_tx_converter_sink_last = soc_tx_cdc_source_last;
-assign soc_tx_converter_sink_payload_data = soc_tx_cdc_source_payload_data;
-assign soc_tx_converter_sink_payload_last_be = soc_tx_cdc_source_payload_last_be;
-assign soc_tx_converter_sink_payload_error = soc_tx_cdc_source_payload_error;
-assign soc_tx_last_be_sink_valid = soc_tx_converter_source_valid;
-assign soc_tx_converter_source_ready = soc_tx_last_be_sink_ready;
-assign soc_tx_last_be_sink_first = soc_tx_converter_source_first;
-assign soc_tx_last_be_sink_last = soc_tx_converter_source_last;
-assign soc_tx_last_be_sink_payload_data = soc_tx_converter_source_payload_data;
-assign soc_tx_last_be_sink_payload_last_be = soc_tx_converter_source_payload_last_be;
-assign soc_tx_last_be_sink_payload_error = soc_tx_converter_source_payload_error;
-assign soc_padding_inserter_sink_valid = soc_tx_last_be_source_valid;
-assign soc_tx_last_be_source_ready = soc_padding_inserter_sink_ready;
-assign soc_padding_inserter_sink_first = soc_tx_last_be_source_first;
-assign soc_padding_inserter_sink_last = soc_tx_last_be_source_last;
-assign soc_padding_inserter_sink_payload_data = soc_tx_last_be_source_payload_data;
-assign soc_padding_inserter_sink_payload_last_be = soc_tx_last_be_source_payload_last_be;
-assign soc_padding_inserter_sink_payload_error = soc_tx_last_be_source_payload_error;
-assign soc_crc32_inserter_sink_valid = soc_padding_inserter_source_valid;
-assign soc_padding_inserter_source_ready = soc_crc32_inserter_sink_ready;
-assign soc_crc32_inserter_sink_first = soc_padding_inserter_source_first;
-assign soc_crc32_inserter_sink_last = soc_padding_inserter_source_last;
-assign soc_crc32_inserter_sink_payload_data = soc_padding_inserter_source_payload_data;
-assign soc_crc32_inserter_sink_payload_last_be = soc_padding_inserter_source_payload_last_be;
-assign soc_crc32_inserter_sink_payload_error = soc_padding_inserter_source_payload_error;
-assign soc_preamble_inserter_sink_valid = soc_crc32_inserter_source_valid;
-assign soc_crc32_inserter_source_ready = soc_preamble_inserter_sink_ready;
-assign soc_preamble_inserter_sink_first = soc_crc32_inserter_source_first;
-assign soc_preamble_inserter_sink_last = soc_crc32_inserter_source_last;
-assign soc_preamble_inserter_sink_payload_data = soc_crc32_inserter_source_payload_data;
-assign soc_preamble_inserter_sink_payload_last_be = soc_crc32_inserter_source_payload_last_be;
-assign soc_preamble_inserter_sink_payload_error = soc_crc32_inserter_source_payload_error;
-assign soc_tx_gap_inserter_sink_valid = soc_preamble_inserter_source_valid;
-assign soc_preamble_inserter_source_ready = soc_tx_gap_inserter_sink_ready;
-assign soc_tx_gap_inserter_sink_first = soc_preamble_inserter_source_first;
-assign soc_tx_gap_inserter_sink_last = soc_preamble_inserter_source_last;
-assign soc_tx_gap_inserter_sink_payload_data = soc_preamble_inserter_source_payload_data;
-assign soc_tx_gap_inserter_sink_payload_last_be = soc_preamble_inserter_source_payload_last_be;
-assign soc_tx_gap_inserter_sink_payload_error = soc_preamble_inserter_source_payload_error;
-assign soc_liteethphymiitx_sink_sink_valid = soc_tx_gap_inserter_source_valid;
-assign soc_tx_gap_inserter_source_ready = soc_liteethphymiitx_sink_sink_ready;
-assign soc_liteethphymiitx_sink_sink_first = soc_tx_gap_inserter_source_first;
-assign soc_liteethphymiitx_sink_sink_last = soc_tx_gap_inserter_source_last;
-assign soc_liteethphymiitx_sink_sink_payload_data = soc_tx_gap_inserter_source_payload_data;
-assign soc_liteethphymiitx_sink_sink_payload_last_be = soc_tx_gap_inserter_source_payload_last_be;
-assign soc_liteethphymiitx_sink_sink_payload_error = soc_tx_gap_inserter_source_payload_error;
-assign soc_preamble_checker_sink_valid = soc_liteethphymiirx_source_source_valid;
-assign soc_liteethphymiirx_source_source_ready = soc_preamble_checker_sink_ready;
-assign soc_preamble_checker_sink_first = soc_liteethphymiirx_source_source_first;
-assign soc_preamble_checker_sink_last = soc_liteethphymiirx_source_source_last;
-assign soc_preamble_checker_sink_payload_data = soc_liteethphymiirx_source_source_payload_data;
-assign soc_preamble_checker_sink_payload_last_be = soc_liteethphymiirx_source_source_payload_last_be;
-assign soc_preamble_checker_sink_payload_error = soc_liteethphymiirx_source_source_payload_error;
-assign soc_crc32_checker_sink_sink_valid = soc_preamble_checker_source_valid;
-assign soc_preamble_checker_source_ready = soc_crc32_checker_sink_sink_ready;
-assign soc_crc32_checker_sink_sink_first = soc_preamble_checker_source_first;
-assign soc_crc32_checker_sink_sink_last = soc_preamble_checker_source_last;
-assign soc_crc32_checker_sink_sink_payload_data = soc_preamble_checker_source_payload_data;
-assign soc_crc32_checker_sink_sink_payload_last_be = soc_preamble_checker_source_payload_last_be;
-assign soc_crc32_checker_sink_sink_payload_error = soc_preamble_checker_source_payload_error;
-assign soc_padding_checker_sink_valid = soc_crc32_checker_source_source_valid;
-assign soc_crc32_checker_source_source_ready = soc_padding_checker_sink_ready;
-assign soc_padding_checker_sink_first = soc_crc32_checker_source_source_first;
-assign soc_padding_checker_sink_last = soc_crc32_checker_source_source_last;
-assign soc_padding_checker_sink_payload_data = soc_crc32_checker_source_source_payload_data;
-assign soc_padding_checker_sink_payload_last_be = soc_crc32_checker_source_source_payload_last_be;
-assign soc_padding_checker_sink_payload_error = soc_crc32_checker_source_source_payload_error;
-assign soc_rx_last_be_sink_valid = soc_padding_checker_source_valid;
-assign soc_padding_checker_source_ready = soc_rx_last_be_sink_ready;
-assign soc_rx_last_be_sink_first = soc_padding_checker_source_first;
-assign soc_rx_last_be_sink_last = soc_padding_checker_source_last;
-assign soc_rx_last_be_sink_payload_data = soc_padding_checker_source_payload_data;
-assign soc_rx_last_be_sink_payload_last_be = soc_padding_checker_source_payload_last_be;
-assign soc_rx_last_be_sink_payload_error = soc_padding_checker_source_payload_error;
-assign soc_rx_converter_sink_valid = soc_rx_last_be_source_valid;
-assign soc_rx_last_be_source_ready = soc_rx_converter_sink_ready;
-assign soc_rx_converter_sink_first = soc_rx_last_be_source_first;
-assign soc_rx_converter_sink_last = soc_rx_last_be_source_last;
-assign soc_rx_converter_sink_payload_data = soc_rx_last_be_source_payload_data;
-assign soc_rx_converter_sink_payload_last_be = soc_rx_last_be_source_payload_last_be;
-assign soc_rx_converter_sink_payload_error = soc_rx_last_be_source_payload_error;
-assign soc_rx_cdc_sink_valid = soc_rx_converter_source_valid;
-assign soc_rx_converter_source_ready = soc_rx_cdc_sink_ready;
-assign soc_rx_cdc_sink_first = soc_rx_converter_source_first;
-assign soc_rx_cdc_sink_last = soc_rx_converter_source_last;
-assign soc_rx_cdc_sink_payload_data = soc_rx_converter_source_payload_data;
-assign soc_rx_cdc_sink_payload_last_be = soc_rx_converter_source_payload_last_be;
-assign soc_rx_cdc_sink_payload_error = soc_rx_converter_source_payload_error;
-assign soc_writer_sink_sink_valid = soc_sink_valid;
-assign soc_sink_ready = soc_writer_sink_sink_ready;
-assign soc_writer_sink_sink_first = soc_sink_first;
-assign soc_writer_sink_sink_last = soc_sink_last;
-assign soc_writer_sink_sink_payload_data = soc_sink_payload_data;
-assign soc_writer_sink_sink_payload_last_be = soc_sink_payload_last_be;
-assign soc_writer_sink_sink_payload_error = soc_sink_payload_error;
-assign soc_source_valid = soc_reader_source_source_valid;
-assign soc_reader_source_source_ready = soc_source_ready;
-assign soc_source_first = soc_reader_source_source_first;
-assign soc_source_last = soc_reader_source_source_last;
-assign soc_source_payload_data = soc_reader_source_source_payload_data;
-assign soc_source_payload_last_be = soc_reader_source_source_payload_last_be;
-assign soc_source_payload_error = soc_reader_source_source_payload_error;
-always @(*) begin
-	soc_writer_inc <= 3'd0;
-	case (soc_writer_sink_sink_payload_last_be)
-		1'd1: begin
-			soc_writer_inc <= 1'd1;
-		end
-		2'd2: begin
-			soc_writer_inc <= 2'd2;
-		end
-		3'd4: begin
-			soc_writer_inc <= 2'd3;
-		end
-		default: begin
-			soc_writer_inc <= 3'd4;
-		end
-	endcase
-end
-assign soc_writer_fifo_sink_payload_slot = soc_writer_slot;
-assign soc_writer_fifo_sink_payload_length = soc_writer_counter;
-assign soc_writer_fifo_source_ready = soc_writer_available_clear;
-assign soc_writer_available_trigger = soc_writer_fifo_source_valid;
-assign soc_writer_slot_status = soc_writer_fifo_source_payload_slot;
-assign soc_writer_length_status = soc_writer_fifo_source_payload_length;
-always @(*) begin
-	soc_writer_memory0_adr <= 9'd0;
-	soc_writer_memory1_dat_w <= 32'd0;
-	soc_writer_memory0_we <= 1'd0;
-	soc_writer_memory0_dat_w <= 32'd0;
-	soc_writer_memory1_adr <= 9'd0;
-	soc_writer_memory1_we <= 1'd0;
-	case (soc_writer_slot)
-		1'd0: begin
-			soc_writer_memory0_adr <= soc_writer_counter[31:2];
-			soc_writer_memory0_dat_w <= soc_writer_sink_sink_payload_data;
-			if ((soc_writer_sink_sink_valid & soc_writer_ongoing)) begin
-				soc_writer_memory0_we <= 4'd15;
-			end
-		end
-		1'd1: begin
-			soc_writer_memory1_adr <= soc_writer_counter[31:2];
-			soc_writer_memory1_dat_w <= soc_writer_sink_sink_payload_data;
-			if ((soc_writer_sink_sink_valid & soc_writer_ongoing)) begin
-				soc_writer_memory1_we <= 4'd15;
-			end
-		end
-	endcase
-end
-assign soc_writer_status_w = soc_writer_available_status;
-always @(*) begin
-	soc_writer_available_clear <= 1'd0;
-	if ((soc_writer_pending_re & soc_writer_pending_r)) begin
-		soc_writer_available_clear <= 1'd1;
-	end
-end
-assign soc_writer_pending_w = soc_writer_available_pending;
-assign soc_writer_irq = (soc_writer_pending_w & soc_writer_storage);
-assign soc_writer_available_status = soc_writer_available_trigger;
-assign soc_writer_available_pending = soc_writer_available_trigger;
-assign soc_writer_fifo_syncfifo_din = {soc_writer_fifo_fifo_in_last, soc_writer_fifo_fifo_in_first, soc_writer_fifo_fifo_in_payload_length, soc_writer_fifo_fifo_in_payload_slot};
-assign {soc_writer_fifo_fifo_out_last, soc_writer_fifo_fifo_out_first, soc_writer_fifo_fifo_out_payload_length, soc_writer_fifo_fifo_out_payload_slot} = soc_writer_fifo_syncfifo_dout;
-assign soc_writer_fifo_sink_ready = soc_writer_fifo_syncfifo_writable;
-assign soc_writer_fifo_syncfifo_we = soc_writer_fifo_sink_valid;
-assign soc_writer_fifo_fifo_in_first = soc_writer_fifo_sink_first;
-assign soc_writer_fifo_fifo_in_last = soc_writer_fifo_sink_last;
-assign soc_writer_fifo_fifo_in_payload_slot = soc_writer_fifo_sink_payload_slot;
-assign soc_writer_fifo_fifo_in_payload_length = soc_writer_fifo_sink_payload_length;
-assign soc_writer_fifo_source_valid = soc_writer_fifo_syncfifo_readable;
-assign soc_writer_fifo_source_first = soc_writer_fifo_fifo_out_first;
-assign soc_writer_fifo_source_last = soc_writer_fifo_fifo_out_last;
-assign soc_writer_fifo_source_payload_slot = soc_writer_fifo_fifo_out_payload_slot;
-assign soc_writer_fifo_source_payload_length = soc_writer_fifo_fifo_out_payload_length;
-assign soc_writer_fifo_syncfifo_re = soc_writer_fifo_source_ready;
-always @(*) begin
-	soc_writer_fifo_wrport_adr <= 1'd0;
-	if (soc_writer_fifo_replace) begin
-		soc_writer_fifo_wrport_adr <= (soc_writer_fifo_produce - 1'd1);
-	end else begin
-		soc_writer_fifo_wrport_adr <= soc_writer_fifo_produce;
-	end
-end
-assign soc_writer_fifo_wrport_dat_w = soc_writer_fifo_syncfifo_din;
-assign soc_writer_fifo_wrport_we = (soc_writer_fifo_syncfifo_we & (soc_writer_fifo_syncfifo_writable | soc_writer_fifo_replace));
-assign soc_writer_fifo_do_read = (soc_writer_fifo_syncfifo_readable & soc_writer_fifo_syncfifo_re);
-assign soc_writer_fifo_rdport_adr = soc_writer_fifo_consume;
-assign soc_writer_fifo_syncfifo_dout = soc_writer_fifo_rdport_dat_r;
-assign soc_writer_fifo_syncfifo_writable = (soc_writer_fifo_level != 2'd2);
-assign soc_writer_fifo_syncfifo_readable = (soc_writer_fifo_level != 1'd0);
-always @(*) begin
-	soc_writer_slot_ce <= 1'd0;
-	soc_writer_errors_status_liteethmac_next_value <= 32'd0;
-	soc_writer_errors_status_liteethmac_next_value_ce <= 1'd0;
-	soc_writer_ongoing <= 1'd0;
-	soc_writer_fifo_sink_valid <= 1'd0;
-	soc_writer_counter_reset <= 1'd0;
-	soc_writer_counter_ce <= 1'd0;
-	vns_liteethmacsramwriter_next_state <= 3'd0;
-	vns_liteethmacsramwriter_next_state <= vns_liteethmacsramwriter_state;
-	case (vns_liteethmacsramwriter_state)
-		1'd1: begin
-			if (soc_writer_sink_sink_valid) begin
-				if ((soc_writer_counter == 11'd1530)) begin
-					vns_liteethmacsramwriter_next_state <= 2'd3;
-				end else begin
-					soc_writer_counter_ce <= 1'd1;
-					soc_writer_ongoing <= 1'd1;
-				end
-				if (soc_writer_sink_sink_last) begin
-					if (((soc_writer_sink_sink_payload_error & soc_writer_sink_sink_payload_last_be) != 1'd0)) begin
-						vns_liteethmacsramwriter_next_state <= 2'd2;
-					end else begin
-						vns_liteethmacsramwriter_next_state <= 3'd4;
-					end
-				end
-			end
-		end
-		2'd2: begin
-			soc_writer_counter_reset <= 1'd1;
-			vns_liteethmacsramwriter_next_state <= 1'd0;
-		end
-		2'd3: begin
-			if ((soc_writer_sink_sink_valid & soc_writer_sink_sink_last)) begin
-				vns_liteethmacsramwriter_next_state <= 3'd4;
-			end
-		end
-		3'd4: begin
-			soc_writer_counter_reset <= 1'd1;
-			soc_writer_slot_ce <= 1'd1;
-			soc_writer_fifo_sink_valid <= 1'd1;
-			vns_liteethmacsramwriter_next_state <= 1'd0;
-		end
-		default: begin
-			if (soc_writer_sink_sink_valid) begin
-				if (soc_writer_fifo_sink_ready) begin
-					soc_writer_ongoing <= 1'd1;
-					soc_writer_counter_ce <= 1'd1;
-					vns_liteethmacsramwriter_next_state <= 1'd1;
-				end else begin
-					soc_writer_errors_status_liteethmac_next_value <= (soc_writer_errors_status + 1'd1);
-					soc_writer_errors_status_liteethmac_next_value_ce <= 1'd1;
-					vns_liteethmacsramwriter_next_state <= 2'd3;
-				end
-			end
-		end
-	endcase
-end
-assign soc_reader_fifo_sink_valid = soc_reader_start_re;
-assign soc_reader_fifo_sink_payload_slot = soc_reader_slot_storage;
-assign soc_reader_fifo_sink_payload_length = soc_reader_length_storage;
-assign soc_reader_ready_status = soc_reader_fifo_sink_ready;
-assign soc_reader_level_status = soc_reader_fifo_level;
-always @(*) begin
-	soc_reader_source_source_payload_last_be <= 4'd0;
-	if (soc_reader_last) begin
-		case (soc_reader_fifo_source_payload_length[1:0])
-			1'd0: begin
-				soc_reader_source_source_payload_last_be <= 4'd8;
-			end
-			1'd1: begin
-				soc_reader_source_source_payload_last_be <= 1'd1;
-			end
-			2'd2: begin
-				soc_reader_source_source_payload_last_be <= 2'd2;
-			end
-			2'd3: begin
-				soc_reader_source_source_payload_last_be <= 3'd4;
-			end
-		endcase
-	end
-end
-assign soc_reader_last = ((soc_reader_counter + 3'd4) >= soc_reader_fifo_source_payload_length);
-assign soc_reader_memory0_adr = soc_reader_counter[10:2];
-assign soc_reader_memory1_adr = soc_reader_counter[10:2];
-always @(*) begin
-	soc_reader_source_source_payload_data <= 32'd0;
-	case (soc_reader_fifo_source_payload_slot)
-		1'd0: begin
-			soc_reader_source_source_payload_data <= soc_reader_memory0_dat_r;
-		end
-		1'd1: begin
-			soc_reader_source_source_payload_data <= soc_reader_memory1_dat_r;
-		end
-	endcase
-end
-assign soc_reader_eventmanager_status_w = soc_reader_done_status;
-always @(*) begin
-	soc_reader_done_clear <= 1'd0;
-	if ((soc_reader_eventmanager_pending_re & soc_reader_eventmanager_pending_r)) begin
-		soc_reader_done_clear <= 1'd1;
-	end
-end
-assign soc_reader_eventmanager_pending_w = soc_reader_done_pending;
-assign soc_reader_irq = (soc_reader_eventmanager_pending_w & soc_reader_eventmanager_storage);
-assign soc_reader_done_status = 1'd0;
-assign soc_reader_fifo_syncfifo_din = {soc_reader_fifo_fifo_in_last, soc_reader_fifo_fifo_in_first, soc_reader_fifo_fifo_in_payload_length, soc_reader_fifo_fifo_in_payload_slot};
-assign {soc_reader_fifo_fifo_out_last, soc_reader_fifo_fifo_out_first, soc_reader_fifo_fifo_out_payload_length, soc_reader_fifo_fifo_out_payload_slot} = soc_reader_fifo_syncfifo_dout;
-assign soc_reader_fifo_sink_ready = soc_reader_fifo_syncfifo_writable;
-assign soc_reader_fifo_syncfifo_we = soc_reader_fifo_sink_valid;
-assign soc_reader_fifo_fifo_in_first = soc_reader_fifo_sink_first;
-assign soc_reader_fifo_fifo_in_last = soc_reader_fifo_sink_last;
-assign soc_reader_fifo_fifo_in_payload_slot = soc_reader_fifo_sink_payload_slot;
-assign soc_reader_fifo_fifo_in_payload_length = soc_reader_fifo_sink_payload_length;
-assign soc_reader_fifo_source_valid = soc_reader_fifo_syncfifo_readable;
-assign soc_reader_fifo_source_first = soc_reader_fifo_fifo_out_first;
-assign soc_reader_fifo_source_last = soc_reader_fifo_fifo_out_last;
-assign soc_reader_fifo_source_payload_slot = soc_reader_fifo_fifo_out_payload_slot;
-assign soc_reader_fifo_source_payload_length = soc_reader_fifo_fifo_out_payload_length;
-assign soc_reader_fifo_syncfifo_re = soc_reader_fifo_source_ready;
-always @(*) begin
-	soc_reader_fifo_wrport_adr <= 1'd0;
-	if (soc_reader_fifo_replace) begin
-		soc_reader_fifo_wrport_adr <= (soc_reader_fifo_produce - 1'd1);
-	end else begin
-		soc_reader_fifo_wrport_adr <= soc_reader_fifo_produce;
-	end
-end
-assign soc_reader_fifo_wrport_dat_w = soc_reader_fifo_syncfifo_din;
-assign soc_reader_fifo_wrport_we = (soc_reader_fifo_syncfifo_we & (soc_reader_fifo_syncfifo_writable | soc_reader_fifo_replace));
-assign soc_reader_fifo_do_read = (soc_reader_fifo_syncfifo_readable & soc_reader_fifo_syncfifo_re);
-assign soc_reader_fifo_rdport_adr = soc_reader_fifo_consume;
-assign soc_reader_fifo_syncfifo_dout = soc_reader_fifo_rdport_dat_r;
-assign soc_reader_fifo_syncfifo_writable = (soc_reader_fifo_level != 2'd2);
-assign soc_reader_fifo_syncfifo_readable = (soc_reader_fifo_level != 1'd0);
-always @(*) begin
-	soc_reader_counter_reset <= 1'd0;
-	soc_reader_counter_ce <= 1'd0;
-	soc_reader_source_source_last <= 1'd0;
-	soc_reader_fifo_source_ready <= 1'd0;
-	vns_liteethmacsramreader_next_state <= 2'd0;
-	soc_reader_source_source_valid <= 1'd0;
-	soc_reader_done_trigger <= 1'd0;
-	vns_liteethmacsramreader_next_state <= vns_liteethmacsramreader_state;
-	case (vns_liteethmacsramreader_state)
-		1'd1: begin
-			if ((~soc_reader_last_d)) begin
-				vns_liteethmacsramreader_next_state <= 2'd2;
-			end else begin
-				vns_liteethmacsramreader_next_state <= 2'd3;
-			end
-		end
-		2'd2: begin
-			soc_reader_source_source_valid <= 1'd1;
-			soc_reader_source_source_last <= soc_reader_last;
-			if (soc_reader_source_source_ready) begin
-				soc_reader_counter_ce <= (~soc_reader_last);
-				vns_liteethmacsramreader_next_state <= 1'd1;
-			end
-		end
-		2'd3: begin
-			soc_reader_fifo_source_ready <= 1'd1;
-			soc_reader_done_trigger <= 1'd1;
-			vns_liteethmacsramreader_next_state <= 1'd0;
-		end
-		default: begin
-			soc_reader_counter_reset <= 1'd1;
-			if (soc_reader_fifo_source_valid) begin
-				vns_liteethmacsramreader_next_state <= 1'd1;
-			end
-		end
-	endcase
-end
-assign soc_ev_irq = (soc_writer_irq | soc_reader_irq);
-assign soc_sram0_adr0 = soc_sram0_bus_adr0[8:0];
-assign soc_sram0_bus_dat_r0 = soc_sram0_dat_r0;
-assign soc_sram1_adr0 = soc_sram1_bus_adr0[8:0];
-assign soc_sram1_bus_dat_r0 = soc_sram1_dat_r0;
-always @(*) begin
-	soc_sram0_we <= 4'd0;
-	soc_sram0_we[0] <= (((soc_sram0_bus_cyc1 & soc_sram0_bus_stb1) & soc_sram0_bus_we1) & soc_sram0_bus_sel1[0]);
-	soc_sram0_we[1] <= (((soc_sram0_bus_cyc1 & soc_sram0_bus_stb1) & soc_sram0_bus_we1) & soc_sram0_bus_sel1[1]);
-	soc_sram0_we[2] <= (((soc_sram0_bus_cyc1 & soc_sram0_bus_stb1) & soc_sram0_bus_we1) & soc_sram0_bus_sel1[2]);
-	soc_sram0_we[3] <= (((soc_sram0_bus_cyc1 & soc_sram0_bus_stb1) & soc_sram0_bus_we1) & soc_sram0_bus_sel1[3]);
-end
-assign soc_sram0_adr1 = soc_sram0_bus_adr1[8:0];
-assign soc_sram0_bus_dat_r1 = soc_sram0_dat_r1;
-assign soc_sram0_dat_w = soc_sram0_bus_dat_w1;
-always @(*) begin
-	soc_sram1_we <= 4'd0;
-	soc_sram1_we[0] <= (((soc_sram1_bus_cyc1 & soc_sram1_bus_stb1) & soc_sram1_bus_we1) & soc_sram1_bus_sel1[0]);
-	soc_sram1_we[1] <= (((soc_sram1_bus_cyc1 & soc_sram1_bus_stb1) & soc_sram1_bus_we1) & soc_sram1_bus_sel1[1]);
-	soc_sram1_we[2] <= (((soc_sram1_bus_cyc1 & soc_sram1_bus_stb1) & soc_sram1_bus_we1) & soc_sram1_bus_sel1[2]);
-	soc_sram1_we[3] <= (((soc_sram1_bus_cyc1 & soc_sram1_bus_stb1) & soc_sram1_bus_we1) & soc_sram1_bus_sel1[3]);
-end
-assign soc_sram1_adr1 = soc_sram1_bus_adr1[8:0];
-assign soc_sram1_bus_dat_r1 = soc_sram1_dat_r1;
-assign soc_sram1_dat_w = soc_sram1_bus_dat_w1;
-always @(*) begin
-	soc_slave_sel <= 4'd0;
-	soc_slave_sel[0] <= (soc_bus_adr[10:9] == 1'd0);
-	soc_slave_sel[1] <= (soc_bus_adr[10:9] == 1'd1);
-	soc_slave_sel[2] <= (soc_bus_adr[10:9] == 2'd2);
-	soc_slave_sel[3] <= (soc_bus_adr[10:9] == 2'd3);
-end
-assign soc_sram0_bus_adr0 = soc_bus_adr;
-assign soc_sram0_bus_dat_w0 = soc_bus_dat_w;
-assign soc_sram0_bus_sel0 = soc_bus_sel;
-assign soc_sram0_bus_stb0 = soc_bus_stb;
-assign soc_sram0_bus_we0 = soc_bus_we;
-assign soc_sram0_bus_cti0 = soc_bus_cti;
-assign soc_sram0_bus_bte0 = soc_bus_bte;
-assign soc_sram1_bus_adr0 = soc_bus_adr;
-assign soc_sram1_bus_dat_w0 = soc_bus_dat_w;
-assign soc_sram1_bus_sel0 = soc_bus_sel;
-assign soc_sram1_bus_stb0 = soc_bus_stb;
-assign soc_sram1_bus_we0 = soc_bus_we;
-assign soc_sram1_bus_cti0 = soc_bus_cti;
-assign soc_sram1_bus_bte0 = soc_bus_bte;
-assign soc_sram0_bus_adr1 = soc_bus_adr;
-assign soc_sram0_bus_dat_w1 = soc_bus_dat_w;
-assign soc_sram0_bus_sel1 = soc_bus_sel;
-assign soc_sram0_bus_stb1 = soc_bus_stb;
-assign soc_sram0_bus_we1 = soc_bus_we;
-assign soc_sram0_bus_cti1 = soc_bus_cti;
-assign soc_sram0_bus_bte1 = soc_bus_bte;
-assign soc_sram1_bus_adr1 = soc_bus_adr;
-assign soc_sram1_bus_dat_w1 = soc_bus_dat_w;
-assign soc_sram1_bus_sel1 = soc_bus_sel;
-assign soc_sram1_bus_stb1 = soc_bus_stb;
-assign soc_sram1_bus_we1 = soc_bus_we;
-assign soc_sram1_bus_cti1 = soc_bus_cti;
-assign soc_sram1_bus_bte1 = soc_bus_bte;
-assign soc_sram0_bus_cyc0 = (soc_bus_cyc & soc_slave_sel[0]);
-assign soc_sram1_bus_cyc0 = (soc_bus_cyc & soc_slave_sel[1]);
-assign soc_sram0_bus_cyc1 = (soc_bus_cyc & soc_slave_sel[2]);
-assign soc_sram1_bus_cyc1 = (soc_bus_cyc & soc_slave_sel[3]);
-assign soc_bus_ack = (((soc_sram0_bus_ack0 | soc_sram1_bus_ack0) | soc_sram0_bus_ack1) | soc_sram1_bus_ack1);
-assign soc_bus_err = (((soc_sram0_bus_err0 | soc_sram1_bus_err0) | soc_sram0_bus_err1) | soc_sram1_bus_err1);
-assign soc_bus_dat_r = (((({32{soc_slave_sel_r[0]}} & soc_sram0_bus_dat_r0) | ({32{soc_slave_sel_r[1]}} & soc_sram1_bus_dat_r0)) | ({32{soc_slave_sel_r[2]}} & soc_sram0_bus_dat_r1)) | ({32{soc_slave_sel_r[3]}} & soc_sram1_bus_dat_r1));
-assign soc_netsoc_interface0_wb_sdram_adr = vns_rhs_array_muxed36;
-assign soc_netsoc_interface0_wb_sdram_dat_w = vns_rhs_array_muxed37;
-assign soc_netsoc_interface0_wb_sdram_sel = vns_rhs_array_muxed38;
-assign soc_netsoc_interface0_wb_sdram_cyc = vns_rhs_array_muxed39;
-assign soc_netsoc_interface0_wb_sdram_stb = vns_rhs_array_muxed40;
-assign soc_netsoc_interface0_wb_sdram_we = vns_rhs_array_muxed41;
-assign soc_netsoc_interface0_wb_sdram_cti = vns_rhs_array_muxed42;
-assign soc_netsoc_interface0_wb_sdram_bte = vns_rhs_array_muxed43;
-assign soc_netsoc_interface1_wb_sdram_dat_r = soc_netsoc_interface0_wb_sdram_dat_r;
-assign soc_netsoc_interface1_wb_sdram_ack = (soc_netsoc_interface0_wb_sdram_ack & (vns_wb_sdram_con_grant == 1'd0));
-assign soc_netsoc_interface1_wb_sdram_err = (soc_netsoc_interface0_wb_sdram_err & (vns_wb_sdram_con_grant == 1'd0));
-assign vns_wb_sdram_con_request = {soc_netsoc_interface1_wb_sdram_cyc};
-assign vns_wb_sdram_con_grant = 1'd0;
-assign vns_netsoc_shared_adr = vns_rhs_array_muxed44;
-assign vns_netsoc_shared_dat_w = vns_rhs_array_muxed45;
-assign vns_netsoc_shared_sel = vns_rhs_array_muxed46;
-assign vns_netsoc_shared_cyc = vns_rhs_array_muxed47;
-assign vns_netsoc_shared_stb = vns_rhs_array_muxed48;
-assign vns_netsoc_shared_we = vns_rhs_array_muxed49;
-assign vns_netsoc_shared_cti = vns_rhs_array_muxed50;
-assign vns_netsoc_shared_bte = vns_rhs_array_muxed51;
-assign soc_netsoc_interface0_soc_bus_dat_r = vns_netsoc_shared_dat_r;
-assign soc_netsoc_interface1_soc_bus_dat_r = vns_netsoc_shared_dat_r;
-assign soc_netsoc_interface0_soc_bus_ack = (vns_netsoc_shared_ack & (vns_netsoc_grant == 1'd0));
-assign soc_netsoc_interface1_soc_bus_ack = (vns_netsoc_shared_ack & (vns_netsoc_grant == 1'd1));
-assign soc_netsoc_interface0_soc_bus_err = (vns_netsoc_shared_err & (vns_netsoc_grant == 1'd0));
-assign soc_netsoc_interface1_soc_bus_err = (vns_netsoc_shared_err & (vns_netsoc_grant == 1'd1));
-assign vns_netsoc_request = {soc_netsoc_interface1_soc_bus_cyc, soc_netsoc_interface0_soc_bus_cyc};
-always @(*) begin
-	vns_netsoc_slave_sel <= 6'd0;
-	vns_netsoc_slave_sel[0] <= (vns_netsoc_shared_adr[28:14] == 1'd0);
-	vns_netsoc_slave_sel[1] <= (vns_netsoc_shared_adr[28:13] == 14'd8192);
-	vns_netsoc_slave_sel[2] <= (vns_netsoc_shared_adr[28:22] == 7'd112);
-	vns_netsoc_slave_sel[3] <= (vns_netsoc_shared_adr[28:12] == 17'd81920);
-	vns_netsoc_slave_sel[4] <= (vns_netsoc_shared_adr[28:26] == 3'd4);
-	vns_netsoc_slave_sel[5] <= (vns_netsoc_shared_adr[28:26] == 2'd3);
-end
-assign soc_netsoc_rom_bus_adr = vns_netsoc_shared_adr;
-assign soc_netsoc_rom_bus_dat_w = vns_netsoc_shared_dat_w;
-assign soc_netsoc_rom_bus_sel = vns_netsoc_shared_sel;
-assign soc_netsoc_rom_bus_stb = vns_netsoc_shared_stb;
-assign soc_netsoc_rom_bus_we = vns_netsoc_shared_we;
-assign soc_netsoc_rom_bus_cti = vns_netsoc_shared_cti;
-assign soc_netsoc_rom_bus_bte = vns_netsoc_shared_bte;
-assign soc_netsoc_sram_bus_adr = vns_netsoc_shared_adr;
-assign soc_netsoc_sram_bus_dat_w = vns_netsoc_shared_dat_w;
-assign soc_netsoc_sram_bus_sel = vns_netsoc_shared_sel;
-assign soc_netsoc_sram_bus_stb = vns_netsoc_shared_stb;
-assign soc_netsoc_sram_bus_we = vns_netsoc_shared_we;
-assign soc_netsoc_sram_bus_cti = vns_netsoc_shared_cti;
-assign soc_netsoc_sram_bus_bte = vns_netsoc_shared_bte;
-assign soc_netsoc_bus_wishbone_adr = vns_netsoc_shared_adr;
-assign soc_netsoc_bus_wishbone_dat_w = vns_netsoc_shared_dat_w;
-assign soc_netsoc_bus_wishbone_sel = vns_netsoc_shared_sel;
-assign soc_netsoc_bus_wishbone_stb = vns_netsoc_shared_stb;
-assign soc_netsoc_bus_wishbone_we = vns_netsoc_shared_we;
-assign soc_netsoc_bus_wishbone_cti = vns_netsoc_shared_cti;
-assign soc_netsoc_bus_wishbone_bte = vns_netsoc_shared_bte;
-assign soc_emulator_ram_bus_adr = vns_netsoc_shared_adr;
-assign soc_emulator_ram_bus_dat_w = vns_netsoc_shared_dat_w;
-assign soc_emulator_ram_bus_sel = vns_netsoc_shared_sel;
-assign soc_emulator_ram_bus_stb = vns_netsoc_shared_stb;
-assign soc_emulator_ram_bus_we = vns_netsoc_shared_we;
-assign soc_emulator_ram_bus_cti = vns_netsoc_shared_cti;
-assign soc_emulator_ram_bus_bte = vns_netsoc_shared_bte;
-assign soc_netsoc_interface1_wb_sdram_adr = vns_netsoc_shared_adr;
-assign soc_netsoc_interface1_wb_sdram_dat_w = vns_netsoc_shared_dat_w;
-assign soc_netsoc_interface1_wb_sdram_sel = vns_netsoc_shared_sel;
-assign soc_netsoc_interface1_wb_sdram_stb = vns_netsoc_shared_stb;
-assign soc_netsoc_interface1_wb_sdram_we = vns_netsoc_shared_we;
-assign soc_netsoc_interface1_wb_sdram_cti = vns_netsoc_shared_cti;
-assign soc_netsoc_interface1_wb_sdram_bte = vns_netsoc_shared_bte;
-assign soc_bus_adr = vns_netsoc_shared_adr;
-assign soc_bus_dat_w = vns_netsoc_shared_dat_w;
-assign soc_bus_sel = vns_netsoc_shared_sel;
-assign soc_bus_stb = vns_netsoc_shared_stb;
-assign soc_bus_we = vns_netsoc_shared_we;
-assign soc_bus_cti = vns_netsoc_shared_cti;
-assign soc_bus_bte = vns_netsoc_shared_bte;
-assign soc_netsoc_rom_bus_cyc = (vns_netsoc_shared_cyc & vns_netsoc_slave_sel[0]);
-assign soc_netsoc_sram_bus_cyc = (vns_netsoc_shared_cyc & vns_netsoc_slave_sel[1]);
-assign soc_netsoc_bus_wishbone_cyc = (vns_netsoc_shared_cyc & vns_netsoc_slave_sel[2]);
-assign soc_emulator_ram_bus_cyc = (vns_netsoc_shared_cyc & vns_netsoc_slave_sel[3]);
-assign soc_netsoc_interface1_wb_sdram_cyc = (vns_netsoc_shared_cyc & vns_netsoc_slave_sel[4]);
-assign soc_bus_cyc = (vns_netsoc_shared_cyc & vns_netsoc_slave_sel[5]);
-assign vns_netsoc_shared_err = (((((soc_netsoc_rom_bus_err | soc_netsoc_sram_bus_err) | soc_netsoc_bus_wishbone_err) | soc_emulator_ram_bus_err) | soc_netsoc_interface1_wb_sdram_err) | soc_bus_err);
-assign vns_netsoc_wait = ((vns_netsoc_shared_stb & vns_netsoc_shared_cyc) & (~vns_netsoc_shared_ack));
-always @(*) begin
-	vns_netsoc_error <= 1'd0;
-	vns_netsoc_shared_ack <= 1'd0;
-	vns_netsoc_shared_dat_r <= 32'd0;
-	vns_netsoc_shared_ack <= (((((soc_netsoc_rom_bus_ack | soc_netsoc_sram_bus_ack) | soc_netsoc_bus_wishbone_ack) | soc_emulator_ram_bus_ack) | soc_netsoc_interface1_wb_sdram_ack) | soc_bus_ack);
-	vns_netsoc_shared_dat_r <= (((((({32{vns_netsoc_slave_sel_r[0]}} & soc_netsoc_rom_bus_dat_r) | ({32{vns_netsoc_slave_sel_r[1]}} & soc_netsoc_sram_bus_dat_r)) | ({32{vns_netsoc_slave_sel_r[2]}} & soc_netsoc_bus_wishbone_dat_r)) | ({32{vns_netsoc_slave_sel_r[3]}} & soc_emulator_ram_bus_dat_r)) | ({32{vns_netsoc_slave_sel_r[4]}} & soc_netsoc_interface1_wb_sdram_dat_r)) | ({32{vns_netsoc_slave_sel_r[5]}} & soc_bus_dat_r));
-	if (vns_netsoc_done) begin
-		vns_netsoc_shared_dat_r <= 32'd4294967295;
-		vns_netsoc_shared_ack <= 1'd1;
-		vns_netsoc_error <= 1'd1;
-	end
-end
-assign vns_netsoc_done = (vns_netsoc_count == 1'd0);
-assign vns_netsoc_csrbankarray_csrbank0_sel = (vns_netsoc_csrbankarray_interface0_bank_bus_adr[13:9] == 1'd1);
-assign soc_netsoc_cpu_latch_r = vns_netsoc_csrbankarray_interface0_bank_bus_dat_w[0];
-assign soc_netsoc_cpu_latch_re = ((vns_netsoc_csrbankarray_csrbank0_sel & vns_netsoc_csrbankarray_interface0_bank_bus_we) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 1'd0));
-assign soc_netsoc_cpu_latch_we = ((vns_netsoc_csrbankarray_csrbank0_sel & (~vns_netsoc_csrbankarray_interface0_bank_bus_we)) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 1'd0));
-assign vns_netsoc_csrbankarray_csrbank0_timer_time7_r = vns_netsoc_csrbankarray_interface0_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank0_timer_time7_re = ((vns_netsoc_csrbankarray_csrbank0_sel & vns_netsoc_csrbankarray_interface0_bank_bus_we) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 1'd1));
-assign vns_netsoc_csrbankarray_csrbank0_timer_time7_we = ((vns_netsoc_csrbankarray_csrbank0_sel & (~vns_netsoc_csrbankarray_interface0_bank_bus_we)) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 1'd1));
-assign vns_netsoc_csrbankarray_csrbank0_timer_time6_r = vns_netsoc_csrbankarray_interface0_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank0_timer_time6_re = ((vns_netsoc_csrbankarray_csrbank0_sel & vns_netsoc_csrbankarray_interface0_bank_bus_we) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 2'd2));
-assign vns_netsoc_csrbankarray_csrbank0_timer_time6_we = ((vns_netsoc_csrbankarray_csrbank0_sel & (~vns_netsoc_csrbankarray_interface0_bank_bus_we)) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 2'd2));
-assign vns_netsoc_csrbankarray_csrbank0_timer_time5_r = vns_netsoc_csrbankarray_interface0_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank0_timer_time5_re = ((vns_netsoc_csrbankarray_csrbank0_sel & vns_netsoc_csrbankarray_interface0_bank_bus_we) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 2'd3));
-assign vns_netsoc_csrbankarray_csrbank0_timer_time5_we = ((vns_netsoc_csrbankarray_csrbank0_sel & (~vns_netsoc_csrbankarray_interface0_bank_bus_we)) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 2'd3));
-assign vns_netsoc_csrbankarray_csrbank0_timer_time4_r = vns_netsoc_csrbankarray_interface0_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank0_timer_time4_re = ((vns_netsoc_csrbankarray_csrbank0_sel & vns_netsoc_csrbankarray_interface0_bank_bus_we) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 3'd4));
-assign vns_netsoc_csrbankarray_csrbank0_timer_time4_we = ((vns_netsoc_csrbankarray_csrbank0_sel & (~vns_netsoc_csrbankarray_interface0_bank_bus_we)) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 3'd4));
-assign vns_netsoc_csrbankarray_csrbank0_timer_time3_r = vns_netsoc_csrbankarray_interface0_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank0_timer_time3_re = ((vns_netsoc_csrbankarray_csrbank0_sel & vns_netsoc_csrbankarray_interface0_bank_bus_we) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 3'd5));
-assign vns_netsoc_csrbankarray_csrbank0_timer_time3_we = ((vns_netsoc_csrbankarray_csrbank0_sel & (~vns_netsoc_csrbankarray_interface0_bank_bus_we)) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 3'd5));
-assign vns_netsoc_csrbankarray_csrbank0_timer_time2_r = vns_netsoc_csrbankarray_interface0_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank0_timer_time2_re = ((vns_netsoc_csrbankarray_csrbank0_sel & vns_netsoc_csrbankarray_interface0_bank_bus_we) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 3'd6));
-assign vns_netsoc_csrbankarray_csrbank0_timer_time2_we = ((vns_netsoc_csrbankarray_csrbank0_sel & (~vns_netsoc_csrbankarray_interface0_bank_bus_we)) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 3'd6));
-assign vns_netsoc_csrbankarray_csrbank0_timer_time1_r = vns_netsoc_csrbankarray_interface0_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank0_timer_time1_re = ((vns_netsoc_csrbankarray_csrbank0_sel & vns_netsoc_csrbankarray_interface0_bank_bus_we) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 3'd7));
-assign vns_netsoc_csrbankarray_csrbank0_timer_time1_we = ((vns_netsoc_csrbankarray_csrbank0_sel & (~vns_netsoc_csrbankarray_interface0_bank_bus_we)) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 3'd7));
-assign vns_netsoc_csrbankarray_csrbank0_timer_time0_r = vns_netsoc_csrbankarray_interface0_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank0_timer_time0_re = ((vns_netsoc_csrbankarray_csrbank0_sel & vns_netsoc_csrbankarray_interface0_bank_bus_we) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 4'd8));
-assign vns_netsoc_csrbankarray_csrbank0_timer_time0_we = ((vns_netsoc_csrbankarray_csrbank0_sel & (~vns_netsoc_csrbankarray_interface0_bank_bus_we)) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 4'd8));
-assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp7_r = vns_netsoc_csrbankarray_interface0_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp7_re = ((vns_netsoc_csrbankarray_csrbank0_sel & vns_netsoc_csrbankarray_interface0_bank_bus_we) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 4'd9));
-assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp7_we = ((vns_netsoc_csrbankarray_csrbank0_sel & (~vns_netsoc_csrbankarray_interface0_bank_bus_we)) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 4'd9));
-assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp6_r = vns_netsoc_csrbankarray_interface0_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp6_re = ((vns_netsoc_csrbankarray_csrbank0_sel & vns_netsoc_csrbankarray_interface0_bank_bus_we) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 4'd10));
-assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp6_we = ((vns_netsoc_csrbankarray_csrbank0_sel & (~vns_netsoc_csrbankarray_interface0_bank_bus_we)) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 4'd10));
-assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp5_r = vns_netsoc_csrbankarray_interface0_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp5_re = ((vns_netsoc_csrbankarray_csrbank0_sel & vns_netsoc_csrbankarray_interface0_bank_bus_we) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 4'd11));
-assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp5_we = ((vns_netsoc_csrbankarray_csrbank0_sel & (~vns_netsoc_csrbankarray_interface0_bank_bus_we)) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 4'd11));
-assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp4_r = vns_netsoc_csrbankarray_interface0_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp4_re = ((vns_netsoc_csrbankarray_csrbank0_sel & vns_netsoc_csrbankarray_interface0_bank_bus_we) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 4'd12));
-assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp4_we = ((vns_netsoc_csrbankarray_csrbank0_sel & (~vns_netsoc_csrbankarray_interface0_bank_bus_we)) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 4'd12));
-assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp3_r = vns_netsoc_csrbankarray_interface0_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp3_re = ((vns_netsoc_csrbankarray_csrbank0_sel & vns_netsoc_csrbankarray_interface0_bank_bus_we) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 4'd13));
-assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp3_we = ((vns_netsoc_csrbankarray_csrbank0_sel & (~vns_netsoc_csrbankarray_interface0_bank_bus_we)) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 4'd13));
-assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp2_r = vns_netsoc_csrbankarray_interface0_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp2_re = ((vns_netsoc_csrbankarray_csrbank0_sel & vns_netsoc_csrbankarray_interface0_bank_bus_we) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 4'd14));
-assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp2_we = ((vns_netsoc_csrbankarray_csrbank0_sel & (~vns_netsoc_csrbankarray_interface0_bank_bus_we)) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 4'd14));
-assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp1_r = vns_netsoc_csrbankarray_interface0_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp1_re = ((vns_netsoc_csrbankarray_csrbank0_sel & vns_netsoc_csrbankarray_interface0_bank_bus_we) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 4'd15));
-assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp1_we = ((vns_netsoc_csrbankarray_csrbank0_sel & (~vns_netsoc_csrbankarray_interface0_bank_bus_we)) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 4'd15));
-assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp0_r = vns_netsoc_csrbankarray_interface0_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp0_re = ((vns_netsoc_csrbankarray_csrbank0_sel & vns_netsoc_csrbankarray_interface0_bank_bus_we) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 5'd16));
-assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp0_we = ((vns_netsoc_csrbankarray_csrbank0_sel & (~vns_netsoc_csrbankarray_interface0_bank_bus_we)) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 5'd16));
-assign vns_netsoc_csrbankarray_csrbank0_timer_time7_w = soc_netsoc_cpu_time_status[63:56];
-assign vns_netsoc_csrbankarray_csrbank0_timer_time6_w = soc_netsoc_cpu_time_status[55:48];
-assign vns_netsoc_csrbankarray_csrbank0_timer_time5_w = soc_netsoc_cpu_time_status[47:40];
-assign vns_netsoc_csrbankarray_csrbank0_timer_time4_w = soc_netsoc_cpu_time_status[39:32];
-assign vns_netsoc_csrbankarray_csrbank0_timer_time3_w = soc_netsoc_cpu_time_status[31:24];
-assign vns_netsoc_csrbankarray_csrbank0_timer_time2_w = soc_netsoc_cpu_time_status[23:16];
-assign vns_netsoc_csrbankarray_csrbank0_timer_time1_w = soc_netsoc_cpu_time_status[15:8];
-assign vns_netsoc_csrbankarray_csrbank0_timer_time0_w = soc_netsoc_cpu_time_status[7:0];
-assign soc_netsoc_cpu_time_we = vns_netsoc_csrbankarray_csrbank0_timer_time0_we;
-assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp7_w = soc_netsoc_cpu_time_cmp_storage[63:56];
-assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp6_w = soc_netsoc_cpu_time_cmp_storage[55:48];
-assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp5_w = soc_netsoc_cpu_time_cmp_storage[47:40];
-assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp4_w = soc_netsoc_cpu_time_cmp_storage[39:32];
-assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp3_w = soc_netsoc_cpu_time_cmp_storage[31:24];
-assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp2_w = soc_netsoc_cpu_time_cmp_storage[23:16];
-assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp1_w = soc_netsoc_cpu_time_cmp_storage[15:8];
-assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp0_w = soc_netsoc_cpu_time_cmp_storage[7:0];
-assign vns_netsoc_csrbankarray_csrbank1_sel = (vns_netsoc_csrbankarray_interface1_bank_bus_adr[13:9] == 1'd0);
-assign soc_netsoc_ctrl_reset_reset_r = vns_netsoc_csrbankarray_interface1_bank_bus_dat_w[0];
-assign soc_netsoc_ctrl_reset_reset_re = ((vns_netsoc_csrbankarray_csrbank1_sel & vns_netsoc_csrbankarray_interface1_bank_bus_we) & (vns_netsoc_csrbankarray_interface1_bank_bus_adr[3:0] == 1'd0));
-assign soc_netsoc_ctrl_reset_reset_we = ((vns_netsoc_csrbankarray_csrbank1_sel & (~vns_netsoc_csrbankarray_interface1_bank_bus_we)) & (vns_netsoc_csrbankarray_interface1_bank_bus_adr[3:0] == 1'd0));
-assign vns_netsoc_csrbankarray_csrbank1_scratch3_r = vns_netsoc_csrbankarray_interface1_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank1_scratch3_re = ((vns_netsoc_csrbankarray_csrbank1_sel & vns_netsoc_csrbankarray_interface1_bank_bus_we) & (vns_netsoc_csrbankarray_interface1_bank_bus_adr[3:0] == 1'd1));
-assign vns_netsoc_csrbankarray_csrbank1_scratch3_we = ((vns_netsoc_csrbankarray_csrbank1_sel & (~vns_netsoc_csrbankarray_interface1_bank_bus_we)) & (vns_netsoc_csrbankarray_interface1_bank_bus_adr[3:0] == 1'd1));
-assign vns_netsoc_csrbankarray_csrbank1_scratch2_r = vns_netsoc_csrbankarray_interface1_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank1_scratch2_re = ((vns_netsoc_csrbankarray_csrbank1_sel & vns_netsoc_csrbankarray_interface1_bank_bus_we) & (vns_netsoc_csrbankarray_interface1_bank_bus_adr[3:0] == 2'd2));
-assign vns_netsoc_csrbankarray_csrbank1_scratch2_we = ((vns_netsoc_csrbankarray_csrbank1_sel & (~vns_netsoc_csrbankarray_interface1_bank_bus_we)) & (vns_netsoc_csrbankarray_interface1_bank_bus_adr[3:0] == 2'd2));
-assign vns_netsoc_csrbankarray_csrbank1_scratch1_r = vns_netsoc_csrbankarray_interface1_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank1_scratch1_re = ((vns_netsoc_csrbankarray_csrbank1_sel & vns_netsoc_csrbankarray_interface1_bank_bus_we) & (vns_netsoc_csrbankarray_interface1_bank_bus_adr[3:0] == 2'd3));
-assign vns_netsoc_csrbankarray_csrbank1_scratch1_we = ((vns_netsoc_csrbankarray_csrbank1_sel & (~vns_netsoc_csrbankarray_interface1_bank_bus_we)) & (vns_netsoc_csrbankarray_interface1_bank_bus_adr[3:0] == 2'd3));
-assign vns_netsoc_csrbankarray_csrbank1_scratch0_r = vns_netsoc_csrbankarray_interface1_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank1_scratch0_re = ((vns_netsoc_csrbankarray_csrbank1_sel & vns_netsoc_csrbankarray_interface1_bank_bus_we) & (vns_netsoc_csrbankarray_interface1_bank_bus_adr[3:0] == 3'd4));
-assign vns_netsoc_csrbankarray_csrbank1_scratch0_we = ((vns_netsoc_csrbankarray_csrbank1_sel & (~vns_netsoc_csrbankarray_interface1_bank_bus_we)) & (vns_netsoc_csrbankarray_interface1_bank_bus_adr[3:0] == 3'd4));
-assign vns_netsoc_csrbankarray_csrbank1_bus_errors3_r = vns_netsoc_csrbankarray_interface1_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank1_bus_errors3_re = ((vns_netsoc_csrbankarray_csrbank1_sel & vns_netsoc_csrbankarray_interface1_bank_bus_we) & (vns_netsoc_csrbankarray_interface1_bank_bus_adr[3:0] == 3'd5));
-assign vns_netsoc_csrbankarray_csrbank1_bus_errors3_we = ((vns_netsoc_csrbankarray_csrbank1_sel & (~vns_netsoc_csrbankarray_interface1_bank_bus_we)) & (vns_netsoc_csrbankarray_interface1_bank_bus_adr[3:0] == 3'd5));
-assign vns_netsoc_csrbankarray_csrbank1_bus_errors2_r = vns_netsoc_csrbankarray_interface1_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank1_bus_errors2_re = ((vns_netsoc_csrbankarray_csrbank1_sel & vns_netsoc_csrbankarray_interface1_bank_bus_we) & (vns_netsoc_csrbankarray_interface1_bank_bus_adr[3:0] == 3'd6));
-assign vns_netsoc_csrbankarray_csrbank1_bus_errors2_we = ((vns_netsoc_csrbankarray_csrbank1_sel & (~vns_netsoc_csrbankarray_interface1_bank_bus_we)) & (vns_netsoc_csrbankarray_interface1_bank_bus_adr[3:0] == 3'd6));
-assign vns_netsoc_csrbankarray_csrbank1_bus_errors1_r = vns_netsoc_csrbankarray_interface1_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank1_bus_errors1_re = ((vns_netsoc_csrbankarray_csrbank1_sel & vns_netsoc_csrbankarray_interface1_bank_bus_we) & (vns_netsoc_csrbankarray_interface1_bank_bus_adr[3:0] == 3'd7));
-assign vns_netsoc_csrbankarray_csrbank1_bus_errors1_we = ((vns_netsoc_csrbankarray_csrbank1_sel & (~vns_netsoc_csrbankarray_interface1_bank_bus_we)) & (vns_netsoc_csrbankarray_interface1_bank_bus_adr[3:0] == 3'd7));
-assign vns_netsoc_csrbankarray_csrbank1_bus_errors0_r = vns_netsoc_csrbankarray_interface1_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank1_bus_errors0_re = ((vns_netsoc_csrbankarray_csrbank1_sel & vns_netsoc_csrbankarray_interface1_bank_bus_we) & (vns_netsoc_csrbankarray_interface1_bank_bus_adr[3:0] == 4'd8));
-assign vns_netsoc_csrbankarray_csrbank1_bus_errors0_we = ((vns_netsoc_csrbankarray_csrbank1_sel & (~vns_netsoc_csrbankarray_interface1_bank_bus_we)) & (vns_netsoc_csrbankarray_interface1_bank_bus_adr[3:0] == 4'd8));
-assign vns_netsoc_csrbankarray_csrbank1_scratch3_w = soc_netsoc_ctrl_storage[31:24];
-assign vns_netsoc_csrbankarray_csrbank1_scratch2_w = soc_netsoc_ctrl_storage[23:16];
-assign vns_netsoc_csrbankarray_csrbank1_scratch1_w = soc_netsoc_ctrl_storage[15:8];
-assign vns_netsoc_csrbankarray_csrbank1_scratch0_w = soc_netsoc_ctrl_storage[7:0];
-assign vns_netsoc_csrbankarray_csrbank1_bus_errors3_w = soc_netsoc_ctrl_bus_errors_status[31:24];
-assign vns_netsoc_csrbankarray_csrbank1_bus_errors2_w = soc_netsoc_ctrl_bus_errors_status[23:16];
-assign vns_netsoc_csrbankarray_csrbank1_bus_errors1_w = soc_netsoc_ctrl_bus_errors_status[15:8];
-assign vns_netsoc_csrbankarray_csrbank1_bus_errors0_w = soc_netsoc_ctrl_bus_errors_status[7:0];
-assign soc_netsoc_ctrl_bus_errors_we = vns_netsoc_csrbankarray_csrbank1_bus_errors0_we;
-assign vns_netsoc_csrbankarray_csrbank2_sel = (vns_netsoc_csrbankarray_interface2_bank_bus_adr[13:9] == 4'd11);
-assign vns_netsoc_csrbankarray_csrbank2_half_sys8x_taps0_r = vns_netsoc_csrbankarray_interface2_bank_bus_dat_w[4:0];
-assign vns_netsoc_csrbankarray_csrbank2_half_sys8x_taps0_re = ((vns_netsoc_csrbankarray_csrbank2_sel & vns_netsoc_csrbankarray_interface2_bank_bus_we) & (vns_netsoc_csrbankarray_interface2_bank_bus_adr[2:0] == 1'd0));
-assign vns_netsoc_csrbankarray_csrbank2_half_sys8x_taps0_we = ((vns_netsoc_csrbankarray_csrbank2_sel & (~vns_netsoc_csrbankarray_interface2_bank_bus_we)) & (vns_netsoc_csrbankarray_interface2_bank_bus_adr[2:0] == 1'd0));
-assign soc_a7ddrphy_cdly_rst_r = vns_netsoc_csrbankarray_interface2_bank_bus_dat_w[0];
-assign soc_a7ddrphy_cdly_rst_re = ((vns_netsoc_csrbankarray_csrbank2_sel & vns_netsoc_csrbankarray_interface2_bank_bus_we) & (vns_netsoc_csrbankarray_interface2_bank_bus_adr[2:0] == 1'd1));
-assign soc_a7ddrphy_cdly_rst_we = ((vns_netsoc_csrbankarray_csrbank2_sel & (~vns_netsoc_csrbankarray_interface2_bank_bus_we)) & (vns_netsoc_csrbankarray_interface2_bank_bus_adr[2:0] == 1'd1));
-assign soc_a7ddrphy_cdly_inc_r = vns_netsoc_csrbankarray_interface2_bank_bus_dat_w[0];
-assign soc_a7ddrphy_cdly_inc_re = ((vns_netsoc_csrbankarray_csrbank2_sel & vns_netsoc_csrbankarray_interface2_bank_bus_we) & (vns_netsoc_csrbankarray_interface2_bank_bus_adr[2:0] == 2'd2));
-assign soc_a7ddrphy_cdly_inc_we = ((vns_netsoc_csrbankarray_csrbank2_sel & (~vns_netsoc_csrbankarray_interface2_bank_bus_we)) & (vns_netsoc_csrbankarray_interface2_bank_bus_adr[2:0] == 2'd2));
-assign vns_netsoc_csrbankarray_csrbank2_dly_sel0_r = vns_netsoc_csrbankarray_interface2_bank_bus_dat_w[1:0];
-assign vns_netsoc_csrbankarray_csrbank2_dly_sel0_re = ((vns_netsoc_csrbankarray_csrbank2_sel & vns_netsoc_csrbankarray_interface2_bank_bus_we) & (vns_netsoc_csrbankarray_interface2_bank_bus_adr[2:0] == 2'd3));
-assign vns_netsoc_csrbankarray_csrbank2_dly_sel0_we = ((vns_netsoc_csrbankarray_csrbank2_sel & (~vns_netsoc_csrbankarray_interface2_bank_bus_we)) & (vns_netsoc_csrbankarray_interface2_bank_bus_adr[2:0] == 2'd3));
-assign soc_a7ddrphy_rdly_dq_rst_r = vns_netsoc_csrbankarray_interface2_bank_bus_dat_w[0];
-assign soc_a7ddrphy_rdly_dq_rst_re = ((vns_netsoc_csrbankarray_csrbank2_sel & vns_netsoc_csrbankarray_interface2_bank_bus_we) & (vns_netsoc_csrbankarray_interface2_bank_bus_adr[2:0] == 3'd4));
-assign soc_a7ddrphy_rdly_dq_rst_we = ((vns_netsoc_csrbankarray_csrbank2_sel & (~vns_netsoc_csrbankarray_interface2_bank_bus_we)) & (vns_netsoc_csrbankarray_interface2_bank_bus_adr[2:0] == 3'd4));
-assign soc_a7ddrphy_rdly_dq_inc_r = vns_netsoc_csrbankarray_interface2_bank_bus_dat_w[0];
-assign soc_a7ddrphy_rdly_dq_inc_re = ((vns_netsoc_csrbankarray_csrbank2_sel & vns_netsoc_csrbankarray_interface2_bank_bus_we) & (vns_netsoc_csrbankarray_interface2_bank_bus_adr[2:0] == 3'd5));
-assign soc_a7ddrphy_rdly_dq_inc_we = ((vns_netsoc_csrbankarray_csrbank2_sel & (~vns_netsoc_csrbankarray_interface2_bank_bus_we)) & (vns_netsoc_csrbankarray_interface2_bank_bus_adr[2:0] == 3'd5));
-assign soc_a7ddrphy_rdly_dq_bitslip_rst_r = vns_netsoc_csrbankarray_interface2_bank_bus_dat_w[0];
-assign soc_a7ddrphy_rdly_dq_bitslip_rst_re = ((vns_netsoc_csrbankarray_csrbank2_sel & vns_netsoc_csrbankarray_interface2_bank_bus_we) & (vns_netsoc_csrbankarray_interface2_bank_bus_adr[2:0] == 3'd6));
-assign soc_a7ddrphy_rdly_dq_bitslip_rst_we = ((vns_netsoc_csrbankarray_csrbank2_sel & (~vns_netsoc_csrbankarray_interface2_bank_bus_we)) & (vns_netsoc_csrbankarray_interface2_bank_bus_adr[2:0] == 3'd6));
-assign soc_a7ddrphy_rdly_dq_bitslip_r = vns_netsoc_csrbankarray_interface2_bank_bus_dat_w[0];
-assign soc_a7ddrphy_rdly_dq_bitslip_re = ((vns_netsoc_csrbankarray_csrbank2_sel & vns_netsoc_csrbankarray_interface2_bank_bus_we) & (vns_netsoc_csrbankarray_interface2_bank_bus_adr[2:0] == 3'd7));
-assign soc_a7ddrphy_rdly_dq_bitslip_we = ((vns_netsoc_csrbankarray_csrbank2_sel & (~vns_netsoc_csrbankarray_interface2_bank_bus_we)) & (vns_netsoc_csrbankarray_interface2_bank_bus_adr[2:0] == 3'd7));
-assign vns_netsoc_csrbankarray_csrbank2_half_sys8x_taps0_w = soc_a7ddrphy_half_sys8x_taps_storage[4:0];
-assign vns_netsoc_csrbankarray_csrbank2_dly_sel0_w = soc_a7ddrphy_dly_sel_storage[1:0];
-assign vns_netsoc_csrbankarray_csrbank3_sel = (vns_netsoc_csrbankarray_interface3_bank_bus_adr[13:9] == 4'd15);
-assign vns_netsoc_csrbankarray_csrbank3_sram_writer_slot_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[0];
-assign vns_netsoc_csrbankarray_csrbank3_sram_writer_slot_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 1'd0));
-assign vns_netsoc_csrbankarray_csrbank3_sram_writer_slot_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 1'd0));
-assign vns_netsoc_csrbankarray_csrbank3_sram_writer_length3_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank3_sram_writer_length3_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 1'd1));
-assign vns_netsoc_csrbankarray_csrbank3_sram_writer_length3_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 1'd1));
-assign vns_netsoc_csrbankarray_csrbank3_sram_writer_length2_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank3_sram_writer_length2_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 2'd2));
-assign vns_netsoc_csrbankarray_csrbank3_sram_writer_length2_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 2'd2));
-assign vns_netsoc_csrbankarray_csrbank3_sram_writer_length1_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank3_sram_writer_length1_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 2'd3));
-assign vns_netsoc_csrbankarray_csrbank3_sram_writer_length1_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 2'd3));
-assign vns_netsoc_csrbankarray_csrbank3_sram_writer_length0_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank3_sram_writer_length0_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 3'd4));
-assign vns_netsoc_csrbankarray_csrbank3_sram_writer_length0_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 3'd4));
-assign vns_netsoc_csrbankarray_csrbank3_sram_writer_errors3_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank3_sram_writer_errors3_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 3'd5));
-assign vns_netsoc_csrbankarray_csrbank3_sram_writer_errors3_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 3'd5));
-assign vns_netsoc_csrbankarray_csrbank3_sram_writer_errors2_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank3_sram_writer_errors2_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 3'd6));
-assign vns_netsoc_csrbankarray_csrbank3_sram_writer_errors2_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 3'd6));
-assign vns_netsoc_csrbankarray_csrbank3_sram_writer_errors1_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank3_sram_writer_errors1_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 3'd7));
-assign vns_netsoc_csrbankarray_csrbank3_sram_writer_errors1_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 3'd7));
-assign vns_netsoc_csrbankarray_csrbank3_sram_writer_errors0_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank3_sram_writer_errors0_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 4'd8));
-assign vns_netsoc_csrbankarray_csrbank3_sram_writer_errors0_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 4'd8));
-assign soc_writer_status_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[0];
-assign soc_writer_status_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 4'd9));
-assign soc_writer_status_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 4'd9));
-assign soc_writer_pending_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[0];
-assign soc_writer_pending_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 4'd10));
-assign soc_writer_pending_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 4'd10));
-assign vns_netsoc_csrbankarray_csrbank3_sram_writer_ev_enable0_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[0];
-assign vns_netsoc_csrbankarray_csrbank3_sram_writer_ev_enable0_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 4'd11));
-assign vns_netsoc_csrbankarray_csrbank3_sram_writer_ev_enable0_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 4'd11));
-assign soc_reader_start_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[0];
-assign soc_reader_start_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 4'd12));
-assign soc_reader_start_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 4'd12));
-assign vns_netsoc_csrbankarray_csrbank3_sram_reader_ready_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[0];
-assign vns_netsoc_csrbankarray_csrbank3_sram_reader_ready_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 4'd13));
-assign vns_netsoc_csrbankarray_csrbank3_sram_reader_ready_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 4'd13));
-assign vns_netsoc_csrbankarray_csrbank3_sram_reader_level_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[1:0];
-assign vns_netsoc_csrbankarray_csrbank3_sram_reader_level_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 4'd14));
-assign vns_netsoc_csrbankarray_csrbank3_sram_reader_level_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 4'd14));
-assign vns_netsoc_csrbankarray_csrbank3_sram_reader_slot0_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[0];
-assign vns_netsoc_csrbankarray_csrbank3_sram_reader_slot0_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 4'd15));
-assign vns_netsoc_csrbankarray_csrbank3_sram_reader_slot0_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 4'd15));
-assign vns_netsoc_csrbankarray_csrbank3_sram_reader_length1_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[2:0];
-assign vns_netsoc_csrbankarray_csrbank3_sram_reader_length1_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 5'd16));
-assign vns_netsoc_csrbankarray_csrbank3_sram_reader_length1_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 5'd16));
-assign vns_netsoc_csrbankarray_csrbank3_sram_reader_length0_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank3_sram_reader_length0_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 5'd17));
-assign vns_netsoc_csrbankarray_csrbank3_sram_reader_length0_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 5'd17));
-assign soc_reader_eventmanager_status_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[0];
-assign soc_reader_eventmanager_status_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 5'd18));
-assign soc_reader_eventmanager_status_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 5'd18));
-assign soc_reader_eventmanager_pending_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[0];
-assign soc_reader_eventmanager_pending_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 5'd19));
-assign soc_reader_eventmanager_pending_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 5'd19));
-assign vns_netsoc_csrbankarray_csrbank3_sram_reader_ev_enable0_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[0];
-assign vns_netsoc_csrbankarray_csrbank3_sram_reader_ev_enable0_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 5'd20));
-assign vns_netsoc_csrbankarray_csrbank3_sram_reader_ev_enable0_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 5'd20));
-assign vns_netsoc_csrbankarray_csrbank3_preamble_crc_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[0];
-assign vns_netsoc_csrbankarray_csrbank3_preamble_crc_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 5'd21));
-assign vns_netsoc_csrbankarray_csrbank3_preamble_crc_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 5'd21));
-assign vns_netsoc_csrbankarray_csrbank3_preamble_errors3_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank3_preamble_errors3_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 5'd22));
-assign vns_netsoc_csrbankarray_csrbank3_preamble_errors3_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 5'd22));
-assign vns_netsoc_csrbankarray_csrbank3_preamble_errors2_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank3_preamble_errors2_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 5'd23));
-assign vns_netsoc_csrbankarray_csrbank3_preamble_errors2_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 5'd23));
-assign vns_netsoc_csrbankarray_csrbank3_preamble_errors1_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank3_preamble_errors1_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 5'd24));
-assign vns_netsoc_csrbankarray_csrbank3_preamble_errors1_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 5'd24));
-assign vns_netsoc_csrbankarray_csrbank3_preamble_errors0_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank3_preamble_errors0_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 5'd25));
-assign vns_netsoc_csrbankarray_csrbank3_preamble_errors0_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 5'd25));
-assign vns_netsoc_csrbankarray_csrbank3_crc_errors3_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank3_crc_errors3_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 5'd26));
-assign vns_netsoc_csrbankarray_csrbank3_crc_errors3_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 5'd26));
-assign vns_netsoc_csrbankarray_csrbank3_crc_errors2_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank3_crc_errors2_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 5'd27));
-assign vns_netsoc_csrbankarray_csrbank3_crc_errors2_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 5'd27));
-assign vns_netsoc_csrbankarray_csrbank3_crc_errors1_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank3_crc_errors1_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 5'd28));
-assign vns_netsoc_csrbankarray_csrbank3_crc_errors1_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 5'd28));
-assign vns_netsoc_csrbankarray_csrbank3_crc_errors0_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank3_crc_errors0_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 5'd29));
-assign vns_netsoc_csrbankarray_csrbank3_crc_errors0_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 5'd29));
-assign vns_netsoc_csrbankarray_csrbank3_sram_writer_slot_w = soc_writer_slot_status;
-assign soc_writer_slot_we = vns_netsoc_csrbankarray_csrbank3_sram_writer_slot_we;
-assign vns_netsoc_csrbankarray_csrbank3_sram_writer_length3_w = soc_writer_length_status[31:24];
-assign vns_netsoc_csrbankarray_csrbank3_sram_writer_length2_w = soc_writer_length_status[23:16];
-assign vns_netsoc_csrbankarray_csrbank3_sram_writer_length1_w = soc_writer_length_status[15:8];
-assign vns_netsoc_csrbankarray_csrbank3_sram_writer_length0_w = soc_writer_length_status[7:0];
-assign soc_writer_length_we = vns_netsoc_csrbankarray_csrbank3_sram_writer_length0_we;
-assign vns_netsoc_csrbankarray_csrbank3_sram_writer_errors3_w = soc_writer_errors_status[31:24];
-assign vns_netsoc_csrbankarray_csrbank3_sram_writer_errors2_w = soc_writer_errors_status[23:16];
-assign vns_netsoc_csrbankarray_csrbank3_sram_writer_errors1_w = soc_writer_errors_status[15:8];
-assign vns_netsoc_csrbankarray_csrbank3_sram_writer_errors0_w = soc_writer_errors_status[7:0];
-assign soc_writer_errors_we = vns_netsoc_csrbankarray_csrbank3_sram_writer_errors0_we;
-assign vns_netsoc_csrbankarray_csrbank3_sram_writer_ev_enable0_w = soc_writer_storage;
-assign vns_netsoc_csrbankarray_csrbank3_sram_reader_ready_w = soc_reader_ready_status;
-assign soc_reader_ready_we = vns_netsoc_csrbankarray_csrbank3_sram_reader_ready_we;
-assign vns_netsoc_csrbankarray_csrbank3_sram_reader_level_w = soc_reader_level_status[1:0];
-assign soc_reader_level_we = vns_netsoc_csrbankarray_csrbank3_sram_reader_level_we;
-assign vns_netsoc_csrbankarray_csrbank3_sram_reader_slot0_w = soc_reader_slot_storage;
-assign vns_netsoc_csrbankarray_csrbank3_sram_reader_length1_w = soc_reader_length_storage[10:8];
-assign vns_netsoc_csrbankarray_csrbank3_sram_reader_length0_w = soc_reader_length_storage[7:0];
-assign vns_netsoc_csrbankarray_csrbank3_sram_reader_ev_enable0_w = soc_reader_eventmanager_storage;
-assign vns_netsoc_csrbankarray_csrbank3_preamble_crc_w = soc_preamble_crc_status;
-assign soc_preamble_crc_we = vns_netsoc_csrbankarray_csrbank3_preamble_crc_we;
-assign vns_netsoc_csrbankarray_csrbank3_preamble_errors3_w = soc_preamble_errors_status[31:24];
-assign vns_netsoc_csrbankarray_csrbank3_preamble_errors2_w = soc_preamble_errors_status[23:16];
-assign vns_netsoc_csrbankarray_csrbank3_preamble_errors1_w = soc_preamble_errors_status[15:8];
-assign vns_netsoc_csrbankarray_csrbank3_preamble_errors0_w = soc_preamble_errors_status[7:0];
-assign soc_preamble_errors_we = vns_netsoc_csrbankarray_csrbank3_preamble_errors0_we;
-assign vns_netsoc_csrbankarray_csrbank3_crc_errors3_w = soc_crc_errors_status[31:24];
-assign vns_netsoc_csrbankarray_csrbank3_crc_errors2_w = soc_crc_errors_status[23:16];
-assign vns_netsoc_csrbankarray_csrbank3_crc_errors1_w = soc_crc_errors_status[15:8];
-assign vns_netsoc_csrbankarray_csrbank3_crc_errors0_w = soc_crc_errors_status[7:0];
-assign soc_crc_errors_we = vns_netsoc_csrbankarray_csrbank3_crc_errors0_we;
-assign vns_netsoc_csrbankarray_csrbank4_sel = (vns_netsoc_csrbankarray_interface4_bank_bus_adr[13:9] == 4'd14);
-assign vns_netsoc_csrbankarray_csrbank4_crg_reset0_r = vns_netsoc_csrbankarray_interface4_bank_bus_dat_w[0];
-assign vns_netsoc_csrbankarray_csrbank4_crg_reset0_re = ((vns_netsoc_csrbankarray_csrbank4_sel & vns_netsoc_csrbankarray_interface4_bank_bus_we) & (vns_netsoc_csrbankarray_interface4_bank_bus_adr[1:0] == 1'd0));
-assign vns_netsoc_csrbankarray_csrbank4_crg_reset0_we = ((vns_netsoc_csrbankarray_csrbank4_sel & (~vns_netsoc_csrbankarray_interface4_bank_bus_we)) & (vns_netsoc_csrbankarray_interface4_bank_bus_adr[1:0] == 1'd0));
-assign vns_netsoc_csrbankarray_csrbank4_mdio_w0_r = vns_netsoc_csrbankarray_interface4_bank_bus_dat_w[2:0];
-assign vns_netsoc_csrbankarray_csrbank4_mdio_w0_re = ((vns_netsoc_csrbankarray_csrbank4_sel & vns_netsoc_csrbankarray_interface4_bank_bus_we) & (vns_netsoc_csrbankarray_interface4_bank_bus_adr[1:0] == 1'd1));
-assign vns_netsoc_csrbankarray_csrbank4_mdio_w0_we = ((vns_netsoc_csrbankarray_csrbank4_sel & (~vns_netsoc_csrbankarray_interface4_bank_bus_we)) & (vns_netsoc_csrbankarray_interface4_bank_bus_adr[1:0] == 1'd1));
-assign vns_netsoc_csrbankarray_csrbank4_mdio_r_r = vns_netsoc_csrbankarray_interface4_bank_bus_dat_w[0];
-assign vns_netsoc_csrbankarray_csrbank4_mdio_r_re = ((vns_netsoc_csrbankarray_csrbank4_sel & vns_netsoc_csrbankarray_interface4_bank_bus_we) & (vns_netsoc_csrbankarray_interface4_bank_bus_adr[1:0] == 2'd2));
-assign vns_netsoc_csrbankarray_csrbank4_mdio_r_we = ((vns_netsoc_csrbankarray_csrbank4_sel & (~vns_netsoc_csrbankarray_interface4_bank_bus_we)) & (vns_netsoc_csrbankarray_interface4_bank_bus_adr[1:0] == 2'd2));
-assign vns_netsoc_csrbankarray_csrbank4_crg_reset0_w = soc_reset_storage;
-assign soc_mdc = soc_storage[0];
-assign soc_oe = soc_storage[1];
-assign soc_w = soc_storage[2];
-assign vns_netsoc_csrbankarray_csrbank4_mdio_w0_w = soc_storage[2:0];
-assign vns_netsoc_csrbankarray_csrbank4_mdio_r_w = soc_status;
-assign soc_we = vns_netsoc_csrbankarray_csrbank4_mdio_r_we;
-assign vns_netsoc_csrbankarray_sel = (vns_netsoc_csrbankarray_sram_bus_adr[13:9] == 3'd4);
-always @(*) begin
-	vns_netsoc_csrbankarray_sram_bus_dat_r <= 8'd0;
-	if (vns_netsoc_csrbankarray_sel_r) begin
-		vns_netsoc_csrbankarray_sram_bus_dat_r <= vns_netsoc_csrbankarray_dat_r;
-	end
-end
-assign vns_netsoc_csrbankarray_adr = vns_netsoc_csrbankarray_sram_bus_adr[2:0];
-assign vns_netsoc_csrbankarray_csrbank5_sel = (vns_netsoc_csrbankarray_interface5_bank_bus_adr[13:9] == 4'd8);
-assign vns_netsoc_csrbankarray_csrbank5_dfii_control0_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[3:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_control0_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 1'd0));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_control0_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 1'd0));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_command0_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[5:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_command0_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 1'd1));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_command0_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 1'd1));
-assign soc_netsoc_sdram_phaseinjector0_command_issue_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[0];
-assign soc_netsoc_sdram_phaseinjector0_command_issue_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 2'd2));
-assign soc_netsoc_sdram_phaseinjector0_command_issue_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 2'd2));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_address1_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[5:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_address1_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 2'd3));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_address1_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 2'd3));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_address0_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_address0_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 3'd4));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_address0_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 3'd4));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_baddress0_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[2:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_baddress0_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 3'd5));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_baddress0_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 3'd5));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata3_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata3_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 3'd6));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata3_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 3'd6));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata2_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata2_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 3'd7));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata2_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 3'd7));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata1_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata1_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 4'd8));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata1_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 4'd8));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata0_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata0_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 4'd9));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata0_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 4'd9));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata3_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata3_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 4'd10));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata3_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 4'd10));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata2_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata2_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 4'd11));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata2_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 4'd11));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata1_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata1_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 4'd12));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata1_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 4'd12));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata0_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata0_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 4'd13));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata0_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 4'd13));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_command0_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[5:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_command0_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 4'd14));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_command0_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 4'd14));
-assign soc_netsoc_sdram_phaseinjector1_command_issue_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[0];
-assign soc_netsoc_sdram_phaseinjector1_command_issue_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 4'd15));
-assign soc_netsoc_sdram_phaseinjector1_command_issue_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 4'd15));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_address1_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[5:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_address1_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd16));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_address1_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd16));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_address0_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_address0_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd17));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_address0_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd17));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_baddress0_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[2:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_baddress0_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd18));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_baddress0_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd18));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata3_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata3_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd19));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata3_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd19));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata2_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata2_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd20));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata2_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd20));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata1_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata1_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd21));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata1_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd21));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata0_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata0_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd22));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata0_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd22));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata3_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata3_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd23));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata3_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd23));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata2_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata2_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd24));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata2_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd24));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata1_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata1_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd25));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata1_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd25));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata0_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata0_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd26));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata0_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd26));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_command0_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[5:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_command0_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd27));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_command0_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd27));
-assign soc_netsoc_sdram_phaseinjector2_command_issue_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[0];
-assign soc_netsoc_sdram_phaseinjector2_command_issue_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd28));
-assign soc_netsoc_sdram_phaseinjector2_command_issue_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd28));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_address1_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[5:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_address1_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd29));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_address1_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd29));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_address0_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_address0_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd30));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_address0_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd30));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_baddress0_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[2:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_baddress0_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd31));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_baddress0_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd31));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata3_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata3_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd32));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata3_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd32));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata2_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata2_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd33));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata2_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd33));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata1_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata1_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd34));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata1_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd34));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata0_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata0_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd35));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata0_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd35));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata3_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata3_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd36));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata3_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd36));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata2_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata2_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd37));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata2_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd37));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata1_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata1_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd38));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata1_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd38));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata0_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata0_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd39));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata0_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd39));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_command0_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[5:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_command0_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd40));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_command0_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd40));
-assign soc_netsoc_sdram_phaseinjector3_command_issue_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[0];
-assign soc_netsoc_sdram_phaseinjector3_command_issue_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd41));
-assign soc_netsoc_sdram_phaseinjector3_command_issue_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd41));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_address1_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[5:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_address1_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd42));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_address1_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd42));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_address0_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_address0_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd43));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_address0_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd43));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_baddress0_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[2:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_baddress0_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd44));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_baddress0_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd44));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata3_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata3_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd45));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata3_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd45));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata2_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata2_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd46));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata2_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd46));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata1_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata1_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd47));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata1_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd47));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata0_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata0_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd48));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata0_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd48));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata3_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata3_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd49));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata3_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd49));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata2_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata2_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd50));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata2_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd50));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata1_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata1_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd51));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata1_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd51));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata0_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata0_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd52));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata0_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd52));
-assign soc_netsoc_sdram_bandwidth_update_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[0];
-assign soc_netsoc_sdram_bandwidth_update_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd53));
-assign soc_netsoc_sdram_bandwidth_update_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd53));
-assign vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nreads2_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nreads2_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd54));
-assign vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nreads2_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd54));
-assign vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nreads1_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nreads1_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd55));
-assign vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nreads1_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd55));
-assign vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nreads0_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nreads0_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd56));
-assign vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nreads0_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd56));
-assign vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nwrites2_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nwrites2_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd57));
-assign vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nwrites2_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd57));
-assign vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nwrites1_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nwrites1_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd58));
-assign vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nwrites1_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd58));
-assign vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nwrites0_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nwrites0_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd59));
-assign vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nwrites0_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd59));
-assign vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_data_width_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_data_width_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd60));
-assign vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_data_width_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd60));
-assign vns_netsoc_csrbankarray_csrbank5_dfii_control0_w = soc_netsoc_sdram_storage[3:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_command0_w = soc_netsoc_sdram_phaseinjector0_command_storage[5:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_address1_w = soc_netsoc_sdram_phaseinjector0_address_storage[13:8];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_address0_w = soc_netsoc_sdram_phaseinjector0_address_storage[7:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_baddress0_w = soc_netsoc_sdram_phaseinjector0_baddress_storage[2:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata3_w = soc_netsoc_sdram_phaseinjector0_wrdata_storage[31:24];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata2_w = soc_netsoc_sdram_phaseinjector0_wrdata_storage[23:16];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata1_w = soc_netsoc_sdram_phaseinjector0_wrdata_storage[15:8];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata0_w = soc_netsoc_sdram_phaseinjector0_wrdata_storage[7:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata3_w = soc_netsoc_sdram_phaseinjector0_status[31:24];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata2_w = soc_netsoc_sdram_phaseinjector0_status[23:16];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata1_w = soc_netsoc_sdram_phaseinjector0_status[15:8];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata0_w = soc_netsoc_sdram_phaseinjector0_status[7:0];
-assign soc_netsoc_sdram_phaseinjector0_we = vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata0_we;
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_command0_w = soc_netsoc_sdram_phaseinjector1_command_storage[5:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_address1_w = soc_netsoc_sdram_phaseinjector1_address_storage[13:8];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_address0_w = soc_netsoc_sdram_phaseinjector1_address_storage[7:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_baddress0_w = soc_netsoc_sdram_phaseinjector1_baddress_storage[2:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata3_w = soc_netsoc_sdram_phaseinjector1_wrdata_storage[31:24];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata2_w = soc_netsoc_sdram_phaseinjector1_wrdata_storage[23:16];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata1_w = soc_netsoc_sdram_phaseinjector1_wrdata_storage[15:8];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata0_w = soc_netsoc_sdram_phaseinjector1_wrdata_storage[7:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata3_w = soc_netsoc_sdram_phaseinjector1_status[31:24];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata2_w = soc_netsoc_sdram_phaseinjector1_status[23:16];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata1_w = soc_netsoc_sdram_phaseinjector1_status[15:8];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata0_w = soc_netsoc_sdram_phaseinjector1_status[7:0];
-assign soc_netsoc_sdram_phaseinjector1_we = vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata0_we;
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_command0_w = soc_netsoc_sdram_phaseinjector2_command_storage[5:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_address1_w = soc_netsoc_sdram_phaseinjector2_address_storage[13:8];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_address0_w = soc_netsoc_sdram_phaseinjector2_address_storage[7:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_baddress0_w = soc_netsoc_sdram_phaseinjector2_baddress_storage[2:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata3_w = soc_netsoc_sdram_phaseinjector2_wrdata_storage[31:24];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata2_w = soc_netsoc_sdram_phaseinjector2_wrdata_storage[23:16];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata1_w = soc_netsoc_sdram_phaseinjector2_wrdata_storage[15:8];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata0_w = soc_netsoc_sdram_phaseinjector2_wrdata_storage[7:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata3_w = soc_netsoc_sdram_phaseinjector2_status[31:24];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata2_w = soc_netsoc_sdram_phaseinjector2_status[23:16];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata1_w = soc_netsoc_sdram_phaseinjector2_status[15:8];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata0_w = soc_netsoc_sdram_phaseinjector2_status[7:0];
-assign soc_netsoc_sdram_phaseinjector2_we = vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata0_we;
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_command0_w = soc_netsoc_sdram_phaseinjector3_command_storage[5:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_address1_w = soc_netsoc_sdram_phaseinjector3_address_storage[13:8];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_address0_w = soc_netsoc_sdram_phaseinjector3_address_storage[7:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_baddress0_w = soc_netsoc_sdram_phaseinjector3_baddress_storage[2:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata3_w = soc_netsoc_sdram_phaseinjector3_wrdata_storage[31:24];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata2_w = soc_netsoc_sdram_phaseinjector3_wrdata_storage[23:16];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata1_w = soc_netsoc_sdram_phaseinjector3_wrdata_storage[15:8];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata0_w = soc_netsoc_sdram_phaseinjector3_wrdata_storage[7:0];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata3_w = soc_netsoc_sdram_phaseinjector3_status[31:24];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata2_w = soc_netsoc_sdram_phaseinjector3_status[23:16];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata1_w = soc_netsoc_sdram_phaseinjector3_status[15:8];
-assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata0_w = soc_netsoc_sdram_phaseinjector3_status[7:0];
-assign soc_netsoc_sdram_phaseinjector3_we = vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata0_we;
-assign vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nreads2_w = soc_netsoc_sdram_bandwidth_nreads_status[23:16];
-assign vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nreads1_w = soc_netsoc_sdram_bandwidth_nreads_status[15:8];
-assign vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nreads0_w = soc_netsoc_sdram_bandwidth_nreads_status[7:0];
-assign soc_netsoc_sdram_bandwidth_nreads_we = vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nreads0_we;
-assign vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nwrites2_w = soc_netsoc_sdram_bandwidth_nwrites_status[23:16];
-assign vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nwrites1_w = soc_netsoc_sdram_bandwidth_nwrites_status[15:8];
-assign vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nwrites0_w = soc_netsoc_sdram_bandwidth_nwrites_status[7:0];
-assign soc_netsoc_sdram_bandwidth_nwrites_we = vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nwrites0_we;
-assign vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_data_width_w = soc_netsoc_sdram_bandwidth_data_width_status[7:0];
-assign soc_netsoc_sdram_bandwidth_data_width_we = vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_data_width_we;
-assign vns_netsoc_csrbankarray_csrbank6_sel = (vns_netsoc_csrbankarray_interface6_bank_bus_adr[13:9] == 3'd5);
-assign vns_netsoc_csrbankarray_csrbank6_load3_r = vns_netsoc_csrbankarray_interface6_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank6_load3_re = ((vns_netsoc_csrbankarray_csrbank6_sel & vns_netsoc_csrbankarray_interface6_bank_bus_we) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 1'd0));
-assign vns_netsoc_csrbankarray_csrbank6_load3_we = ((vns_netsoc_csrbankarray_csrbank6_sel & (~vns_netsoc_csrbankarray_interface6_bank_bus_we)) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 1'd0));
-assign vns_netsoc_csrbankarray_csrbank6_load2_r = vns_netsoc_csrbankarray_interface6_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank6_load2_re = ((vns_netsoc_csrbankarray_csrbank6_sel & vns_netsoc_csrbankarray_interface6_bank_bus_we) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 1'd1));
-assign vns_netsoc_csrbankarray_csrbank6_load2_we = ((vns_netsoc_csrbankarray_csrbank6_sel & (~vns_netsoc_csrbankarray_interface6_bank_bus_we)) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 1'd1));
-assign vns_netsoc_csrbankarray_csrbank6_load1_r = vns_netsoc_csrbankarray_interface6_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank6_load1_re = ((vns_netsoc_csrbankarray_csrbank6_sel & vns_netsoc_csrbankarray_interface6_bank_bus_we) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 2'd2));
-assign vns_netsoc_csrbankarray_csrbank6_load1_we = ((vns_netsoc_csrbankarray_csrbank6_sel & (~vns_netsoc_csrbankarray_interface6_bank_bus_we)) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 2'd2));
-assign vns_netsoc_csrbankarray_csrbank6_load0_r = vns_netsoc_csrbankarray_interface6_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank6_load0_re = ((vns_netsoc_csrbankarray_csrbank6_sel & vns_netsoc_csrbankarray_interface6_bank_bus_we) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 2'd3));
-assign vns_netsoc_csrbankarray_csrbank6_load0_we = ((vns_netsoc_csrbankarray_csrbank6_sel & (~vns_netsoc_csrbankarray_interface6_bank_bus_we)) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 2'd3));
-assign vns_netsoc_csrbankarray_csrbank6_reload3_r = vns_netsoc_csrbankarray_interface6_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank6_reload3_re = ((vns_netsoc_csrbankarray_csrbank6_sel & vns_netsoc_csrbankarray_interface6_bank_bus_we) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 3'd4));
-assign vns_netsoc_csrbankarray_csrbank6_reload3_we = ((vns_netsoc_csrbankarray_csrbank6_sel & (~vns_netsoc_csrbankarray_interface6_bank_bus_we)) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 3'd4));
-assign vns_netsoc_csrbankarray_csrbank6_reload2_r = vns_netsoc_csrbankarray_interface6_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank6_reload2_re = ((vns_netsoc_csrbankarray_csrbank6_sel & vns_netsoc_csrbankarray_interface6_bank_bus_we) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 3'd5));
-assign vns_netsoc_csrbankarray_csrbank6_reload2_we = ((vns_netsoc_csrbankarray_csrbank6_sel & (~vns_netsoc_csrbankarray_interface6_bank_bus_we)) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 3'd5));
-assign vns_netsoc_csrbankarray_csrbank6_reload1_r = vns_netsoc_csrbankarray_interface6_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank6_reload1_re = ((vns_netsoc_csrbankarray_csrbank6_sel & vns_netsoc_csrbankarray_interface6_bank_bus_we) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 3'd6));
-assign vns_netsoc_csrbankarray_csrbank6_reload1_we = ((vns_netsoc_csrbankarray_csrbank6_sel & (~vns_netsoc_csrbankarray_interface6_bank_bus_we)) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 3'd6));
-assign vns_netsoc_csrbankarray_csrbank6_reload0_r = vns_netsoc_csrbankarray_interface6_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank6_reload0_re = ((vns_netsoc_csrbankarray_csrbank6_sel & vns_netsoc_csrbankarray_interface6_bank_bus_we) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 3'd7));
-assign vns_netsoc_csrbankarray_csrbank6_reload0_we = ((vns_netsoc_csrbankarray_csrbank6_sel & (~vns_netsoc_csrbankarray_interface6_bank_bus_we)) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 3'd7));
-assign vns_netsoc_csrbankarray_csrbank6_en0_r = vns_netsoc_csrbankarray_interface6_bank_bus_dat_w[0];
-assign vns_netsoc_csrbankarray_csrbank6_en0_re = ((vns_netsoc_csrbankarray_csrbank6_sel & vns_netsoc_csrbankarray_interface6_bank_bus_we) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 4'd8));
-assign vns_netsoc_csrbankarray_csrbank6_en0_we = ((vns_netsoc_csrbankarray_csrbank6_sel & (~vns_netsoc_csrbankarray_interface6_bank_bus_we)) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 4'd8));
-assign vns_netsoc_csrbankarray_csrbank6_update_value0_r = vns_netsoc_csrbankarray_interface6_bank_bus_dat_w[0];
-assign vns_netsoc_csrbankarray_csrbank6_update_value0_re = ((vns_netsoc_csrbankarray_csrbank6_sel & vns_netsoc_csrbankarray_interface6_bank_bus_we) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 4'd9));
-assign vns_netsoc_csrbankarray_csrbank6_update_value0_we = ((vns_netsoc_csrbankarray_csrbank6_sel & (~vns_netsoc_csrbankarray_interface6_bank_bus_we)) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 4'd9));
-assign vns_netsoc_csrbankarray_csrbank6_value3_r = vns_netsoc_csrbankarray_interface6_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank6_value3_re = ((vns_netsoc_csrbankarray_csrbank6_sel & vns_netsoc_csrbankarray_interface6_bank_bus_we) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 4'd10));
-assign vns_netsoc_csrbankarray_csrbank6_value3_we = ((vns_netsoc_csrbankarray_csrbank6_sel & (~vns_netsoc_csrbankarray_interface6_bank_bus_we)) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 4'd10));
-assign vns_netsoc_csrbankarray_csrbank6_value2_r = vns_netsoc_csrbankarray_interface6_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank6_value2_re = ((vns_netsoc_csrbankarray_csrbank6_sel & vns_netsoc_csrbankarray_interface6_bank_bus_we) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 4'd11));
-assign vns_netsoc_csrbankarray_csrbank6_value2_we = ((vns_netsoc_csrbankarray_csrbank6_sel & (~vns_netsoc_csrbankarray_interface6_bank_bus_we)) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 4'd11));
-assign vns_netsoc_csrbankarray_csrbank6_value1_r = vns_netsoc_csrbankarray_interface6_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank6_value1_re = ((vns_netsoc_csrbankarray_csrbank6_sel & vns_netsoc_csrbankarray_interface6_bank_bus_we) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 4'd12));
-assign vns_netsoc_csrbankarray_csrbank6_value1_we = ((vns_netsoc_csrbankarray_csrbank6_sel & (~vns_netsoc_csrbankarray_interface6_bank_bus_we)) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 4'd12));
-assign vns_netsoc_csrbankarray_csrbank6_value0_r = vns_netsoc_csrbankarray_interface6_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank6_value0_re = ((vns_netsoc_csrbankarray_csrbank6_sel & vns_netsoc_csrbankarray_interface6_bank_bus_we) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 4'd13));
-assign vns_netsoc_csrbankarray_csrbank6_value0_we = ((vns_netsoc_csrbankarray_csrbank6_sel & (~vns_netsoc_csrbankarray_interface6_bank_bus_we)) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 4'd13));
-assign soc_netsoc_timer0_eventmanager_status_r = vns_netsoc_csrbankarray_interface6_bank_bus_dat_w[0];
-assign soc_netsoc_timer0_eventmanager_status_re = ((vns_netsoc_csrbankarray_csrbank6_sel & vns_netsoc_csrbankarray_interface6_bank_bus_we) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 4'd14));
-assign soc_netsoc_timer0_eventmanager_status_we = ((vns_netsoc_csrbankarray_csrbank6_sel & (~vns_netsoc_csrbankarray_interface6_bank_bus_we)) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 4'd14));
-assign soc_netsoc_timer0_eventmanager_pending_r = vns_netsoc_csrbankarray_interface6_bank_bus_dat_w[0];
-assign soc_netsoc_timer0_eventmanager_pending_re = ((vns_netsoc_csrbankarray_csrbank6_sel & vns_netsoc_csrbankarray_interface6_bank_bus_we) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 4'd15));
-assign soc_netsoc_timer0_eventmanager_pending_we = ((vns_netsoc_csrbankarray_csrbank6_sel & (~vns_netsoc_csrbankarray_interface6_bank_bus_we)) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 4'd15));
-assign vns_netsoc_csrbankarray_csrbank6_ev_enable0_r = vns_netsoc_csrbankarray_interface6_bank_bus_dat_w[0];
-assign vns_netsoc_csrbankarray_csrbank6_ev_enable0_re = ((vns_netsoc_csrbankarray_csrbank6_sel & vns_netsoc_csrbankarray_interface6_bank_bus_we) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 5'd16));
-assign vns_netsoc_csrbankarray_csrbank6_ev_enable0_we = ((vns_netsoc_csrbankarray_csrbank6_sel & (~vns_netsoc_csrbankarray_interface6_bank_bus_we)) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 5'd16));
-assign vns_netsoc_csrbankarray_csrbank6_load3_w = soc_netsoc_timer0_load_storage[31:24];
-assign vns_netsoc_csrbankarray_csrbank6_load2_w = soc_netsoc_timer0_load_storage[23:16];
-assign vns_netsoc_csrbankarray_csrbank6_load1_w = soc_netsoc_timer0_load_storage[15:8];
-assign vns_netsoc_csrbankarray_csrbank6_load0_w = soc_netsoc_timer0_load_storage[7:0];
-assign vns_netsoc_csrbankarray_csrbank6_reload3_w = soc_netsoc_timer0_reload_storage[31:24];
-assign vns_netsoc_csrbankarray_csrbank6_reload2_w = soc_netsoc_timer0_reload_storage[23:16];
-assign vns_netsoc_csrbankarray_csrbank6_reload1_w = soc_netsoc_timer0_reload_storage[15:8];
-assign vns_netsoc_csrbankarray_csrbank6_reload0_w = soc_netsoc_timer0_reload_storage[7:0];
-assign vns_netsoc_csrbankarray_csrbank6_en0_w = soc_netsoc_timer0_en_storage;
-assign vns_netsoc_csrbankarray_csrbank6_update_value0_w = soc_netsoc_timer0_update_value_storage;
-assign vns_netsoc_csrbankarray_csrbank6_value3_w = soc_netsoc_timer0_value_status[31:24];
-assign vns_netsoc_csrbankarray_csrbank6_value2_w = soc_netsoc_timer0_value_status[23:16];
-assign vns_netsoc_csrbankarray_csrbank6_value1_w = soc_netsoc_timer0_value_status[15:8];
-assign vns_netsoc_csrbankarray_csrbank6_value0_w = soc_netsoc_timer0_value_status[7:0];
-assign soc_netsoc_timer0_value_we = vns_netsoc_csrbankarray_csrbank6_value0_we;
-assign vns_netsoc_csrbankarray_csrbank6_ev_enable0_w = soc_netsoc_timer0_eventmanager_storage;
-assign vns_netsoc_csrbankarray_csrbank7_sel = (vns_netsoc_csrbankarray_interface7_bank_bus_adr[13:9] == 2'd3);
-assign soc_netsoc_uart_rxtx_r = vns_netsoc_csrbankarray_interface7_bank_bus_dat_w[7:0];
-assign soc_netsoc_uart_rxtx_re = ((vns_netsoc_csrbankarray_csrbank7_sel & vns_netsoc_csrbankarray_interface7_bank_bus_we) & (vns_netsoc_csrbankarray_interface7_bank_bus_adr[2:0] == 1'd0));
-assign soc_netsoc_uart_rxtx_we = ((vns_netsoc_csrbankarray_csrbank7_sel & (~vns_netsoc_csrbankarray_interface7_bank_bus_we)) & (vns_netsoc_csrbankarray_interface7_bank_bus_adr[2:0] == 1'd0));
-assign vns_netsoc_csrbankarray_csrbank7_txfull_r = vns_netsoc_csrbankarray_interface7_bank_bus_dat_w[0];
-assign vns_netsoc_csrbankarray_csrbank7_txfull_re = ((vns_netsoc_csrbankarray_csrbank7_sel & vns_netsoc_csrbankarray_interface7_bank_bus_we) & (vns_netsoc_csrbankarray_interface7_bank_bus_adr[2:0] == 1'd1));
-assign vns_netsoc_csrbankarray_csrbank7_txfull_we = ((vns_netsoc_csrbankarray_csrbank7_sel & (~vns_netsoc_csrbankarray_interface7_bank_bus_we)) & (vns_netsoc_csrbankarray_interface7_bank_bus_adr[2:0] == 1'd1));
-assign vns_netsoc_csrbankarray_csrbank7_rxempty_r = vns_netsoc_csrbankarray_interface7_bank_bus_dat_w[0];
-assign vns_netsoc_csrbankarray_csrbank7_rxempty_re = ((vns_netsoc_csrbankarray_csrbank7_sel & vns_netsoc_csrbankarray_interface7_bank_bus_we) & (vns_netsoc_csrbankarray_interface7_bank_bus_adr[2:0] == 2'd2));
-assign vns_netsoc_csrbankarray_csrbank7_rxempty_we = ((vns_netsoc_csrbankarray_csrbank7_sel & (~vns_netsoc_csrbankarray_interface7_bank_bus_we)) & (vns_netsoc_csrbankarray_interface7_bank_bus_adr[2:0] == 2'd2));
-assign soc_netsoc_uart_eventmanager_status_r = vns_netsoc_csrbankarray_interface7_bank_bus_dat_w[1:0];
-assign soc_netsoc_uart_eventmanager_status_re = ((vns_netsoc_csrbankarray_csrbank7_sel & vns_netsoc_csrbankarray_interface7_bank_bus_we) & (vns_netsoc_csrbankarray_interface7_bank_bus_adr[2:0] == 2'd3));
-assign soc_netsoc_uart_eventmanager_status_we = ((vns_netsoc_csrbankarray_csrbank7_sel & (~vns_netsoc_csrbankarray_interface7_bank_bus_we)) & (vns_netsoc_csrbankarray_interface7_bank_bus_adr[2:0] == 2'd3));
-assign soc_netsoc_uart_eventmanager_pending_r = vns_netsoc_csrbankarray_interface7_bank_bus_dat_w[1:0];
-assign soc_netsoc_uart_eventmanager_pending_re = ((vns_netsoc_csrbankarray_csrbank7_sel & vns_netsoc_csrbankarray_interface7_bank_bus_we) & (vns_netsoc_csrbankarray_interface7_bank_bus_adr[2:0] == 3'd4));
-assign soc_netsoc_uart_eventmanager_pending_we = ((vns_netsoc_csrbankarray_csrbank7_sel & (~vns_netsoc_csrbankarray_interface7_bank_bus_we)) & (vns_netsoc_csrbankarray_interface7_bank_bus_adr[2:0] == 3'd4));
-assign vns_netsoc_csrbankarray_csrbank7_ev_enable0_r = vns_netsoc_csrbankarray_interface7_bank_bus_dat_w[1:0];
-assign vns_netsoc_csrbankarray_csrbank7_ev_enable0_re = ((vns_netsoc_csrbankarray_csrbank7_sel & vns_netsoc_csrbankarray_interface7_bank_bus_we) & (vns_netsoc_csrbankarray_interface7_bank_bus_adr[2:0] == 3'd5));
-assign vns_netsoc_csrbankarray_csrbank7_ev_enable0_we = ((vns_netsoc_csrbankarray_csrbank7_sel & (~vns_netsoc_csrbankarray_interface7_bank_bus_we)) & (vns_netsoc_csrbankarray_interface7_bank_bus_adr[2:0] == 3'd5));
-assign vns_netsoc_csrbankarray_csrbank7_txfull_w = soc_netsoc_uart_txfull_status;
-assign soc_netsoc_uart_txfull_we = vns_netsoc_csrbankarray_csrbank7_txfull_we;
-assign vns_netsoc_csrbankarray_csrbank7_rxempty_w = soc_netsoc_uart_rxempty_status;
-assign soc_netsoc_uart_rxempty_we = vns_netsoc_csrbankarray_csrbank7_rxempty_we;
-assign vns_netsoc_csrbankarray_csrbank7_ev_enable0_w = soc_netsoc_uart_eventmanager_storage[1:0];
-assign vns_netsoc_csrbankarray_csrbank8_sel = (vns_netsoc_csrbankarray_interface8_bank_bus_adr[13:9] == 2'd2);
-assign vns_netsoc_csrbankarray_csrbank8_tuning_word3_r = vns_netsoc_csrbankarray_interface8_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank8_tuning_word3_re = ((vns_netsoc_csrbankarray_csrbank8_sel & vns_netsoc_csrbankarray_interface8_bank_bus_we) & (vns_netsoc_csrbankarray_interface8_bank_bus_adr[1:0] == 1'd0));
-assign vns_netsoc_csrbankarray_csrbank8_tuning_word3_we = ((vns_netsoc_csrbankarray_csrbank8_sel & (~vns_netsoc_csrbankarray_interface8_bank_bus_we)) & (vns_netsoc_csrbankarray_interface8_bank_bus_adr[1:0] == 1'd0));
-assign vns_netsoc_csrbankarray_csrbank8_tuning_word2_r = vns_netsoc_csrbankarray_interface8_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank8_tuning_word2_re = ((vns_netsoc_csrbankarray_csrbank8_sel & vns_netsoc_csrbankarray_interface8_bank_bus_we) & (vns_netsoc_csrbankarray_interface8_bank_bus_adr[1:0] == 1'd1));
-assign vns_netsoc_csrbankarray_csrbank8_tuning_word2_we = ((vns_netsoc_csrbankarray_csrbank8_sel & (~vns_netsoc_csrbankarray_interface8_bank_bus_we)) & (vns_netsoc_csrbankarray_interface8_bank_bus_adr[1:0] == 1'd1));
-assign vns_netsoc_csrbankarray_csrbank8_tuning_word1_r = vns_netsoc_csrbankarray_interface8_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank8_tuning_word1_re = ((vns_netsoc_csrbankarray_csrbank8_sel & vns_netsoc_csrbankarray_interface8_bank_bus_we) & (vns_netsoc_csrbankarray_interface8_bank_bus_adr[1:0] == 2'd2));
-assign vns_netsoc_csrbankarray_csrbank8_tuning_word1_we = ((vns_netsoc_csrbankarray_csrbank8_sel & (~vns_netsoc_csrbankarray_interface8_bank_bus_we)) & (vns_netsoc_csrbankarray_interface8_bank_bus_adr[1:0] == 2'd2));
-assign vns_netsoc_csrbankarray_csrbank8_tuning_word0_r = vns_netsoc_csrbankarray_interface8_bank_bus_dat_w[7:0];
-assign vns_netsoc_csrbankarray_csrbank8_tuning_word0_re = ((vns_netsoc_csrbankarray_csrbank8_sel & vns_netsoc_csrbankarray_interface8_bank_bus_we) & (vns_netsoc_csrbankarray_interface8_bank_bus_adr[1:0] == 2'd3));
-assign vns_netsoc_csrbankarray_csrbank8_tuning_word0_we = ((vns_netsoc_csrbankarray_csrbank8_sel & (~vns_netsoc_csrbankarray_interface8_bank_bus_we)) & (vns_netsoc_csrbankarray_interface8_bank_bus_adr[1:0] == 2'd3));
-assign vns_netsoc_csrbankarray_csrbank8_tuning_word3_w = soc_netsoc_uart_phy_storage[31:24];
-assign vns_netsoc_csrbankarray_csrbank8_tuning_word2_w = soc_netsoc_uart_phy_storage[23:16];
-assign vns_netsoc_csrbankarray_csrbank8_tuning_word1_w = soc_netsoc_uart_phy_storage[15:8];
-assign vns_netsoc_csrbankarray_csrbank8_tuning_word0_w = soc_netsoc_uart_phy_storage[7:0];
-assign vns_netsoc_csrcon_adr = soc_netsoc_interface_adr;
-assign vns_netsoc_csrcon_we = soc_netsoc_interface_we;
-assign vns_netsoc_csrcon_dat_w = soc_netsoc_interface_dat_w;
-assign soc_netsoc_interface_dat_r = vns_netsoc_csrcon_dat_r;
-assign vns_netsoc_csrbankarray_interface0_bank_bus_adr = vns_netsoc_csrcon_adr;
-assign vns_netsoc_csrbankarray_interface1_bank_bus_adr = vns_netsoc_csrcon_adr;
-assign vns_netsoc_csrbankarray_interface2_bank_bus_adr = vns_netsoc_csrcon_adr;
-assign vns_netsoc_csrbankarray_interface3_bank_bus_adr = vns_netsoc_csrcon_adr;
-assign vns_netsoc_csrbankarray_interface4_bank_bus_adr = vns_netsoc_csrcon_adr;
-assign vns_netsoc_csrbankarray_interface5_bank_bus_adr = vns_netsoc_csrcon_adr;
-assign vns_netsoc_csrbankarray_interface6_bank_bus_adr = vns_netsoc_csrcon_adr;
-assign vns_netsoc_csrbankarray_interface7_bank_bus_adr = vns_netsoc_csrcon_adr;
-assign vns_netsoc_csrbankarray_interface8_bank_bus_adr = vns_netsoc_csrcon_adr;
-assign vns_netsoc_csrbankarray_sram_bus_adr = vns_netsoc_csrcon_adr;
-assign vns_netsoc_csrbankarray_interface0_bank_bus_we = vns_netsoc_csrcon_we;
-assign vns_netsoc_csrbankarray_interface1_bank_bus_we = vns_netsoc_csrcon_we;
-assign vns_netsoc_csrbankarray_interface2_bank_bus_we = vns_netsoc_csrcon_we;
-assign vns_netsoc_csrbankarray_interface3_bank_bus_we = vns_netsoc_csrcon_we;
-assign vns_netsoc_csrbankarray_interface4_bank_bus_we = vns_netsoc_csrcon_we;
-assign vns_netsoc_csrbankarray_interface5_bank_bus_we = vns_netsoc_csrcon_we;
-assign vns_netsoc_csrbankarray_interface6_bank_bus_we = vns_netsoc_csrcon_we;
-assign vns_netsoc_csrbankarray_interface7_bank_bus_we = vns_netsoc_csrcon_we;
-assign vns_netsoc_csrbankarray_interface8_bank_bus_we = vns_netsoc_csrcon_we;
-assign vns_netsoc_csrbankarray_sram_bus_we = vns_netsoc_csrcon_we;
-assign vns_netsoc_csrbankarray_interface0_bank_bus_dat_w = vns_netsoc_csrcon_dat_w;
-assign vns_netsoc_csrbankarray_interface1_bank_bus_dat_w = vns_netsoc_csrcon_dat_w;
-assign vns_netsoc_csrbankarray_interface2_bank_bus_dat_w = vns_netsoc_csrcon_dat_w;
-assign vns_netsoc_csrbankarray_interface3_bank_bus_dat_w = vns_netsoc_csrcon_dat_w;
-assign vns_netsoc_csrbankarray_interface4_bank_bus_dat_w = vns_netsoc_csrcon_dat_w;
-assign vns_netsoc_csrbankarray_interface5_bank_bus_dat_w = vns_netsoc_csrcon_dat_w;
-assign vns_netsoc_csrbankarray_interface6_bank_bus_dat_w = vns_netsoc_csrcon_dat_w;
-assign vns_netsoc_csrbankarray_interface7_bank_bus_dat_w = vns_netsoc_csrcon_dat_w;
-assign vns_netsoc_csrbankarray_interface8_bank_bus_dat_w = vns_netsoc_csrcon_dat_w;
-assign vns_netsoc_csrbankarray_sram_bus_dat_w = vns_netsoc_csrcon_dat_w;
-assign vns_netsoc_csrcon_dat_r = (((((((((vns_netsoc_csrbankarray_interface0_bank_bus_dat_r | vns_netsoc_csrbankarray_interface1_bank_bus_dat_r) | vns_netsoc_csrbankarray_interface2_bank_bus_dat_r) | vns_netsoc_csrbankarray_interface3_bank_bus_dat_r) | vns_netsoc_csrbankarray_interface4_bank_bus_dat_r) | vns_netsoc_csrbankarray_interface5_bank_bus_dat_r) | vns_netsoc_csrbankarray_interface6_bank_bus_dat_r) | vns_netsoc_csrbankarray_interface7_bank_bus_dat_r) | vns_netsoc_csrbankarray_interface8_bank_bus_dat_r) | vns_netsoc_csrbankarray_sram_bus_dat_r);
-always @(*) begin
-	vns_rhs_array_muxed0 <= 1'd0;
-	case (soc_netsoc_sdram_choose_cmd_grant)
-		1'd0: begin
-			vns_rhs_array_muxed0 <= soc_netsoc_sdram_choose_cmd_valids[0];
-		end
-		1'd1: begin
-			vns_rhs_array_muxed0 <= soc_netsoc_sdram_choose_cmd_valids[1];
-		end
-		2'd2: begin
-			vns_rhs_array_muxed0 <= soc_netsoc_sdram_choose_cmd_valids[2];
-		end
-		2'd3: begin
-			vns_rhs_array_muxed0 <= soc_netsoc_sdram_choose_cmd_valids[3];
-		end
-		3'd4: begin
-			vns_rhs_array_muxed0 <= soc_netsoc_sdram_choose_cmd_valids[4];
-		end
-		3'd5: begin
-			vns_rhs_array_muxed0 <= soc_netsoc_sdram_choose_cmd_valids[5];
-		end
-		3'd6: begin
-			vns_rhs_array_muxed0 <= soc_netsoc_sdram_choose_cmd_valids[6];
-		end
-		default: begin
-			vns_rhs_array_muxed0 <= soc_netsoc_sdram_choose_cmd_valids[7];
-		end
-	endcase
-end
-always @(*) begin
-	vns_rhs_array_muxed1 <= 14'd0;
-	case (soc_netsoc_sdram_choose_cmd_grant)
-		1'd0: begin
-			vns_rhs_array_muxed1 <= soc_netsoc_sdram_bankmachine0_cmd_payload_a;
-		end
-		1'd1: begin
-			vns_rhs_array_muxed1 <= soc_netsoc_sdram_bankmachine1_cmd_payload_a;
-		end
-		2'd2: begin
-			vns_rhs_array_muxed1 <= soc_netsoc_sdram_bankmachine2_cmd_payload_a;
-		end
-		2'd3: begin
-			vns_rhs_array_muxed1 <= soc_netsoc_sdram_bankmachine3_cmd_payload_a;
-		end
-		3'd4: begin
-			vns_rhs_array_muxed1 <= soc_netsoc_sdram_bankmachine4_cmd_payload_a;
-		end
-		3'd5: begin
-			vns_rhs_array_muxed1 <= soc_netsoc_sdram_bankmachine5_cmd_payload_a;
-		end
-		3'd6: begin
-			vns_rhs_array_muxed1 <= soc_netsoc_sdram_bankmachine6_cmd_payload_a;
-		end
-		default: begin
-			vns_rhs_array_muxed1 <= soc_netsoc_sdram_bankmachine7_cmd_payload_a;
-		end
-	endcase
-end
-always @(*) begin
-	vns_rhs_array_muxed2 <= 3'd0;
-	case (soc_netsoc_sdram_choose_cmd_grant)
-		1'd0: begin
-			vns_rhs_array_muxed2 <= soc_netsoc_sdram_bankmachine0_cmd_payload_ba;
-		end
-		1'd1: begin
-			vns_rhs_array_muxed2 <= soc_netsoc_sdram_bankmachine1_cmd_payload_ba;
-		end
-		2'd2: begin
-			vns_rhs_array_muxed2 <= soc_netsoc_sdram_bankmachine2_cmd_payload_ba;
-		end
-		2'd3: begin
-			vns_rhs_array_muxed2 <= soc_netsoc_sdram_bankmachine3_cmd_payload_ba;
-		end
-		3'd4: begin
-			vns_rhs_array_muxed2 <= soc_netsoc_sdram_bankmachine4_cmd_payload_ba;
-		end
-		3'd5: begin
-			vns_rhs_array_muxed2 <= soc_netsoc_sdram_bankmachine5_cmd_payload_ba;
-		end
-		3'd6: begin
-			vns_rhs_array_muxed2 <= soc_netsoc_sdram_bankmachine6_cmd_payload_ba;
-		end
-		default: begin
-			vns_rhs_array_muxed2 <= soc_netsoc_sdram_bankmachine7_cmd_payload_ba;
-		end
-	endcase
-end
-always @(*) begin
-	vns_rhs_array_muxed3 <= 1'd0;
-	case (soc_netsoc_sdram_choose_cmd_grant)
-		1'd0: begin
-			vns_rhs_array_muxed3 <= soc_netsoc_sdram_bankmachine0_cmd_payload_is_read;
-		end
-		1'd1: begin
-			vns_rhs_array_muxed3 <= soc_netsoc_sdram_bankmachine1_cmd_payload_is_read;
-		end
-		2'd2: begin
-			vns_rhs_array_muxed3 <= soc_netsoc_sdram_bankmachine2_cmd_payload_is_read;
-		end
-		2'd3: begin
-			vns_rhs_array_muxed3 <= soc_netsoc_sdram_bankmachine3_cmd_payload_is_read;
-		end
-		3'd4: begin
-			vns_rhs_array_muxed3 <= soc_netsoc_sdram_bankmachine4_cmd_payload_is_read;
-		end
-		3'd5: begin
-			vns_rhs_array_muxed3 <= soc_netsoc_sdram_bankmachine5_cmd_payload_is_read;
-		end
-		3'd6: begin
-			vns_rhs_array_muxed3 <= soc_netsoc_sdram_bankmachine6_cmd_payload_is_read;
-		end
-		default: begin
-			vns_rhs_array_muxed3 <= soc_netsoc_sdram_bankmachine7_cmd_payload_is_read;
-		end
-	endcase
-end
-always @(*) begin
-	vns_rhs_array_muxed4 <= 1'd0;
-	case (soc_netsoc_sdram_choose_cmd_grant)
-		1'd0: begin
-			vns_rhs_array_muxed4 <= soc_netsoc_sdram_bankmachine0_cmd_payload_is_write;
-		end
-		1'd1: begin
-			vns_rhs_array_muxed4 <= soc_netsoc_sdram_bankmachine1_cmd_payload_is_write;
-		end
-		2'd2: begin
-			vns_rhs_array_muxed4 <= soc_netsoc_sdram_bankmachine2_cmd_payload_is_write;
-		end
-		2'd3: begin
-			vns_rhs_array_muxed4 <= soc_netsoc_sdram_bankmachine3_cmd_payload_is_write;
-		end
-		3'd4: begin
-			vns_rhs_array_muxed4 <= soc_netsoc_sdram_bankmachine4_cmd_payload_is_write;
-		end
-		3'd5: begin
-			vns_rhs_array_muxed4 <= soc_netsoc_sdram_bankmachine5_cmd_payload_is_write;
-		end
-		3'd6: begin
-			vns_rhs_array_muxed4 <= soc_netsoc_sdram_bankmachine6_cmd_payload_is_write;
-		end
-		default: begin
-			vns_rhs_array_muxed4 <= soc_netsoc_sdram_bankmachine7_cmd_payload_is_write;
-		end
-	endcase
-end
-always @(*) begin
-	vns_rhs_array_muxed5 <= 1'd0;
-	case (soc_netsoc_sdram_choose_cmd_grant)
-		1'd0: begin
-			vns_rhs_array_muxed5 <= soc_netsoc_sdram_bankmachine0_cmd_payload_is_cmd;
-		end
-		1'd1: begin
-			vns_rhs_array_muxed5 <= soc_netsoc_sdram_bankmachine1_cmd_payload_is_cmd;
-		end
-		2'd2: begin
-			vns_rhs_array_muxed5 <= soc_netsoc_sdram_bankmachine2_cmd_payload_is_cmd;
-		end
-		2'd3: begin
-			vns_rhs_array_muxed5 <= soc_netsoc_sdram_bankmachine3_cmd_payload_is_cmd;
-		end
-		3'd4: begin
-			vns_rhs_array_muxed5 <= soc_netsoc_sdram_bankmachine4_cmd_payload_is_cmd;
-		end
-		3'd5: begin
-			vns_rhs_array_muxed5 <= soc_netsoc_sdram_bankmachine5_cmd_payload_is_cmd;
-		end
-		3'd6: begin
-			vns_rhs_array_muxed5 <= soc_netsoc_sdram_bankmachine6_cmd_payload_is_cmd;
-		end
-		default: begin
-			vns_rhs_array_muxed5 <= soc_netsoc_sdram_bankmachine7_cmd_payload_is_cmd;
-		end
-	endcase
-end
-always @(*) begin
-	vns_t_array_muxed0 <= 1'd0;
-	case (soc_netsoc_sdram_choose_cmd_grant)
-		1'd0: begin
-			vns_t_array_muxed0 <= soc_netsoc_sdram_bankmachine0_cmd_payload_cas;
-		end
-		1'd1: begin
-			vns_t_array_muxed0 <= soc_netsoc_sdram_bankmachine1_cmd_payload_cas;
-		end
-		2'd2: begin
-			vns_t_array_muxed0 <= soc_netsoc_sdram_bankmachine2_cmd_payload_cas;
-		end
-		2'd3: begin
-			vns_t_array_muxed0 <= soc_netsoc_sdram_bankmachine3_cmd_payload_cas;
-		end
-		3'd4: begin
-			vns_t_array_muxed0 <= soc_netsoc_sdram_bankmachine4_cmd_payload_cas;
-		end
-		3'd5: begin
-			vns_t_array_muxed0 <= soc_netsoc_sdram_bankmachine5_cmd_payload_cas;
-		end
-		3'd6: begin
-			vns_t_array_muxed0 <= soc_netsoc_sdram_bankmachine6_cmd_payload_cas;
-		end
-		default: begin
-			vns_t_array_muxed0 <= soc_netsoc_sdram_bankmachine7_cmd_payload_cas;
-		end
-	endcase
-end
-always @(*) begin
-	vns_t_array_muxed1 <= 1'd0;
-	case (soc_netsoc_sdram_choose_cmd_grant)
-		1'd0: begin
-			vns_t_array_muxed1 <= soc_netsoc_sdram_bankmachine0_cmd_payload_ras;
-		end
-		1'd1: begin
-			vns_t_array_muxed1 <= soc_netsoc_sdram_bankmachine1_cmd_payload_ras;
-		end
-		2'd2: begin
-			vns_t_array_muxed1 <= soc_netsoc_sdram_bankmachine2_cmd_payload_ras;
-		end
-		2'd3: begin
-			vns_t_array_muxed1 <= soc_netsoc_sdram_bankmachine3_cmd_payload_ras;
-		end
-		3'd4: begin
-			vns_t_array_muxed1 <= soc_netsoc_sdram_bankmachine4_cmd_payload_ras;
-		end
-		3'd5: begin
-			vns_t_array_muxed1 <= soc_netsoc_sdram_bankmachine5_cmd_payload_ras;
-		end
-		3'd6: begin
-			vns_t_array_muxed1 <= soc_netsoc_sdram_bankmachine6_cmd_payload_ras;
-		end
-		default: begin
-			vns_t_array_muxed1 <= soc_netsoc_sdram_bankmachine7_cmd_payload_ras;
-		end
-	endcase
-end
-always @(*) begin
-	vns_t_array_muxed2 <= 1'd0;
-	case (soc_netsoc_sdram_choose_cmd_grant)
-		1'd0: begin
-			vns_t_array_muxed2 <= soc_netsoc_sdram_bankmachine0_cmd_payload_we;
-		end
-		1'd1: begin
-			vns_t_array_muxed2 <= soc_netsoc_sdram_bankmachine1_cmd_payload_we;
-		end
-		2'd2: begin
-			vns_t_array_muxed2 <= soc_netsoc_sdram_bankmachine2_cmd_payload_we;
-		end
-		2'd3: begin
-			vns_t_array_muxed2 <= soc_netsoc_sdram_bankmachine3_cmd_payload_we;
-		end
-		3'd4: begin
-			vns_t_array_muxed2 <= soc_netsoc_sdram_bankmachine4_cmd_payload_we;
-		end
-		3'd5: begin
-			vns_t_array_muxed2 <= soc_netsoc_sdram_bankmachine5_cmd_payload_we;
-		end
-		3'd6: begin
-			vns_t_array_muxed2 <= soc_netsoc_sdram_bankmachine6_cmd_payload_we;
-		end
-		default: begin
-			vns_t_array_muxed2 <= soc_netsoc_sdram_bankmachine7_cmd_payload_we;
-		end
-	endcase
-end
-always @(*) begin
-	vns_rhs_array_muxed6 <= 1'd0;
-	case (soc_netsoc_sdram_choose_req_grant)
-		1'd0: begin
-			vns_rhs_array_muxed6 <= soc_netsoc_sdram_choose_req_valids[0];
-		end
-		1'd1: begin
-			vns_rhs_array_muxed6 <= soc_netsoc_sdram_choose_req_valids[1];
-		end
-		2'd2: begin
-			vns_rhs_array_muxed6 <= soc_netsoc_sdram_choose_req_valids[2];
-		end
-		2'd3: begin
-			vns_rhs_array_muxed6 <= soc_netsoc_sdram_choose_req_valids[3];
-		end
-		3'd4: begin
-			vns_rhs_array_muxed6 <= soc_netsoc_sdram_choose_req_valids[4];
-		end
-		3'd5: begin
-			vns_rhs_array_muxed6 <= soc_netsoc_sdram_choose_req_valids[5];
-		end
-		3'd6: begin
-			vns_rhs_array_muxed6 <= soc_netsoc_sdram_choose_req_valids[6];
-		end
-		default: begin
-			vns_rhs_array_muxed6 <= soc_netsoc_sdram_choose_req_valids[7];
-		end
-	endcase
-end
-always @(*) begin
-	vns_rhs_array_muxed7 <= 14'd0;
-	case (soc_netsoc_sdram_choose_req_grant)
-		1'd0: begin
-			vns_rhs_array_muxed7 <= soc_netsoc_sdram_bankmachine0_cmd_payload_a;
-		end
-		1'd1: begin
-			vns_rhs_array_muxed7 <= soc_netsoc_sdram_bankmachine1_cmd_payload_a;
-		end
-		2'd2: begin
-			vns_rhs_array_muxed7 <= soc_netsoc_sdram_bankmachine2_cmd_payload_a;
-		end
-		2'd3: begin
-			vns_rhs_array_muxed7 <= soc_netsoc_sdram_bankmachine3_cmd_payload_a;
-		end
-		3'd4: begin
-			vns_rhs_array_muxed7 <= soc_netsoc_sdram_bankmachine4_cmd_payload_a;
-		end
-		3'd5: begin
-			vns_rhs_array_muxed7 <= soc_netsoc_sdram_bankmachine5_cmd_payload_a;
-		end
-		3'd6: begin
-			vns_rhs_array_muxed7 <= soc_netsoc_sdram_bankmachine6_cmd_payload_a;
-		end
-		default: begin
-			vns_rhs_array_muxed7 <= soc_netsoc_sdram_bankmachine7_cmd_payload_a;
-		end
-	endcase
-end
-always @(*) begin
-	vns_rhs_array_muxed8 <= 3'd0;
-	case (soc_netsoc_sdram_choose_req_grant)
-		1'd0: begin
-			vns_rhs_array_muxed8 <= soc_netsoc_sdram_bankmachine0_cmd_payload_ba;
-		end
-		1'd1: begin
-			vns_rhs_array_muxed8 <= soc_netsoc_sdram_bankmachine1_cmd_payload_ba;
-		end
-		2'd2: begin
-			vns_rhs_array_muxed8 <= soc_netsoc_sdram_bankmachine2_cmd_payload_ba;
-		end
-		2'd3: begin
-			vns_rhs_array_muxed8 <= soc_netsoc_sdram_bankmachine3_cmd_payload_ba;
-		end
-		3'd4: begin
-			vns_rhs_array_muxed8 <= soc_netsoc_sdram_bankmachine4_cmd_payload_ba;
-		end
-		3'd5: begin
-			vns_rhs_array_muxed8 <= soc_netsoc_sdram_bankmachine5_cmd_payload_ba;
-		end
-		3'd6: begin
-			vns_rhs_array_muxed8 <= soc_netsoc_sdram_bankmachine6_cmd_payload_ba;
-		end
-		default: begin
-			vns_rhs_array_muxed8 <= soc_netsoc_sdram_bankmachine7_cmd_payload_ba;
-		end
-	endcase
-end
-always @(*) begin
-	vns_rhs_array_muxed9 <= 1'd0;
-	case (soc_netsoc_sdram_choose_req_grant)
-		1'd0: begin
-			vns_rhs_array_muxed9 <= soc_netsoc_sdram_bankmachine0_cmd_payload_is_read;
-		end
-		1'd1: begin
-			vns_rhs_array_muxed9 <= soc_netsoc_sdram_bankmachine1_cmd_payload_is_read;
-		end
-		2'd2: begin
-			vns_rhs_array_muxed9 <= soc_netsoc_sdram_bankmachine2_cmd_payload_is_read;
-		end
-		2'd3: begin
-			vns_rhs_array_muxed9 <= soc_netsoc_sdram_bankmachine3_cmd_payload_is_read;
-		end
-		3'd4: begin
-			vns_rhs_array_muxed9 <= soc_netsoc_sdram_bankmachine4_cmd_payload_is_read;
-		end
-		3'd5: begin
-			vns_rhs_array_muxed9 <= soc_netsoc_sdram_bankmachine5_cmd_payload_is_read;
-		end
-		3'd6: begin
-			vns_rhs_array_muxed9 <= soc_netsoc_sdram_bankmachine6_cmd_payload_is_read;
-		end
-		default: begin
-			vns_rhs_array_muxed9 <= soc_netsoc_sdram_bankmachine7_cmd_payload_is_read;
-		end
-	endcase
-end
-always @(*) begin
-	vns_rhs_array_muxed10 <= 1'd0;
-	case (soc_netsoc_sdram_choose_req_grant)
-		1'd0: begin
-			vns_rhs_array_muxed10 <= soc_netsoc_sdram_bankmachine0_cmd_payload_is_write;
-		end
-		1'd1: begin
-			vns_rhs_array_muxed10 <= soc_netsoc_sdram_bankmachine1_cmd_payload_is_write;
-		end
-		2'd2: begin
-			vns_rhs_array_muxed10 <= soc_netsoc_sdram_bankmachine2_cmd_payload_is_write;
-		end
-		2'd3: begin
-			vns_rhs_array_muxed10 <= soc_netsoc_sdram_bankmachine3_cmd_payload_is_write;
-		end
-		3'd4: begin
-			vns_rhs_array_muxed10 <= soc_netsoc_sdram_bankmachine4_cmd_payload_is_write;
-		end
-		3'd5: begin
-			vns_rhs_array_muxed10 <= soc_netsoc_sdram_bankmachine5_cmd_payload_is_write;
-		end
-		3'd6: begin
-			vns_rhs_array_muxed10 <= soc_netsoc_sdram_bankmachine6_cmd_payload_is_write;
-		end
-		default: begin
-			vns_rhs_array_muxed10 <= soc_netsoc_sdram_bankmachine7_cmd_payload_is_write;
-		end
-	endcase
-end
-always @(*) begin
-	vns_rhs_array_muxed11 <= 1'd0;
-	case (soc_netsoc_sdram_choose_req_grant)
-		1'd0: begin
-			vns_rhs_array_muxed11 <= soc_netsoc_sdram_bankmachine0_cmd_payload_is_cmd;
-		end
-		1'd1: begin
-			vns_rhs_array_muxed11 <= soc_netsoc_sdram_bankmachine1_cmd_payload_is_cmd;
-		end
-		2'd2: begin
-			vns_rhs_array_muxed11 <= soc_netsoc_sdram_bankmachine2_cmd_payload_is_cmd;
-		end
-		2'd3: begin
-			vns_rhs_array_muxed11 <= soc_netsoc_sdram_bankmachine3_cmd_payload_is_cmd;
-		end
-		3'd4: begin
-			vns_rhs_array_muxed11 <= soc_netsoc_sdram_bankmachine4_cmd_payload_is_cmd;
-		end
-		3'd5: begin
-			vns_rhs_array_muxed11 <= soc_netsoc_sdram_bankmachine5_cmd_payload_is_cmd;
-		end
-		3'd6: begin
-			vns_rhs_array_muxed11 <= soc_netsoc_sdram_bankmachine6_cmd_payload_is_cmd;
-		end
-		default: begin
-			vns_rhs_array_muxed11 <= soc_netsoc_sdram_bankmachine7_cmd_payload_is_cmd;
-		end
-	endcase
-end
-always @(*) begin
-	vns_t_array_muxed3 <= 1'd0;
-	case (soc_netsoc_sdram_choose_req_grant)
-		1'd0: begin
-			vns_t_array_muxed3 <= soc_netsoc_sdram_bankmachine0_cmd_payload_cas;
-		end
-		1'd1: begin
-			vns_t_array_muxed3 <= soc_netsoc_sdram_bankmachine1_cmd_payload_cas;
-		end
-		2'd2: begin
-			vns_t_array_muxed3 <= soc_netsoc_sdram_bankmachine2_cmd_payload_cas;
-		end
-		2'd3: begin
-			vns_t_array_muxed3 <= soc_netsoc_sdram_bankmachine3_cmd_payload_cas;
-		end
-		3'd4: begin
-			vns_t_array_muxed3 <= soc_netsoc_sdram_bankmachine4_cmd_payload_cas;
-		end
-		3'd5: begin
-			vns_t_array_muxed3 <= soc_netsoc_sdram_bankmachine5_cmd_payload_cas;
-		end
-		3'd6: begin
-			vns_t_array_muxed3 <= soc_netsoc_sdram_bankmachine6_cmd_payload_cas;
-		end
-		default: begin
-			vns_t_array_muxed3 <= soc_netsoc_sdram_bankmachine7_cmd_payload_cas;
-		end
-	endcase
-end
-always @(*) begin
-	vns_t_array_muxed4 <= 1'd0;
-	case (soc_netsoc_sdram_choose_req_grant)
-		1'd0: begin
-			vns_t_array_muxed4 <= soc_netsoc_sdram_bankmachine0_cmd_payload_ras;
-		end
-		1'd1: begin
-			vns_t_array_muxed4 <= soc_netsoc_sdram_bankmachine1_cmd_payload_ras;
-		end
-		2'd2: begin
-			vns_t_array_muxed4 <= soc_netsoc_sdram_bankmachine2_cmd_payload_ras;
-		end
-		2'd3: begin
-			vns_t_array_muxed4 <= soc_netsoc_sdram_bankmachine3_cmd_payload_ras;
-		end
-		3'd4: begin
-			vns_t_array_muxed4 <= soc_netsoc_sdram_bankmachine4_cmd_payload_ras;
-		end
-		3'd5: begin
-			vns_t_array_muxed4 <= soc_netsoc_sdram_bankmachine5_cmd_payload_ras;
-		end
-		3'd6: begin
-			vns_t_array_muxed4 <= soc_netsoc_sdram_bankmachine6_cmd_payload_ras;
-		end
-		default: begin
-			vns_t_array_muxed4 <= soc_netsoc_sdram_bankmachine7_cmd_payload_ras;
-		end
-	endcase
-end
-always @(*) begin
-	vns_t_array_muxed5 <= 1'd0;
-	case (soc_netsoc_sdram_choose_req_grant)
-		1'd0: begin
-			vns_t_array_muxed5 <= soc_netsoc_sdram_bankmachine0_cmd_payload_we;
-		end
-		1'd1: begin
-			vns_t_array_muxed5 <= soc_netsoc_sdram_bankmachine1_cmd_payload_we;
-		end
-		2'd2: begin
-			vns_t_array_muxed5 <= soc_netsoc_sdram_bankmachine2_cmd_payload_we;
-		end
-		2'd3: begin
-			vns_t_array_muxed5 <= soc_netsoc_sdram_bankmachine3_cmd_payload_we;
-		end
-		3'd4: begin
-			vns_t_array_muxed5 <= soc_netsoc_sdram_bankmachine4_cmd_payload_we;
-		end
-		3'd5: begin
-			vns_t_array_muxed5 <= soc_netsoc_sdram_bankmachine5_cmd_payload_we;
-		end
-		3'd6: begin
-			vns_t_array_muxed5 <= soc_netsoc_sdram_bankmachine6_cmd_payload_we;
-		end
-		default: begin
-			vns_t_array_muxed5 <= soc_netsoc_sdram_bankmachine7_cmd_payload_we;
-		end
-	endcase
-end
-always @(*) begin
-	vns_rhs_array_muxed12 <= 21'd0;
-	case (vns_roundrobin0_grant)
-		default: begin
-			vns_rhs_array_muxed12 <= {soc_netsoc_port_cmd_payload_addr[23:10], soc_netsoc_port_cmd_payload_addr[6:0]};
-		end
-	endcase
-end
-always @(*) begin
-	vns_rhs_array_muxed13 <= 1'd0;
-	case (vns_roundrobin0_grant)
-		default: begin
-			vns_rhs_array_muxed13 <= soc_netsoc_port_cmd_payload_we;
-		end
-	endcase
-end
-always @(*) begin
-	vns_rhs_array_muxed14 <= 1'd0;
-	case (vns_roundrobin0_grant)
-		default: begin
-			vns_rhs_array_muxed14 <= (((soc_netsoc_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked0 | (soc_netsoc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_netsoc_port_cmd_valid);
-		end
-	endcase
-end
-always @(*) begin
-	vns_rhs_array_muxed15 <= 21'd0;
-	case (vns_roundrobin1_grant)
-		default: begin
-			vns_rhs_array_muxed15 <= {soc_netsoc_port_cmd_payload_addr[23:10], soc_netsoc_port_cmd_payload_addr[6:0]};
-		end
-	endcase
-end
-always @(*) begin
-	vns_rhs_array_muxed16 <= 1'd0;
-	case (vns_roundrobin1_grant)
-		default: begin
-			vns_rhs_array_muxed16 <= soc_netsoc_port_cmd_payload_we;
-		end
-	endcase
-end
-always @(*) begin
-	vns_rhs_array_muxed17 <= 1'd0;
-	case (vns_roundrobin1_grant)
-		default: begin
-			vns_rhs_array_muxed17 <= (((soc_netsoc_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked1 | (soc_netsoc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_netsoc_port_cmd_valid);
-		end
-	endcase
-end
-always @(*) begin
-	vns_rhs_array_muxed18 <= 21'd0;
-	case (vns_roundrobin2_grant)
-		default: begin
-			vns_rhs_array_muxed18 <= {soc_netsoc_port_cmd_payload_addr[23:10], soc_netsoc_port_cmd_payload_addr[6:0]};
-		end
-	endcase
-end
-always @(*) begin
-	vns_rhs_array_muxed19 <= 1'd0;
-	case (vns_roundrobin2_grant)
-		default: begin
-			vns_rhs_array_muxed19 <= soc_netsoc_port_cmd_payload_we;
-		end
-	endcase
-end
-always @(*) begin
-	vns_rhs_array_muxed20 <= 1'd0;
-	case (vns_roundrobin2_grant)
-		default: begin
-			vns_rhs_array_muxed20 <= (((soc_netsoc_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked2 | (soc_netsoc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_netsoc_port_cmd_valid);
-		end
-	endcase
-end
-always @(*) begin
-	vns_rhs_array_muxed21 <= 21'd0;
-	case (vns_roundrobin3_grant)
-		default: begin
-			vns_rhs_array_muxed21 <= {soc_netsoc_port_cmd_payload_addr[23:10], soc_netsoc_port_cmd_payload_addr[6:0]};
-		end
-	endcase
-end
-always @(*) begin
-	vns_rhs_array_muxed22 <= 1'd0;
-	case (vns_roundrobin3_grant)
-		default: begin
-			vns_rhs_array_muxed22 <= soc_netsoc_port_cmd_payload_we;
-		end
-	endcase
-end
-always @(*) begin
-	vns_rhs_array_muxed23 <= 1'd0;
-	case (vns_roundrobin3_grant)
-		default: begin
-			vns_rhs_array_muxed23 <= (((soc_netsoc_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked3 | (soc_netsoc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_netsoc_port_cmd_valid);
-		end
-	endcase
-end
-always @(*) begin
-	vns_rhs_array_muxed24 <= 21'd0;
-	case (vns_roundrobin4_grant)
-		default: begin
-			vns_rhs_array_muxed24 <= {soc_netsoc_port_cmd_payload_addr[23:10], soc_netsoc_port_cmd_payload_addr[6:0]};
-		end
-	endcase
-end
-always @(*) begin
-	vns_rhs_array_muxed25 <= 1'd0;
-	case (vns_roundrobin4_grant)
-		default: begin
-			vns_rhs_array_muxed25 <= soc_netsoc_port_cmd_payload_we;
-		end
-	endcase
-end
-always @(*) begin
-	vns_rhs_array_muxed26 <= 1'd0;
-	case (vns_roundrobin4_grant)
-		default: begin
-			vns_rhs_array_muxed26 <= (((soc_netsoc_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked4 | (soc_netsoc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_netsoc_port_cmd_valid);
-		end
-	endcase
-end
-always @(*) begin
-	vns_rhs_array_muxed27 <= 21'd0;
-	case (vns_roundrobin5_grant)
-		default: begin
-			vns_rhs_array_muxed27 <= {soc_netsoc_port_cmd_payload_addr[23:10], soc_netsoc_port_cmd_payload_addr[6:0]};
-		end
-	endcase
-end
-always @(*) begin
-	vns_rhs_array_muxed28 <= 1'd0;
-	case (vns_roundrobin5_grant)
-		default: begin
-			vns_rhs_array_muxed28 <= soc_netsoc_port_cmd_payload_we;
-		end
-	endcase
-end
-always @(*) begin
-	vns_rhs_array_muxed29 <= 1'd0;
-	case (vns_roundrobin5_grant)
-		default: begin
-			vns_rhs_array_muxed29 <= (((soc_netsoc_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked5 | (soc_netsoc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_netsoc_port_cmd_valid);
-		end
-	endcase
-end
-always @(*) begin
-	vns_rhs_array_muxed30 <= 21'd0;
-	case (vns_roundrobin6_grant)
-		default: begin
-			vns_rhs_array_muxed30 <= {soc_netsoc_port_cmd_payload_addr[23:10], soc_netsoc_port_cmd_payload_addr[6:0]};
-		end
-	endcase
-end
-always @(*) begin
-	vns_rhs_array_muxed31 <= 1'd0;
-	case (vns_roundrobin6_grant)
-		default: begin
-			vns_rhs_array_muxed31 <= soc_netsoc_port_cmd_payload_we;
-		end
-	endcase
-end
-always @(*) begin
-	vns_rhs_array_muxed32 <= 1'd0;
-	case (vns_roundrobin6_grant)
-		default: begin
-			vns_rhs_array_muxed32 <= (((soc_netsoc_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked6 | (soc_netsoc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_netsoc_port_cmd_valid);
-		end
-	endcase
-end
-always @(*) begin
-	vns_rhs_array_muxed33 <= 21'd0;
-	case (vns_roundrobin7_grant)
-		default: begin
-			vns_rhs_array_muxed33 <= {soc_netsoc_port_cmd_payload_addr[23:10], soc_netsoc_port_cmd_payload_addr[6:0]};
-		end
-	endcase
-end
-always @(*) begin
-	vns_rhs_array_muxed34 <= 1'd0;
-	case (vns_roundrobin7_grant)
-		default: begin
-			vns_rhs_array_muxed34 <= soc_netsoc_port_cmd_payload_we;
-		end
-	endcase
-end
-always @(*) begin
-	vns_rhs_array_muxed35 <= 1'd0;
-	case (vns_roundrobin7_grant)
-		default: begin
-			vns_rhs_array_muxed35 <= (((soc_netsoc_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked7 | (soc_netsoc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))))) & soc_netsoc_port_cmd_valid);
-		end
-	endcase
-end
-always @(*) begin
-	vns_rhs_array_muxed36 <= 30'd0;
-	case (vns_wb_sdram_con_grant)
-		default: begin
-			vns_rhs_array_muxed36 <= soc_netsoc_interface1_wb_sdram_adr;
-		end
-	endcase
-end
-always @(*) begin
-	vns_rhs_array_muxed37 <= 32'd0;
-	case (vns_wb_sdram_con_grant)
-		default: begin
-			vns_rhs_array_muxed37 <= soc_netsoc_interface1_wb_sdram_dat_w;
-		end
-	endcase
-end
-always @(*) begin
-	vns_rhs_array_muxed38 <= 4'd0;
-	case (vns_wb_sdram_con_grant)
-		default: begin
-			vns_rhs_array_muxed38 <= soc_netsoc_interface1_wb_sdram_sel;
-		end
-	endcase
-end
-always @(*) begin
-	vns_rhs_array_muxed39 <= 1'd0;
-	case (vns_wb_sdram_con_grant)
-		default: begin
-			vns_rhs_array_muxed39 <= soc_netsoc_interface1_wb_sdram_cyc;
-		end
-	endcase
-end
-always @(*) begin
-	vns_rhs_array_muxed40 <= 1'd0;
-	case (vns_wb_sdram_con_grant)
-		default: begin
-			vns_rhs_array_muxed40 <= soc_netsoc_interface1_wb_sdram_stb;
-		end
-	endcase
-end
-always @(*) begin
-	vns_rhs_array_muxed41 <= 1'd0;
-	case (vns_wb_sdram_con_grant)
-		default: begin
-			vns_rhs_array_muxed41 <= soc_netsoc_interface1_wb_sdram_we;
-		end
-	endcase
-end
-always @(*) begin
-	vns_rhs_array_muxed42 <= 3'd0;
-	case (vns_wb_sdram_con_grant)
-		default: begin
-			vns_rhs_array_muxed42 <= soc_netsoc_interface1_wb_sdram_cti;
-		end
-	endcase
-end
-always @(*) begin
-	vns_rhs_array_muxed43 <= 2'd0;
-	case (vns_wb_sdram_con_grant)
-		default: begin
-			vns_rhs_array_muxed43 <= soc_netsoc_interface1_wb_sdram_bte;
-		end
-	endcase
-end
-always @(*) begin
-	vns_rhs_array_muxed44 <= 30'd0;
-	case (vns_netsoc_grant)
-		1'd0: begin
-			vns_rhs_array_muxed44 <= soc_netsoc_interface0_soc_bus_adr;
-		end
-		default: begin
-			vns_rhs_array_muxed44 <= soc_netsoc_interface1_soc_bus_adr;
-		end
-	endcase
-end
-always @(*) begin
-	vns_rhs_array_muxed45 <= 32'd0;
-	case (vns_netsoc_grant)
-		1'd0: begin
-			vns_rhs_array_muxed45 <= soc_netsoc_interface0_soc_bus_dat_w;
-		end
-		default: begin
-			vns_rhs_array_muxed45 <= soc_netsoc_interface1_soc_bus_dat_w;
-		end
-	endcase
-end
-always @(*) begin
-	vns_rhs_array_muxed46 <= 4'd0;
-	case (vns_netsoc_grant)
-		1'd0: begin
-			vns_rhs_array_muxed46 <= soc_netsoc_interface0_soc_bus_sel;
-		end
-		default: begin
-			vns_rhs_array_muxed46 <= soc_netsoc_interface1_soc_bus_sel;
-		end
-	endcase
-end
-always @(*) begin
-	vns_rhs_array_muxed47 <= 1'd0;
-	case (vns_netsoc_grant)
-		1'd0: begin
-			vns_rhs_array_muxed47 <= soc_netsoc_interface0_soc_bus_cyc;
-		end
-		default: begin
-			vns_rhs_array_muxed47 <= soc_netsoc_interface1_soc_bus_cyc;
-		end
-	endcase
-end
-always @(*) begin
-	vns_rhs_array_muxed48 <= 1'd0;
-	case (vns_netsoc_grant)
-		1'd0: begin
-			vns_rhs_array_muxed48 <= soc_netsoc_interface0_soc_bus_stb;
-		end
-		default: begin
-			vns_rhs_array_muxed48 <= soc_netsoc_interface1_soc_bus_stb;
-		end
-	endcase
-end
-always @(*) begin
-	vns_rhs_array_muxed49 <= 1'd0;
-	case (vns_netsoc_grant)
-		1'd0: begin
-			vns_rhs_array_muxed49 <= soc_netsoc_interface0_soc_bus_we;
-		end
-		default: begin
-			vns_rhs_array_muxed49 <= soc_netsoc_interface1_soc_bus_we;
-		end
-	endcase
-end
-always @(*) begin
-	vns_rhs_array_muxed50 <= 3'd0;
-	case (vns_netsoc_grant)
-		1'd0: begin
-			vns_rhs_array_muxed50 <= soc_netsoc_interface0_soc_bus_cti;
-		end
-		default: begin
-			vns_rhs_array_muxed50 <= soc_netsoc_interface1_soc_bus_cti;
-		end
-	endcase
-end
-always @(*) begin
-	vns_rhs_array_muxed51 <= 2'd0;
-	case (vns_netsoc_grant)
-		1'd0: begin
-			vns_rhs_array_muxed51 <= soc_netsoc_interface0_soc_bus_bte;
-		end
-		default: begin
-			vns_rhs_array_muxed51 <= soc_netsoc_interface1_soc_bus_bte;
-		end
-	endcase
-end
-always @(*) begin
-	vns_array_muxed0 <= 3'd0;
-	case (soc_netsoc_sdram_steerer_sel0)
-		1'd0: begin
-			vns_array_muxed0 <= soc_netsoc_sdram_nop_ba[2:0];
-		end
-		1'd1: begin
-			vns_array_muxed0 <= soc_netsoc_sdram_choose_cmd_cmd_payload_ba[2:0];
-		end
-		2'd2: begin
-			vns_array_muxed0 <= soc_netsoc_sdram_choose_req_cmd_payload_ba[2:0];
-		end
-		default: begin
-			vns_array_muxed0 <= soc_netsoc_sdram_cmd_payload_ba[2:0];
-		end
-	endcase
-end
-always @(*) begin
-	vns_array_muxed1 <= 14'd0;
-	case (soc_netsoc_sdram_steerer_sel0)
-		1'd0: begin
-			vns_array_muxed1 <= soc_netsoc_sdram_nop_a;
-		end
-		1'd1: begin
-			vns_array_muxed1 <= soc_netsoc_sdram_choose_cmd_cmd_payload_a;
-		end
-		2'd2: begin
-			vns_array_muxed1 <= soc_netsoc_sdram_choose_req_cmd_payload_a;
-		end
-		default: begin
-			vns_array_muxed1 <= soc_netsoc_sdram_cmd_payload_a;
-		end
-	endcase
-end
-always @(*) begin
-	vns_array_muxed2 <= 1'd0;
-	case (soc_netsoc_sdram_steerer_sel0)
-		1'd0: begin
-			vns_array_muxed2 <= 1'd0;
-		end
-		1'd1: begin
-			vns_array_muxed2 <= ((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & soc_netsoc_sdram_choose_cmd_cmd_payload_cas);
-		end
-		2'd2: begin
-			vns_array_muxed2 <= ((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & soc_netsoc_sdram_choose_req_cmd_payload_cas);
-		end
-		default: begin
-			vns_array_muxed2 <= ((soc_netsoc_sdram_cmd_valid & soc_netsoc_sdram_cmd_ready) & soc_netsoc_sdram_cmd_payload_cas);
-		end
-	endcase
-end
-always @(*) begin
-	vns_array_muxed3 <= 1'd0;
-	case (soc_netsoc_sdram_steerer_sel0)
-		1'd0: begin
-			vns_array_muxed3 <= 1'd0;
-		end
-		1'd1: begin
-			vns_array_muxed3 <= ((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & soc_netsoc_sdram_choose_cmd_cmd_payload_ras);
-		end
-		2'd2: begin
-			vns_array_muxed3 <= ((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & soc_netsoc_sdram_choose_req_cmd_payload_ras);
-		end
-		default: begin
-			vns_array_muxed3 <= ((soc_netsoc_sdram_cmd_valid & soc_netsoc_sdram_cmd_ready) & soc_netsoc_sdram_cmd_payload_ras);
-		end
-	endcase
-end
-always @(*) begin
-	vns_array_muxed4 <= 1'd0;
-	case (soc_netsoc_sdram_steerer_sel0)
-		1'd0: begin
-			vns_array_muxed4 <= 1'd0;
-		end
-		1'd1: begin
-			vns_array_muxed4 <= ((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & soc_netsoc_sdram_choose_cmd_cmd_payload_we);
-		end
-		2'd2: begin
-			vns_array_muxed4 <= ((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & soc_netsoc_sdram_choose_req_cmd_payload_we);
-		end
-		default: begin
-			vns_array_muxed4 <= ((soc_netsoc_sdram_cmd_valid & soc_netsoc_sdram_cmd_ready) & soc_netsoc_sdram_cmd_payload_we);
-		end
-	endcase
-end
-always @(*) begin
-	vns_array_muxed5 <= 1'd0;
-	case (soc_netsoc_sdram_steerer_sel0)
-		1'd0: begin
-			vns_array_muxed5 <= 1'd0;
-		end
-		1'd1: begin
-			vns_array_muxed5 <= ((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & soc_netsoc_sdram_choose_cmd_cmd_payload_is_read);
-		end
-		2'd2: begin
-			vns_array_muxed5 <= ((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & soc_netsoc_sdram_choose_req_cmd_payload_is_read);
-		end
-		default: begin
-			vns_array_muxed5 <= ((soc_netsoc_sdram_cmd_valid & soc_netsoc_sdram_cmd_ready) & soc_netsoc_sdram_cmd_payload_is_read);
-		end
-	endcase
-end
-always @(*) begin
-	vns_array_muxed6 <= 1'd0;
-	case (soc_netsoc_sdram_steerer_sel0)
-		1'd0: begin
-			vns_array_muxed6 <= 1'd0;
-		end
-		1'd1: begin
-			vns_array_muxed6 <= ((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & soc_netsoc_sdram_choose_cmd_cmd_payload_is_write);
-		end
-		2'd2: begin
-			vns_array_muxed6 <= ((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & soc_netsoc_sdram_choose_req_cmd_payload_is_write);
-		end
-		default: begin
-			vns_array_muxed6 <= ((soc_netsoc_sdram_cmd_valid & soc_netsoc_sdram_cmd_ready) & soc_netsoc_sdram_cmd_payload_is_write);
-		end
-	endcase
-end
-always @(*) begin
-	vns_array_muxed7 <= 3'd0;
-	case (soc_netsoc_sdram_steerer_sel1)
-		1'd0: begin
-			vns_array_muxed7 <= soc_netsoc_sdram_nop_ba[2:0];
-		end
-		1'd1: begin
-			vns_array_muxed7 <= soc_netsoc_sdram_choose_cmd_cmd_payload_ba[2:0];
-		end
-		2'd2: begin
-			vns_array_muxed7 <= soc_netsoc_sdram_choose_req_cmd_payload_ba[2:0];
-		end
-		default: begin
-			vns_array_muxed7 <= soc_netsoc_sdram_cmd_payload_ba[2:0];
-		end
-	endcase
-end
-always @(*) begin
-	vns_array_muxed8 <= 14'd0;
-	case (soc_netsoc_sdram_steerer_sel1)
-		1'd0: begin
-			vns_array_muxed8 <= soc_netsoc_sdram_nop_a;
-		end
-		1'd1: begin
-			vns_array_muxed8 <= soc_netsoc_sdram_choose_cmd_cmd_payload_a;
-		end
-		2'd2: begin
-			vns_array_muxed8 <= soc_netsoc_sdram_choose_req_cmd_payload_a;
-		end
-		default: begin
-			vns_array_muxed8 <= soc_netsoc_sdram_cmd_payload_a;
-		end
-	endcase
-end
-always @(*) begin
-	vns_array_muxed9 <= 1'd0;
-	case (soc_netsoc_sdram_steerer_sel1)
-		1'd0: begin
-			vns_array_muxed9 <= 1'd0;
-		end
-		1'd1: begin
-			vns_array_muxed9 <= ((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & soc_netsoc_sdram_choose_cmd_cmd_payload_cas);
-		end
-		2'd2: begin
-			vns_array_muxed9 <= ((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & soc_netsoc_sdram_choose_req_cmd_payload_cas);
-		end
-		default: begin
-			vns_array_muxed9 <= ((soc_netsoc_sdram_cmd_valid & soc_netsoc_sdram_cmd_ready) & soc_netsoc_sdram_cmd_payload_cas);
-		end
-	endcase
-end
-always @(*) begin
-	vns_array_muxed10 <= 1'd0;
-	case (soc_netsoc_sdram_steerer_sel1)
-		1'd0: begin
-			vns_array_muxed10 <= 1'd0;
-		end
-		1'd1: begin
-			vns_array_muxed10 <= ((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & soc_netsoc_sdram_choose_cmd_cmd_payload_ras);
-		end
-		2'd2: begin
-			vns_array_muxed10 <= ((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & soc_netsoc_sdram_choose_req_cmd_payload_ras);
-		end
-		default: begin
-			vns_array_muxed10 <= ((soc_netsoc_sdram_cmd_valid & soc_netsoc_sdram_cmd_ready) & soc_netsoc_sdram_cmd_payload_ras);
-		end
-	endcase
-end
-always @(*) begin
-	vns_array_muxed11 <= 1'd0;
-	case (soc_netsoc_sdram_steerer_sel1)
-		1'd0: begin
-			vns_array_muxed11 <= 1'd0;
-		end
-		1'd1: begin
-			vns_array_muxed11 <= ((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & soc_netsoc_sdram_choose_cmd_cmd_payload_we);
-		end
-		2'd2: begin
-			vns_array_muxed11 <= ((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & soc_netsoc_sdram_choose_req_cmd_payload_we);
-		end
-		default: begin
-			vns_array_muxed11 <= ((soc_netsoc_sdram_cmd_valid & soc_netsoc_sdram_cmd_ready) & soc_netsoc_sdram_cmd_payload_we);
-		end
-	endcase
-end
-always @(*) begin
-	vns_array_muxed12 <= 1'd0;
-	case (soc_netsoc_sdram_steerer_sel1)
-		1'd0: begin
-			vns_array_muxed12 <= 1'd0;
-		end
-		1'd1: begin
-			vns_array_muxed12 <= ((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & soc_netsoc_sdram_choose_cmd_cmd_payload_is_read);
-		end
-		2'd2: begin
-			vns_array_muxed12 <= ((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & soc_netsoc_sdram_choose_req_cmd_payload_is_read);
-		end
-		default: begin
-			vns_array_muxed12 <= ((soc_netsoc_sdram_cmd_valid & soc_netsoc_sdram_cmd_ready) & soc_netsoc_sdram_cmd_payload_is_read);
-		end
-	endcase
-end
-always @(*) begin
-	vns_array_muxed13 <= 1'd0;
-	case (soc_netsoc_sdram_steerer_sel1)
-		1'd0: begin
-			vns_array_muxed13 <= 1'd0;
-		end
-		1'd1: begin
-			vns_array_muxed13 <= ((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & soc_netsoc_sdram_choose_cmd_cmd_payload_is_write);
-		end
-		2'd2: begin
-			vns_array_muxed13 <= ((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & soc_netsoc_sdram_choose_req_cmd_payload_is_write);
-		end
-		default: begin
-			vns_array_muxed13 <= ((soc_netsoc_sdram_cmd_valid & soc_netsoc_sdram_cmd_ready) & soc_netsoc_sdram_cmd_payload_is_write);
-		end
-	endcase
-end
-always @(*) begin
-	vns_array_muxed14 <= 3'd0;
-	case (soc_netsoc_sdram_steerer_sel2)
-		1'd0: begin
-			vns_array_muxed14 <= soc_netsoc_sdram_nop_ba[2:0];
-		end
-		1'd1: begin
-			vns_array_muxed14 <= soc_netsoc_sdram_choose_cmd_cmd_payload_ba[2:0];
-		end
-		2'd2: begin
-			vns_array_muxed14 <= soc_netsoc_sdram_choose_req_cmd_payload_ba[2:0];
-		end
-		default: begin
-			vns_array_muxed14 <= soc_netsoc_sdram_cmd_payload_ba[2:0];
-		end
-	endcase
-end
-always @(*) begin
-	vns_array_muxed15 <= 14'd0;
-	case (soc_netsoc_sdram_steerer_sel2)
-		1'd0: begin
-			vns_array_muxed15 <= soc_netsoc_sdram_nop_a;
-		end
-		1'd1: begin
-			vns_array_muxed15 <= soc_netsoc_sdram_choose_cmd_cmd_payload_a;
-		end
-		2'd2: begin
-			vns_array_muxed15 <= soc_netsoc_sdram_choose_req_cmd_payload_a;
-		end
-		default: begin
-			vns_array_muxed15 <= soc_netsoc_sdram_cmd_payload_a;
-		end
-	endcase
-end
-always @(*) begin
-	vns_array_muxed16 <= 1'd0;
-	case (soc_netsoc_sdram_steerer_sel2)
-		1'd0: begin
-			vns_array_muxed16 <= 1'd0;
-		end
-		1'd1: begin
-			vns_array_muxed16 <= ((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & soc_netsoc_sdram_choose_cmd_cmd_payload_cas);
-		end
-		2'd2: begin
-			vns_array_muxed16 <= ((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & soc_netsoc_sdram_choose_req_cmd_payload_cas);
-		end
-		default: begin
-			vns_array_muxed16 <= ((soc_netsoc_sdram_cmd_valid & soc_netsoc_sdram_cmd_ready) & soc_netsoc_sdram_cmd_payload_cas);
-		end
-	endcase
-end
-always @(*) begin
-	vns_array_muxed17 <= 1'd0;
-	case (soc_netsoc_sdram_steerer_sel2)
-		1'd0: begin
-			vns_array_muxed17 <= 1'd0;
-		end
-		1'd1: begin
-			vns_array_muxed17 <= ((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & soc_netsoc_sdram_choose_cmd_cmd_payload_ras);
-		end
-		2'd2: begin
-			vns_array_muxed17 <= ((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & soc_netsoc_sdram_choose_req_cmd_payload_ras);
-		end
-		default: begin
-			vns_array_muxed17 <= ((soc_netsoc_sdram_cmd_valid & soc_netsoc_sdram_cmd_ready) & soc_netsoc_sdram_cmd_payload_ras);
-		end
-	endcase
-end
-always @(*) begin
-	vns_array_muxed18 <= 1'd0;
-	case (soc_netsoc_sdram_steerer_sel2)
-		1'd0: begin
-			vns_array_muxed18 <= 1'd0;
-		end
-		1'd1: begin
-			vns_array_muxed18 <= ((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & soc_netsoc_sdram_choose_cmd_cmd_payload_we);
-		end
-		2'd2: begin
-			vns_array_muxed18 <= ((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & soc_netsoc_sdram_choose_req_cmd_payload_we);
-		end
-		default: begin
-			vns_array_muxed18 <= ((soc_netsoc_sdram_cmd_valid & soc_netsoc_sdram_cmd_ready) & soc_netsoc_sdram_cmd_payload_we);
-		end
-	endcase
-end
-always @(*) begin
-	vns_array_muxed19 <= 1'd0;
-	case (soc_netsoc_sdram_steerer_sel2)
-		1'd0: begin
-			vns_array_muxed19 <= 1'd0;
-		end
-		1'd1: begin
-			vns_array_muxed19 <= ((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & soc_netsoc_sdram_choose_cmd_cmd_payload_is_read);
-		end
-		2'd2: begin
-			vns_array_muxed19 <= ((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & soc_netsoc_sdram_choose_req_cmd_payload_is_read);
-		end
-		default: begin
-			vns_array_muxed19 <= ((soc_netsoc_sdram_cmd_valid & soc_netsoc_sdram_cmd_ready) & soc_netsoc_sdram_cmd_payload_is_read);
-		end
-	endcase
-end
-always @(*) begin
-	vns_array_muxed20 <= 1'd0;
-	case (soc_netsoc_sdram_steerer_sel2)
-		1'd0: begin
-			vns_array_muxed20 <= 1'd0;
-		end
-		1'd1: begin
-			vns_array_muxed20 <= ((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & soc_netsoc_sdram_choose_cmd_cmd_payload_is_write);
-		end
-		2'd2: begin
-			vns_array_muxed20 <= ((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & soc_netsoc_sdram_choose_req_cmd_payload_is_write);
-		end
-		default: begin
-			vns_array_muxed20 <= ((soc_netsoc_sdram_cmd_valid & soc_netsoc_sdram_cmd_ready) & soc_netsoc_sdram_cmd_payload_is_write);
-		end
-	endcase
-end
-always @(*) begin
-	vns_array_muxed21 <= 3'd0;
-	case (soc_netsoc_sdram_steerer_sel3)
-		1'd0: begin
-			vns_array_muxed21 <= soc_netsoc_sdram_nop_ba[2:0];
-		end
-		1'd1: begin
-			vns_array_muxed21 <= soc_netsoc_sdram_choose_cmd_cmd_payload_ba[2:0];
-		end
-		2'd2: begin
-			vns_array_muxed21 <= soc_netsoc_sdram_choose_req_cmd_payload_ba[2:0];
-		end
-		default: begin
-			vns_array_muxed21 <= soc_netsoc_sdram_cmd_payload_ba[2:0];
-		end
-	endcase
-end
-always @(*) begin
-	vns_array_muxed22 <= 14'd0;
-	case (soc_netsoc_sdram_steerer_sel3)
-		1'd0: begin
-			vns_array_muxed22 <= soc_netsoc_sdram_nop_a;
-		end
-		1'd1: begin
-			vns_array_muxed22 <= soc_netsoc_sdram_choose_cmd_cmd_payload_a;
-		end
-		2'd2: begin
-			vns_array_muxed22 <= soc_netsoc_sdram_choose_req_cmd_payload_a;
-		end
-		default: begin
-			vns_array_muxed22 <= soc_netsoc_sdram_cmd_payload_a;
-		end
-	endcase
-end
-always @(*) begin
-	vns_array_muxed23 <= 1'd0;
-	case (soc_netsoc_sdram_steerer_sel3)
-		1'd0: begin
-			vns_array_muxed23 <= 1'd0;
-		end
-		1'd1: begin
-			vns_array_muxed23 <= ((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & soc_netsoc_sdram_choose_cmd_cmd_payload_cas);
-		end
-		2'd2: begin
-			vns_array_muxed23 <= ((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & soc_netsoc_sdram_choose_req_cmd_payload_cas);
-		end
-		default: begin
-			vns_array_muxed23 <= ((soc_netsoc_sdram_cmd_valid & soc_netsoc_sdram_cmd_ready) & soc_netsoc_sdram_cmd_payload_cas);
-		end
-	endcase
-end
-always @(*) begin
-	vns_array_muxed24 <= 1'd0;
-	case (soc_netsoc_sdram_steerer_sel3)
-		1'd0: begin
-			vns_array_muxed24 <= 1'd0;
-		end
-		1'd1: begin
-			vns_array_muxed24 <= ((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & soc_netsoc_sdram_choose_cmd_cmd_payload_ras);
-		end
-		2'd2: begin
-			vns_array_muxed24 <= ((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & soc_netsoc_sdram_choose_req_cmd_payload_ras);
-		end
-		default: begin
-			vns_array_muxed24 <= ((soc_netsoc_sdram_cmd_valid & soc_netsoc_sdram_cmd_ready) & soc_netsoc_sdram_cmd_payload_ras);
-		end
-	endcase
-end
-always @(*) begin
-	vns_array_muxed25 <= 1'd0;
-	case (soc_netsoc_sdram_steerer_sel3)
-		1'd0: begin
-			vns_array_muxed25 <= 1'd0;
-		end
-		1'd1: begin
-			vns_array_muxed25 <= ((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & soc_netsoc_sdram_choose_cmd_cmd_payload_we);
-		end
-		2'd2: begin
-			vns_array_muxed25 <= ((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & soc_netsoc_sdram_choose_req_cmd_payload_we);
-		end
-		default: begin
-			vns_array_muxed25 <= ((soc_netsoc_sdram_cmd_valid & soc_netsoc_sdram_cmd_ready) & soc_netsoc_sdram_cmd_payload_we);
-		end
-	endcase
-end
-always @(*) begin
-	vns_array_muxed26 <= 1'd0;
-	case (soc_netsoc_sdram_steerer_sel3)
-		1'd0: begin
-			vns_array_muxed26 <= 1'd0;
-		end
-		1'd1: begin
-			vns_array_muxed26 <= ((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & soc_netsoc_sdram_choose_cmd_cmd_payload_is_read);
-		end
-		2'd2: begin
-			vns_array_muxed26 <= ((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & soc_netsoc_sdram_choose_req_cmd_payload_is_read);
-		end
-		default: begin
-			vns_array_muxed26 <= ((soc_netsoc_sdram_cmd_valid & soc_netsoc_sdram_cmd_ready) & soc_netsoc_sdram_cmd_payload_is_read);
-		end
-	endcase
-end
-always @(*) begin
-	vns_array_muxed27 <= 1'd0;
-	case (soc_netsoc_sdram_steerer_sel3)
-		1'd0: begin
-			vns_array_muxed27 <= 1'd0;
-		end
-		1'd1: begin
-			vns_array_muxed27 <= ((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & soc_netsoc_sdram_choose_cmd_cmd_payload_is_write);
-		end
-		2'd2: begin
-			vns_array_muxed27 <= ((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & soc_netsoc_sdram_choose_req_cmd_payload_is_write);
-		end
-		default: begin
-			vns_array_muxed27 <= ((soc_netsoc_sdram_cmd_valid & soc_netsoc_sdram_cmd_ready) & soc_netsoc_sdram_cmd_payload_is_write);
-		end
-	endcase
-end
-assign soc_netsoc_uart_phy_rx = vns_xilinxmultiregimpl0_regs1;
-assign vns_xilinxasyncresetsynchronizerimpl0 = ((~soc_pll_locked) | (~cpu_reset));
-assign vns_xilinxasyncresetsynchronizerimpl1 = ((~soc_pll_locked) | (~cpu_reset));
-always @(*) begin
-	soc_status <= 1'd0;
-	soc_status <= soc_r;
-	soc_status <= vns_xilinxmultiregimpl1_regs1;
-end
-assign soc_ps_preamble_error_toggle_o = vns_xilinxmultiregimpl2_regs1;
-assign soc_ps_crc_error_toggle_o = vns_xilinxmultiregimpl3_regs1;
-assign soc_tx_cdc_produce_rdomain = vns_xilinxmultiregimpl4_regs1;
-assign soc_tx_cdc_consume_wdomain = vns_xilinxmultiregimpl5_regs1;
-assign soc_rx_cdc_produce_rdomain = vns_xilinxmultiregimpl6_regs1;
-assign soc_rx_cdc_consume_wdomain = vns_xilinxmultiregimpl7_regs1;
-
-always @(posedge clk200_clk) begin
-	if ((soc_reset_counter != 1'd0)) begin
-		soc_reset_counter <= (soc_reset_counter - 1'd1);
-	end else begin
-		soc_ic_reset <= 1'd0;
-	end
-	if (clk200_rst) begin
-		soc_reset_counter <= 4'd15;
-		soc_ic_reset <= 1'd1;
-	end
-end
-
-always @(posedge eth_rx_clk) begin
-	soc_liteethphymiirx_converter_reset <= (~eth_rx_dv);
-	soc_liteethphymiirx_converter_sink_valid <= 1'd1;
-	soc_liteethphymiirx_converter_sink_payload_data <= eth_rx_data;
-	if (soc_liteethphymiirx_converter_converter_source_ready) begin
-		soc_liteethphymiirx_converter_converter_strobe_all <= 1'd0;
-	end
-	if (soc_liteethphymiirx_converter_converter_load_part) begin
-		if (((soc_liteethphymiirx_converter_converter_demux == 1'd1) | soc_liteethphymiirx_converter_converter_sink_last)) begin
-			soc_liteethphymiirx_converter_converter_demux <= 1'd0;
-			soc_liteethphymiirx_converter_converter_strobe_all <= 1'd1;
-		end else begin
-			soc_liteethphymiirx_converter_converter_demux <= (soc_liteethphymiirx_converter_converter_demux + 1'd1);
-		end
-	end
-	if ((soc_liteethphymiirx_converter_converter_source_valid & soc_liteethphymiirx_converter_converter_source_ready)) begin
-		if ((soc_liteethphymiirx_converter_converter_sink_valid & soc_liteethphymiirx_converter_converter_sink_ready)) begin
-			soc_liteethphymiirx_converter_converter_source_first <= soc_liteethphymiirx_converter_converter_sink_first;
-			soc_liteethphymiirx_converter_converter_source_last <= soc_liteethphymiirx_converter_converter_sink_last;
-		end else begin
-			soc_liteethphymiirx_converter_converter_source_first <= 1'd0;
-			soc_liteethphymiirx_converter_converter_source_last <= 1'd0;
-		end
-	end else begin
-		if ((soc_liteethphymiirx_converter_converter_sink_valid & soc_liteethphymiirx_converter_converter_sink_ready)) begin
-			soc_liteethphymiirx_converter_converter_source_first <= (soc_liteethphymiirx_converter_converter_sink_first | soc_liteethphymiirx_converter_converter_source_first);
-			soc_liteethphymiirx_converter_converter_source_last <= (soc_liteethphymiirx_converter_converter_sink_last | soc_liteethphymiirx_converter_converter_source_last);
-		end
-	end
-	if (soc_liteethphymiirx_converter_converter_load_part) begin
-		case (soc_liteethphymiirx_converter_converter_demux)
-			1'd0: begin
-				soc_liteethphymiirx_converter_converter_source_payload_data[3:0] <= soc_liteethphymiirx_converter_converter_sink_payload_data;
-			end
-			1'd1: begin
-				soc_liteethphymiirx_converter_converter_source_payload_data[7:4] <= soc_liteethphymiirx_converter_converter_sink_payload_data;
-			end
-		endcase
-	end
-	if (soc_liteethphymiirx_converter_converter_load_part) begin
-		soc_liteethphymiirx_converter_converter_source_payload_valid_token_count <= (soc_liteethphymiirx_converter_converter_demux + 1'd1);
-	end
-	if (soc_liteethphymiirx_converter_reset) begin
-		soc_liteethphymiirx_converter_converter_source_first <= 1'd0;
-		soc_liteethphymiirx_converter_converter_source_last <= 1'd0;
-		soc_liteethphymiirx_converter_converter_source_payload_data <= 8'd0;
-		soc_liteethphymiirx_converter_converter_source_payload_valid_token_count <= 2'd0;
-		soc_liteethphymiirx_converter_converter_demux <= 1'd0;
-		soc_liteethphymiirx_converter_converter_strobe_all <= 1'd0;
-	end
-	vns_liteethmacpreamblechecker_state <= vns_liteethmacpreamblechecker_next_state;
-	if (soc_crc32_checker_crc_ce) begin
-		soc_crc32_checker_crc_reg <= soc_crc32_checker_crc_next;
-	end
-	if (soc_crc32_checker_crc_reset) begin
-		soc_crc32_checker_crc_reg <= 32'd4294967295;
-	end
-	if (((soc_crc32_checker_syncfifo_syncfifo_we & soc_crc32_checker_syncfifo_syncfifo_writable) & (~soc_crc32_checker_syncfifo_replace))) begin
-		if ((soc_crc32_checker_syncfifo_produce == 3'd4)) begin
-			soc_crc32_checker_syncfifo_produce <= 1'd0;
-		end else begin
-			soc_crc32_checker_syncfifo_produce <= (soc_crc32_checker_syncfifo_produce + 1'd1);
-		end
-	end
-	if (soc_crc32_checker_syncfifo_do_read) begin
-		if ((soc_crc32_checker_syncfifo_consume == 3'd4)) begin
-			soc_crc32_checker_syncfifo_consume <= 1'd0;
-		end else begin
-			soc_crc32_checker_syncfifo_consume <= (soc_crc32_checker_syncfifo_consume + 1'd1);
-		end
-	end
-	if (((soc_crc32_checker_syncfifo_syncfifo_we & soc_crc32_checker_syncfifo_syncfifo_writable) & (~soc_crc32_checker_syncfifo_replace))) begin
-		if ((~soc_crc32_checker_syncfifo_do_read)) begin
-			soc_crc32_checker_syncfifo_level <= (soc_crc32_checker_syncfifo_level + 1'd1);
-		end
-	end else begin
-		if (soc_crc32_checker_syncfifo_do_read) begin
-			soc_crc32_checker_syncfifo_level <= (soc_crc32_checker_syncfifo_level - 1'd1);
-		end
-	end
-	if (soc_crc32_checker_fifo_reset) begin
-		soc_crc32_checker_syncfifo_level <= 3'd0;
-		soc_crc32_checker_syncfifo_produce <= 3'd0;
-		soc_crc32_checker_syncfifo_consume <= 3'd0;
-	end
-	vns_liteethmaccrc32checker_state <= vns_liteethmaccrc32checker_next_state;
-	if (soc_ps_preamble_error_i) begin
-		soc_ps_preamble_error_toggle_i <= (~soc_ps_preamble_error_toggle_i);
-	end
-	if (soc_ps_crc_error_i) begin
-		soc_ps_crc_error_toggle_i <= (~soc_ps_crc_error_toggle_i);
-	end
-	if (soc_rx_converter_converter_source_ready) begin
-		soc_rx_converter_converter_strobe_all <= 1'd0;
-	end
-	if (soc_rx_converter_converter_load_part) begin
-		if (((soc_rx_converter_converter_demux == 2'd3) | soc_rx_converter_converter_sink_last)) begin
-			soc_rx_converter_converter_demux <= 1'd0;
-			soc_rx_converter_converter_strobe_all <= 1'd1;
-		end else begin
-			soc_rx_converter_converter_demux <= (soc_rx_converter_converter_demux + 1'd1);
-		end
-	end
-	if ((soc_rx_converter_converter_source_valid & soc_rx_converter_converter_source_ready)) begin
-		if ((soc_rx_converter_converter_sink_valid & soc_rx_converter_converter_sink_ready)) begin
-			soc_rx_converter_converter_source_first <= soc_rx_converter_converter_sink_first;
-			soc_rx_converter_converter_source_last <= soc_rx_converter_converter_sink_last;
-		end else begin
-			soc_rx_converter_converter_source_first <= 1'd0;
-			soc_rx_converter_converter_source_last <= 1'd0;
-		end
-	end else begin
-		if ((soc_rx_converter_converter_sink_valid & soc_rx_converter_converter_sink_ready)) begin
-			soc_rx_converter_converter_source_first <= (soc_rx_converter_converter_sink_first | soc_rx_converter_converter_source_first);
-			soc_rx_converter_converter_source_last <= (soc_rx_converter_converter_sink_last | soc_rx_converter_converter_source_last);
-		end
-	end
-	if (soc_rx_converter_converter_load_part) begin
-		case (soc_rx_converter_converter_demux)
-			1'd0: begin
-				soc_rx_converter_converter_source_payload_data[9:0] <= soc_rx_converter_converter_sink_payload_data;
-			end
-			1'd1: begin
-				soc_rx_converter_converter_source_payload_data[19:10] <= soc_rx_converter_converter_sink_payload_data;
-			end
-			2'd2: begin
-				soc_rx_converter_converter_source_payload_data[29:20] <= soc_rx_converter_converter_sink_payload_data;
-			end
-			2'd3: begin
-				soc_rx_converter_converter_source_payload_data[39:30] <= soc_rx_converter_converter_sink_payload_data;
-			end
-		endcase
-	end
-	if (soc_rx_converter_converter_load_part) begin
-		soc_rx_converter_converter_source_payload_valid_token_count <= (soc_rx_converter_converter_demux + 1'd1);
-	end
-	soc_rx_cdc_graycounter0_q_binary <= soc_rx_cdc_graycounter0_q_next_binary;
-	soc_rx_cdc_graycounter0_q <= soc_rx_cdc_graycounter0_q_next;
-	if (eth_rx_rst) begin
-		soc_liteethphymiirx_converter_sink_valid <= 1'd0;
-		soc_liteethphymiirx_converter_sink_payload_data <= 4'd0;
-		soc_liteethphymiirx_converter_converter_source_first <= 1'd0;
-		soc_liteethphymiirx_converter_converter_source_last <= 1'd0;
-		soc_liteethphymiirx_converter_converter_source_payload_data <= 8'd0;
-		soc_liteethphymiirx_converter_converter_source_payload_valid_token_count <= 2'd0;
-		soc_liteethphymiirx_converter_converter_demux <= 1'd0;
-		soc_liteethphymiirx_converter_converter_strobe_all <= 1'd0;
-		soc_liteethphymiirx_converter_reset <= 1'd0;
-		soc_crc32_checker_crc_reg <= 32'd4294967295;
-		soc_crc32_checker_syncfifo_level <= 3'd0;
-		soc_crc32_checker_syncfifo_produce <= 3'd0;
-		soc_crc32_checker_syncfifo_consume <= 3'd0;
-		soc_rx_converter_converter_source_first <= 1'd0;
-		soc_rx_converter_converter_source_last <= 1'd0;
-		soc_rx_converter_converter_source_payload_data <= 40'd0;
-		soc_rx_converter_converter_source_payload_valid_token_count <= 3'd0;
-		soc_rx_converter_converter_demux <= 2'd0;
-		soc_rx_converter_converter_strobe_all <= 1'd0;
-		soc_rx_cdc_graycounter0_q <= 7'd0;
-		soc_rx_cdc_graycounter0_q_binary <= 7'd0;
-		vns_liteethmacpreamblechecker_state <= 1'd0;
-		vns_liteethmaccrc32checker_state <= 2'd0;
-	end
-	vns_xilinxmultiregimpl7_regs0 <= soc_rx_cdc_graycounter1_q;
-	vns_xilinxmultiregimpl7_regs1 <= vns_xilinxmultiregimpl7_regs0;
-end
-
-always @(posedge eth_tx_clk) begin
-	eth_tx_en <= soc_liteethphymiitx_converter_source_valid;
-	eth_tx_data <= soc_liteethphymiitx_converter_source_payload_data;
-	if ((soc_liteethphymiitx_converter_converter_source_valid & soc_liteethphymiitx_converter_converter_source_ready)) begin
-		if (soc_liteethphymiitx_converter_converter_last) begin
-			soc_liteethphymiitx_converter_converter_mux <= 1'd0;
-		end else begin
-			soc_liteethphymiitx_converter_converter_mux <= (soc_liteethphymiitx_converter_converter_mux + 1'd1);
-		end
-	end
-	if (soc_tx_gap_inserter_counter_reset) begin
-		soc_tx_gap_inserter_counter <= 1'd0;
-	end else begin
-		if (soc_tx_gap_inserter_counter_ce) begin
-			soc_tx_gap_inserter_counter <= (soc_tx_gap_inserter_counter + 1'd1);
-		end
-	end
-	vns_liteethmacgap_state <= vns_liteethmacgap_next_state;
-	if (soc_preamble_inserter_clr_cnt) begin
-		soc_preamble_inserter_cnt <= 1'd0;
-	end else begin
-		if (soc_preamble_inserter_inc_cnt) begin
-			soc_preamble_inserter_cnt <= (soc_preamble_inserter_cnt + 1'd1);
-		end
-	end
-	vns_liteethmacpreambleinserter_state <= vns_liteethmacpreambleinserter_next_state;
-	if (soc_crc32_inserter_is_ongoing0) begin
-		soc_crc32_inserter_cnt <= 2'd3;
-	end else begin
-		if ((soc_crc32_inserter_is_ongoing1 & (~soc_crc32_inserter_cnt_done))) begin
-			soc_crc32_inserter_cnt <= (soc_crc32_inserter_cnt - soc_crc32_inserter_source_ready);
-		end
-	end
-	if (soc_crc32_inserter_ce) begin
-		soc_crc32_inserter_reg <= soc_crc32_inserter_next;
-	end
-	if (soc_crc32_inserter_reset) begin
-		soc_crc32_inserter_reg <= 32'd4294967295;
-	end
-	vns_liteethmaccrc32inserter_state <= vns_liteethmaccrc32inserter_next_state;
-	if (soc_padding_inserter_counter_reset) begin
-		soc_padding_inserter_counter <= 1'd0;
-	end else begin
-		if (soc_padding_inserter_counter_ce) begin
-			soc_padding_inserter_counter <= (soc_padding_inserter_counter + 1'd1);
-		end
-	end
-	vns_liteethmacpaddinginserter_state <= vns_liteethmacpaddinginserter_next_state;
-	if ((soc_tx_last_be_sink_valid & soc_tx_last_be_sink_ready)) begin
-		if (soc_tx_last_be_sink_last) begin
-			soc_tx_last_be_ongoing <= 1'd1;
-		end else begin
-			if (soc_tx_last_be_sink_payload_last_be) begin
-				soc_tx_last_be_ongoing <= 1'd0;
-			end
-		end
-	end
-	if ((soc_tx_converter_converter_source_valid & soc_tx_converter_converter_source_ready)) begin
-		if (soc_tx_converter_converter_last) begin
-			soc_tx_converter_converter_mux <= 1'd0;
-		end else begin
-			soc_tx_converter_converter_mux <= (soc_tx_converter_converter_mux + 1'd1);
-		end
-	end
-	soc_tx_cdc_graycounter1_q_binary <= soc_tx_cdc_graycounter1_q_next_binary;
-	soc_tx_cdc_graycounter1_q <= soc_tx_cdc_graycounter1_q_next;
-	if (eth_tx_rst) begin
-		soc_liteethphymiitx_converter_converter_mux <= 1'd0;
-		soc_crc32_inserter_reg <= 32'd4294967295;
-		soc_crc32_inserter_cnt <= 2'd3;
-		soc_padding_inserter_counter <= 16'd1;
-		soc_tx_last_be_ongoing <= 1'd1;
-		soc_tx_converter_converter_mux <= 2'd0;
-		soc_tx_cdc_graycounter1_q <= 7'd0;
-		soc_tx_cdc_graycounter1_q_binary <= 7'd0;
-		vns_liteethmacgap_state <= 1'd0;
-		vns_liteethmacpreambleinserter_state <= 2'd0;
-		vns_liteethmaccrc32inserter_state <= 2'd0;
-		vns_liteethmacpaddinginserter_state <= 1'd0;
-	end
-	vns_xilinxmultiregimpl4_regs0 <= soc_tx_cdc_graycounter0_q;
-	vns_xilinxmultiregimpl4_regs1 <= vns_xilinxmultiregimpl4_regs0;
-end
-
-always @(posedge sys_clk) begin
-	if ((soc_netsoc_ctrl_bus_errors != 32'd4294967295)) begin
-		if (soc_netsoc_ctrl_bus_error) begin
-			soc_netsoc_ctrl_bus_errors <= (soc_netsoc_ctrl_bus_errors + 1'd1);
-		end
-	end
-	soc_netsoc_cpu_time <= (soc_netsoc_cpu_time + 1'd1);
-	if (soc_netsoc_cpu_latch_re) begin
-		soc_netsoc_cpu_time_status <= soc_netsoc_cpu_time;
-	end
-	if (soc_netsoc_cpu_latch_re) begin
-		soc_netsoc_cpu_time_cmp <= soc_netsoc_cpu_time_cmp_storage;
-	end
-	soc_netsoc_rom_bus_ack <= 1'd0;
-	if (((soc_netsoc_rom_bus_cyc & soc_netsoc_rom_bus_stb) & (~soc_netsoc_rom_bus_ack))) begin
-		soc_netsoc_rom_bus_ack <= 1'd1;
-	end
-	soc_netsoc_sram_bus_ack <= 1'd0;
-	if (((soc_netsoc_sram_bus_cyc & soc_netsoc_sram_bus_stb) & (~soc_netsoc_sram_bus_ack))) begin
-		soc_netsoc_sram_bus_ack <= 1'd1;
-	end
-	soc_netsoc_uart_phy_sink_ready <= 1'd0;
-	if (((soc_netsoc_uart_phy_sink_valid & (~soc_netsoc_uart_phy_tx_busy)) & (~soc_netsoc_uart_phy_sink_ready))) begin
-		soc_netsoc_uart_phy_tx_reg <= soc_netsoc_uart_phy_sink_payload_data;
-		soc_netsoc_uart_phy_tx_bitcount <= 1'd0;
-		soc_netsoc_uart_phy_tx_busy <= 1'd1;
-		serial_tx <= 1'd0;
-	end else begin
-		if ((soc_netsoc_uart_phy_uart_clk_txen & soc_netsoc_uart_phy_tx_busy)) begin
-			soc_netsoc_uart_phy_tx_bitcount <= (soc_netsoc_uart_phy_tx_bitcount + 1'd1);
-			if ((soc_netsoc_uart_phy_tx_bitcount == 4'd8)) begin
-				serial_tx <= 1'd1;
-			end else begin
-				if ((soc_netsoc_uart_phy_tx_bitcount == 4'd9)) begin
-					serial_tx <= 1'd1;
-					soc_netsoc_uart_phy_tx_busy <= 1'd0;
-					soc_netsoc_uart_phy_sink_ready <= 1'd1;
-				end else begin
-					serial_tx <= soc_netsoc_uart_phy_tx_reg[0];
-					soc_netsoc_uart_phy_tx_reg <= {1'd0, soc_netsoc_uart_phy_tx_reg[7:1]};
-				end
-			end
-		end
-	end
-	if (soc_netsoc_uart_phy_tx_busy) begin
-		{soc_netsoc_uart_phy_uart_clk_txen, soc_netsoc_uart_phy_phase_accumulator_tx} <= (soc_netsoc_uart_phy_phase_accumulator_tx + soc_netsoc_uart_phy_storage);
-	end else begin
-		{soc_netsoc_uart_phy_uart_clk_txen, soc_netsoc_uart_phy_phase_accumulator_tx} <= 1'd0;
-	end
-	soc_netsoc_uart_phy_source_valid <= 1'd0;
-	soc_netsoc_uart_phy_rx_r <= soc_netsoc_uart_phy_rx;
-	if ((~soc_netsoc_uart_phy_rx_busy)) begin
-		if (((~soc_netsoc_uart_phy_rx) & soc_netsoc_uart_phy_rx_r)) begin
-			soc_netsoc_uart_phy_rx_busy <= 1'd1;
-			soc_netsoc_uart_phy_rx_bitcount <= 1'd0;
-		end
-	end else begin
-		if (soc_netsoc_uart_phy_uart_clk_rxen) begin
-			soc_netsoc_uart_phy_rx_bitcount <= (soc_netsoc_uart_phy_rx_bitcount + 1'd1);
-			if ((soc_netsoc_uart_phy_rx_bitcount == 1'd0)) begin
-				if (soc_netsoc_uart_phy_rx) begin
-					soc_netsoc_uart_phy_rx_busy <= 1'd0;
-				end
-			end else begin
-				if ((soc_netsoc_uart_phy_rx_bitcount == 4'd9)) begin
-					soc_netsoc_uart_phy_rx_busy <= 1'd0;
-					if (soc_netsoc_uart_phy_rx) begin
-						soc_netsoc_uart_phy_source_payload_data <= soc_netsoc_uart_phy_rx_reg;
-						soc_netsoc_uart_phy_source_valid <= 1'd1;
-					end
-				end else begin
-					soc_netsoc_uart_phy_rx_reg <= {soc_netsoc_uart_phy_rx, soc_netsoc_uart_phy_rx_reg[7:1]};
-				end
-			end
-		end
-	end
-	if (soc_netsoc_uart_phy_rx_busy) begin
-		{soc_netsoc_uart_phy_uart_clk_rxen, soc_netsoc_uart_phy_phase_accumulator_rx} <= (soc_netsoc_uart_phy_phase_accumulator_rx + soc_netsoc_uart_phy_storage);
-	end else begin
-		{soc_netsoc_uart_phy_uart_clk_rxen, soc_netsoc_uart_phy_phase_accumulator_rx} <= 32'd2147483648;
-	end
-	if (soc_netsoc_uart_tx_clear) begin
-		soc_netsoc_uart_tx_pending <= 1'd0;
-	end
-	soc_netsoc_uart_tx_old_trigger <= soc_netsoc_uart_tx_trigger;
-	if (((~soc_netsoc_uart_tx_trigger) & soc_netsoc_uart_tx_old_trigger)) begin
-		soc_netsoc_uart_tx_pending <= 1'd1;
-	end
-	if (soc_netsoc_uart_rx_clear) begin
-		soc_netsoc_uart_rx_pending <= 1'd0;
-	end
-	soc_netsoc_uart_rx_old_trigger <= soc_netsoc_uart_rx_trigger;
-	if (((~soc_netsoc_uart_rx_trigger) & soc_netsoc_uart_rx_old_trigger)) begin
-		soc_netsoc_uart_rx_pending <= 1'd1;
-	end
-	if (soc_netsoc_uart_tx_fifo_syncfifo_re) begin
-		soc_netsoc_uart_tx_fifo_readable <= 1'd1;
-	end else begin
-		if (soc_netsoc_uart_tx_fifo_re) begin
-			soc_netsoc_uart_tx_fifo_readable <= 1'd0;
-		end
-	end
-	if (((soc_netsoc_uart_tx_fifo_syncfifo_we & soc_netsoc_uart_tx_fifo_syncfifo_writable) & (~soc_netsoc_uart_tx_fifo_replace))) begin
-		soc_netsoc_uart_tx_fifo_produce <= (soc_netsoc_uart_tx_fifo_produce + 1'd1);
-	end
-	if (soc_netsoc_uart_tx_fifo_do_read) begin
-		soc_netsoc_uart_tx_fifo_consume <= (soc_netsoc_uart_tx_fifo_consume + 1'd1);
-	end
-	if (((soc_netsoc_uart_tx_fifo_syncfifo_we & soc_netsoc_uart_tx_fifo_syncfifo_writable) & (~soc_netsoc_uart_tx_fifo_replace))) begin
-		if ((~soc_netsoc_uart_tx_fifo_do_read)) begin
-			soc_netsoc_uart_tx_fifo_level0 <= (soc_netsoc_uart_tx_fifo_level0 + 1'd1);
-		end
-	end else begin
-		if (soc_netsoc_uart_tx_fifo_do_read) begin
-			soc_netsoc_uart_tx_fifo_level0 <= (soc_netsoc_uart_tx_fifo_level0 - 1'd1);
-		end
-	end
-	if (soc_netsoc_uart_rx_fifo_syncfifo_re) begin
-		soc_netsoc_uart_rx_fifo_readable <= 1'd1;
-	end else begin
-		if (soc_netsoc_uart_rx_fifo_re) begin
-			soc_netsoc_uart_rx_fifo_readable <= 1'd0;
-		end
-	end
-	if (((soc_netsoc_uart_rx_fifo_syncfifo_we & soc_netsoc_uart_rx_fifo_syncfifo_writable) & (~soc_netsoc_uart_rx_fifo_replace))) begin
-		soc_netsoc_uart_rx_fifo_produce <= (soc_netsoc_uart_rx_fifo_produce + 1'd1);
-	end
-	if (soc_netsoc_uart_rx_fifo_do_read) begin
-		soc_netsoc_uart_rx_fifo_consume <= (soc_netsoc_uart_rx_fifo_consume + 1'd1);
-	end
-	if (((soc_netsoc_uart_rx_fifo_syncfifo_we & soc_netsoc_uart_rx_fifo_syncfifo_writable) & (~soc_netsoc_uart_rx_fifo_replace))) begin
-		if ((~soc_netsoc_uart_rx_fifo_do_read)) begin
-			soc_netsoc_uart_rx_fifo_level0 <= (soc_netsoc_uart_rx_fifo_level0 + 1'd1);
-		end
-	end else begin
-		if (soc_netsoc_uart_rx_fifo_do_read) begin
-			soc_netsoc_uart_rx_fifo_level0 <= (soc_netsoc_uart_rx_fifo_level0 - 1'd1);
-		end
-	end
-	if (soc_netsoc_uart_reset) begin
-		soc_netsoc_uart_tx_pending <= 1'd0;
-		soc_netsoc_uart_tx_old_trigger <= 1'd0;
-		soc_netsoc_uart_rx_pending <= 1'd0;
-		soc_netsoc_uart_rx_old_trigger <= 1'd0;
-		soc_netsoc_uart_tx_fifo_readable <= 1'd0;
-		soc_netsoc_uart_tx_fifo_level0 <= 5'd0;
-		soc_netsoc_uart_tx_fifo_produce <= 4'd0;
-		soc_netsoc_uart_tx_fifo_consume <= 4'd0;
-		soc_netsoc_uart_rx_fifo_readable <= 1'd0;
-		soc_netsoc_uart_rx_fifo_level0 <= 5'd0;
-		soc_netsoc_uart_rx_fifo_produce <= 4'd0;
-		soc_netsoc_uart_rx_fifo_consume <= 4'd0;
-	end
-	if (soc_netsoc_timer0_en_storage) begin
-		if ((soc_netsoc_timer0_value == 1'd0)) begin
-			soc_netsoc_timer0_value <= soc_netsoc_timer0_reload_storage;
-		end else begin
-			soc_netsoc_timer0_value <= (soc_netsoc_timer0_value - 1'd1);
-		end
-	end else begin
-		soc_netsoc_timer0_value <= soc_netsoc_timer0_load_storage;
-	end
-	if (soc_netsoc_timer0_update_value_re) begin
-		soc_netsoc_timer0_value_status <= soc_netsoc_timer0_value;
-	end
-	if (soc_netsoc_timer0_zero_clear) begin
-		soc_netsoc_timer0_zero_pending <= 1'd0;
-	end
-	soc_netsoc_timer0_zero_old_trigger <= soc_netsoc_timer0_zero_trigger;
-	if (((~soc_netsoc_timer0_zero_trigger) & soc_netsoc_timer0_zero_old_trigger)) begin
-		soc_netsoc_timer0_zero_pending <= 1'd1;
-	end
-	vns_wb2csr_state <= vns_wb2csr_next_state;
-	soc_emulator_ram_bus_ack <= 1'd0;
-	if (((soc_emulator_ram_bus_cyc & soc_emulator_ram_bus_stb) & (~soc_emulator_ram_bus_ack))) begin
-		soc_emulator_ram_bus_ack <= 1'd1;
-	end
-	if (soc_a7ddrphy_dly_sel_storage[0]) begin
-		if (soc_a7ddrphy_rdly_dq_bitslip_rst_re) begin
-			soc_a7ddrphy_bitslip0_value <= 1'd0;
-		end else begin
-			if (soc_a7ddrphy_rdly_dq_bitslip_re) begin
-				soc_a7ddrphy_bitslip0_value <= (soc_a7ddrphy_bitslip0_value + 1'd1);
-			end
-		end
-	end
-	if (soc_a7ddrphy_dly_sel_storage[0]) begin
-		if (soc_a7ddrphy_rdly_dq_bitslip_rst_re) begin
-			soc_a7ddrphy_bitslip1_value <= 1'd0;
-		end else begin
-			if (soc_a7ddrphy_rdly_dq_bitslip_re) begin
-				soc_a7ddrphy_bitslip1_value <= (soc_a7ddrphy_bitslip1_value + 1'd1);
-			end
-		end
-	end
-	if (soc_a7ddrphy_dly_sel_storage[0]) begin
-		if (soc_a7ddrphy_rdly_dq_bitslip_rst_re) begin
-			soc_a7ddrphy_bitslip2_value <= 1'd0;
-		end else begin
-			if (soc_a7ddrphy_rdly_dq_bitslip_re) begin
-				soc_a7ddrphy_bitslip2_value <= (soc_a7ddrphy_bitslip2_value + 1'd1);
-			end
-		end
-	end
-	if (soc_a7ddrphy_dly_sel_storage[0]) begin
-		if (soc_a7ddrphy_rdly_dq_bitslip_rst_re) begin
-			soc_a7ddrphy_bitslip3_value <= 1'd0;
-		end else begin
-			if (soc_a7ddrphy_rdly_dq_bitslip_re) begin
-				soc_a7ddrphy_bitslip3_value <= (soc_a7ddrphy_bitslip3_value + 1'd1);
-			end
-		end
-	end
-	if (soc_a7ddrphy_dly_sel_storage[0]) begin
-		if (soc_a7ddrphy_rdly_dq_bitslip_rst_re) begin
-			soc_a7ddrphy_bitslip4_value <= 1'd0;
-		end else begin
-			if (soc_a7ddrphy_rdly_dq_bitslip_re) begin
-				soc_a7ddrphy_bitslip4_value <= (soc_a7ddrphy_bitslip4_value + 1'd1);
-			end
-		end
-	end
-	if (soc_a7ddrphy_dly_sel_storage[0]) begin
-		if (soc_a7ddrphy_rdly_dq_bitslip_rst_re) begin
-			soc_a7ddrphy_bitslip5_value <= 1'd0;
-		end else begin
-			if (soc_a7ddrphy_rdly_dq_bitslip_re) begin
-				soc_a7ddrphy_bitslip5_value <= (soc_a7ddrphy_bitslip5_value + 1'd1);
-			end
-		end
-	end
-	if (soc_a7ddrphy_dly_sel_storage[0]) begin
-		if (soc_a7ddrphy_rdly_dq_bitslip_rst_re) begin
-			soc_a7ddrphy_bitslip6_value <= 1'd0;
-		end else begin
-			if (soc_a7ddrphy_rdly_dq_bitslip_re) begin
-				soc_a7ddrphy_bitslip6_value <= (soc_a7ddrphy_bitslip6_value + 1'd1);
-			end
-		end
-	end
-	if (soc_a7ddrphy_dly_sel_storage[0]) begin
-		if (soc_a7ddrphy_rdly_dq_bitslip_rst_re) begin
-			soc_a7ddrphy_bitslip7_value <= 1'd0;
-		end else begin
-			if (soc_a7ddrphy_rdly_dq_bitslip_re) begin
-				soc_a7ddrphy_bitslip7_value <= (soc_a7ddrphy_bitslip7_value + 1'd1);
-			end
-		end
-	end
-	if (soc_a7ddrphy_dly_sel_storage[1]) begin
-		if (soc_a7ddrphy_rdly_dq_bitslip_rst_re) begin
-			soc_a7ddrphy_bitslip8_value <= 1'd0;
-		end else begin
-			if (soc_a7ddrphy_rdly_dq_bitslip_re) begin
-				soc_a7ddrphy_bitslip8_value <= (soc_a7ddrphy_bitslip8_value + 1'd1);
-			end
-		end
-	end
-	if (soc_a7ddrphy_dly_sel_storage[1]) begin
-		if (soc_a7ddrphy_rdly_dq_bitslip_rst_re) begin
-			soc_a7ddrphy_bitslip9_value <= 1'd0;
-		end else begin
-			if (soc_a7ddrphy_rdly_dq_bitslip_re) begin
-				soc_a7ddrphy_bitslip9_value <= (soc_a7ddrphy_bitslip9_value + 1'd1);
-			end
-		end
-	end
-	if (soc_a7ddrphy_dly_sel_storage[1]) begin
-		if (soc_a7ddrphy_rdly_dq_bitslip_rst_re) begin
-			soc_a7ddrphy_bitslip10_value <= 1'd0;
-		end else begin
-			if (soc_a7ddrphy_rdly_dq_bitslip_re) begin
-				soc_a7ddrphy_bitslip10_value <= (soc_a7ddrphy_bitslip10_value + 1'd1);
-			end
-		end
-	end
-	if (soc_a7ddrphy_dly_sel_storage[1]) begin
-		if (soc_a7ddrphy_rdly_dq_bitslip_rst_re) begin
-			soc_a7ddrphy_bitslip11_value <= 1'd0;
-		end else begin
-			if (soc_a7ddrphy_rdly_dq_bitslip_re) begin
-				soc_a7ddrphy_bitslip11_value <= (soc_a7ddrphy_bitslip11_value + 1'd1);
-			end
-		end
-	end
-	if (soc_a7ddrphy_dly_sel_storage[1]) begin
-		if (soc_a7ddrphy_rdly_dq_bitslip_rst_re) begin
-			soc_a7ddrphy_bitslip12_value <= 1'd0;
-		end else begin
-			if (soc_a7ddrphy_rdly_dq_bitslip_re) begin
-				soc_a7ddrphy_bitslip12_value <= (soc_a7ddrphy_bitslip12_value + 1'd1);
-			end
-		end
-	end
-	if (soc_a7ddrphy_dly_sel_storage[1]) begin
-		if (soc_a7ddrphy_rdly_dq_bitslip_rst_re) begin
-			soc_a7ddrphy_bitslip13_value <= 1'd0;
-		end else begin
-			if (soc_a7ddrphy_rdly_dq_bitslip_re) begin
-				soc_a7ddrphy_bitslip13_value <= (soc_a7ddrphy_bitslip13_value + 1'd1);
-			end
-		end
-	end
-	if (soc_a7ddrphy_dly_sel_storage[1]) begin
-		if (soc_a7ddrphy_rdly_dq_bitslip_rst_re) begin
-			soc_a7ddrphy_bitslip14_value <= 1'd0;
-		end else begin
-			if (soc_a7ddrphy_rdly_dq_bitslip_re) begin
-				soc_a7ddrphy_bitslip14_value <= (soc_a7ddrphy_bitslip14_value + 1'd1);
-			end
-		end
-	end
-	if (soc_a7ddrphy_dly_sel_storage[1]) begin
-		if (soc_a7ddrphy_rdly_dq_bitslip_rst_re) begin
-			soc_a7ddrphy_bitslip15_value <= 1'd0;
-		end else begin
-			if (soc_a7ddrphy_rdly_dq_bitslip_re) begin
-				soc_a7ddrphy_bitslip15_value <= (soc_a7ddrphy_bitslip15_value + 1'd1);
-			end
-		end
-	end
-	soc_a7ddrphy_n_rddata_en0 <= soc_a7ddrphy_dfi_p2_rddata_en;
-	soc_a7ddrphy_n_rddata_en1 <= soc_a7ddrphy_n_rddata_en0;
-	soc_a7ddrphy_n_rddata_en2 <= soc_a7ddrphy_n_rddata_en1;
-	soc_a7ddrphy_n_rddata_en3 <= soc_a7ddrphy_n_rddata_en2;
-	soc_a7ddrphy_n_rddata_en4 <= soc_a7ddrphy_n_rddata_en3;
-	soc_a7ddrphy_n_rddata_en5 <= soc_a7ddrphy_n_rddata_en4;
-	soc_a7ddrphy_n_rddata_en6 <= soc_a7ddrphy_n_rddata_en5;
-	soc_a7ddrphy_n_rddata_en7 <= soc_a7ddrphy_n_rddata_en6;
-	soc_a7ddrphy_dfi_p0_rddata_valid <= soc_a7ddrphy_n_rddata_en7;
-	soc_a7ddrphy_dfi_p1_rddata_valid <= soc_a7ddrphy_n_rddata_en7;
-	soc_a7ddrphy_dfi_p2_rddata_valid <= soc_a7ddrphy_n_rddata_en7;
-	soc_a7ddrphy_dfi_p3_rddata_valid <= soc_a7ddrphy_n_rddata_en7;
-	soc_a7ddrphy_last_wrdata_en <= {soc_a7ddrphy_last_wrdata_en[2:0], soc_a7ddrphy_dfi_p3_wrdata_en};
-	soc_a7ddrphy_oe_dqs <= soc_a7ddrphy_oe;
-	soc_a7ddrphy_oe_dq <= soc_a7ddrphy_oe;
-	soc_a7ddrphy_bitslip0_r <= {soc_a7ddrphy_bitslip0_i, soc_a7ddrphy_bitslip0_r[15:8]};
-	case (soc_a7ddrphy_bitslip0_value)
-		1'd0: begin
-			soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[7:0];
-		end
-		1'd1: begin
-			soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[8:1];
-		end
-		2'd2: begin
-			soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[9:2];
-		end
-		2'd3: begin
-			soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[10:3];
-		end
-		3'd4: begin
-			soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[11:4];
-		end
-		3'd5: begin
-			soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[12:5];
-		end
-		3'd6: begin
-			soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[13:6];
-		end
-		3'd7: begin
-			soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[14:7];
-		end
-	endcase
-	soc_a7ddrphy_bitslip1_r <= {soc_a7ddrphy_bitslip1_i, soc_a7ddrphy_bitslip1_r[15:8]};
-	case (soc_a7ddrphy_bitslip1_value)
-		1'd0: begin
-			soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[7:0];
-		end
-		1'd1: begin
-			soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[8:1];
-		end
-		2'd2: begin
-			soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[9:2];
-		end
-		2'd3: begin
-			soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[10:3];
-		end
-		3'd4: begin
-			soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[11:4];
-		end
-		3'd5: begin
-			soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[12:5];
-		end
-		3'd6: begin
-			soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[13:6];
-		end
-		3'd7: begin
-			soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[14:7];
-		end
-	endcase
-	soc_a7ddrphy_bitslip2_r <= {soc_a7ddrphy_bitslip2_i, soc_a7ddrphy_bitslip2_r[15:8]};
-	case (soc_a7ddrphy_bitslip2_value)
-		1'd0: begin
-			soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[7:0];
-		end
-		1'd1: begin
-			soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[8:1];
-		end
-		2'd2: begin
-			soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[9:2];
-		end
-		2'd3: begin
-			soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[10:3];
-		end
-		3'd4: begin
-			soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[11:4];
-		end
-		3'd5: begin
-			soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[12:5];
-		end
-		3'd6: begin
-			soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[13:6];
-		end
-		3'd7: begin
-			soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[14:7];
-		end
-	endcase
-	soc_a7ddrphy_bitslip3_r <= {soc_a7ddrphy_bitslip3_i, soc_a7ddrphy_bitslip3_r[15:8]};
-	case (soc_a7ddrphy_bitslip3_value)
-		1'd0: begin
-			soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[7:0];
-		end
-		1'd1: begin
-			soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[8:1];
-		end
-		2'd2: begin
-			soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[9:2];
-		end
-		2'd3: begin
-			soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[10:3];
-		end
-		3'd4: begin
-			soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[11:4];
-		end
-		3'd5: begin
-			soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[12:5];
-		end
-		3'd6: begin
-			soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[13:6];
-		end
-		3'd7: begin
-			soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[14:7];
-		end
-	endcase
-	soc_a7ddrphy_bitslip4_r <= {soc_a7ddrphy_bitslip4_i, soc_a7ddrphy_bitslip4_r[15:8]};
-	case (soc_a7ddrphy_bitslip4_value)
-		1'd0: begin
-			soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[7:0];
-		end
-		1'd1: begin
-			soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[8:1];
-		end
-		2'd2: begin
-			soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[9:2];
-		end
-		2'd3: begin
-			soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[10:3];
-		end
-		3'd4: begin
-			soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[11:4];
-		end
-		3'd5: begin
-			soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[12:5];
-		end
-		3'd6: begin
-			soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[13:6];
-		end
-		3'd7: begin
-			soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[14:7];
-		end
-	endcase
-	soc_a7ddrphy_bitslip5_r <= {soc_a7ddrphy_bitslip5_i, soc_a7ddrphy_bitslip5_r[15:8]};
-	case (soc_a7ddrphy_bitslip5_value)
-		1'd0: begin
-			soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[7:0];
-		end
-		1'd1: begin
-			soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[8:1];
-		end
-		2'd2: begin
-			soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[9:2];
-		end
-		2'd3: begin
-			soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[10:3];
-		end
-		3'd4: begin
-			soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[11:4];
-		end
-		3'd5: begin
-			soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[12:5];
-		end
-		3'd6: begin
-			soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[13:6];
-		end
-		3'd7: begin
-			soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[14:7];
-		end
-	endcase
-	soc_a7ddrphy_bitslip6_r <= {soc_a7ddrphy_bitslip6_i, soc_a7ddrphy_bitslip6_r[15:8]};
-	case (soc_a7ddrphy_bitslip6_value)
-		1'd0: begin
-			soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[7:0];
-		end
-		1'd1: begin
-			soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[8:1];
-		end
-		2'd2: begin
-			soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[9:2];
-		end
-		2'd3: begin
-			soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[10:3];
-		end
-		3'd4: begin
-			soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[11:4];
-		end
-		3'd5: begin
-			soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[12:5];
-		end
-		3'd6: begin
-			soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[13:6];
-		end
-		3'd7: begin
-			soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[14:7];
-		end
-	endcase
-	soc_a7ddrphy_bitslip7_r <= {soc_a7ddrphy_bitslip7_i, soc_a7ddrphy_bitslip7_r[15:8]};
-	case (soc_a7ddrphy_bitslip7_value)
-		1'd0: begin
-			soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[7:0];
-		end
-		1'd1: begin
-			soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[8:1];
-		end
-		2'd2: begin
-			soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[9:2];
-		end
-		2'd3: begin
-			soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[10:3];
-		end
-		3'd4: begin
-			soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[11:4];
-		end
-		3'd5: begin
-			soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[12:5];
-		end
-		3'd6: begin
-			soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[13:6];
-		end
-		3'd7: begin
-			soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[14:7];
-		end
-	endcase
-	soc_a7ddrphy_bitslip8_r <= {soc_a7ddrphy_bitslip8_i, soc_a7ddrphy_bitslip8_r[15:8]};
-	case (soc_a7ddrphy_bitslip8_value)
-		1'd0: begin
-			soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[7:0];
-		end
-		1'd1: begin
-			soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[8:1];
-		end
-		2'd2: begin
-			soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[9:2];
-		end
-		2'd3: begin
-			soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[10:3];
-		end
-		3'd4: begin
-			soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[11:4];
-		end
-		3'd5: begin
-			soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[12:5];
-		end
-		3'd6: begin
-			soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[13:6];
-		end
-		3'd7: begin
-			soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[14:7];
-		end
-	endcase
-	soc_a7ddrphy_bitslip9_r <= {soc_a7ddrphy_bitslip9_i, soc_a7ddrphy_bitslip9_r[15:8]};
-	case (soc_a7ddrphy_bitslip9_value)
-		1'd0: begin
-			soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[7:0];
-		end
-		1'd1: begin
-			soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[8:1];
-		end
-		2'd2: begin
-			soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[9:2];
-		end
-		2'd3: begin
-			soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[10:3];
-		end
-		3'd4: begin
-			soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[11:4];
-		end
-		3'd5: begin
-			soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[12:5];
-		end
-		3'd6: begin
-			soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[13:6];
-		end
-		3'd7: begin
-			soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[14:7];
-		end
-	endcase
-	soc_a7ddrphy_bitslip10_r <= {soc_a7ddrphy_bitslip10_i, soc_a7ddrphy_bitslip10_r[15:8]};
-	case (soc_a7ddrphy_bitslip10_value)
-		1'd0: begin
-			soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[7:0];
-		end
-		1'd1: begin
-			soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[8:1];
-		end
-		2'd2: begin
-			soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[9:2];
-		end
-		2'd3: begin
-			soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[10:3];
-		end
-		3'd4: begin
-			soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[11:4];
-		end
-		3'd5: begin
-			soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[12:5];
-		end
-		3'd6: begin
-			soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[13:6];
-		end
-		3'd7: begin
-			soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[14:7];
-		end
-	endcase
-	soc_a7ddrphy_bitslip11_r <= {soc_a7ddrphy_bitslip11_i, soc_a7ddrphy_bitslip11_r[15:8]};
-	case (soc_a7ddrphy_bitslip11_value)
-		1'd0: begin
-			soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[7:0];
-		end
-		1'd1: begin
-			soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[8:1];
-		end
-		2'd2: begin
-			soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[9:2];
-		end
-		2'd3: begin
-			soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[10:3];
-		end
-		3'd4: begin
-			soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[11:4];
-		end
-		3'd5: begin
-			soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[12:5];
-		end
-		3'd6: begin
-			soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[13:6];
-		end
-		3'd7: begin
-			soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[14:7];
-		end
-	endcase
-	soc_a7ddrphy_bitslip12_r <= {soc_a7ddrphy_bitslip12_i, soc_a7ddrphy_bitslip12_r[15:8]};
-	case (soc_a7ddrphy_bitslip12_value)
-		1'd0: begin
-			soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[7:0];
-		end
-		1'd1: begin
-			soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[8:1];
-		end
-		2'd2: begin
-			soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[9:2];
-		end
-		2'd3: begin
-			soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[10:3];
-		end
-		3'd4: begin
-			soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[11:4];
-		end
-		3'd5: begin
-			soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[12:5];
-		end
-		3'd6: begin
-			soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[13:6];
-		end
-		3'd7: begin
-			soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[14:7];
-		end
-	endcase
-	soc_a7ddrphy_bitslip13_r <= {soc_a7ddrphy_bitslip13_i, soc_a7ddrphy_bitslip13_r[15:8]};
-	case (soc_a7ddrphy_bitslip13_value)
-		1'd0: begin
-			soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[7:0];
-		end
-		1'd1: begin
-			soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[8:1];
-		end
-		2'd2: begin
-			soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[9:2];
-		end
-		2'd3: begin
-			soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[10:3];
-		end
-		3'd4: begin
-			soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[11:4];
-		end
-		3'd5: begin
-			soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[12:5];
-		end
-		3'd6: begin
-			soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[13:6];
-		end
-		3'd7: begin
-			soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[14:7];
-		end
-	endcase
-	soc_a7ddrphy_bitslip14_r <= {soc_a7ddrphy_bitslip14_i, soc_a7ddrphy_bitslip14_r[15:8]};
-	case (soc_a7ddrphy_bitslip14_value)
-		1'd0: begin
-			soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[7:0];
-		end
-		1'd1: begin
-			soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[8:1];
-		end
-		2'd2: begin
-			soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[9:2];
-		end
-		2'd3: begin
-			soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[10:3];
-		end
-		3'd4: begin
-			soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[11:4];
-		end
-		3'd5: begin
-			soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[12:5];
-		end
-		3'd6: begin
-			soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[13:6];
-		end
-		3'd7: begin
-			soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[14:7];
-		end
-	endcase
-	soc_a7ddrphy_bitslip15_r <= {soc_a7ddrphy_bitslip15_i, soc_a7ddrphy_bitslip15_r[15:8]};
-	case (soc_a7ddrphy_bitslip15_value)
-		1'd0: begin
-			soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[7:0];
-		end
-		1'd1: begin
-			soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[8:1];
-		end
-		2'd2: begin
-			soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[9:2];
-		end
-		2'd3: begin
-			soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[10:3];
-		end
-		3'd4: begin
-			soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[11:4];
-		end
-		3'd5: begin
-			soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[12:5];
-		end
-		3'd6: begin
-			soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[13:6];
-		end
-		3'd7: begin
-			soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[14:7];
-		end
-	endcase
-	if (soc_netsoc_sdram_inti_p0_rddata_valid) begin
-		soc_netsoc_sdram_phaseinjector0_status <= soc_netsoc_sdram_inti_p0_rddata;
-	end
-	if (soc_netsoc_sdram_inti_p1_rddata_valid) begin
-		soc_netsoc_sdram_phaseinjector1_status <= soc_netsoc_sdram_inti_p1_rddata;
-	end
-	if (soc_netsoc_sdram_inti_p2_rddata_valid) begin
-		soc_netsoc_sdram_phaseinjector2_status <= soc_netsoc_sdram_inti_p2_rddata;
-	end
-	if (soc_netsoc_sdram_inti_p3_rddata_valid) begin
-		soc_netsoc_sdram_phaseinjector3_status <= soc_netsoc_sdram_inti_p3_rddata;
-	end
-	if ((soc_netsoc_sdram_timer_wait & (~soc_netsoc_sdram_timer_done0))) begin
-		soc_netsoc_sdram_timer_count1 <= (soc_netsoc_sdram_timer_count1 - 1'd1);
-	end else begin
-		soc_netsoc_sdram_timer_count1 <= 9'd468;
-	end
-	soc_netsoc_sdram_postponer_req_o <= 1'd0;
-	if (soc_netsoc_sdram_postponer_req_i) begin
-		soc_netsoc_sdram_postponer_count <= (soc_netsoc_sdram_postponer_count - 1'd1);
-		if ((soc_netsoc_sdram_postponer_count == 1'd0)) begin
-			soc_netsoc_sdram_postponer_count <= 1'd0;
-			soc_netsoc_sdram_postponer_req_o <= 1'd1;
-		end
-	end
-	if (soc_netsoc_sdram_sequencer_start0) begin
-		soc_netsoc_sdram_sequencer_count <= 1'd0;
-	end else begin
-		if (soc_netsoc_sdram_sequencer_done1) begin
-			if ((soc_netsoc_sdram_sequencer_count != 1'd0)) begin
-				soc_netsoc_sdram_sequencer_count <= (soc_netsoc_sdram_sequencer_count - 1'd1);
-			end
-		end
-	end
-	soc_netsoc_sdram_cmd_payload_a <= 1'd0;
-	soc_netsoc_sdram_cmd_payload_ba <= 1'd0;
-	soc_netsoc_sdram_cmd_payload_cas <= 1'd0;
-	soc_netsoc_sdram_cmd_payload_ras <= 1'd0;
-	soc_netsoc_sdram_cmd_payload_we <= 1'd0;
-	soc_netsoc_sdram_sequencer_done1 <= 1'd0;
-	if ((soc_netsoc_sdram_sequencer_start1 & (soc_netsoc_sdram_sequencer_counter == 1'd0))) begin
-		soc_netsoc_sdram_cmd_payload_a <= 11'd1024;
-		soc_netsoc_sdram_cmd_payload_ba <= 1'd0;
-		soc_netsoc_sdram_cmd_payload_cas <= 1'd0;
-		soc_netsoc_sdram_cmd_payload_ras <= 1'd1;
-		soc_netsoc_sdram_cmd_payload_we <= 1'd1;
-	end
-	if ((soc_netsoc_sdram_sequencer_counter == 2'd2)) begin
-		soc_netsoc_sdram_cmd_payload_a <= 1'd0;
-		soc_netsoc_sdram_cmd_payload_ba <= 1'd0;
-		soc_netsoc_sdram_cmd_payload_cas <= 1'd1;
-		soc_netsoc_sdram_cmd_payload_ras <= 1'd1;
-		soc_netsoc_sdram_cmd_payload_we <= 1'd0;
-	end
-	if ((soc_netsoc_sdram_sequencer_counter == 6'd34)) begin
-		soc_netsoc_sdram_cmd_payload_a <= 1'd0;
-		soc_netsoc_sdram_cmd_payload_ba <= 1'd0;
-		soc_netsoc_sdram_cmd_payload_cas <= 1'd0;
-		soc_netsoc_sdram_cmd_payload_ras <= 1'd0;
-		soc_netsoc_sdram_cmd_payload_we <= 1'd0;
-		soc_netsoc_sdram_sequencer_done1 <= 1'd1;
-	end
-	if ((soc_netsoc_sdram_sequencer_counter == 6'd34)) begin
-		soc_netsoc_sdram_sequencer_counter <= 1'd0;
-	end else begin
-		if ((soc_netsoc_sdram_sequencer_counter != 1'd0)) begin
-			soc_netsoc_sdram_sequencer_counter <= (soc_netsoc_sdram_sequencer_counter + 1'd1);
-		end else begin
-			if (soc_netsoc_sdram_sequencer_start1) begin
-				soc_netsoc_sdram_sequencer_counter <= 1'd1;
-			end
-		end
-	end
-	if ((soc_netsoc_sdram_zqcs_timer_wait & (~soc_netsoc_sdram_zqcs_timer_done0))) begin
-		soc_netsoc_sdram_zqcs_timer_count1 <= (soc_netsoc_sdram_zqcs_timer_count1 - 1'd1);
-	end else begin
-		soc_netsoc_sdram_zqcs_timer_count1 <= 26'd59999999;
-	end
-	soc_netsoc_sdram_zqcs_executer_done <= 1'd0;
-	if ((soc_netsoc_sdram_zqcs_executer_start & (soc_netsoc_sdram_zqcs_executer_counter == 1'd0))) begin
-		soc_netsoc_sdram_cmd_payload_a <= 11'd1024;
-		soc_netsoc_sdram_cmd_payload_ba <= 1'd0;
-		soc_netsoc_sdram_cmd_payload_cas <= 1'd0;
-		soc_netsoc_sdram_cmd_payload_ras <= 1'd1;
-		soc_netsoc_sdram_cmd_payload_we <= 1'd1;
-	end
-	if ((soc_netsoc_sdram_zqcs_executer_counter == 2'd2)) begin
-		soc_netsoc_sdram_cmd_payload_a <= 1'd0;
-		soc_netsoc_sdram_cmd_payload_ba <= 1'd0;
-		soc_netsoc_sdram_cmd_payload_cas <= 1'd0;
-		soc_netsoc_sdram_cmd_payload_ras <= 1'd0;
-		soc_netsoc_sdram_cmd_payload_we <= 1'd1;
-	end
-	if ((soc_netsoc_sdram_zqcs_executer_counter == 5'd18)) begin
-		soc_netsoc_sdram_cmd_payload_a <= 1'd0;
-		soc_netsoc_sdram_cmd_payload_ba <= 1'd0;
-		soc_netsoc_sdram_cmd_payload_cas <= 1'd0;
-		soc_netsoc_sdram_cmd_payload_ras <= 1'd0;
-		soc_netsoc_sdram_cmd_payload_we <= 1'd0;
-		soc_netsoc_sdram_zqcs_executer_done <= 1'd1;
-	end
-	if ((soc_netsoc_sdram_zqcs_executer_counter == 5'd18)) begin
-		soc_netsoc_sdram_zqcs_executer_counter <= 1'd0;
-	end else begin
-		if ((soc_netsoc_sdram_zqcs_executer_counter != 1'd0)) begin
-			soc_netsoc_sdram_zqcs_executer_counter <= (soc_netsoc_sdram_zqcs_executer_counter + 1'd1);
-		end else begin
-			if (soc_netsoc_sdram_zqcs_executer_start) begin
-				soc_netsoc_sdram_zqcs_executer_counter <= 1'd1;
-			end
-		end
-	end
-	vns_refresher_state <= vns_refresher_next_state;
-	if (soc_netsoc_sdram_bankmachine0_row_close) begin
-		soc_netsoc_sdram_bankmachine0_row_opened <= 1'd0;
-	end else begin
-		if (soc_netsoc_sdram_bankmachine0_row_open) begin
-			soc_netsoc_sdram_bankmachine0_row_opened <= 1'd1;
-			soc_netsoc_sdram_bankmachine0_row <= soc_netsoc_sdram_bankmachine0_cmd_buffer_source_payload_addr[20:7];
-		end
-	end
-	if (((soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_replace))) begin
-		soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_produce <= (soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_produce + 1'd1);
-	end
-	if (soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_do_read) begin
-		soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_consume <= (soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_consume + 1'd1);
-	end
-	if (((soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_replace))) begin
-		if ((~soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_do_read)) begin
-			soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_level <= (soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_level + 1'd1);
-		end
-	end else begin
-		if (soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_do_read) begin
-			soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_level <= (soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_level - 1'd1);
-		end
-	end
-	if (soc_netsoc_sdram_bankmachine0_cmd_buffer_pipe_ce) begin
-		soc_netsoc_sdram_bankmachine0_cmd_buffer_valid_n <= soc_netsoc_sdram_bankmachine0_cmd_buffer_sink_valid;
-	end
-	if (soc_netsoc_sdram_bankmachine0_cmd_buffer_pipe_ce) begin
-		soc_netsoc_sdram_bankmachine0_cmd_buffer_first_n <= (soc_netsoc_sdram_bankmachine0_cmd_buffer_sink_valid & soc_netsoc_sdram_bankmachine0_cmd_buffer_sink_first);
-		soc_netsoc_sdram_bankmachine0_cmd_buffer_last_n <= (soc_netsoc_sdram_bankmachine0_cmd_buffer_sink_valid & soc_netsoc_sdram_bankmachine0_cmd_buffer_sink_last);
-	end
-	if (soc_netsoc_sdram_bankmachine0_cmd_buffer_pipe_ce) begin
-		soc_netsoc_sdram_bankmachine0_cmd_buffer_source_payload_we <= soc_netsoc_sdram_bankmachine0_cmd_buffer_sink_payload_we;
-		soc_netsoc_sdram_bankmachine0_cmd_buffer_source_payload_addr <= soc_netsoc_sdram_bankmachine0_cmd_buffer_sink_payload_addr;
-	end
-	if (soc_netsoc_sdram_bankmachine0_twtpcon_valid) begin
-		soc_netsoc_sdram_bankmachine0_twtpcon_count <= 3'd4;
-		if (1'd0) begin
-			soc_netsoc_sdram_bankmachine0_twtpcon_ready <= 1'd1;
-		end else begin
-			soc_netsoc_sdram_bankmachine0_twtpcon_ready <= 1'd0;
-		end
-	end else begin
-		if ((~soc_netsoc_sdram_bankmachine0_twtpcon_ready)) begin
-			soc_netsoc_sdram_bankmachine0_twtpcon_count <= (soc_netsoc_sdram_bankmachine0_twtpcon_count - 1'd1);
-			if ((soc_netsoc_sdram_bankmachine0_twtpcon_count == 1'd1)) begin
-				soc_netsoc_sdram_bankmachine0_twtpcon_ready <= 1'd1;
-			end
-		end
-	end
-	if (soc_netsoc_sdram_bankmachine0_trccon_valid) begin
-		soc_netsoc_sdram_bankmachine0_trccon_count <= 2'd3;
-		if (1'd0) begin
-			soc_netsoc_sdram_bankmachine0_trccon_ready <= 1'd1;
-		end else begin
-			soc_netsoc_sdram_bankmachine0_trccon_ready <= 1'd0;
-		end
-	end else begin
-		if ((~soc_netsoc_sdram_bankmachine0_trccon_ready)) begin
-			soc_netsoc_sdram_bankmachine0_trccon_count <= (soc_netsoc_sdram_bankmachine0_trccon_count - 1'd1);
-			if ((soc_netsoc_sdram_bankmachine0_trccon_count == 1'd1)) begin
-				soc_netsoc_sdram_bankmachine0_trccon_ready <= 1'd1;
-			end
-		end
-	end
-	if (soc_netsoc_sdram_bankmachine0_trascon_valid) begin
-		soc_netsoc_sdram_bankmachine0_trascon_count <= 2'd2;
-		if (1'd0) begin
-			soc_netsoc_sdram_bankmachine0_trascon_ready <= 1'd1;
-		end else begin
-			soc_netsoc_sdram_bankmachine0_trascon_ready <= 1'd0;
-		end
-	end else begin
-		if ((~soc_netsoc_sdram_bankmachine0_trascon_ready)) begin
-			soc_netsoc_sdram_bankmachine0_trascon_count <= (soc_netsoc_sdram_bankmachine0_trascon_count - 1'd1);
-			if ((soc_netsoc_sdram_bankmachine0_trascon_count == 1'd1)) begin
-				soc_netsoc_sdram_bankmachine0_trascon_ready <= 1'd1;
-			end
-		end
-	end
-	vns_bankmachine0_state <= vns_bankmachine0_next_state;
-	if (soc_netsoc_sdram_bankmachine1_row_close) begin
-		soc_netsoc_sdram_bankmachine1_row_opened <= 1'd0;
-	end else begin
-		if (soc_netsoc_sdram_bankmachine1_row_open) begin
-			soc_netsoc_sdram_bankmachine1_row_opened <= 1'd1;
-			soc_netsoc_sdram_bankmachine1_row <= soc_netsoc_sdram_bankmachine1_cmd_buffer_source_payload_addr[20:7];
-		end
-	end
-	if (((soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_replace))) begin
-		soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_produce <= (soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_produce + 1'd1);
-	end
-	if (soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_do_read) begin
-		soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_consume <= (soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_consume + 1'd1);
-	end
-	if (((soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_replace))) begin
-		if ((~soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_do_read)) begin
-			soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_level <= (soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_level + 1'd1);
-		end
-	end else begin
-		if (soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_do_read) begin
-			soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_level <= (soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_level - 1'd1);
-		end
-	end
-	if (soc_netsoc_sdram_bankmachine1_cmd_buffer_pipe_ce) begin
-		soc_netsoc_sdram_bankmachine1_cmd_buffer_valid_n <= soc_netsoc_sdram_bankmachine1_cmd_buffer_sink_valid;
-	end
-	if (soc_netsoc_sdram_bankmachine1_cmd_buffer_pipe_ce) begin
-		soc_netsoc_sdram_bankmachine1_cmd_buffer_first_n <= (soc_netsoc_sdram_bankmachine1_cmd_buffer_sink_valid & soc_netsoc_sdram_bankmachine1_cmd_buffer_sink_first);
-		soc_netsoc_sdram_bankmachine1_cmd_buffer_last_n <= (soc_netsoc_sdram_bankmachine1_cmd_buffer_sink_valid & soc_netsoc_sdram_bankmachine1_cmd_buffer_sink_last);
-	end
-	if (soc_netsoc_sdram_bankmachine1_cmd_buffer_pipe_ce) begin
-		soc_netsoc_sdram_bankmachine1_cmd_buffer_source_payload_we <= soc_netsoc_sdram_bankmachine1_cmd_buffer_sink_payload_we;
-		soc_netsoc_sdram_bankmachine1_cmd_buffer_source_payload_addr <= soc_netsoc_sdram_bankmachine1_cmd_buffer_sink_payload_addr;
-	end
-	if (soc_netsoc_sdram_bankmachine1_twtpcon_valid) begin
-		soc_netsoc_sdram_bankmachine1_twtpcon_count <= 3'd4;
-		if (1'd0) begin
-			soc_netsoc_sdram_bankmachine1_twtpcon_ready <= 1'd1;
-		end else begin
-			soc_netsoc_sdram_bankmachine1_twtpcon_ready <= 1'd0;
-		end
-	end else begin
-		if ((~soc_netsoc_sdram_bankmachine1_twtpcon_ready)) begin
-			soc_netsoc_sdram_bankmachine1_twtpcon_count <= (soc_netsoc_sdram_bankmachine1_twtpcon_count - 1'd1);
-			if ((soc_netsoc_sdram_bankmachine1_twtpcon_count == 1'd1)) begin
-				soc_netsoc_sdram_bankmachine1_twtpcon_ready <= 1'd1;
-			end
-		end
-	end
-	if (soc_netsoc_sdram_bankmachine1_trccon_valid) begin
-		soc_netsoc_sdram_bankmachine1_trccon_count <= 2'd3;
-		if (1'd0) begin
-			soc_netsoc_sdram_bankmachine1_trccon_ready <= 1'd1;
-		end else begin
-			soc_netsoc_sdram_bankmachine1_trccon_ready <= 1'd0;
-		end
-	end else begin
-		if ((~soc_netsoc_sdram_bankmachine1_trccon_ready)) begin
-			soc_netsoc_sdram_bankmachine1_trccon_count <= (soc_netsoc_sdram_bankmachine1_trccon_count - 1'd1);
-			if ((soc_netsoc_sdram_bankmachine1_trccon_count == 1'd1)) begin
-				soc_netsoc_sdram_bankmachine1_trccon_ready <= 1'd1;
-			end
-		end
-	end
-	if (soc_netsoc_sdram_bankmachine1_trascon_valid) begin
-		soc_netsoc_sdram_bankmachine1_trascon_count <= 2'd2;
-		if (1'd0) begin
-			soc_netsoc_sdram_bankmachine1_trascon_ready <= 1'd1;
-		end else begin
-			soc_netsoc_sdram_bankmachine1_trascon_ready <= 1'd0;
-		end
-	end else begin
-		if ((~soc_netsoc_sdram_bankmachine1_trascon_ready)) begin
-			soc_netsoc_sdram_bankmachine1_trascon_count <= (soc_netsoc_sdram_bankmachine1_trascon_count - 1'd1);
-			if ((soc_netsoc_sdram_bankmachine1_trascon_count == 1'd1)) begin
-				soc_netsoc_sdram_bankmachine1_trascon_ready <= 1'd1;
-			end
-		end
-	end
-	vns_bankmachine1_state <= vns_bankmachine1_next_state;
-	if (soc_netsoc_sdram_bankmachine2_row_close) begin
-		soc_netsoc_sdram_bankmachine2_row_opened <= 1'd0;
-	end else begin
-		if (soc_netsoc_sdram_bankmachine2_row_open) begin
-			soc_netsoc_sdram_bankmachine2_row_opened <= 1'd1;
-			soc_netsoc_sdram_bankmachine2_row <= soc_netsoc_sdram_bankmachine2_cmd_buffer_source_payload_addr[20:7];
-		end
-	end
-	if (((soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_replace))) begin
-		soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_produce <= (soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_produce + 1'd1);
-	end
-	if (soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_do_read) begin
-		soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_consume <= (soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_consume + 1'd1);
-	end
-	if (((soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_replace))) begin
-		if ((~soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_do_read)) begin
-			soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_level <= (soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_level + 1'd1);
-		end
-	end else begin
-		if (soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_do_read) begin
-			soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_level <= (soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_level - 1'd1);
-		end
-	end
-	if (soc_netsoc_sdram_bankmachine2_cmd_buffer_pipe_ce) begin
-		soc_netsoc_sdram_bankmachine2_cmd_buffer_valid_n <= soc_netsoc_sdram_bankmachine2_cmd_buffer_sink_valid;
-	end
-	if (soc_netsoc_sdram_bankmachine2_cmd_buffer_pipe_ce) begin
-		soc_netsoc_sdram_bankmachine2_cmd_buffer_first_n <= (soc_netsoc_sdram_bankmachine2_cmd_buffer_sink_valid & soc_netsoc_sdram_bankmachine2_cmd_buffer_sink_first);
-		soc_netsoc_sdram_bankmachine2_cmd_buffer_last_n <= (soc_netsoc_sdram_bankmachine2_cmd_buffer_sink_valid & soc_netsoc_sdram_bankmachine2_cmd_buffer_sink_last);
-	end
-	if (soc_netsoc_sdram_bankmachine2_cmd_buffer_pipe_ce) begin
-		soc_netsoc_sdram_bankmachine2_cmd_buffer_source_payload_we <= soc_netsoc_sdram_bankmachine2_cmd_buffer_sink_payload_we;
-		soc_netsoc_sdram_bankmachine2_cmd_buffer_source_payload_addr <= soc_netsoc_sdram_bankmachine2_cmd_buffer_sink_payload_addr;
-	end
-	if (soc_netsoc_sdram_bankmachine2_twtpcon_valid) begin
-		soc_netsoc_sdram_bankmachine2_twtpcon_count <= 3'd4;
-		if (1'd0) begin
-			soc_netsoc_sdram_bankmachine2_twtpcon_ready <= 1'd1;
-		end else begin
-			soc_netsoc_sdram_bankmachine2_twtpcon_ready <= 1'd0;
-		end
-	end else begin
-		if ((~soc_netsoc_sdram_bankmachine2_twtpcon_ready)) begin
-			soc_netsoc_sdram_bankmachine2_twtpcon_count <= (soc_netsoc_sdram_bankmachine2_twtpcon_count - 1'd1);
-			if ((soc_netsoc_sdram_bankmachine2_twtpcon_count == 1'd1)) begin
-				soc_netsoc_sdram_bankmachine2_twtpcon_ready <= 1'd1;
-			end
-		end
-	end
-	if (soc_netsoc_sdram_bankmachine2_trccon_valid) begin
-		soc_netsoc_sdram_bankmachine2_trccon_count <= 2'd3;
-		if (1'd0) begin
-			soc_netsoc_sdram_bankmachine2_trccon_ready <= 1'd1;
-		end else begin
-			soc_netsoc_sdram_bankmachine2_trccon_ready <= 1'd0;
-		end
-	end else begin
-		if ((~soc_netsoc_sdram_bankmachine2_trccon_ready)) begin
-			soc_netsoc_sdram_bankmachine2_trccon_count <= (soc_netsoc_sdram_bankmachine2_trccon_count - 1'd1);
-			if ((soc_netsoc_sdram_bankmachine2_trccon_count == 1'd1)) begin
-				soc_netsoc_sdram_bankmachine2_trccon_ready <= 1'd1;
-			end
-		end
-	end
-	if (soc_netsoc_sdram_bankmachine2_trascon_valid) begin
-		soc_netsoc_sdram_bankmachine2_trascon_count <= 2'd2;
-		if (1'd0) begin
-			soc_netsoc_sdram_bankmachine2_trascon_ready <= 1'd1;
-		end else begin
-			soc_netsoc_sdram_bankmachine2_trascon_ready <= 1'd0;
-		end
-	end else begin
-		if ((~soc_netsoc_sdram_bankmachine2_trascon_ready)) begin
-			soc_netsoc_sdram_bankmachine2_trascon_count <= (soc_netsoc_sdram_bankmachine2_trascon_count - 1'd1);
-			if ((soc_netsoc_sdram_bankmachine2_trascon_count == 1'd1)) begin
-				soc_netsoc_sdram_bankmachine2_trascon_ready <= 1'd1;
-			end
-		end
-	end
-	vns_bankmachine2_state <= vns_bankmachine2_next_state;
-	if (soc_netsoc_sdram_bankmachine3_row_close) begin
-		soc_netsoc_sdram_bankmachine3_row_opened <= 1'd0;
-	end else begin
-		if (soc_netsoc_sdram_bankmachine3_row_open) begin
-			soc_netsoc_sdram_bankmachine3_row_opened <= 1'd1;
-			soc_netsoc_sdram_bankmachine3_row <= soc_netsoc_sdram_bankmachine3_cmd_buffer_source_payload_addr[20:7];
-		end
-	end
-	if (((soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_replace))) begin
-		soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_produce <= (soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_produce + 1'd1);
-	end
-	if (soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_do_read) begin
-		soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_consume <= (soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_consume + 1'd1);
-	end
-	if (((soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_replace))) begin
-		if ((~soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_do_read)) begin
-			soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_level <= (soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_level + 1'd1);
-		end
-	end else begin
-		if (soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_do_read) begin
-			soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_level <= (soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_level - 1'd1);
-		end
-	end
-	if (soc_netsoc_sdram_bankmachine3_cmd_buffer_pipe_ce) begin
-		soc_netsoc_sdram_bankmachine3_cmd_buffer_valid_n <= soc_netsoc_sdram_bankmachine3_cmd_buffer_sink_valid;
-	end
-	if (soc_netsoc_sdram_bankmachine3_cmd_buffer_pipe_ce) begin
-		soc_netsoc_sdram_bankmachine3_cmd_buffer_first_n <= (soc_netsoc_sdram_bankmachine3_cmd_buffer_sink_valid & soc_netsoc_sdram_bankmachine3_cmd_buffer_sink_first);
-		soc_netsoc_sdram_bankmachine3_cmd_buffer_last_n <= (soc_netsoc_sdram_bankmachine3_cmd_buffer_sink_valid & soc_netsoc_sdram_bankmachine3_cmd_buffer_sink_last);
-	end
-	if (soc_netsoc_sdram_bankmachine3_cmd_buffer_pipe_ce) begin
-		soc_netsoc_sdram_bankmachine3_cmd_buffer_source_payload_we <= soc_netsoc_sdram_bankmachine3_cmd_buffer_sink_payload_we;
-		soc_netsoc_sdram_bankmachine3_cmd_buffer_source_payload_addr <= soc_netsoc_sdram_bankmachine3_cmd_buffer_sink_payload_addr;
-	end
-	if (soc_netsoc_sdram_bankmachine3_twtpcon_valid) begin
-		soc_netsoc_sdram_bankmachine3_twtpcon_count <= 3'd4;
-		if (1'd0) begin
-			soc_netsoc_sdram_bankmachine3_twtpcon_ready <= 1'd1;
-		end else begin
-			soc_netsoc_sdram_bankmachine3_twtpcon_ready <= 1'd0;
-		end
-	end else begin
-		if ((~soc_netsoc_sdram_bankmachine3_twtpcon_ready)) begin
-			soc_netsoc_sdram_bankmachine3_twtpcon_count <= (soc_netsoc_sdram_bankmachine3_twtpcon_count - 1'd1);
-			if ((soc_netsoc_sdram_bankmachine3_twtpcon_count == 1'd1)) begin
-				soc_netsoc_sdram_bankmachine3_twtpcon_ready <= 1'd1;
-			end
-		end
-	end
-	if (soc_netsoc_sdram_bankmachine3_trccon_valid) begin
-		soc_netsoc_sdram_bankmachine3_trccon_count <= 2'd3;
-		if (1'd0) begin
-			soc_netsoc_sdram_bankmachine3_trccon_ready <= 1'd1;
-		end else begin
-			soc_netsoc_sdram_bankmachine3_trccon_ready <= 1'd0;
-		end
-	end else begin
-		if ((~soc_netsoc_sdram_bankmachine3_trccon_ready)) begin
-			soc_netsoc_sdram_bankmachine3_trccon_count <= (soc_netsoc_sdram_bankmachine3_trccon_count - 1'd1);
-			if ((soc_netsoc_sdram_bankmachine3_trccon_count == 1'd1)) begin
-				soc_netsoc_sdram_bankmachine3_trccon_ready <= 1'd1;
-			end
-		end
-	end
-	if (soc_netsoc_sdram_bankmachine3_trascon_valid) begin
-		soc_netsoc_sdram_bankmachine3_trascon_count <= 2'd2;
-		if (1'd0) begin
-			soc_netsoc_sdram_bankmachine3_trascon_ready <= 1'd1;
-		end else begin
-			soc_netsoc_sdram_bankmachine3_trascon_ready <= 1'd0;
-		end
-	end else begin
-		if ((~soc_netsoc_sdram_bankmachine3_trascon_ready)) begin
-			soc_netsoc_sdram_bankmachine3_trascon_count <= (soc_netsoc_sdram_bankmachine3_trascon_count - 1'd1);
-			if ((soc_netsoc_sdram_bankmachine3_trascon_count == 1'd1)) begin
-				soc_netsoc_sdram_bankmachine3_trascon_ready <= 1'd1;
-			end
-		end
-	end
-	vns_bankmachine3_state <= vns_bankmachine3_next_state;
-	if (soc_netsoc_sdram_bankmachine4_row_close) begin
-		soc_netsoc_sdram_bankmachine4_row_opened <= 1'd0;
-	end else begin
-		if (soc_netsoc_sdram_bankmachine4_row_open) begin
-			soc_netsoc_sdram_bankmachine4_row_opened <= 1'd1;
-			soc_netsoc_sdram_bankmachine4_row <= soc_netsoc_sdram_bankmachine4_cmd_buffer_source_payload_addr[20:7];
-		end
-	end
-	if (((soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_replace))) begin
-		soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_produce <= (soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_produce + 1'd1);
-	end
-	if (soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_do_read) begin
-		soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_consume <= (soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_consume + 1'd1);
-	end
-	if (((soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_replace))) begin
-		if ((~soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_do_read)) begin
-			soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_level <= (soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_level + 1'd1);
-		end
-	end else begin
-		if (soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_do_read) begin
-			soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_level <= (soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_level - 1'd1);
-		end
-	end
-	if (soc_netsoc_sdram_bankmachine4_cmd_buffer_pipe_ce) begin
-		soc_netsoc_sdram_bankmachine4_cmd_buffer_valid_n <= soc_netsoc_sdram_bankmachine4_cmd_buffer_sink_valid;
-	end
-	if (soc_netsoc_sdram_bankmachine4_cmd_buffer_pipe_ce) begin
-		soc_netsoc_sdram_bankmachine4_cmd_buffer_first_n <= (soc_netsoc_sdram_bankmachine4_cmd_buffer_sink_valid & soc_netsoc_sdram_bankmachine4_cmd_buffer_sink_first);
-		soc_netsoc_sdram_bankmachine4_cmd_buffer_last_n <= (soc_netsoc_sdram_bankmachine4_cmd_buffer_sink_valid & soc_netsoc_sdram_bankmachine4_cmd_buffer_sink_last);
-	end
-	if (soc_netsoc_sdram_bankmachine4_cmd_buffer_pipe_ce) begin
-		soc_netsoc_sdram_bankmachine4_cmd_buffer_source_payload_we <= soc_netsoc_sdram_bankmachine4_cmd_buffer_sink_payload_we;
-		soc_netsoc_sdram_bankmachine4_cmd_buffer_source_payload_addr <= soc_netsoc_sdram_bankmachine4_cmd_buffer_sink_payload_addr;
-	end
-	if (soc_netsoc_sdram_bankmachine4_twtpcon_valid) begin
-		soc_netsoc_sdram_bankmachine4_twtpcon_count <= 3'd4;
-		if (1'd0) begin
-			soc_netsoc_sdram_bankmachine4_twtpcon_ready <= 1'd1;
-		end else begin
-			soc_netsoc_sdram_bankmachine4_twtpcon_ready <= 1'd0;
-		end
-	end else begin
-		if ((~soc_netsoc_sdram_bankmachine4_twtpcon_ready)) begin
-			soc_netsoc_sdram_bankmachine4_twtpcon_count <= (soc_netsoc_sdram_bankmachine4_twtpcon_count - 1'd1);
-			if ((soc_netsoc_sdram_bankmachine4_twtpcon_count == 1'd1)) begin
-				soc_netsoc_sdram_bankmachine4_twtpcon_ready <= 1'd1;
-			end
-		end
-	end
-	if (soc_netsoc_sdram_bankmachine4_trccon_valid) begin
-		soc_netsoc_sdram_bankmachine4_trccon_count <= 2'd3;
-		if (1'd0) begin
-			soc_netsoc_sdram_bankmachine4_trccon_ready <= 1'd1;
-		end else begin
-			soc_netsoc_sdram_bankmachine4_trccon_ready <= 1'd0;
-		end
-	end else begin
-		if ((~soc_netsoc_sdram_bankmachine4_trccon_ready)) begin
-			soc_netsoc_sdram_bankmachine4_trccon_count <= (soc_netsoc_sdram_bankmachine4_trccon_count - 1'd1);
-			if ((soc_netsoc_sdram_bankmachine4_trccon_count == 1'd1)) begin
-				soc_netsoc_sdram_bankmachine4_trccon_ready <= 1'd1;
-			end
-		end
-	end
-	if (soc_netsoc_sdram_bankmachine4_trascon_valid) begin
-		soc_netsoc_sdram_bankmachine4_trascon_count <= 2'd2;
-		if (1'd0) begin
-			soc_netsoc_sdram_bankmachine4_trascon_ready <= 1'd1;
-		end else begin
-			soc_netsoc_sdram_bankmachine4_trascon_ready <= 1'd0;
-		end
-	end else begin
-		if ((~soc_netsoc_sdram_bankmachine4_trascon_ready)) begin
-			soc_netsoc_sdram_bankmachine4_trascon_count <= (soc_netsoc_sdram_bankmachine4_trascon_count - 1'd1);
-			if ((soc_netsoc_sdram_bankmachine4_trascon_count == 1'd1)) begin
-				soc_netsoc_sdram_bankmachine4_trascon_ready <= 1'd1;
-			end
-		end
-	end
-	vns_bankmachine4_state <= vns_bankmachine4_next_state;
-	if (soc_netsoc_sdram_bankmachine5_row_close) begin
-		soc_netsoc_sdram_bankmachine5_row_opened <= 1'd0;
-	end else begin
-		if (soc_netsoc_sdram_bankmachine5_row_open) begin
-			soc_netsoc_sdram_bankmachine5_row_opened <= 1'd1;
-			soc_netsoc_sdram_bankmachine5_row <= soc_netsoc_sdram_bankmachine5_cmd_buffer_source_payload_addr[20:7];
-		end
-	end
-	if (((soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_replace))) begin
-		soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_produce <= (soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_produce + 1'd1);
-	end
-	if (soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_do_read) begin
-		soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_consume <= (soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_consume + 1'd1);
-	end
-	if (((soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_replace))) begin
-		if ((~soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_do_read)) begin
-			soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_level <= (soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_level + 1'd1);
-		end
-	end else begin
-		if (soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_do_read) begin
-			soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_level <= (soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_level - 1'd1);
-		end
-	end
-	if (soc_netsoc_sdram_bankmachine5_cmd_buffer_pipe_ce) begin
-		soc_netsoc_sdram_bankmachine5_cmd_buffer_valid_n <= soc_netsoc_sdram_bankmachine5_cmd_buffer_sink_valid;
-	end
-	if (soc_netsoc_sdram_bankmachine5_cmd_buffer_pipe_ce) begin
-		soc_netsoc_sdram_bankmachine5_cmd_buffer_first_n <= (soc_netsoc_sdram_bankmachine5_cmd_buffer_sink_valid & soc_netsoc_sdram_bankmachine5_cmd_buffer_sink_first);
-		soc_netsoc_sdram_bankmachine5_cmd_buffer_last_n <= (soc_netsoc_sdram_bankmachine5_cmd_buffer_sink_valid & soc_netsoc_sdram_bankmachine5_cmd_buffer_sink_last);
-	end
-	if (soc_netsoc_sdram_bankmachine5_cmd_buffer_pipe_ce) begin
-		soc_netsoc_sdram_bankmachine5_cmd_buffer_source_payload_we <= soc_netsoc_sdram_bankmachine5_cmd_buffer_sink_payload_we;
-		soc_netsoc_sdram_bankmachine5_cmd_buffer_source_payload_addr <= soc_netsoc_sdram_bankmachine5_cmd_buffer_sink_payload_addr;
-	end
-	if (soc_netsoc_sdram_bankmachine5_twtpcon_valid) begin
-		soc_netsoc_sdram_bankmachine5_twtpcon_count <= 3'd4;
-		if (1'd0) begin
-			soc_netsoc_sdram_bankmachine5_twtpcon_ready <= 1'd1;
-		end else begin
-			soc_netsoc_sdram_bankmachine5_twtpcon_ready <= 1'd0;
-		end
-	end else begin
-		if ((~soc_netsoc_sdram_bankmachine5_twtpcon_ready)) begin
-			soc_netsoc_sdram_bankmachine5_twtpcon_count <= (soc_netsoc_sdram_bankmachine5_twtpcon_count - 1'd1);
-			if ((soc_netsoc_sdram_bankmachine5_twtpcon_count == 1'd1)) begin
-				soc_netsoc_sdram_bankmachine5_twtpcon_ready <= 1'd1;
-			end
-		end
-	end
-	if (soc_netsoc_sdram_bankmachine5_trccon_valid) begin
-		soc_netsoc_sdram_bankmachine5_trccon_count <= 2'd3;
-		if (1'd0) begin
-			soc_netsoc_sdram_bankmachine5_trccon_ready <= 1'd1;
-		end else begin
-			soc_netsoc_sdram_bankmachine5_trccon_ready <= 1'd0;
-		end
-	end else begin
-		if ((~soc_netsoc_sdram_bankmachine5_trccon_ready)) begin
-			soc_netsoc_sdram_bankmachine5_trccon_count <= (soc_netsoc_sdram_bankmachine5_trccon_count - 1'd1);
-			if ((soc_netsoc_sdram_bankmachine5_trccon_count == 1'd1)) begin
-				soc_netsoc_sdram_bankmachine5_trccon_ready <= 1'd1;
-			end
-		end
-	end
-	if (soc_netsoc_sdram_bankmachine5_trascon_valid) begin
-		soc_netsoc_sdram_bankmachine5_trascon_count <= 2'd2;
-		if (1'd0) begin
-			soc_netsoc_sdram_bankmachine5_trascon_ready <= 1'd1;
-		end else begin
-			soc_netsoc_sdram_bankmachine5_trascon_ready <= 1'd0;
-		end
-	end else begin
-		if ((~soc_netsoc_sdram_bankmachine5_trascon_ready)) begin
-			soc_netsoc_sdram_bankmachine5_trascon_count <= (soc_netsoc_sdram_bankmachine5_trascon_count - 1'd1);
-			if ((soc_netsoc_sdram_bankmachine5_trascon_count == 1'd1)) begin
-				soc_netsoc_sdram_bankmachine5_trascon_ready <= 1'd1;
-			end
-		end
-	end
-	vns_bankmachine5_state <= vns_bankmachine5_next_state;
-	if (soc_netsoc_sdram_bankmachine6_row_close) begin
-		soc_netsoc_sdram_bankmachine6_row_opened <= 1'd0;
-	end else begin
-		if (soc_netsoc_sdram_bankmachine6_row_open) begin
-			soc_netsoc_sdram_bankmachine6_row_opened <= 1'd1;
-			soc_netsoc_sdram_bankmachine6_row <= soc_netsoc_sdram_bankmachine6_cmd_buffer_source_payload_addr[20:7];
-		end
-	end
-	if (((soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_replace))) begin
-		soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_produce <= (soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_produce + 1'd1);
-	end
-	if (soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_do_read) begin
-		soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_consume <= (soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_consume + 1'd1);
-	end
-	if (((soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_replace))) begin
-		if ((~soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_do_read)) begin
-			soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_level <= (soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_level + 1'd1);
-		end
-	end else begin
-		if (soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_do_read) begin
-			soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_level <= (soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_level - 1'd1);
-		end
-	end
-	if (soc_netsoc_sdram_bankmachine6_cmd_buffer_pipe_ce) begin
-		soc_netsoc_sdram_bankmachine6_cmd_buffer_valid_n <= soc_netsoc_sdram_bankmachine6_cmd_buffer_sink_valid;
-	end
-	if (soc_netsoc_sdram_bankmachine6_cmd_buffer_pipe_ce) begin
-		soc_netsoc_sdram_bankmachine6_cmd_buffer_first_n <= (soc_netsoc_sdram_bankmachine6_cmd_buffer_sink_valid & soc_netsoc_sdram_bankmachine6_cmd_buffer_sink_first);
-		soc_netsoc_sdram_bankmachine6_cmd_buffer_last_n <= (soc_netsoc_sdram_bankmachine6_cmd_buffer_sink_valid & soc_netsoc_sdram_bankmachine6_cmd_buffer_sink_last);
-	end
-	if (soc_netsoc_sdram_bankmachine6_cmd_buffer_pipe_ce) begin
-		soc_netsoc_sdram_bankmachine6_cmd_buffer_source_payload_we <= soc_netsoc_sdram_bankmachine6_cmd_buffer_sink_payload_we;
-		soc_netsoc_sdram_bankmachine6_cmd_buffer_source_payload_addr <= soc_netsoc_sdram_bankmachine6_cmd_buffer_sink_payload_addr;
-	end
-	if (soc_netsoc_sdram_bankmachine6_twtpcon_valid) begin
-		soc_netsoc_sdram_bankmachine6_twtpcon_count <= 3'd4;
-		if (1'd0) begin
-			soc_netsoc_sdram_bankmachine6_twtpcon_ready <= 1'd1;
-		end else begin
-			soc_netsoc_sdram_bankmachine6_twtpcon_ready <= 1'd0;
-		end
-	end else begin
-		if ((~soc_netsoc_sdram_bankmachine6_twtpcon_ready)) begin
-			soc_netsoc_sdram_bankmachine6_twtpcon_count <= (soc_netsoc_sdram_bankmachine6_twtpcon_count - 1'd1);
-			if ((soc_netsoc_sdram_bankmachine6_twtpcon_count == 1'd1)) begin
-				soc_netsoc_sdram_bankmachine6_twtpcon_ready <= 1'd1;
-			end
-		end
-	end
-	if (soc_netsoc_sdram_bankmachine6_trccon_valid) begin
-		soc_netsoc_sdram_bankmachine6_trccon_count <= 2'd3;
-		if (1'd0) begin
-			soc_netsoc_sdram_bankmachine6_trccon_ready <= 1'd1;
-		end else begin
-			soc_netsoc_sdram_bankmachine6_trccon_ready <= 1'd0;
-		end
-	end else begin
-		if ((~soc_netsoc_sdram_bankmachine6_trccon_ready)) begin
-			soc_netsoc_sdram_bankmachine6_trccon_count <= (soc_netsoc_sdram_bankmachine6_trccon_count - 1'd1);
-			if ((soc_netsoc_sdram_bankmachine6_trccon_count == 1'd1)) begin
-				soc_netsoc_sdram_bankmachine6_trccon_ready <= 1'd1;
-			end
-		end
-	end
-	if (soc_netsoc_sdram_bankmachine6_trascon_valid) begin
-		soc_netsoc_sdram_bankmachine6_trascon_count <= 2'd2;
-		if (1'd0) begin
-			soc_netsoc_sdram_bankmachine6_trascon_ready <= 1'd1;
-		end else begin
-			soc_netsoc_sdram_bankmachine6_trascon_ready <= 1'd0;
-		end
-	end else begin
-		if ((~soc_netsoc_sdram_bankmachine6_trascon_ready)) begin
-			soc_netsoc_sdram_bankmachine6_trascon_count <= (soc_netsoc_sdram_bankmachine6_trascon_count - 1'd1);
-			if ((soc_netsoc_sdram_bankmachine6_trascon_count == 1'd1)) begin
-				soc_netsoc_sdram_bankmachine6_trascon_ready <= 1'd1;
-			end
-		end
-	end
-	vns_bankmachine6_state <= vns_bankmachine6_next_state;
-	if (soc_netsoc_sdram_bankmachine7_row_close) begin
-		soc_netsoc_sdram_bankmachine7_row_opened <= 1'd0;
-	end else begin
-		if (soc_netsoc_sdram_bankmachine7_row_open) begin
-			soc_netsoc_sdram_bankmachine7_row_opened <= 1'd1;
-			soc_netsoc_sdram_bankmachine7_row <= soc_netsoc_sdram_bankmachine7_cmd_buffer_source_payload_addr[20:7];
-		end
-	end
-	if (((soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_replace))) begin
-		soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_produce <= (soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_produce + 1'd1);
-	end
-	if (soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_do_read) begin
-		soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_consume <= (soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_consume + 1'd1);
-	end
-	if (((soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_replace))) begin
-		if ((~soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_do_read)) begin
-			soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_level <= (soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_level + 1'd1);
-		end
-	end else begin
-		if (soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_do_read) begin
-			soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_level <= (soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_level - 1'd1);
-		end
-	end
-	if (soc_netsoc_sdram_bankmachine7_cmd_buffer_pipe_ce) begin
-		soc_netsoc_sdram_bankmachine7_cmd_buffer_valid_n <= soc_netsoc_sdram_bankmachine7_cmd_buffer_sink_valid;
-	end
-	if (soc_netsoc_sdram_bankmachine7_cmd_buffer_pipe_ce) begin
-		soc_netsoc_sdram_bankmachine7_cmd_buffer_first_n <= (soc_netsoc_sdram_bankmachine7_cmd_buffer_sink_valid & soc_netsoc_sdram_bankmachine7_cmd_buffer_sink_first);
-		soc_netsoc_sdram_bankmachine7_cmd_buffer_last_n <= (soc_netsoc_sdram_bankmachine7_cmd_buffer_sink_valid & soc_netsoc_sdram_bankmachine7_cmd_buffer_sink_last);
-	end
-	if (soc_netsoc_sdram_bankmachine7_cmd_buffer_pipe_ce) begin
-		soc_netsoc_sdram_bankmachine7_cmd_buffer_source_payload_we <= soc_netsoc_sdram_bankmachine7_cmd_buffer_sink_payload_we;
-		soc_netsoc_sdram_bankmachine7_cmd_buffer_source_payload_addr <= soc_netsoc_sdram_bankmachine7_cmd_buffer_sink_payload_addr;
-	end
-	if (soc_netsoc_sdram_bankmachine7_twtpcon_valid) begin
-		soc_netsoc_sdram_bankmachine7_twtpcon_count <= 3'd4;
-		if (1'd0) begin
-			soc_netsoc_sdram_bankmachine7_twtpcon_ready <= 1'd1;
-		end else begin
-			soc_netsoc_sdram_bankmachine7_twtpcon_ready <= 1'd0;
-		end
-	end else begin
-		if ((~soc_netsoc_sdram_bankmachine7_twtpcon_ready)) begin
-			soc_netsoc_sdram_bankmachine7_twtpcon_count <= (soc_netsoc_sdram_bankmachine7_twtpcon_count - 1'd1);
-			if ((soc_netsoc_sdram_bankmachine7_twtpcon_count == 1'd1)) begin
-				soc_netsoc_sdram_bankmachine7_twtpcon_ready <= 1'd1;
-			end
-		end
-	end
-	if (soc_netsoc_sdram_bankmachine7_trccon_valid) begin
-		soc_netsoc_sdram_bankmachine7_trccon_count <= 2'd3;
-		if (1'd0) begin
-			soc_netsoc_sdram_bankmachine7_trccon_ready <= 1'd1;
-		end else begin
-			soc_netsoc_sdram_bankmachine7_trccon_ready <= 1'd0;
-		end
-	end else begin
-		if ((~soc_netsoc_sdram_bankmachine7_trccon_ready)) begin
-			soc_netsoc_sdram_bankmachine7_trccon_count <= (soc_netsoc_sdram_bankmachine7_trccon_count - 1'd1);
-			if ((soc_netsoc_sdram_bankmachine7_trccon_count == 1'd1)) begin
-				soc_netsoc_sdram_bankmachine7_trccon_ready <= 1'd1;
-			end
-		end
-	end
-	if (soc_netsoc_sdram_bankmachine7_trascon_valid) begin
-		soc_netsoc_sdram_bankmachine7_trascon_count <= 2'd2;
-		if (1'd0) begin
-			soc_netsoc_sdram_bankmachine7_trascon_ready <= 1'd1;
-		end else begin
-			soc_netsoc_sdram_bankmachine7_trascon_ready <= 1'd0;
-		end
-	end else begin
-		if ((~soc_netsoc_sdram_bankmachine7_trascon_ready)) begin
-			soc_netsoc_sdram_bankmachine7_trascon_count <= (soc_netsoc_sdram_bankmachine7_trascon_count - 1'd1);
-			if ((soc_netsoc_sdram_bankmachine7_trascon_count == 1'd1)) begin
-				soc_netsoc_sdram_bankmachine7_trascon_ready <= 1'd1;
-			end
-		end
-	end
-	vns_bankmachine7_state <= vns_bankmachine7_next_state;
-	if ((~soc_netsoc_sdram_en0)) begin
-		soc_netsoc_sdram_time0 <= 5'd31;
-	end else begin
-		if ((~soc_netsoc_sdram_max_time0)) begin
-			soc_netsoc_sdram_time0 <= (soc_netsoc_sdram_time0 - 1'd1);
-		end
-	end
-	if ((~soc_netsoc_sdram_en1)) begin
-		soc_netsoc_sdram_time1 <= 4'd15;
-	end else begin
-		if ((~soc_netsoc_sdram_max_time1)) begin
-			soc_netsoc_sdram_time1 <= (soc_netsoc_sdram_time1 - 1'd1);
-		end
-	end
-	if (soc_netsoc_sdram_choose_cmd_ce) begin
-		case (soc_netsoc_sdram_choose_cmd_grant)
-			1'd0: begin
-				if (soc_netsoc_sdram_choose_cmd_request[1]) begin
-					soc_netsoc_sdram_choose_cmd_grant <= 1'd1;
-				end else begin
-					if (soc_netsoc_sdram_choose_cmd_request[2]) begin
-						soc_netsoc_sdram_choose_cmd_grant <= 2'd2;
-					end else begin
-						if (soc_netsoc_sdram_choose_cmd_request[3]) begin
-							soc_netsoc_sdram_choose_cmd_grant <= 2'd3;
-						end else begin
-							if (soc_netsoc_sdram_choose_cmd_request[4]) begin
-								soc_netsoc_sdram_choose_cmd_grant <= 3'd4;
-							end else begin
-								if (soc_netsoc_sdram_choose_cmd_request[5]) begin
-									soc_netsoc_sdram_choose_cmd_grant <= 3'd5;
-								end else begin
-									if (soc_netsoc_sdram_choose_cmd_request[6]) begin
-										soc_netsoc_sdram_choose_cmd_grant <= 3'd6;
-									end else begin
-										if (soc_netsoc_sdram_choose_cmd_request[7]) begin
-											soc_netsoc_sdram_choose_cmd_grant <= 3'd7;
-										end
-									end
-								end
-							end
-						end
-					end
-				end
-			end
-			1'd1: begin
-				if (soc_netsoc_sdram_choose_cmd_request[2]) begin
-					soc_netsoc_sdram_choose_cmd_grant <= 2'd2;
-				end else begin
-					if (soc_netsoc_sdram_choose_cmd_request[3]) begin
-						soc_netsoc_sdram_choose_cmd_grant <= 2'd3;
-					end else begin
-						if (soc_netsoc_sdram_choose_cmd_request[4]) begin
-							soc_netsoc_sdram_choose_cmd_grant <= 3'd4;
-						end else begin
-							if (soc_netsoc_sdram_choose_cmd_request[5]) begin
-								soc_netsoc_sdram_choose_cmd_grant <= 3'd5;
-							end else begin
-								if (soc_netsoc_sdram_choose_cmd_request[6]) begin
-									soc_netsoc_sdram_choose_cmd_grant <= 3'd6;
-								end else begin
-									if (soc_netsoc_sdram_choose_cmd_request[7]) begin
-										soc_netsoc_sdram_choose_cmd_grant <= 3'd7;
-									end else begin
-										if (soc_netsoc_sdram_choose_cmd_request[0]) begin
-											soc_netsoc_sdram_choose_cmd_grant <= 1'd0;
-										end
-									end
-								end
-							end
-						end
-					end
-				end
-			end
-			2'd2: begin
-				if (soc_netsoc_sdram_choose_cmd_request[3]) begin
-					soc_netsoc_sdram_choose_cmd_grant <= 2'd3;
-				end else begin
-					if (soc_netsoc_sdram_choose_cmd_request[4]) begin
-						soc_netsoc_sdram_choose_cmd_grant <= 3'd4;
-					end else begin
-						if (soc_netsoc_sdram_choose_cmd_request[5]) begin
-							soc_netsoc_sdram_choose_cmd_grant <= 3'd5;
-						end else begin
-							if (soc_netsoc_sdram_choose_cmd_request[6]) begin
-								soc_netsoc_sdram_choose_cmd_grant <= 3'd6;
-							end else begin
-								if (soc_netsoc_sdram_choose_cmd_request[7]) begin
-									soc_netsoc_sdram_choose_cmd_grant <= 3'd7;
-								end else begin
-									if (soc_netsoc_sdram_choose_cmd_request[0]) begin
-										soc_netsoc_sdram_choose_cmd_grant <= 1'd0;
-									end else begin
-										if (soc_netsoc_sdram_choose_cmd_request[1]) begin
-											soc_netsoc_sdram_choose_cmd_grant <= 1'd1;
-										end
-									end
-								end
-							end
-						end
-					end
-				end
-			end
-			2'd3: begin
-				if (soc_netsoc_sdram_choose_cmd_request[4]) begin
-					soc_netsoc_sdram_choose_cmd_grant <= 3'd4;
-				end else begin
-					if (soc_netsoc_sdram_choose_cmd_request[5]) begin
-						soc_netsoc_sdram_choose_cmd_grant <= 3'd5;
-					end else begin
-						if (soc_netsoc_sdram_choose_cmd_request[6]) begin
-							soc_netsoc_sdram_choose_cmd_grant <= 3'd6;
-						end else begin
-							if (soc_netsoc_sdram_choose_cmd_request[7]) begin
-								soc_netsoc_sdram_choose_cmd_grant <= 3'd7;
-							end else begin
-								if (soc_netsoc_sdram_choose_cmd_request[0]) begin
-									soc_netsoc_sdram_choose_cmd_grant <= 1'd0;
-								end else begin
-									if (soc_netsoc_sdram_choose_cmd_request[1]) begin
-										soc_netsoc_sdram_choose_cmd_grant <= 1'd1;
-									end else begin
-										if (soc_netsoc_sdram_choose_cmd_request[2]) begin
-											soc_netsoc_sdram_choose_cmd_grant <= 2'd2;
-										end
-									end
-								end
-							end
-						end
-					end
-				end
-			end
-			3'd4: begin
-				if (soc_netsoc_sdram_choose_cmd_request[5]) begin
-					soc_netsoc_sdram_choose_cmd_grant <= 3'd5;
-				end else begin
-					if (soc_netsoc_sdram_choose_cmd_request[6]) begin
-						soc_netsoc_sdram_choose_cmd_grant <= 3'd6;
-					end else begin
-						if (soc_netsoc_sdram_choose_cmd_request[7]) begin
-							soc_netsoc_sdram_choose_cmd_grant <= 3'd7;
-						end else begin
-							if (soc_netsoc_sdram_choose_cmd_request[0]) begin
-								soc_netsoc_sdram_choose_cmd_grant <= 1'd0;
-							end else begin
-								if (soc_netsoc_sdram_choose_cmd_request[1]) begin
-									soc_netsoc_sdram_choose_cmd_grant <= 1'd1;
-								end else begin
-									if (soc_netsoc_sdram_choose_cmd_request[2]) begin
-										soc_netsoc_sdram_choose_cmd_grant <= 2'd2;
-									end else begin
-										if (soc_netsoc_sdram_choose_cmd_request[3]) begin
-											soc_netsoc_sdram_choose_cmd_grant <= 2'd3;
-										end
-									end
-								end
-							end
-						end
-					end
-				end
-			end
-			3'd5: begin
-				if (soc_netsoc_sdram_choose_cmd_request[6]) begin
-					soc_netsoc_sdram_choose_cmd_grant <= 3'd6;
-				end else begin
-					if (soc_netsoc_sdram_choose_cmd_request[7]) begin
-						soc_netsoc_sdram_choose_cmd_grant <= 3'd7;
-					end else begin
-						if (soc_netsoc_sdram_choose_cmd_request[0]) begin
-							soc_netsoc_sdram_choose_cmd_grant <= 1'd0;
-						end else begin
-							if (soc_netsoc_sdram_choose_cmd_request[1]) begin
-								soc_netsoc_sdram_choose_cmd_grant <= 1'd1;
-							end else begin
-								if (soc_netsoc_sdram_choose_cmd_request[2]) begin
-									soc_netsoc_sdram_choose_cmd_grant <= 2'd2;
-								end else begin
-									if (soc_netsoc_sdram_choose_cmd_request[3]) begin
-										soc_netsoc_sdram_choose_cmd_grant <= 2'd3;
-									end else begin
-										if (soc_netsoc_sdram_choose_cmd_request[4]) begin
-											soc_netsoc_sdram_choose_cmd_grant <= 3'd4;
-										end
-									end
-								end
-							end
-						end
-					end
-				end
-			end
-			3'd6: begin
-				if (soc_netsoc_sdram_choose_cmd_request[7]) begin
-					soc_netsoc_sdram_choose_cmd_grant <= 3'd7;
-				end else begin
-					if (soc_netsoc_sdram_choose_cmd_request[0]) begin
-						soc_netsoc_sdram_choose_cmd_grant <= 1'd0;
-					end else begin
-						if (soc_netsoc_sdram_choose_cmd_request[1]) begin
-							soc_netsoc_sdram_choose_cmd_grant <= 1'd1;
-						end else begin
-							if (soc_netsoc_sdram_choose_cmd_request[2]) begin
-								soc_netsoc_sdram_choose_cmd_grant <= 2'd2;
-							end else begin
-								if (soc_netsoc_sdram_choose_cmd_request[3]) begin
-									soc_netsoc_sdram_choose_cmd_grant <= 2'd3;
-								end else begin
-									if (soc_netsoc_sdram_choose_cmd_request[4]) begin
-										soc_netsoc_sdram_choose_cmd_grant <= 3'd4;
-									end else begin
-										if (soc_netsoc_sdram_choose_cmd_request[5]) begin
-											soc_netsoc_sdram_choose_cmd_grant <= 3'd5;
-										end
-									end
-								end
-							end
-						end
-					end
-				end
-			end
-			3'd7: begin
-				if (soc_netsoc_sdram_choose_cmd_request[0]) begin
-					soc_netsoc_sdram_choose_cmd_grant <= 1'd0;
-				end else begin
-					if (soc_netsoc_sdram_choose_cmd_request[1]) begin
-						soc_netsoc_sdram_choose_cmd_grant <= 1'd1;
-					end else begin
-						if (soc_netsoc_sdram_choose_cmd_request[2]) begin
-							soc_netsoc_sdram_choose_cmd_grant <= 2'd2;
-						end else begin
-							if (soc_netsoc_sdram_choose_cmd_request[3]) begin
-								soc_netsoc_sdram_choose_cmd_grant <= 2'd3;
-							end else begin
-								if (soc_netsoc_sdram_choose_cmd_request[4]) begin
-									soc_netsoc_sdram_choose_cmd_grant <= 3'd4;
-								end else begin
-									if (soc_netsoc_sdram_choose_cmd_request[5]) begin
-										soc_netsoc_sdram_choose_cmd_grant <= 3'd5;
-									end else begin
-										if (soc_netsoc_sdram_choose_cmd_request[6]) begin
-											soc_netsoc_sdram_choose_cmd_grant <= 3'd6;
-										end
-									end
-								end
-							end
-						end
-					end
-				end
-			end
-		endcase
-	end
-	if (soc_netsoc_sdram_choose_req_ce) begin
-		case (soc_netsoc_sdram_choose_req_grant)
-			1'd0: begin
-				if (soc_netsoc_sdram_choose_req_request[1]) begin
-					soc_netsoc_sdram_choose_req_grant <= 1'd1;
-				end else begin
-					if (soc_netsoc_sdram_choose_req_request[2]) begin
-						soc_netsoc_sdram_choose_req_grant <= 2'd2;
-					end else begin
-						if (soc_netsoc_sdram_choose_req_request[3]) begin
-							soc_netsoc_sdram_choose_req_grant <= 2'd3;
-						end else begin
-							if (soc_netsoc_sdram_choose_req_request[4]) begin
-								soc_netsoc_sdram_choose_req_grant <= 3'd4;
-							end else begin
-								if (soc_netsoc_sdram_choose_req_request[5]) begin
-									soc_netsoc_sdram_choose_req_grant <= 3'd5;
-								end else begin
-									if (soc_netsoc_sdram_choose_req_request[6]) begin
-										soc_netsoc_sdram_choose_req_grant <= 3'd6;
-									end else begin
-										if (soc_netsoc_sdram_choose_req_request[7]) begin
-											soc_netsoc_sdram_choose_req_grant <= 3'd7;
-										end
-									end
-								end
-							end
-						end
-					end
-				end
-			end
-			1'd1: begin
-				if (soc_netsoc_sdram_choose_req_request[2]) begin
-					soc_netsoc_sdram_choose_req_grant <= 2'd2;
-				end else begin
-					if (soc_netsoc_sdram_choose_req_request[3]) begin
-						soc_netsoc_sdram_choose_req_grant <= 2'd3;
-					end else begin
-						if (soc_netsoc_sdram_choose_req_request[4]) begin
-							soc_netsoc_sdram_choose_req_grant <= 3'd4;
-						end else begin
-							if (soc_netsoc_sdram_choose_req_request[5]) begin
-								soc_netsoc_sdram_choose_req_grant <= 3'd5;
-							end else begin
-								if (soc_netsoc_sdram_choose_req_request[6]) begin
-									soc_netsoc_sdram_choose_req_grant <= 3'd6;
-								end else begin
-									if (soc_netsoc_sdram_choose_req_request[7]) begin
-										soc_netsoc_sdram_choose_req_grant <= 3'd7;
-									end else begin
-										if (soc_netsoc_sdram_choose_req_request[0]) begin
-											soc_netsoc_sdram_choose_req_grant <= 1'd0;
-										end
-									end
-								end
-							end
-						end
-					end
-				end
-			end
-			2'd2: begin
-				if (soc_netsoc_sdram_choose_req_request[3]) begin
-					soc_netsoc_sdram_choose_req_grant <= 2'd3;
-				end else begin
-					if (soc_netsoc_sdram_choose_req_request[4]) begin
-						soc_netsoc_sdram_choose_req_grant <= 3'd4;
-					end else begin
-						if (soc_netsoc_sdram_choose_req_request[5]) begin
-							soc_netsoc_sdram_choose_req_grant <= 3'd5;
-						end else begin
-							if (soc_netsoc_sdram_choose_req_request[6]) begin
-								soc_netsoc_sdram_choose_req_grant <= 3'd6;
-							end else begin
-								if (soc_netsoc_sdram_choose_req_request[7]) begin
-									soc_netsoc_sdram_choose_req_grant <= 3'd7;
-								end else begin
-									if (soc_netsoc_sdram_choose_req_request[0]) begin
-										soc_netsoc_sdram_choose_req_grant <= 1'd0;
-									end else begin
-										if (soc_netsoc_sdram_choose_req_request[1]) begin
-											soc_netsoc_sdram_choose_req_grant <= 1'd1;
-										end
-									end
-								end
-							end
-						end
-					end
-				end
-			end
-			2'd3: begin
-				if (soc_netsoc_sdram_choose_req_request[4]) begin
-					soc_netsoc_sdram_choose_req_grant <= 3'd4;
-				end else begin
-					if (soc_netsoc_sdram_choose_req_request[5]) begin
-						soc_netsoc_sdram_choose_req_grant <= 3'd5;
-					end else begin
-						if (soc_netsoc_sdram_choose_req_request[6]) begin
-							soc_netsoc_sdram_choose_req_grant <= 3'd6;
-						end else begin
-							if (soc_netsoc_sdram_choose_req_request[7]) begin
-								soc_netsoc_sdram_choose_req_grant <= 3'd7;
-							end else begin
-								if (soc_netsoc_sdram_choose_req_request[0]) begin
-									soc_netsoc_sdram_choose_req_grant <= 1'd0;
-								end else begin
-									if (soc_netsoc_sdram_choose_req_request[1]) begin
-										soc_netsoc_sdram_choose_req_grant <= 1'd1;
-									end else begin
-										if (soc_netsoc_sdram_choose_req_request[2]) begin
-											soc_netsoc_sdram_choose_req_grant <= 2'd2;
-										end
-									end
-								end
-							end
-						end
-					end
-				end
-			end
-			3'd4: begin
-				if (soc_netsoc_sdram_choose_req_request[5]) begin
-					soc_netsoc_sdram_choose_req_grant <= 3'd5;
-				end else begin
-					if (soc_netsoc_sdram_choose_req_request[6]) begin
-						soc_netsoc_sdram_choose_req_grant <= 3'd6;
-					end else begin
-						if (soc_netsoc_sdram_choose_req_request[7]) begin
-							soc_netsoc_sdram_choose_req_grant <= 3'd7;
-						end else begin
-							if (soc_netsoc_sdram_choose_req_request[0]) begin
-								soc_netsoc_sdram_choose_req_grant <= 1'd0;
-							end else begin
-								if (soc_netsoc_sdram_choose_req_request[1]) begin
-									soc_netsoc_sdram_choose_req_grant <= 1'd1;
-								end else begin
-									if (soc_netsoc_sdram_choose_req_request[2]) begin
-										soc_netsoc_sdram_choose_req_grant <= 2'd2;
-									end else begin
-										if (soc_netsoc_sdram_choose_req_request[3]) begin
-											soc_netsoc_sdram_choose_req_grant <= 2'd3;
-										end
-									end
-								end
-							end
-						end
-					end
-				end
-			end
-			3'd5: begin
-				if (soc_netsoc_sdram_choose_req_request[6]) begin
-					soc_netsoc_sdram_choose_req_grant <= 3'd6;
-				end else begin
-					if (soc_netsoc_sdram_choose_req_request[7]) begin
-						soc_netsoc_sdram_choose_req_grant <= 3'd7;
-					end else begin
-						if (soc_netsoc_sdram_choose_req_request[0]) begin
-							soc_netsoc_sdram_choose_req_grant <= 1'd0;
-						end else begin
-							if (soc_netsoc_sdram_choose_req_request[1]) begin
-								soc_netsoc_sdram_choose_req_grant <= 1'd1;
-							end else begin
-								if (soc_netsoc_sdram_choose_req_request[2]) begin
-									soc_netsoc_sdram_choose_req_grant <= 2'd2;
-								end else begin
-									if (soc_netsoc_sdram_choose_req_request[3]) begin
-										soc_netsoc_sdram_choose_req_grant <= 2'd3;
-									end else begin
-										if (soc_netsoc_sdram_choose_req_request[4]) begin
-											soc_netsoc_sdram_choose_req_grant <= 3'd4;
-										end
-									end
-								end
-							end
-						end
-					end
-				end
-			end
-			3'd6: begin
-				if (soc_netsoc_sdram_choose_req_request[7]) begin
-					soc_netsoc_sdram_choose_req_grant <= 3'd7;
-				end else begin
-					if (soc_netsoc_sdram_choose_req_request[0]) begin
-						soc_netsoc_sdram_choose_req_grant <= 1'd0;
-					end else begin
-						if (soc_netsoc_sdram_choose_req_request[1]) begin
-							soc_netsoc_sdram_choose_req_grant <= 1'd1;
-						end else begin
-							if (soc_netsoc_sdram_choose_req_request[2]) begin
-								soc_netsoc_sdram_choose_req_grant <= 2'd2;
-							end else begin
-								if (soc_netsoc_sdram_choose_req_request[3]) begin
-									soc_netsoc_sdram_choose_req_grant <= 2'd3;
-								end else begin
-									if (soc_netsoc_sdram_choose_req_request[4]) begin
-										soc_netsoc_sdram_choose_req_grant <= 3'd4;
-									end else begin
-										if (soc_netsoc_sdram_choose_req_request[5]) begin
-											soc_netsoc_sdram_choose_req_grant <= 3'd5;
-										end
-									end
-								end
-							end
-						end
-					end
-				end
-			end
-			3'd7: begin
-				if (soc_netsoc_sdram_choose_req_request[0]) begin
-					soc_netsoc_sdram_choose_req_grant <= 1'd0;
-				end else begin
-					if (soc_netsoc_sdram_choose_req_request[1]) begin
-						soc_netsoc_sdram_choose_req_grant <= 1'd1;
-					end else begin
-						if (soc_netsoc_sdram_choose_req_request[2]) begin
-							soc_netsoc_sdram_choose_req_grant <= 2'd2;
-						end else begin
-							if (soc_netsoc_sdram_choose_req_request[3]) begin
-								soc_netsoc_sdram_choose_req_grant <= 2'd3;
-							end else begin
-								if (soc_netsoc_sdram_choose_req_request[4]) begin
-									soc_netsoc_sdram_choose_req_grant <= 3'd4;
-								end else begin
-									if (soc_netsoc_sdram_choose_req_request[5]) begin
-										soc_netsoc_sdram_choose_req_grant <= 3'd5;
-									end else begin
-										if (soc_netsoc_sdram_choose_req_request[6]) begin
-											soc_netsoc_sdram_choose_req_grant <= 3'd6;
-										end
-									end
-								end
-							end
-						end
-					end
-				end
-			end
-		endcase
-	end
-	soc_netsoc_sdram_dfi_p0_cs_n <= 1'd0;
-	soc_netsoc_sdram_dfi_p0_bank <= vns_array_muxed0;
-	soc_netsoc_sdram_dfi_p0_address <= vns_array_muxed1;
-	soc_netsoc_sdram_dfi_p0_cas_n <= (~vns_array_muxed2);
-	soc_netsoc_sdram_dfi_p0_ras_n <= (~vns_array_muxed3);
-	soc_netsoc_sdram_dfi_p0_we_n <= (~vns_array_muxed4);
-	soc_netsoc_sdram_dfi_p0_rddata_en <= vns_array_muxed5;
-	soc_netsoc_sdram_dfi_p0_wrdata_en <= vns_array_muxed6;
-	soc_netsoc_sdram_dfi_p1_cs_n <= 1'd0;
-	soc_netsoc_sdram_dfi_p1_bank <= vns_array_muxed7;
-	soc_netsoc_sdram_dfi_p1_address <= vns_array_muxed8;
-	soc_netsoc_sdram_dfi_p1_cas_n <= (~vns_array_muxed9);
-	soc_netsoc_sdram_dfi_p1_ras_n <= (~vns_array_muxed10);
-	soc_netsoc_sdram_dfi_p1_we_n <= (~vns_array_muxed11);
-	soc_netsoc_sdram_dfi_p1_rddata_en <= vns_array_muxed12;
-	soc_netsoc_sdram_dfi_p1_wrdata_en <= vns_array_muxed13;
-	soc_netsoc_sdram_dfi_p2_cs_n <= 1'd0;
-	soc_netsoc_sdram_dfi_p2_bank <= vns_array_muxed14;
-	soc_netsoc_sdram_dfi_p2_address <= vns_array_muxed15;
-	soc_netsoc_sdram_dfi_p2_cas_n <= (~vns_array_muxed16);
-	soc_netsoc_sdram_dfi_p2_ras_n <= (~vns_array_muxed17);
-	soc_netsoc_sdram_dfi_p2_we_n <= (~vns_array_muxed18);
-	soc_netsoc_sdram_dfi_p2_rddata_en <= vns_array_muxed19;
-	soc_netsoc_sdram_dfi_p2_wrdata_en <= vns_array_muxed20;
-	soc_netsoc_sdram_dfi_p3_cs_n <= 1'd0;
-	soc_netsoc_sdram_dfi_p3_bank <= vns_array_muxed21;
-	soc_netsoc_sdram_dfi_p3_address <= vns_array_muxed22;
-	soc_netsoc_sdram_dfi_p3_cas_n <= (~vns_array_muxed23);
-	soc_netsoc_sdram_dfi_p3_ras_n <= (~vns_array_muxed24);
-	soc_netsoc_sdram_dfi_p3_we_n <= (~vns_array_muxed25);
-	soc_netsoc_sdram_dfi_p3_rddata_en <= vns_array_muxed26;
-	soc_netsoc_sdram_dfi_p3_wrdata_en <= vns_array_muxed27;
-	if (soc_netsoc_sdram_trrdcon_valid) begin
-		soc_netsoc_sdram_trrdcon_count <= 1'd1;
-		if (1'd0) begin
-			soc_netsoc_sdram_trrdcon_ready <= 1'd1;
-		end else begin
-			soc_netsoc_sdram_trrdcon_ready <= 1'd0;
-		end
-	end else begin
-		if ((~soc_netsoc_sdram_trrdcon_ready)) begin
-			soc_netsoc_sdram_trrdcon_count <= (soc_netsoc_sdram_trrdcon_count - 1'd1);
-			if ((soc_netsoc_sdram_trrdcon_count == 1'd1)) begin
-				soc_netsoc_sdram_trrdcon_ready <= 1'd1;
-			end
-		end
-	end
-	soc_netsoc_sdram_tfawcon_window <= {soc_netsoc_sdram_tfawcon_window, soc_netsoc_sdram_tfawcon_valid};
-	if ((soc_netsoc_sdram_tfawcon_count < 3'd4)) begin
-		if ((soc_netsoc_sdram_tfawcon_count == 2'd3)) begin
-			soc_netsoc_sdram_tfawcon_ready <= (~soc_netsoc_sdram_tfawcon_valid);
-		end else begin
-			soc_netsoc_sdram_tfawcon_ready <= 1'd1;
-		end
-	end
-	if (soc_netsoc_sdram_tccdcon_valid) begin
-		soc_netsoc_sdram_tccdcon_count <= 1'd0;
-		if (1'd1) begin
-			soc_netsoc_sdram_tccdcon_ready <= 1'd1;
-		end else begin
-			soc_netsoc_sdram_tccdcon_ready <= 1'd0;
-		end
-	end else begin
-		if ((~soc_netsoc_sdram_tccdcon_ready)) begin
-			soc_netsoc_sdram_tccdcon_count <= (soc_netsoc_sdram_tccdcon_count - 1'd1);
-			if ((soc_netsoc_sdram_tccdcon_count == 1'd1)) begin
-				soc_netsoc_sdram_tccdcon_ready <= 1'd1;
-			end
-		end
-	end
-	if (soc_netsoc_sdram_twtrcon_valid) begin
-		soc_netsoc_sdram_twtrcon_count <= 3'd4;
-		if (1'd0) begin
-			soc_netsoc_sdram_twtrcon_ready <= 1'd1;
-		end else begin
-			soc_netsoc_sdram_twtrcon_ready <= 1'd0;
-		end
-	end else begin
-		if ((~soc_netsoc_sdram_twtrcon_ready)) begin
-			soc_netsoc_sdram_twtrcon_count <= (soc_netsoc_sdram_twtrcon_count - 1'd1);
-			if ((soc_netsoc_sdram_twtrcon_count == 1'd1)) begin
-				soc_netsoc_sdram_twtrcon_ready <= 1'd1;
-			end
-		end
-	end
-	vns_multiplexer_state <= vns_multiplexer_next_state;
-	soc_netsoc_sdram_bandwidth_cmd_valid <= soc_netsoc_sdram_choose_req_cmd_valid;
-	soc_netsoc_sdram_bandwidth_cmd_ready <= soc_netsoc_sdram_choose_req_cmd_ready;
-	soc_netsoc_sdram_bandwidth_cmd_is_read <= soc_netsoc_sdram_choose_req_cmd_payload_is_read;
-	soc_netsoc_sdram_bandwidth_cmd_is_write <= soc_netsoc_sdram_choose_req_cmd_payload_is_write;
-	{soc_netsoc_sdram_bandwidth_period, soc_netsoc_sdram_bandwidth_counter} <= (soc_netsoc_sdram_bandwidth_counter + 1'd1);
-	if (soc_netsoc_sdram_bandwidth_period) begin
-		soc_netsoc_sdram_bandwidth_nreads_r <= soc_netsoc_sdram_bandwidth_nreads;
-		soc_netsoc_sdram_bandwidth_nwrites_r <= soc_netsoc_sdram_bandwidth_nwrites;
-		soc_netsoc_sdram_bandwidth_nreads <= 1'd0;
-		soc_netsoc_sdram_bandwidth_nwrites <= 1'd0;
-	end else begin
-		if ((soc_netsoc_sdram_bandwidth_cmd_valid & soc_netsoc_sdram_bandwidth_cmd_ready)) begin
-			if (soc_netsoc_sdram_bandwidth_cmd_is_read) begin
-				soc_netsoc_sdram_bandwidth_nreads <= (soc_netsoc_sdram_bandwidth_nreads + 1'd1);
-			end
-			if (soc_netsoc_sdram_bandwidth_cmd_is_write) begin
-				soc_netsoc_sdram_bandwidth_nwrites <= (soc_netsoc_sdram_bandwidth_nwrites + 1'd1);
-			end
-		end
-	end
-	if (soc_netsoc_sdram_bandwidth_update_re) begin
-		soc_netsoc_sdram_bandwidth_nreads_status <= soc_netsoc_sdram_bandwidth_nreads_r;
-		soc_netsoc_sdram_bandwidth_nwrites_status <= soc_netsoc_sdram_bandwidth_nwrites_r;
-	end
-	if (((vns_roundrobin0_grant == 1'd0) & soc_netsoc_sdram_interface_bank0_rdata_valid)) begin
-		vns_rbank <= 1'd0;
-	end
-	if (((vns_roundrobin0_grant == 1'd0) & soc_netsoc_sdram_interface_bank0_wdata_ready)) begin
-		vns_wbank <= 1'd0;
-	end
-	if (((vns_roundrobin1_grant == 1'd0) & soc_netsoc_sdram_interface_bank1_rdata_valid)) begin
-		vns_rbank <= 1'd1;
-	end
-	if (((vns_roundrobin1_grant == 1'd0) & soc_netsoc_sdram_interface_bank1_wdata_ready)) begin
-		vns_wbank <= 1'd1;
-	end
-	if (((vns_roundrobin2_grant == 1'd0) & soc_netsoc_sdram_interface_bank2_rdata_valid)) begin
-		vns_rbank <= 2'd2;
-	end
-	if (((vns_roundrobin2_grant == 1'd0) & soc_netsoc_sdram_interface_bank2_wdata_ready)) begin
-		vns_wbank <= 2'd2;
-	end
-	if (((vns_roundrobin3_grant == 1'd0) & soc_netsoc_sdram_interface_bank3_rdata_valid)) begin
-		vns_rbank <= 2'd3;
-	end
-	if (((vns_roundrobin3_grant == 1'd0) & soc_netsoc_sdram_interface_bank3_wdata_ready)) begin
-		vns_wbank <= 2'd3;
-	end
-	if (((vns_roundrobin4_grant == 1'd0) & soc_netsoc_sdram_interface_bank4_rdata_valid)) begin
-		vns_rbank <= 3'd4;
-	end
-	if (((vns_roundrobin4_grant == 1'd0) & soc_netsoc_sdram_interface_bank4_wdata_ready)) begin
-		vns_wbank <= 3'd4;
-	end
-	if (((vns_roundrobin5_grant == 1'd0) & soc_netsoc_sdram_interface_bank5_rdata_valid)) begin
-		vns_rbank <= 3'd5;
-	end
-	if (((vns_roundrobin5_grant == 1'd0) & soc_netsoc_sdram_interface_bank5_wdata_ready)) begin
-		vns_wbank <= 3'd5;
-	end
-	if (((vns_roundrobin6_grant == 1'd0) & soc_netsoc_sdram_interface_bank6_rdata_valid)) begin
-		vns_rbank <= 3'd6;
-	end
-	if (((vns_roundrobin6_grant == 1'd0) & soc_netsoc_sdram_interface_bank6_wdata_ready)) begin
-		vns_wbank <= 3'd6;
-	end
-	if (((vns_roundrobin7_grant == 1'd0) & soc_netsoc_sdram_interface_bank7_rdata_valid)) begin
-		vns_rbank <= 3'd7;
-	end
-	if (((vns_roundrobin7_grant == 1'd0) & soc_netsoc_sdram_interface_bank7_wdata_ready)) begin
-		vns_wbank <= 3'd7;
-	end
-	vns_new_master_wdata_ready0 <= ((((((((1'd0 | ((vns_roundrobin0_grant == 1'd0) & soc_netsoc_sdram_interface_bank0_wdata_ready)) | ((vns_roundrobin1_grant == 1'd0) & soc_netsoc_sdram_interface_bank1_wdata_ready)) | ((vns_roundrobin2_grant == 1'd0) & soc_netsoc_sdram_interface_bank2_wdata_ready)) | ((vns_roundrobin3_grant == 1'd0) & soc_netsoc_sdram_interface_bank3_wdata_ready)) | ((vns_roundrobin4_grant == 1'd0) & soc_netsoc_sdram_interface_bank4_wdata_ready)) | ((vns_roundrobin5_grant == 1'd0) & soc_netsoc_sdram_interface_bank5_wdata_ready)) | ((vns_roundrobin6_grant == 1'd0) & soc_netsoc_sdram_interface_bank6_wdata_ready)) | ((vns_roundrobin7_grant == 1'd0) & soc_netsoc_sdram_interface_bank7_wdata_ready));
-	vns_new_master_wdata_ready1 <= vns_new_master_wdata_ready0;
-	vns_new_master_wdata_ready2 <= vns_new_master_wdata_ready1;
-	vns_new_master_rdata_valid0 <= ((((((((1'd0 | ((vns_roundrobin0_grant == 1'd0) & soc_netsoc_sdram_interface_bank0_rdata_valid)) | ((vns_roundrobin1_grant == 1'd0) & soc_netsoc_sdram_interface_bank1_rdata_valid)) | ((vns_roundrobin2_grant == 1'd0) & soc_netsoc_sdram_interface_bank2_rdata_valid)) | ((vns_roundrobin3_grant == 1'd0) & soc_netsoc_sdram_interface_bank3_rdata_valid)) | ((vns_roundrobin4_grant == 1'd0) & soc_netsoc_sdram_interface_bank4_rdata_valid)) | ((vns_roundrobin5_grant == 1'd0) & soc_netsoc_sdram_interface_bank5_rdata_valid)) | ((vns_roundrobin6_grant == 1'd0) & soc_netsoc_sdram_interface_bank6_rdata_valid)) | ((vns_roundrobin7_grant == 1'd0) & soc_netsoc_sdram_interface_bank7_rdata_valid));
-	vns_new_master_rdata_valid1 <= vns_new_master_rdata_valid0;
-	vns_new_master_rdata_valid2 <= vns_new_master_rdata_valid1;
-	vns_new_master_rdata_valid3 <= vns_new_master_rdata_valid2;
-	vns_new_master_rdata_valid4 <= vns_new_master_rdata_valid3;
-	vns_new_master_rdata_valid5 <= vns_new_master_rdata_valid4;
-	vns_new_master_rdata_valid6 <= vns_new_master_rdata_valid5;
-	vns_new_master_rdata_valid7 <= vns_new_master_rdata_valid6;
-	vns_new_master_rdata_valid8 <= vns_new_master_rdata_valid7;
-	vns_new_master_rdata_valid9 <= vns_new_master_rdata_valid8;
-	soc_netsoc_adr_offset_r <= soc_netsoc_interface0_wb_sdram_adr[1:0];
-	vns_fullmemorywe_state <= vns_fullmemorywe_next_state;
-	vns_litedramwishbone2native_state <= vns_litedramwishbone2native_next_state;
-	if (soc_netsoc_count_litedramwishbone2native_next_value_ce) begin
-		soc_netsoc_count <= soc_netsoc_count_litedramwishbone2native_next_value;
-	end
-	if (soc_counter_ce) begin
-		soc_counter <= (soc_counter + 1'd1);
-	end
-	if (soc_ps_preamble_error_o) begin
-		soc_preamble_errors_status <= (soc_preamble_errors_status + 1'd1);
-	end
-	if (soc_ps_crc_error_o) begin
-		soc_crc_errors_status <= (soc_crc_errors_status + 1'd1);
-	end
-	soc_ps_preamble_error_toggle_o_r <= soc_ps_preamble_error_toggle_o;
-	soc_ps_crc_error_toggle_o_r <= soc_ps_crc_error_toggle_o;
-	soc_tx_cdc_graycounter0_q_binary <= soc_tx_cdc_graycounter0_q_next_binary;
-	soc_tx_cdc_graycounter0_q <= soc_tx_cdc_graycounter0_q_next;
-	soc_rx_cdc_graycounter1_q_binary <= soc_rx_cdc_graycounter1_q_next_binary;
-	soc_rx_cdc_graycounter1_q <= soc_rx_cdc_graycounter1_q_next;
-	if (soc_writer_counter_reset) begin
-		soc_writer_counter <= 1'd0;
-	end else begin
-		if (soc_writer_counter_ce) begin
-			soc_writer_counter <= (soc_writer_counter + soc_writer_inc);
-		end
-	end
-	if (soc_writer_slot_ce) begin
-		soc_writer_slot <= (soc_writer_slot + 1'd1);
-	end
-	if (((soc_writer_fifo_syncfifo_we & soc_writer_fifo_syncfifo_writable) & (~soc_writer_fifo_replace))) begin
-		soc_writer_fifo_produce <= (soc_writer_fifo_produce + 1'd1);
-	end
-	if (soc_writer_fifo_do_read) begin
-		soc_writer_fifo_consume <= (soc_writer_fifo_consume + 1'd1);
-	end
-	if (((soc_writer_fifo_syncfifo_we & soc_writer_fifo_syncfifo_writable) & (~soc_writer_fifo_replace))) begin
-		if ((~soc_writer_fifo_do_read)) begin
-			soc_writer_fifo_level <= (soc_writer_fifo_level + 1'd1);
-		end
-	end else begin
-		if (soc_writer_fifo_do_read) begin
-			soc_writer_fifo_level <= (soc_writer_fifo_level - 1'd1);
-		end
-	end
-	vns_liteethmacsramwriter_state <= vns_liteethmacsramwriter_next_state;
-	if (soc_writer_errors_status_liteethmac_next_value_ce) begin
-		soc_writer_errors_status <= soc_writer_errors_status_liteethmac_next_value;
-	end
-	if (soc_reader_counter_reset) begin
-		soc_reader_counter <= 1'd0;
-	end else begin
-		if (soc_reader_counter_ce) begin
-			soc_reader_counter <= (soc_reader_counter + 3'd4);
-		end
-	end
-	soc_reader_last_d <= soc_reader_last;
-	if (soc_reader_done_clear) begin
-		soc_reader_done_pending <= 1'd0;
-	end
-	if (soc_reader_done_trigger) begin
-		soc_reader_done_pending <= 1'd1;
-	end
-	if (((soc_reader_fifo_syncfifo_we & soc_reader_fifo_syncfifo_writable) & (~soc_reader_fifo_replace))) begin
-		soc_reader_fifo_produce <= (soc_reader_fifo_produce + 1'd1);
-	end
-	if (soc_reader_fifo_do_read) begin
-		soc_reader_fifo_consume <= (soc_reader_fifo_consume + 1'd1);
-	end
-	if (((soc_reader_fifo_syncfifo_we & soc_reader_fifo_syncfifo_writable) & (~soc_reader_fifo_replace))) begin
-		if ((~soc_reader_fifo_do_read)) begin
-			soc_reader_fifo_level <= (soc_reader_fifo_level + 1'd1);
-		end
-	end else begin
-		if (soc_reader_fifo_do_read) begin
-			soc_reader_fifo_level <= (soc_reader_fifo_level - 1'd1);
-		end
-	end
-	vns_liteethmacsramreader_state <= vns_liteethmacsramreader_next_state;
-	soc_sram0_bus_ack0 <= 1'd0;
-	if (((soc_sram0_bus_cyc0 & soc_sram0_bus_stb0) & (~soc_sram0_bus_ack0))) begin
-		soc_sram0_bus_ack0 <= 1'd1;
-	end
-	soc_sram1_bus_ack0 <= 1'd0;
-	if (((soc_sram1_bus_cyc0 & soc_sram1_bus_stb0) & (~soc_sram1_bus_ack0))) begin
-		soc_sram1_bus_ack0 <= 1'd1;
-	end
-	soc_sram0_bus_ack1 <= 1'd0;
-	if (((soc_sram0_bus_cyc1 & soc_sram0_bus_stb1) & (~soc_sram0_bus_ack1))) begin
-		soc_sram0_bus_ack1 <= 1'd1;
-	end
-	soc_sram1_bus_ack1 <= 1'd0;
-	if (((soc_sram1_bus_cyc1 & soc_sram1_bus_stb1) & (~soc_sram1_bus_ack1))) begin
-		soc_sram1_bus_ack1 <= 1'd1;
-	end
-	soc_slave_sel_r <= soc_slave_sel;
-	case (vns_netsoc_grant)
-		1'd0: begin
-			if ((~vns_netsoc_request[0])) begin
-				if (vns_netsoc_request[1]) begin
-					vns_netsoc_grant <= 1'd1;
-				end
-			end
-		end
-		1'd1: begin
-			if ((~vns_netsoc_request[1])) begin
-				if (vns_netsoc_request[0]) begin
-					vns_netsoc_grant <= 1'd0;
-				end
-			end
-		end
-	endcase
-	vns_netsoc_slave_sel_r <= vns_netsoc_slave_sel;
-	if (vns_netsoc_wait) begin
-		if ((~vns_netsoc_done)) begin
-			vns_netsoc_count <= (vns_netsoc_count - 1'd1);
-		end
-	end else begin
-		vns_netsoc_count <= 20'd1000000;
-	end
-	vns_netsoc_csrbankarray_interface0_bank_bus_dat_r <= 1'd0;
-	if (vns_netsoc_csrbankarray_csrbank0_sel) begin
-		case (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0])
-			1'd0: begin
-				vns_netsoc_csrbankarray_interface0_bank_bus_dat_r <= soc_netsoc_cpu_latch_w;
-			end
-			1'd1: begin
-				vns_netsoc_csrbankarray_interface0_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank0_timer_time7_w;
-			end
-			2'd2: begin
-				vns_netsoc_csrbankarray_interface0_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank0_timer_time6_w;
-			end
-			2'd3: begin
-				vns_netsoc_csrbankarray_interface0_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank0_timer_time5_w;
-			end
-			3'd4: begin
-				vns_netsoc_csrbankarray_interface0_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank0_timer_time4_w;
-			end
-			3'd5: begin
-				vns_netsoc_csrbankarray_interface0_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank0_timer_time3_w;
-			end
-			3'd6: begin
-				vns_netsoc_csrbankarray_interface0_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank0_timer_time2_w;
-			end
-			3'd7: begin
-				vns_netsoc_csrbankarray_interface0_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank0_timer_time1_w;
-			end
-			4'd8: begin
-				vns_netsoc_csrbankarray_interface0_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank0_timer_time0_w;
-			end
-			4'd9: begin
-				vns_netsoc_csrbankarray_interface0_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank0_timer_time_cmp7_w;
-			end
-			4'd10: begin
-				vns_netsoc_csrbankarray_interface0_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank0_timer_time_cmp6_w;
-			end
-			4'd11: begin
-				vns_netsoc_csrbankarray_interface0_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank0_timer_time_cmp5_w;
-			end
-			4'd12: begin
-				vns_netsoc_csrbankarray_interface0_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank0_timer_time_cmp4_w;
-			end
-			4'd13: begin
-				vns_netsoc_csrbankarray_interface0_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank0_timer_time_cmp3_w;
-			end
-			4'd14: begin
-				vns_netsoc_csrbankarray_interface0_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank0_timer_time_cmp2_w;
-			end
-			4'd15: begin
-				vns_netsoc_csrbankarray_interface0_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank0_timer_time_cmp1_w;
-			end
-			5'd16: begin
-				vns_netsoc_csrbankarray_interface0_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank0_timer_time_cmp0_w;
-			end
-		endcase
-	end
-	if (vns_netsoc_csrbankarray_csrbank0_timer_time_cmp7_re) begin
-		soc_netsoc_cpu_time_cmp_storage[63:56] <= vns_netsoc_csrbankarray_csrbank0_timer_time_cmp7_r;
-	end
-	if (vns_netsoc_csrbankarray_csrbank0_timer_time_cmp6_re) begin
-		soc_netsoc_cpu_time_cmp_storage[55:48] <= vns_netsoc_csrbankarray_csrbank0_timer_time_cmp6_r;
-	end
-	if (vns_netsoc_csrbankarray_csrbank0_timer_time_cmp5_re) begin
-		soc_netsoc_cpu_time_cmp_storage[47:40] <= vns_netsoc_csrbankarray_csrbank0_timer_time_cmp5_r;
-	end
-	if (vns_netsoc_csrbankarray_csrbank0_timer_time_cmp4_re) begin
-		soc_netsoc_cpu_time_cmp_storage[39:32] <= vns_netsoc_csrbankarray_csrbank0_timer_time_cmp4_r;
-	end
-	if (vns_netsoc_csrbankarray_csrbank0_timer_time_cmp3_re) begin
-		soc_netsoc_cpu_time_cmp_storage[31:24] <= vns_netsoc_csrbankarray_csrbank0_timer_time_cmp3_r;
-	end
-	if (vns_netsoc_csrbankarray_csrbank0_timer_time_cmp2_re) begin
-		soc_netsoc_cpu_time_cmp_storage[23:16] <= vns_netsoc_csrbankarray_csrbank0_timer_time_cmp2_r;
-	end
-	if (vns_netsoc_csrbankarray_csrbank0_timer_time_cmp1_re) begin
-		soc_netsoc_cpu_time_cmp_storage[15:8] <= vns_netsoc_csrbankarray_csrbank0_timer_time_cmp1_r;
-	end
-	if (vns_netsoc_csrbankarray_csrbank0_timer_time_cmp0_re) begin
-		soc_netsoc_cpu_time_cmp_storage[7:0] <= vns_netsoc_csrbankarray_csrbank0_timer_time_cmp0_r;
-	end
-	soc_netsoc_cpu_time_cmp_re <= vns_netsoc_csrbankarray_csrbank0_timer_time_cmp0_re;
-	vns_netsoc_csrbankarray_interface1_bank_bus_dat_r <= 1'd0;
-	if (vns_netsoc_csrbankarray_csrbank1_sel) begin
-		case (vns_netsoc_csrbankarray_interface1_bank_bus_adr[3:0])
-			1'd0: begin
-				vns_netsoc_csrbankarray_interface1_bank_bus_dat_r <= soc_netsoc_ctrl_reset_reset_w;
-			end
-			1'd1: begin
-				vns_netsoc_csrbankarray_interface1_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank1_scratch3_w;
-			end
-			2'd2: begin
-				vns_netsoc_csrbankarray_interface1_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank1_scratch2_w;
-			end
-			2'd3: begin
-				vns_netsoc_csrbankarray_interface1_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank1_scratch1_w;
-			end
-			3'd4: begin
-				vns_netsoc_csrbankarray_interface1_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank1_scratch0_w;
-			end
-			3'd5: begin
-				vns_netsoc_csrbankarray_interface1_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank1_bus_errors3_w;
-			end
-			3'd6: begin
-				vns_netsoc_csrbankarray_interface1_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank1_bus_errors2_w;
-			end
-			3'd7: begin
-				vns_netsoc_csrbankarray_interface1_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank1_bus_errors1_w;
-			end
-			4'd8: begin
-				vns_netsoc_csrbankarray_interface1_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank1_bus_errors0_w;
-			end
-		endcase
-	end
-	if (vns_netsoc_csrbankarray_csrbank1_scratch3_re) begin
-		soc_netsoc_ctrl_storage[31:24] <= vns_netsoc_csrbankarray_csrbank1_scratch3_r;
-	end
-	if (vns_netsoc_csrbankarray_csrbank1_scratch2_re) begin
-		soc_netsoc_ctrl_storage[23:16] <= vns_netsoc_csrbankarray_csrbank1_scratch2_r;
-	end
-	if (vns_netsoc_csrbankarray_csrbank1_scratch1_re) begin
-		soc_netsoc_ctrl_storage[15:8] <= vns_netsoc_csrbankarray_csrbank1_scratch1_r;
-	end
-	if (vns_netsoc_csrbankarray_csrbank1_scratch0_re) begin
-		soc_netsoc_ctrl_storage[7:0] <= vns_netsoc_csrbankarray_csrbank1_scratch0_r;
-	end
-	soc_netsoc_ctrl_re <= vns_netsoc_csrbankarray_csrbank1_scratch0_re;
-	vns_netsoc_csrbankarray_interface2_bank_bus_dat_r <= 1'd0;
-	if (vns_netsoc_csrbankarray_csrbank2_sel) begin
-		case (vns_netsoc_csrbankarray_interface2_bank_bus_adr[2:0])
-			1'd0: begin
-				vns_netsoc_csrbankarray_interface2_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank2_half_sys8x_taps0_w;
-			end
-			1'd1: begin
-				vns_netsoc_csrbankarray_interface2_bank_bus_dat_r <= soc_a7ddrphy_cdly_rst_w;
-			end
-			2'd2: begin
-				vns_netsoc_csrbankarray_interface2_bank_bus_dat_r <= soc_a7ddrphy_cdly_inc_w;
-			end
-			2'd3: begin
-				vns_netsoc_csrbankarray_interface2_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank2_dly_sel0_w;
-			end
-			3'd4: begin
-				vns_netsoc_csrbankarray_interface2_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_rst_w;
-			end
-			3'd5: begin
-				vns_netsoc_csrbankarray_interface2_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_inc_w;
-			end
-			3'd6: begin
-				vns_netsoc_csrbankarray_interface2_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_bitslip_rst_w;
-			end
-			3'd7: begin
-				vns_netsoc_csrbankarray_interface2_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_bitslip_w;
-			end
-		endcase
-	end
-	if (vns_netsoc_csrbankarray_csrbank2_half_sys8x_taps0_re) begin
-		soc_a7ddrphy_half_sys8x_taps_storage[4:0] <= vns_netsoc_csrbankarray_csrbank2_half_sys8x_taps0_r;
-	end
-	soc_a7ddrphy_half_sys8x_taps_re <= vns_netsoc_csrbankarray_csrbank2_half_sys8x_taps0_re;
-	if (vns_netsoc_csrbankarray_csrbank2_dly_sel0_re) begin
-		soc_a7ddrphy_dly_sel_storage[1:0] <= vns_netsoc_csrbankarray_csrbank2_dly_sel0_r;
-	end
-	soc_a7ddrphy_dly_sel_re <= vns_netsoc_csrbankarray_csrbank2_dly_sel0_re;
-	vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= 1'd0;
-	if (vns_netsoc_csrbankarray_csrbank3_sel) begin
-		case (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0])
-			1'd0: begin
-				vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank3_sram_writer_slot_w;
-			end
-			1'd1: begin
-				vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank3_sram_writer_length3_w;
-			end
-			2'd2: begin
-				vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank3_sram_writer_length2_w;
-			end
-			2'd3: begin
-				vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank3_sram_writer_length1_w;
-			end
-			3'd4: begin
-				vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank3_sram_writer_length0_w;
-			end
-			3'd5: begin
-				vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank3_sram_writer_errors3_w;
-			end
-			3'd6: begin
-				vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank3_sram_writer_errors2_w;
-			end
-			3'd7: begin
-				vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank3_sram_writer_errors1_w;
-			end
-			4'd8: begin
-				vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank3_sram_writer_errors0_w;
-			end
-			4'd9: begin
-				vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= soc_writer_status_w;
-			end
-			4'd10: begin
-				vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= soc_writer_pending_w;
-			end
-			4'd11: begin
-				vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank3_sram_writer_ev_enable0_w;
-			end
-			4'd12: begin
-				vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= soc_reader_start_w;
-			end
-			4'd13: begin
-				vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank3_sram_reader_ready_w;
-			end
-			4'd14: begin
-				vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank3_sram_reader_level_w;
-			end
-			4'd15: begin
-				vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank3_sram_reader_slot0_w;
-			end
-			5'd16: begin
-				vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank3_sram_reader_length1_w;
-			end
-			5'd17: begin
-				vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank3_sram_reader_length0_w;
-			end
-			5'd18: begin
-				vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= soc_reader_eventmanager_status_w;
-			end
-			5'd19: begin
-				vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= soc_reader_eventmanager_pending_w;
-			end
-			5'd20: begin
-				vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank3_sram_reader_ev_enable0_w;
-			end
-			5'd21: begin
-				vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank3_preamble_crc_w;
-			end
-			5'd22: begin
-				vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank3_preamble_errors3_w;
-			end
-			5'd23: begin
-				vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank3_preamble_errors2_w;
-			end
-			5'd24: begin
-				vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank3_preamble_errors1_w;
-			end
-			5'd25: begin
-				vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank3_preamble_errors0_w;
-			end
-			5'd26: begin
-				vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank3_crc_errors3_w;
-			end
-			5'd27: begin
-				vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank3_crc_errors2_w;
-			end
-			5'd28: begin
-				vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank3_crc_errors1_w;
-			end
-			5'd29: begin
-				vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank3_crc_errors0_w;
-			end
-		endcase
-	end
-	if (vns_netsoc_csrbankarray_csrbank3_sram_writer_ev_enable0_re) begin
-		soc_writer_storage <= vns_netsoc_csrbankarray_csrbank3_sram_writer_ev_enable0_r;
-	end
-	soc_writer_re <= vns_netsoc_csrbankarray_csrbank3_sram_writer_ev_enable0_re;
-	if (vns_netsoc_csrbankarray_csrbank3_sram_reader_slot0_re) begin
-		soc_reader_slot_storage <= vns_netsoc_csrbankarray_csrbank3_sram_reader_slot0_r;
-	end
-	soc_reader_slot_re <= vns_netsoc_csrbankarray_csrbank3_sram_reader_slot0_re;
-	if (vns_netsoc_csrbankarray_csrbank3_sram_reader_length1_re) begin
-		soc_reader_length_storage[10:8] <= vns_netsoc_csrbankarray_csrbank3_sram_reader_length1_r;
-	end
-	if (vns_netsoc_csrbankarray_csrbank3_sram_reader_length0_re) begin
-		soc_reader_length_storage[7:0] <= vns_netsoc_csrbankarray_csrbank3_sram_reader_length0_r;
-	end
-	soc_reader_length_re <= vns_netsoc_csrbankarray_csrbank3_sram_reader_length0_re;
-	if (vns_netsoc_csrbankarray_csrbank3_sram_reader_ev_enable0_re) begin
-		soc_reader_eventmanager_storage <= vns_netsoc_csrbankarray_csrbank3_sram_reader_ev_enable0_r;
-	end
-	soc_reader_eventmanager_re <= vns_netsoc_csrbankarray_csrbank3_sram_reader_ev_enable0_re;
-	vns_netsoc_csrbankarray_interface4_bank_bus_dat_r <= 1'd0;
-	if (vns_netsoc_csrbankarray_csrbank4_sel) begin
-		case (vns_netsoc_csrbankarray_interface4_bank_bus_adr[1:0])
-			1'd0: begin
-				vns_netsoc_csrbankarray_interface4_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank4_crg_reset0_w;
-			end
-			1'd1: begin
-				vns_netsoc_csrbankarray_interface4_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank4_mdio_w0_w;
-			end
-			2'd2: begin
-				vns_netsoc_csrbankarray_interface4_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank4_mdio_r_w;
-			end
-		endcase
-	end
-	if (vns_netsoc_csrbankarray_csrbank4_crg_reset0_re) begin
-		soc_reset_storage <= vns_netsoc_csrbankarray_csrbank4_crg_reset0_r;
-	end
-	soc_reset_re <= vns_netsoc_csrbankarray_csrbank4_crg_reset0_re;
-	if (vns_netsoc_csrbankarray_csrbank4_mdio_w0_re) begin
-		soc_storage[2:0] <= vns_netsoc_csrbankarray_csrbank4_mdio_w0_r;
-	end
-	soc_re <= vns_netsoc_csrbankarray_csrbank4_mdio_w0_re;
-	vns_netsoc_csrbankarray_sel_r <= vns_netsoc_csrbankarray_sel;
-	vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= 1'd0;
-	if (vns_netsoc_csrbankarray_csrbank5_sel) begin
-		case (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0])
-			1'd0: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_control0_w;
-			end
-			1'd1: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi0_command0_w;
-			end
-			2'd2: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= soc_netsoc_sdram_phaseinjector0_command_issue_w;
-			end
-			2'd3: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi0_address1_w;
-			end
-			3'd4: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi0_address0_w;
-			end
-			3'd5: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi0_baddress0_w;
-			end
-			3'd6: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata3_w;
-			end
-			3'd7: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata2_w;
-			end
-			4'd8: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata1_w;
-			end
-			4'd9: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata0_w;
-			end
-			4'd10: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata3_w;
-			end
-			4'd11: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata2_w;
-			end
-			4'd12: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata1_w;
-			end
-			4'd13: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata0_w;
-			end
-			4'd14: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi1_command0_w;
-			end
-			4'd15: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= soc_netsoc_sdram_phaseinjector1_command_issue_w;
-			end
-			5'd16: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi1_address1_w;
-			end
-			5'd17: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi1_address0_w;
-			end
-			5'd18: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi1_baddress0_w;
-			end
-			5'd19: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata3_w;
-			end
-			5'd20: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata2_w;
-			end
-			5'd21: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata1_w;
-			end
-			5'd22: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata0_w;
-			end
-			5'd23: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata3_w;
-			end
-			5'd24: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata2_w;
-			end
-			5'd25: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata1_w;
-			end
-			5'd26: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata0_w;
-			end
-			5'd27: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi2_command0_w;
-			end
-			5'd28: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= soc_netsoc_sdram_phaseinjector2_command_issue_w;
-			end
-			5'd29: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi2_address1_w;
-			end
-			5'd30: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi2_address0_w;
-			end
-			5'd31: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi2_baddress0_w;
-			end
-			6'd32: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata3_w;
-			end
-			6'd33: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata2_w;
-			end
-			6'd34: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata1_w;
-			end
-			6'd35: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata0_w;
-			end
-			6'd36: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata3_w;
-			end
-			6'd37: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata2_w;
-			end
-			6'd38: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata1_w;
-			end
-			6'd39: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata0_w;
-			end
-			6'd40: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi3_command0_w;
-			end
-			6'd41: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= soc_netsoc_sdram_phaseinjector3_command_issue_w;
-			end
-			6'd42: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi3_address1_w;
-			end
-			6'd43: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi3_address0_w;
-			end
-			6'd44: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi3_baddress0_w;
-			end
-			6'd45: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata3_w;
-			end
-			6'd46: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata2_w;
-			end
-			6'd47: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata1_w;
-			end
-			6'd48: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata0_w;
-			end
-			6'd49: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata3_w;
-			end
-			6'd50: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata2_w;
-			end
-			6'd51: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata1_w;
-			end
-			6'd52: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata0_w;
-			end
-			6'd53: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= soc_netsoc_sdram_bandwidth_update_w;
-			end
-			6'd54: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nreads2_w;
-			end
-			6'd55: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nreads1_w;
-			end
-			6'd56: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nreads0_w;
-			end
-			6'd57: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nwrites2_w;
-			end
-			6'd58: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nwrites1_w;
-			end
-			6'd59: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nwrites0_w;
-			end
-			6'd60: begin
-				vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_data_width_w;
-			end
-		endcase
-	end
-	if (vns_netsoc_csrbankarray_csrbank5_dfii_control0_re) begin
-		soc_netsoc_sdram_storage[3:0] <= vns_netsoc_csrbankarray_csrbank5_dfii_control0_r;
-	end
-	soc_netsoc_sdram_re <= vns_netsoc_csrbankarray_csrbank5_dfii_control0_re;
-	if (vns_netsoc_csrbankarray_csrbank5_dfii_pi0_command0_re) begin
-		soc_netsoc_sdram_phaseinjector0_command_storage[5:0] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi0_command0_r;
-	end
-	soc_netsoc_sdram_phaseinjector0_command_re <= vns_netsoc_csrbankarray_csrbank5_dfii_pi0_command0_re;
-	if (vns_netsoc_csrbankarray_csrbank5_dfii_pi0_address1_re) begin
-		soc_netsoc_sdram_phaseinjector0_address_storage[13:8] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi0_address1_r;
-	end
-	if (vns_netsoc_csrbankarray_csrbank5_dfii_pi0_address0_re) begin
-		soc_netsoc_sdram_phaseinjector0_address_storage[7:0] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi0_address0_r;
-	end
-	soc_netsoc_sdram_phaseinjector0_address_re <= vns_netsoc_csrbankarray_csrbank5_dfii_pi0_address0_re;
-	if (vns_netsoc_csrbankarray_csrbank5_dfii_pi0_baddress0_re) begin
-		soc_netsoc_sdram_phaseinjector0_baddress_storage[2:0] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi0_baddress0_r;
-	end
-	soc_netsoc_sdram_phaseinjector0_baddress_re <= vns_netsoc_csrbankarray_csrbank5_dfii_pi0_baddress0_re;
-	if (vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata3_re) begin
-		soc_netsoc_sdram_phaseinjector0_wrdata_storage[31:24] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata3_r;
-	end
-	if (vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata2_re) begin
-		soc_netsoc_sdram_phaseinjector0_wrdata_storage[23:16] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata2_r;
-	end
-	if (vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata1_re) begin
-		soc_netsoc_sdram_phaseinjector0_wrdata_storage[15:8] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata1_r;
-	end
-	if (vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata0_re) begin
-		soc_netsoc_sdram_phaseinjector0_wrdata_storage[7:0] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata0_r;
-	end
-	soc_netsoc_sdram_phaseinjector0_wrdata_re <= vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata0_re;
-	if (vns_netsoc_csrbankarray_csrbank5_dfii_pi1_command0_re) begin
-		soc_netsoc_sdram_phaseinjector1_command_storage[5:0] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi1_command0_r;
-	end
-	soc_netsoc_sdram_phaseinjector1_command_re <= vns_netsoc_csrbankarray_csrbank5_dfii_pi1_command0_re;
-	if (vns_netsoc_csrbankarray_csrbank5_dfii_pi1_address1_re) begin
-		soc_netsoc_sdram_phaseinjector1_address_storage[13:8] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi1_address1_r;
-	end
-	if (vns_netsoc_csrbankarray_csrbank5_dfii_pi1_address0_re) begin
-		soc_netsoc_sdram_phaseinjector1_address_storage[7:0] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi1_address0_r;
-	end
-	soc_netsoc_sdram_phaseinjector1_address_re <= vns_netsoc_csrbankarray_csrbank5_dfii_pi1_address0_re;
-	if (vns_netsoc_csrbankarray_csrbank5_dfii_pi1_baddress0_re) begin
-		soc_netsoc_sdram_phaseinjector1_baddress_storage[2:0] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi1_baddress0_r;
-	end
-	soc_netsoc_sdram_phaseinjector1_baddress_re <= vns_netsoc_csrbankarray_csrbank5_dfii_pi1_baddress0_re;
-	if (vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata3_re) begin
-		soc_netsoc_sdram_phaseinjector1_wrdata_storage[31:24] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata3_r;
-	end
-	if (vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata2_re) begin
-		soc_netsoc_sdram_phaseinjector1_wrdata_storage[23:16] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata2_r;
-	end
-	if (vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata1_re) begin
-		soc_netsoc_sdram_phaseinjector1_wrdata_storage[15:8] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata1_r;
-	end
-	if (vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata0_re) begin
-		soc_netsoc_sdram_phaseinjector1_wrdata_storage[7:0] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata0_r;
-	end
-	soc_netsoc_sdram_phaseinjector1_wrdata_re <= vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata0_re;
-	if (vns_netsoc_csrbankarray_csrbank5_dfii_pi2_command0_re) begin
-		soc_netsoc_sdram_phaseinjector2_command_storage[5:0] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi2_command0_r;
-	end
-	soc_netsoc_sdram_phaseinjector2_command_re <= vns_netsoc_csrbankarray_csrbank5_dfii_pi2_command0_re;
-	if (vns_netsoc_csrbankarray_csrbank5_dfii_pi2_address1_re) begin
-		soc_netsoc_sdram_phaseinjector2_address_storage[13:8] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi2_address1_r;
-	end
-	if (vns_netsoc_csrbankarray_csrbank5_dfii_pi2_address0_re) begin
-		soc_netsoc_sdram_phaseinjector2_address_storage[7:0] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi2_address0_r;
-	end
-	soc_netsoc_sdram_phaseinjector2_address_re <= vns_netsoc_csrbankarray_csrbank5_dfii_pi2_address0_re;
-	if (vns_netsoc_csrbankarray_csrbank5_dfii_pi2_baddress0_re) begin
-		soc_netsoc_sdram_phaseinjector2_baddress_storage[2:0] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi2_baddress0_r;
-	end
-	soc_netsoc_sdram_phaseinjector2_baddress_re <= vns_netsoc_csrbankarray_csrbank5_dfii_pi2_baddress0_re;
-	if (vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata3_re) begin
-		soc_netsoc_sdram_phaseinjector2_wrdata_storage[31:24] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata3_r;
-	end
-	if (vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata2_re) begin
-		soc_netsoc_sdram_phaseinjector2_wrdata_storage[23:16] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata2_r;
-	end
-	if (vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata1_re) begin
-		soc_netsoc_sdram_phaseinjector2_wrdata_storage[15:8] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata1_r;
-	end
-	if (vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata0_re) begin
-		soc_netsoc_sdram_phaseinjector2_wrdata_storage[7:0] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata0_r;
-	end
-	soc_netsoc_sdram_phaseinjector2_wrdata_re <= vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata0_re;
-	if (vns_netsoc_csrbankarray_csrbank5_dfii_pi3_command0_re) begin
-		soc_netsoc_sdram_phaseinjector3_command_storage[5:0] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi3_command0_r;
-	end
-	soc_netsoc_sdram_phaseinjector3_command_re <= vns_netsoc_csrbankarray_csrbank5_dfii_pi3_command0_re;
-	if (vns_netsoc_csrbankarray_csrbank5_dfii_pi3_address1_re) begin
-		soc_netsoc_sdram_phaseinjector3_address_storage[13:8] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi3_address1_r;
-	end
-	if (vns_netsoc_csrbankarray_csrbank5_dfii_pi3_address0_re) begin
-		soc_netsoc_sdram_phaseinjector3_address_storage[7:0] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi3_address0_r;
-	end
-	soc_netsoc_sdram_phaseinjector3_address_re <= vns_netsoc_csrbankarray_csrbank5_dfii_pi3_address0_re;
-	if (vns_netsoc_csrbankarray_csrbank5_dfii_pi3_baddress0_re) begin
-		soc_netsoc_sdram_phaseinjector3_baddress_storage[2:0] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi3_baddress0_r;
-	end
-	soc_netsoc_sdram_phaseinjector3_baddress_re <= vns_netsoc_csrbankarray_csrbank5_dfii_pi3_baddress0_re;
-	if (vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata3_re) begin
-		soc_netsoc_sdram_phaseinjector3_wrdata_storage[31:24] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata3_r;
-	end
-	if (vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata2_re) begin
-		soc_netsoc_sdram_phaseinjector3_wrdata_storage[23:16] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata2_r;
-	end
-	if (vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata1_re) begin
-		soc_netsoc_sdram_phaseinjector3_wrdata_storage[15:8] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata1_r;
-	end
-	if (vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata0_re) begin
-		soc_netsoc_sdram_phaseinjector3_wrdata_storage[7:0] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata0_r;
-	end
-	soc_netsoc_sdram_phaseinjector3_wrdata_re <= vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata0_re;
-	vns_netsoc_csrbankarray_interface6_bank_bus_dat_r <= 1'd0;
-	if (vns_netsoc_csrbankarray_csrbank6_sel) begin
-		case (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0])
-			1'd0: begin
-				vns_netsoc_csrbankarray_interface6_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank6_load3_w;
-			end
-			1'd1: begin
-				vns_netsoc_csrbankarray_interface6_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank6_load2_w;
-			end
-			2'd2: begin
-				vns_netsoc_csrbankarray_interface6_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank6_load1_w;
-			end
-			2'd3: begin
-				vns_netsoc_csrbankarray_interface6_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank6_load0_w;
-			end
-			3'd4: begin
-				vns_netsoc_csrbankarray_interface6_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank6_reload3_w;
-			end
-			3'd5: begin
-				vns_netsoc_csrbankarray_interface6_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank6_reload2_w;
-			end
-			3'd6: begin
-				vns_netsoc_csrbankarray_interface6_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank6_reload1_w;
-			end
-			3'd7: begin
-				vns_netsoc_csrbankarray_interface6_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank6_reload0_w;
-			end
-			4'd8: begin
-				vns_netsoc_csrbankarray_interface6_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank6_en0_w;
-			end
-			4'd9: begin
-				vns_netsoc_csrbankarray_interface6_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank6_update_value0_w;
-			end
-			4'd10: begin
-				vns_netsoc_csrbankarray_interface6_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank6_value3_w;
-			end
-			4'd11: begin
-				vns_netsoc_csrbankarray_interface6_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank6_value2_w;
-			end
-			4'd12: begin
-				vns_netsoc_csrbankarray_interface6_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank6_value1_w;
-			end
-			4'd13: begin
-				vns_netsoc_csrbankarray_interface6_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank6_value0_w;
-			end
-			4'd14: begin
-				vns_netsoc_csrbankarray_interface6_bank_bus_dat_r <= soc_netsoc_timer0_eventmanager_status_w;
-			end
-			4'd15: begin
-				vns_netsoc_csrbankarray_interface6_bank_bus_dat_r <= soc_netsoc_timer0_eventmanager_pending_w;
-			end
-			5'd16: begin
-				vns_netsoc_csrbankarray_interface6_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank6_ev_enable0_w;
-			end
-		endcase
-	end
-	if (vns_netsoc_csrbankarray_csrbank6_load3_re) begin
-		soc_netsoc_timer0_load_storage[31:24] <= vns_netsoc_csrbankarray_csrbank6_load3_r;
-	end
-	if (vns_netsoc_csrbankarray_csrbank6_load2_re) begin
-		soc_netsoc_timer0_load_storage[23:16] <= vns_netsoc_csrbankarray_csrbank6_load2_r;
-	end
-	if (vns_netsoc_csrbankarray_csrbank6_load1_re) begin
-		soc_netsoc_timer0_load_storage[15:8] <= vns_netsoc_csrbankarray_csrbank6_load1_r;
-	end
-	if (vns_netsoc_csrbankarray_csrbank6_load0_re) begin
-		soc_netsoc_timer0_load_storage[7:0] <= vns_netsoc_csrbankarray_csrbank6_load0_r;
-	end
-	soc_netsoc_timer0_load_re <= vns_netsoc_csrbankarray_csrbank6_load0_re;
-	if (vns_netsoc_csrbankarray_csrbank6_reload3_re) begin
-		soc_netsoc_timer0_reload_storage[31:24] <= vns_netsoc_csrbankarray_csrbank6_reload3_r;
-	end
-	if (vns_netsoc_csrbankarray_csrbank6_reload2_re) begin
-		soc_netsoc_timer0_reload_storage[23:16] <= vns_netsoc_csrbankarray_csrbank6_reload2_r;
-	end
-	if (vns_netsoc_csrbankarray_csrbank6_reload1_re) begin
-		soc_netsoc_timer0_reload_storage[15:8] <= vns_netsoc_csrbankarray_csrbank6_reload1_r;
-	end
-	if (vns_netsoc_csrbankarray_csrbank6_reload0_re) begin
-		soc_netsoc_timer0_reload_storage[7:0] <= vns_netsoc_csrbankarray_csrbank6_reload0_r;
-	end
-	soc_netsoc_timer0_reload_re <= vns_netsoc_csrbankarray_csrbank6_reload0_re;
-	if (vns_netsoc_csrbankarray_csrbank6_en0_re) begin
-		soc_netsoc_timer0_en_storage <= vns_netsoc_csrbankarray_csrbank6_en0_r;
-	end
-	soc_netsoc_timer0_en_re <= vns_netsoc_csrbankarray_csrbank6_en0_re;
-	if (vns_netsoc_csrbankarray_csrbank6_update_value0_re) begin
-		soc_netsoc_timer0_update_value_storage <= vns_netsoc_csrbankarray_csrbank6_update_value0_r;
-	end
-	soc_netsoc_timer0_update_value_re <= vns_netsoc_csrbankarray_csrbank6_update_value0_re;
-	if (vns_netsoc_csrbankarray_csrbank6_ev_enable0_re) begin
-		soc_netsoc_timer0_eventmanager_storage <= vns_netsoc_csrbankarray_csrbank6_ev_enable0_r;
-	end
-	soc_netsoc_timer0_eventmanager_re <= vns_netsoc_csrbankarray_csrbank6_ev_enable0_re;
-	vns_netsoc_csrbankarray_interface7_bank_bus_dat_r <= 1'd0;
-	if (vns_netsoc_csrbankarray_csrbank7_sel) begin
-		case (vns_netsoc_csrbankarray_interface7_bank_bus_adr[2:0])
-			1'd0: begin
-				vns_netsoc_csrbankarray_interface7_bank_bus_dat_r <= soc_netsoc_uart_rxtx_w;
-			end
-			1'd1: begin
-				vns_netsoc_csrbankarray_interface7_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank7_txfull_w;
-			end
-			2'd2: begin
-				vns_netsoc_csrbankarray_interface7_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank7_rxempty_w;
-			end
-			2'd3: begin
-				vns_netsoc_csrbankarray_interface7_bank_bus_dat_r <= soc_netsoc_uart_eventmanager_status_w;
-			end
-			3'd4: begin
-				vns_netsoc_csrbankarray_interface7_bank_bus_dat_r <= soc_netsoc_uart_eventmanager_pending_w;
-			end
-			3'd5: begin
-				vns_netsoc_csrbankarray_interface7_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank7_ev_enable0_w;
-			end
-		endcase
-	end
-	if (vns_netsoc_csrbankarray_csrbank7_ev_enable0_re) begin
-		soc_netsoc_uart_eventmanager_storage[1:0] <= vns_netsoc_csrbankarray_csrbank7_ev_enable0_r;
-	end
-	soc_netsoc_uart_eventmanager_re <= vns_netsoc_csrbankarray_csrbank7_ev_enable0_re;
-	vns_netsoc_csrbankarray_interface8_bank_bus_dat_r <= 1'd0;
-	if (vns_netsoc_csrbankarray_csrbank8_sel) begin
-		case (vns_netsoc_csrbankarray_interface8_bank_bus_adr[1:0])
-			1'd0: begin
-				vns_netsoc_csrbankarray_interface8_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank8_tuning_word3_w;
-			end
-			1'd1: begin
-				vns_netsoc_csrbankarray_interface8_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank8_tuning_word2_w;
-			end
-			2'd2: begin
-				vns_netsoc_csrbankarray_interface8_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank8_tuning_word1_w;
-			end
-			2'd3: begin
-				vns_netsoc_csrbankarray_interface8_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank8_tuning_word0_w;
-			end
-		endcase
-	end
-	if (vns_netsoc_csrbankarray_csrbank8_tuning_word3_re) begin
-		soc_netsoc_uart_phy_storage[31:24] <= vns_netsoc_csrbankarray_csrbank8_tuning_word3_r;
-	end
-	if (vns_netsoc_csrbankarray_csrbank8_tuning_word2_re) begin
-		soc_netsoc_uart_phy_storage[23:16] <= vns_netsoc_csrbankarray_csrbank8_tuning_word2_r;
-	end
-	if (vns_netsoc_csrbankarray_csrbank8_tuning_word1_re) begin
-		soc_netsoc_uart_phy_storage[15:8] <= vns_netsoc_csrbankarray_csrbank8_tuning_word1_r;
-	end
-	if (vns_netsoc_csrbankarray_csrbank8_tuning_word0_re) begin
-		soc_netsoc_uart_phy_storage[7:0] <= vns_netsoc_csrbankarray_csrbank8_tuning_word0_r;
-	end
-	soc_netsoc_uart_phy_re <= vns_netsoc_csrbankarray_csrbank8_tuning_word0_re;
-	if (sys_rst) begin
-		soc_netsoc_ctrl_storage <= 32'd305419896;
-		soc_netsoc_ctrl_re <= 1'd0;
-		soc_netsoc_ctrl_bus_errors <= 32'd0;
-		soc_netsoc_cpu_time_status <= 64'd0;
-		soc_netsoc_cpu_time_cmp_storage <= 64'd18446744073709551615;
-		soc_netsoc_cpu_time_cmp_re <= 1'd0;
-		soc_netsoc_cpu_time <= 64'd0;
-		soc_netsoc_cpu_time_cmp <= 64'd18446744073709551615;
-		soc_netsoc_rom_bus_ack <= 1'd0;
-		soc_netsoc_sram_bus_ack <= 1'd0;
-		serial_tx <= 1'd1;
-		soc_netsoc_uart_phy_storage <= 32'd8246337;
-		soc_netsoc_uart_phy_re <= 1'd0;
-		soc_netsoc_uart_phy_sink_ready <= 1'd0;
-		soc_netsoc_uart_phy_uart_clk_txen <= 1'd0;
-		soc_netsoc_uart_phy_phase_accumulator_tx <= 32'd0;
-		soc_netsoc_uart_phy_tx_reg <= 8'd0;
-		soc_netsoc_uart_phy_tx_bitcount <= 4'd0;
-		soc_netsoc_uart_phy_tx_busy <= 1'd0;
-		soc_netsoc_uart_phy_source_valid <= 1'd0;
-		soc_netsoc_uart_phy_source_payload_data <= 8'd0;
-		soc_netsoc_uart_phy_uart_clk_rxen <= 1'd0;
-		soc_netsoc_uart_phy_phase_accumulator_rx <= 32'd0;
-		soc_netsoc_uart_phy_rx_r <= 1'd0;
-		soc_netsoc_uart_phy_rx_reg <= 8'd0;
-		soc_netsoc_uart_phy_rx_bitcount <= 4'd0;
-		soc_netsoc_uart_phy_rx_busy <= 1'd0;
-		soc_netsoc_uart_tx_pending <= 1'd0;
-		soc_netsoc_uart_tx_old_trigger <= 1'd0;
-		soc_netsoc_uart_rx_pending <= 1'd0;
-		soc_netsoc_uart_rx_old_trigger <= 1'd0;
-		soc_netsoc_uart_eventmanager_storage <= 2'd0;
-		soc_netsoc_uart_eventmanager_re <= 1'd0;
-		soc_netsoc_uart_tx_fifo_readable <= 1'd0;
-		soc_netsoc_uart_tx_fifo_level0 <= 5'd0;
-		soc_netsoc_uart_tx_fifo_produce <= 4'd0;
-		soc_netsoc_uart_tx_fifo_consume <= 4'd0;
-		soc_netsoc_uart_rx_fifo_readable <= 1'd0;
-		soc_netsoc_uart_rx_fifo_level0 <= 5'd0;
-		soc_netsoc_uart_rx_fifo_produce <= 4'd0;
-		soc_netsoc_uart_rx_fifo_consume <= 4'd0;
-		soc_netsoc_timer0_load_storage <= 32'd0;
-		soc_netsoc_timer0_load_re <= 1'd0;
-		soc_netsoc_timer0_reload_storage <= 32'd0;
-		soc_netsoc_timer0_reload_re <= 1'd0;
-		soc_netsoc_timer0_en_storage <= 1'd0;
-		soc_netsoc_timer0_en_re <= 1'd0;
-		soc_netsoc_timer0_update_value_storage <= 1'd0;
-		soc_netsoc_timer0_update_value_re <= 1'd0;
-		soc_netsoc_timer0_value_status <= 32'd0;
-		soc_netsoc_timer0_zero_pending <= 1'd0;
-		soc_netsoc_timer0_zero_old_trigger <= 1'd0;
-		soc_netsoc_timer0_eventmanager_storage <= 1'd0;
-		soc_netsoc_timer0_eventmanager_re <= 1'd0;
-		soc_netsoc_timer0_value <= 32'd0;
-		soc_emulator_ram_bus_ack <= 1'd0;
-		soc_a7ddrphy_half_sys8x_taps_storage <= 5'd8;
-		soc_a7ddrphy_half_sys8x_taps_re <= 1'd0;
-		soc_a7ddrphy_dly_sel_storage <= 2'd0;
-		soc_a7ddrphy_dly_sel_re <= 1'd0;
-		soc_a7ddrphy_dfi_p0_rddata_valid <= 1'd0;
-		soc_a7ddrphy_dfi_p1_rddata_valid <= 1'd0;
-		soc_a7ddrphy_dfi_p2_rddata_valid <= 1'd0;
-		soc_a7ddrphy_dfi_p3_rddata_valid <= 1'd0;
-		soc_a7ddrphy_oe_dqs <= 1'd0;
-		soc_a7ddrphy_oe_dq <= 1'd0;
-		soc_a7ddrphy_bitslip0_o <= 8'd0;
-		soc_a7ddrphy_bitslip0_value <= 3'd0;
-		soc_a7ddrphy_bitslip0_r <= 16'd0;
-		soc_a7ddrphy_bitslip1_o <= 8'd0;
-		soc_a7ddrphy_bitslip1_value <= 3'd0;
-		soc_a7ddrphy_bitslip1_r <= 16'd0;
-		soc_a7ddrphy_bitslip2_o <= 8'd0;
-		soc_a7ddrphy_bitslip2_value <= 3'd0;
-		soc_a7ddrphy_bitslip2_r <= 16'd0;
-		soc_a7ddrphy_bitslip3_o <= 8'd0;
-		soc_a7ddrphy_bitslip3_value <= 3'd0;
-		soc_a7ddrphy_bitslip3_r <= 16'd0;
-		soc_a7ddrphy_bitslip4_o <= 8'd0;
-		soc_a7ddrphy_bitslip4_value <= 3'd0;
-		soc_a7ddrphy_bitslip4_r <= 16'd0;
-		soc_a7ddrphy_bitslip5_o <= 8'd0;
-		soc_a7ddrphy_bitslip5_value <= 3'd0;
-		soc_a7ddrphy_bitslip5_r <= 16'd0;
-		soc_a7ddrphy_bitslip6_o <= 8'd0;
-		soc_a7ddrphy_bitslip6_value <= 3'd0;
-		soc_a7ddrphy_bitslip6_r <= 16'd0;
-		soc_a7ddrphy_bitslip7_o <= 8'd0;
-		soc_a7ddrphy_bitslip7_value <= 3'd0;
-		soc_a7ddrphy_bitslip7_r <= 16'd0;
-		soc_a7ddrphy_bitslip8_o <= 8'd0;
-		soc_a7ddrphy_bitslip8_value <= 3'd0;
-		soc_a7ddrphy_bitslip8_r <= 16'd0;
-		soc_a7ddrphy_bitslip9_o <= 8'd0;
-		soc_a7ddrphy_bitslip9_value <= 3'd0;
-		soc_a7ddrphy_bitslip9_r <= 16'd0;
-		soc_a7ddrphy_bitslip10_o <= 8'd0;
-		soc_a7ddrphy_bitslip10_value <= 3'd0;
-		soc_a7ddrphy_bitslip10_r <= 16'd0;
-		soc_a7ddrphy_bitslip11_o <= 8'd0;
-		soc_a7ddrphy_bitslip11_value <= 3'd0;
-		soc_a7ddrphy_bitslip11_r <= 16'd0;
-		soc_a7ddrphy_bitslip12_o <= 8'd0;
-		soc_a7ddrphy_bitslip12_value <= 3'd0;
-		soc_a7ddrphy_bitslip12_r <= 16'd0;
-		soc_a7ddrphy_bitslip13_o <= 8'd0;
-		soc_a7ddrphy_bitslip13_value <= 3'd0;
-		soc_a7ddrphy_bitslip13_r <= 16'd0;
-		soc_a7ddrphy_bitslip14_o <= 8'd0;
-		soc_a7ddrphy_bitslip14_value <= 3'd0;
-		soc_a7ddrphy_bitslip14_r <= 16'd0;
-		soc_a7ddrphy_bitslip15_o <= 8'd0;
-		soc_a7ddrphy_bitslip15_value <= 3'd0;
-		soc_a7ddrphy_bitslip15_r <= 16'd0;
-		soc_a7ddrphy_n_rddata_en0 <= 1'd0;
-		soc_a7ddrphy_n_rddata_en1 <= 1'd0;
-		soc_a7ddrphy_n_rddata_en2 <= 1'd0;
-		soc_a7ddrphy_n_rddata_en3 <= 1'd0;
-		soc_a7ddrphy_n_rddata_en4 <= 1'd0;
-		soc_a7ddrphy_n_rddata_en5 <= 1'd0;
-		soc_a7ddrphy_n_rddata_en6 <= 1'd0;
-		soc_a7ddrphy_n_rddata_en7 <= 1'd0;
-		soc_a7ddrphy_last_wrdata_en <= 4'd0;
-		soc_netsoc_sdram_storage <= 4'd0;
-		soc_netsoc_sdram_re <= 1'd0;
-		soc_netsoc_sdram_phaseinjector0_command_storage <= 6'd0;
-		soc_netsoc_sdram_phaseinjector0_command_re <= 1'd0;
-		soc_netsoc_sdram_phaseinjector0_address_storage <= 14'd0;
-		soc_netsoc_sdram_phaseinjector0_address_re <= 1'd0;
-		soc_netsoc_sdram_phaseinjector0_baddress_storage <= 3'd0;
-		soc_netsoc_sdram_phaseinjector0_baddress_re <= 1'd0;
-		soc_netsoc_sdram_phaseinjector0_wrdata_storage <= 32'd0;
-		soc_netsoc_sdram_phaseinjector0_wrdata_re <= 1'd0;
-		soc_netsoc_sdram_phaseinjector0_status <= 32'd0;
-		soc_netsoc_sdram_phaseinjector1_command_storage <= 6'd0;
-		soc_netsoc_sdram_phaseinjector1_command_re <= 1'd0;
-		soc_netsoc_sdram_phaseinjector1_address_storage <= 14'd0;
-		soc_netsoc_sdram_phaseinjector1_address_re <= 1'd0;
-		soc_netsoc_sdram_phaseinjector1_baddress_storage <= 3'd0;
-		soc_netsoc_sdram_phaseinjector1_baddress_re <= 1'd0;
-		soc_netsoc_sdram_phaseinjector1_wrdata_storage <= 32'd0;
-		soc_netsoc_sdram_phaseinjector1_wrdata_re <= 1'd0;
-		soc_netsoc_sdram_phaseinjector1_status <= 32'd0;
-		soc_netsoc_sdram_phaseinjector2_command_storage <= 6'd0;
-		soc_netsoc_sdram_phaseinjector2_command_re <= 1'd0;
-		soc_netsoc_sdram_phaseinjector2_address_storage <= 14'd0;
-		soc_netsoc_sdram_phaseinjector2_address_re <= 1'd0;
-		soc_netsoc_sdram_phaseinjector2_baddress_storage <= 3'd0;
-		soc_netsoc_sdram_phaseinjector2_baddress_re <= 1'd0;
-		soc_netsoc_sdram_phaseinjector2_wrdata_storage <= 32'd0;
-		soc_netsoc_sdram_phaseinjector2_wrdata_re <= 1'd0;
-		soc_netsoc_sdram_phaseinjector2_status <= 32'd0;
-		soc_netsoc_sdram_phaseinjector3_command_storage <= 6'd0;
-		soc_netsoc_sdram_phaseinjector3_command_re <= 1'd0;
-		soc_netsoc_sdram_phaseinjector3_address_storage <= 14'd0;
-		soc_netsoc_sdram_phaseinjector3_address_re <= 1'd0;
-		soc_netsoc_sdram_phaseinjector3_baddress_storage <= 3'd0;
-		soc_netsoc_sdram_phaseinjector3_baddress_re <= 1'd0;
-		soc_netsoc_sdram_phaseinjector3_wrdata_storage <= 32'd0;
-		soc_netsoc_sdram_phaseinjector3_wrdata_re <= 1'd0;
-		soc_netsoc_sdram_phaseinjector3_status <= 32'd0;
-		soc_netsoc_sdram_dfi_p0_address <= 14'd0;
-		soc_netsoc_sdram_dfi_p0_bank <= 3'd0;
-		soc_netsoc_sdram_dfi_p0_cas_n <= 1'd1;
-		soc_netsoc_sdram_dfi_p0_cs_n <= 1'd1;
-		soc_netsoc_sdram_dfi_p0_ras_n <= 1'd1;
-		soc_netsoc_sdram_dfi_p0_we_n <= 1'd1;
-		soc_netsoc_sdram_dfi_p0_wrdata_en <= 1'd0;
-		soc_netsoc_sdram_dfi_p0_rddata_en <= 1'd0;
-		soc_netsoc_sdram_dfi_p1_address <= 14'd0;
-		soc_netsoc_sdram_dfi_p1_bank <= 3'd0;
-		soc_netsoc_sdram_dfi_p1_cas_n <= 1'd1;
-		soc_netsoc_sdram_dfi_p1_cs_n <= 1'd1;
-		soc_netsoc_sdram_dfi_p1_ras_n <= 1'd1;
-		soc_netsoc_sdram_dfi_p1_we_n <= 1'd1;
-		soc_netsoc_sdram_dfi_p1_wrdata_en <= 1'd0;
-		soc_netsoc_sdram_dfi_p1_rddata_en <= 1'd0;
-		soc_netsoc_sdram_dfi_p2_address <= 14'd0;
-		soc_netsoc_sdram_dfi_p2_bank <= 3'd0;
-		soc_netsoc_sdram_dfi_p2_cas_n <= 1'd1;
-		soc_netsoc_sdram_dfi_p2_cs_n <= 1'd1;
-		soc_netsoc_sdram_dfi_p2_ras_n <= 1'd1;
-		soc_netsoc_sdram_dfi_p2_we_n <= 1'd1;
-		soc_netsoc_sdram_dfi_p2_wrdata_en <= 1'd0;
-		soc_netsoc_sdram_dfi_p2_rddata_en <= 1'd0;
-		soc_netsoc_sdram_dfi_p3_address <= 14'd0;
-		soc_netsoc_sdram_dfi_p3_bank <= 3'd0;
-		soc_netsoc_sdram_dfi_p3_cas_n <= 1'd1;
-		soc_netsoc_sdram_dfi_p3_cs_n <= 1'd1;
-		soc_netsoc_sdram_dfi_p3_ras_n <= 1'd1;
-		soc_netsoc_sdram_dfi_p3_we_n <= 1'd1;
-		soc_netsoc_sdram_dfi_p3_wrdata_en <= 1'd0;
-		soc_netsoc_sdram_dfi_p3_rddata_en <= 1'd0;
-		soc_netsoc_sdram_cmd_payload_a <= 14'd0;
-		soc_netsoc_sdram_cmd_payload_ba <= 3'd0;
-		soc_netsoc_sdram_cmd_payload_cas <= 1'd0;
-		soc_netsoc_sdram_cmd_payload_ras <= 1'd0;
-		soc_netsoc_sdram_cmd_payload_we <= 1'd0;
-		soc_netsoc_sdram_timer_count1 <= 9'd468;
-		soc_netsoc_sdram_postponer_req_o <= 1'd0;
-		soc_netsoc_sdram_postponer_count <= 1'd0;
-		soc_netsoc_sdram_sequencer_done1 <= 1'd0;
-		soc_netsoc_sdram_sequencer_counter <= 6'd0;
-		soc_netsoc_sdram_sequencer_count <= 1'd0;
-		soc_netsoc_sdram_zqcs_timer_count1 <= 26'd59999999;
-		soc_netsoc_sdram_zqcs_executer_done <= 1'd0;
-		soc_netsoc_sdram_zqcs_executer_counter <= 5'd0;
-		soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_level <= 4'd0;
-		soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_produce <= 3'd0;
-		soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_consume <= 3'd0;
-		soc_netsoc_sdram_bankmachine0_cmd_buffer_source_payload_we <= 1'd0;
-		soc_netsoc_sdram_bankmachine0_cmd_buffer_source_payload_addr <= 21'd0;
-		soc_netsoc_sdram_bankmachine0_cmd_buffer_valid_n <= 1'd0;
-		soc_netsoc_sdram_bankmachine0_cmd_buffer_first_n <= 1'd0;
-		soc_netsoc_sdram_bankmachine0_cmd_buffer_last_n <= 1'd0;
-		soc_netsoc_sdram_bankmachine0_row <= 14'd0;
-		soc_netsoc_sdram_bankmachine0_row_opened <= 1'd0;
-		soc_netsoc_sdram_bankmachine0_twtpcon_ready <= 1'd1;
-		soc_netsoc_sdram_bankmachine0_twtpcon_count <= 3'd0;
-		soc_netsoc_sdram_bankmachine0_trccon_ready <= 1'd1;
-		soc_netsoc_sdram_bankmachine0_trccon_count <= 2'd0;
-		soc_netsoc_sdram_bankmachine0_trascon_ready <= 1'd1;
-		soc_netsoc_sdram_bankmachine0_trascon_count <= 2'd0;
-		soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_level <= 4'd0;
-		soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_produce <= 3'd0;
-		soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_consume <= 3'd0;
-		soc_netsoc_sdram_bankmachine1_cmd_buffer_source_payload_we <= 1'd0;
-		soc_netsoc_sdram_bankmachine1_cmd_buffer_source_payload_addr <= 21'd0;
-		soc_netsoc_sdram_bankmachine1_cmd_buffer_valid_n <= 1'd0;
-		soc_netsoc_sdram_bankmachine1_cmd_buffer_first_n <= 1'd0;
-		soc_netsoc_sdram_bankmachine1_cmd_buffer_last_n <= 1'd0;
-		soc_netsoc_sdram_bankmachine1_row <= 14'd0;
-		soc_netsoc_sdram_bankmachine1_row_opened <= 1'd0;
-		soc_netsoc_sdram_bankmachine1_twtpcon_ready <= 1'd1;
-		soc_netsoc_sdram_bankmachine1_twtpcon_count <= 3'd0;
-		soc_netsoc_sdram_bankmachine1_trccon_ready <= 1'd1;
-		soc_netsoc_sdram_bankmachine1_trccon_count <= 2'd0;
-		soc_netsoc_sdram_bankmachine1_trascon_ready <= 1'd1;
-		soc_netsoc_sdram_bankmachine1_trascon_count <= 2'd0;
-		soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_level <= 4'd0;
-		soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_produce <= 3'd0;
-		soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_consume <= 3'd0;
-		soc_netsoc_sdram_bankmachine2_cmd_buffer_source_payload_we <= 1'd0;
-		soc_netsoc_sdram_bankmachine2_cmd_buffer_source_payload_addr <= 21'd0;
-		soc_netsoc_sdram_bankmachine2_cmd_buffer_valid_n <= 1'd0;
-		soc_netsoc_sdram_bankmachine2_cmd_buffer_first_n <= 1'd0;
-		soc_netsoc_sdram_bankmachine2_cmd_buffer_last_n <= 1'd0;
-		soc_netsoc_sdram_bankmachine2_row <= 14'd0;
-		soc_netsoc_sdram_bankmachine2_row_opened <= 1'd0;
-		soc_netsoc_sdram_bankmachine2_twtpcon_ready <= 1'd1;
-		soc_netsoc_sdram_bankmachine2_twtpcon_count <= 3'd0;
-		soc_netsoc_sdram_bankmachine2_trccon_ready <= 1'd1;
-		soc_netsoc_sdram_bankmachine2_trccon_count <= 2'd0;
-		soc_netsoc_sdram_bankmachine2_trascon_ready <= 1'd1;
-		soc_netsoc_sdram_bankmachine2_trascon_count <= 2'd0;
-		soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_level <= 4'd0;
-		soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_produce <= 3'd0;
-		soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_consume <= 3'd0;
-		soc_netsoc_sdram_bankmachine3_cmd_buffer_source_payload_we <= 1'd0;
-		soc_netsoc_sdram_bankmachine3_cmd_buffer_source_payload_addr <= 21'd0;
-		soc_netsoc_sdram_bankmachine3_cmd_buffer_valid_n <= 1'd0;
-		soc_netsoc_sdram_bankmachine3_cmd_buffer_first_n <= 1'd0;
-		soc_netsoc_sdram_bankmachine3_cmd_buffer_last_n <= 1'd0;
-		soc_netsoc_sdram_bankmachine3_row <= 14'd0;
-		soc_netsoc_sdram_bankmachine3_row_opened <= 1'd0;
-		soc_netsoc_sdram_bankmachine3_twtpcon_ready <= 1'd1;
-		soc_netsoc_sdram_bankmachine3_twtpcon_count <= 3'd0;
-		soc_netsoc_sdram_bankmachine3_trccon_ready <= 1'd1;
-		soc_netsoc_sdram_bankmachine3_trccon_count <= 2'd0;
-		soc_netsoc_sdram_bankmachine3_trascon_ready <= 1'd1;
-		soc_netsoc_sdram_bankmachine3_trascon_count <= 2'd0;
-		soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_level <= 4'd0;
-		soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_produce <= 3'd0;
-		soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_consume <= 3'd0;
-		soc_netsoc_sdram_bankmachine4_cmd_buffer_source_payload_we <= 1'd0;
-		soc_netsoc_sdram_bankmachine4_cmd_buffer_source_payload_addr <= 21'd0;
-		soc_netsoc_sdram_bankmachine4_cmd_buffer_valid_n <= 1'd0;
-		soc_netsoc_sdram_bankmachine4_cmd_buffer_first_n <= 1'd0;
-		soc_netsoc_sdram_bankmachine4_cmd_buffer_last_n <= 1'd0;
-		soc_netsoc_sdram_bankmachine4_row <= 14'd0;
-		soc_netsoc_sdram_bankmachine4_row_opened <= 1'd0;
-		soc_netsoc_sdram_bankmachine4_twtpcon_ready <= 1'd1;
-		soc_netsoc_sdram_bankmachine4_twtpcon_count <= 3'd0;
-		soc_netsoc_sdram_bankmachine4_trccon_ready <= 1'd1;
-		soc_netsoc_sdram_bankmachine4_trccon_count <= 2'd0;
-		soc_netsoc_sdram_bankmachine4_trascon_ready <= 1'd1;
-		soc_netsoc_sdram_bankmachine4_trascon_count <= 2'd0;
-		soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_level <= 4'd0;
-		soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_produce <= 3'd0;
-		soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_consume <= 3'd0;
-		soc_netsoc_sdram_bankmachine5_cmd_buffer_source_payload_we <= 1'd0;
-		soc_netsoc_sdram_bankmachine5_cmd_buffer_source_payload_addr <= 21'd0;
-		soc_netsoc_sdram_bankmachine5_cmd_buffer_valid_n <= 1'd0;
-		soc_netsoc_sdram_bankmachine5_cmd_buffer_first_n <= 1'd0;
-		soc_netsoc_sdram_bankmachine5_cmd_buffer_last_n <= 1'd0;
-		soc_netsoc_sdram_bankmachine5_row <= 14'd0;
-		soc_netsoc_sdram_bankmachine5_row_opened <= 1'd0;
-		soc_netsoc_sdram_bankmachine5_twtpcon_ready <= 1'd1;
-		soc_netsoc_sdram_bankmachine5_twtpcon_count <= 3'd0;
-		soc_netsoc_sdram_bankmachine5_trccon_ready <= 1'd1;
-		soc_netsoc_sdram_bankmachine5_trccon_count <= 2'd0;
-		soc_netsoc_sdram_bankmachine5_trascon_ready <= 1'd1;
-		soc_netsoc_sdram_bankmachine5_trascon_count <= 2'd0;
-		soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_level <= 4'd0;
-		soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_produce <= 3'd0;
-		soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_consume <= 3'd0;
-		soc_netsoc_sdram_bankmachine6_cmd_buffer_source_payload_we <= 1'd0;
-		soc_netsoc_sdram_bankmachine6_cmd_buffer_source_payload_addr <= 21'd0;
-		soc_netsoc_sdram_bankmachine6_cmd_buffer_valid_n <= 1'd0;
-		soc_netsoc_sdram_bankmachine6_cmd_buffer_first_n <= 1'd0;
-		soc_netsoc_sdram_bankmachine6_cmd_buffer_last_n <= 1'd0;
-		soc_netsoc_sdram_bankmachine6_row <= 14'd0;
-		soc_netsoc_sdram_bankmachine6_row_opened <= 1'd0;
-		soc_netsoc_sdram_bankmachine6_twtpcon_ready <= 1'd1;
-		soc_netsoc_sdram_bankmachine6_twtpcon_count <= 3'd0;
-		soc_netsoc_sdram_bankmachine6_trccon_ready <= 1'd1;
-		soc_netsoc_sdram_bankmachine6_trccon_count <= 2'd0;
-		soc_netsoc_sdram_bankmachine6_trascon_ready <= 1'd1;
-		soc_netsoc_sdram_bankmachine6_trascon_count <= 2'd0;
-		soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_level <= 4'd0;
-		soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_produce <= 3'd0;
-		soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_consume <= 3'd0;
-		soc_netsoc_sdram_bankmachine7_cmd_buffer_source_payload_we <= 1'd0;
-		soc_netsoc_sdram_bankmachine7_cmd_buffer_source_payload_addr <= 21'd0;
-		soc_netsoc_sdram_bankmachine7_cmd_buffer_valid_n <= 1'd0;
-		soc_netsoc_sdram_bankmachine7_cmd_buffer_first_n <= 1'd0;
-		soc_netsoc_sdram_bankmachine7_cmd_buffer_last_n <= 1'd0;
-		soc_netsoc_sdram_bankmachine7_row <= 14'd0;
-		soc_netsoc_sdram_bankmachine7_row_opened <= 1'd0;
-		soc_netsoc_sdram_bankmachine7_twtpcon_ready <= 1'd1;
-		soc_netsoc_sdram_bankmachine7_twtpcon_count <= 3'd0;
-		soc_netsoc_sdram_bankmachine7_trccon_ready <= 1'd1;
-		soc_netsoc_sdram_bankmachine7_trccon_count <= 2'd0;
-		soc_netsoc_sdram_bankmachine7_trascon_ready <= 1'd1;
-		soc_netsoc_sdram_bankmachine7_trascon_count <= 2'd0;
-		soc_netsoc_sdram_choose_cmd_grant <= 3'd0;
-		soc_netsoc_sdram_choose_req_grant <= 3'd0;
-		soc_netsoc_sdram_trrdcon_ready <= 1'd1;
-		soc_netsoc_sdram_trrdcon_count <= 1'd0;
-		soc_netsoc_sdram_tfawcon_ready <= 1'd1;
-		soc_netsoc_sdram_tfawcon_window <= 4'd0;
-		soc_netsoc_sdram_tccdcon_ready <= 1'd1;
-		soc_netsoc_sdram_tccdcon_count <= 1'd0;
-		soc_netsoc_sdram_twtrcon_ready <= 1'd1;
-		soc_netsoc_sdram_twtrcon_count <= 3'd0;
-		soc_netsoc_sdram_time0 <= 5'd0;
-		soc_netsoc_sdram_time1 <= 4'd0;
-		soc_netsoc_sdram_bandwidth_nreads_status <= 24'd0;
-		soc_netsoc_sdram_bandwidth_nwrites_status <= 24'd0;
-		soc_netsoc_sdram_bandwidth_cmd_valid <= 1'd0;
-		soc_netsoc_sdram_bandwidth_cmd_ready <= 1'd0;
-		soc_netsoc_sdram_bandwidth_cmd_is_read <= 1'd0;
-		soc_netsoc_sdram_bandwidth_cmd_is_write <= 1'd0;
-		soc_netsoc_sdram_bandwidth_counter <= 24'd0;
-		soc_netsoc_sdram_bandwidth_period <= 1'd0;
-		soc_netsoc_sdram_bandwidth_nreads <= 24'd0;
-		soc_netsoc_sdram_bandwidth_nwrites <= 24'd0;
-		soc_netsoc_sdram_bandwidth_nreads_r <= 24'd0;
-		soc_netsoc_sdram_bandwidth_nwrites_r <= 24'd0;
-		soc_netsoc_adr_offset_r <= 2'd0;
-		soc_netsoc_count <= 1'd0;
-		soc_reset_storage <= 1'd0;
-		soc_reset_re <= 1'd0;
-		soc_counter <= 9'd0;
-		soc_storage <= 3'd0;
-		soc_re <= 1'd0;
-		soc_preamble_errors_status <= 32'd0;
-		soc_crc_errors_status <= 32'd0;
-		soc_tx_cdc_graycounter0_q <= 7'd0;
-		soc_tx_cdc_graycounter0_q_binary <= 7'd0;
-		soc_rx_cdc_graycounter1_q <= 7'd0;
-		soc_rx_cdc_graycounter1_q_binary <= 7'd0;
-		soc_writer_errors_status <= 32'd0;
-		soc_writer_storage <= 1'd0;
-		soc_writer_re <= 1'd0;
-		soc_writer_counter <= 32'd0;
-		soc_writer_slot <= 1'd0;
-		soc_writer_fifo_level <= 2'd0;
-		soc_writer_fifo_produce <= 1'd0;
-		soc_writer_fifo_consume <= 1'd0;
-		soc_reader_slot_storage <= 1'd0;
-		soc_reader_slot_re <= 1'd0;
-		soc_reader_length_storage <= 11'd0;
-		soc_reader_length_re <= 1'd0;
-		soc_reader_done_pending <= 1'd0;
-		soc_reader_eventmanager_storage <= 1'd0;
-		soc_reader_eventmanager_re <= 1'd0;
-		soc_reader_fifo_level <= 2'd0;
-		soc_reader_fifo_produce <= 1'd0;
-		soc_reader_fifo_consume <= 1'd0;
-		soc_reader_counter <= 11'd0;
-		soc_reader_last_d <= 1'd0;
-		soc_sram0_bus_ack0 <= 1'd0;
-		soc_sram1_bus_ack0 <= 1'd0;
-		soc_sram0_bus_ack1 <= 1'd0;
-		soc_sram1_bus_ack1 <= 1'd0;
-		soc_slave_sel_r <= 4'd0;
-		vns_wb2csr_state <= 1'd0;
-		vns_refresher_state <= 2'd0;
-		vns_bankmachine0_state <= 3'd0;
-		vns_bankmachine1_state <= 3'd0;
-		vns_bankmachine2_state <= 3'd0;
-		vns_bankmachine3_state <= 3'd0;
-		vns_bankmachine4_state <= 3'd0;
-		vns_bankmachine5_state <= 3'd0;
-		vns_bankmachine6_state <= 3'd0;
-		vns_bankmachine7_state <= 3'd0;
-		vns_multiplexer_state <= 4'd0;
-		vns_rbank <= 3'd0;
-		vns_wbank <= 3'd0;
-		vns_new_master_wdata_ready0 <= 1'd0;
-		vns_new_master_wdata_ready1 <= 1'd0;
-		vns_new_master_wdata_ready2 <= 1'd0;
-		vns_new_master_rdata_valid0 <= 1'd0;
-		vns_new_master_rdata_valid1 <= 1'd0;
-		vns_new_master_rdata_valid2 <= 1'd0;
-		vns_new_master_rdata_valid3 <= 1'd0;
-		vns_new_master_rdata_valid4 <= 1'd0;
-		vns_new_master_rdata_valid5 <= 1'd0;
-		vns_new_master_rdata_valid6 <= 1'd0;
-		vns_new_master_rdata_valid7 <= 1'd0;
-		vns_new_master_rdata_valid8 <= 1'd0;
-		vns_new_master_rdata_valid9 <= 1'd0;
-		vns_fullmemorywe_state <= 3'd0;
-		vns_litedramwishbone2native_state <= 2'd0;
-		vns_liteethmacsramwriter_state <= 3'd0;
-		vns_liteethmacsramreader_state <= 2'd0;
-		vns_netsoc_grant <= 1'd0;
-		vns_netsoc_slave_sel_r <= 6'd0;
-		vns_netsoc_count <= 20'd1000000;
-		vns_netsoc_csrbankarray_interface0_bank_bus_dat_r <= 8'd0;
-		vns_netsoc_csrbankarray_interface1_bank_bus_dat_r <= 8'd0;
-		vns_netsoc_csrbankarray_interface2_bank_bus_dat_r <= 8'd0;
-		vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= 8'd0;
-		vns_netsoc_csrbankarray_interface4_bank_bus_dat_r <= 8'd0;
-		vns_netsoc_csrbankarray_sel_r <= 1'd0;
-		vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= 8'd0;
-		vns_netsoc_csrbankarray_interface6_bank_bus_dat_r <= 8'd0;
-		vns_netsoc_csrbankarray_interface7_bank_bus_dat_r <= 8'd0;
-		vns_netsoc_csrbankarray_interface8_bank_bus_dat_r <= 8'd0;
-	end
-	vns_xilinxmultiregimpl0_regs0 <= serial_rx;
-	vns_xilinxmultiregimpl0_regs1 <= vns_xilinxmultiregimpl0_regs0;
-	vns_xilinxmultiregimpl1_regs0 <= soc_data_r;
-	vns_xilinxmultiregimpl1_regs1 <= vns_xilinxmultiregimpl1_regs0;
-	vns_xilinxmultiregimpl2_regs0 <= soc_ps_preamble_error_toggle_i;
-	vns_xilinxmultiregimpl2_regs1 <= vns_xilinxmultiregimpl2_regs0;
-	vns_xilinxmultiregimpl3_regs0 <= soc_ps_crc_error_toggle_i;
-	vns_xilinxmultiregimpl3_regs1 <= vns_xilinxmultiregimpl3_regs0;
-	vns_xilinxmultiregimpl5_regs0 <= soc_tx_cdc_graycounter1_q;
-	vns_xilinxmultiregimpl5_regs1 <= vns_xilinxmultiregimpl5_regs0;
-	vns_xilinxmultiregimpl6_regs0 <= soc_rx_cdc_graycounter0_q;
-	vns_xilinxmultiregimpl6_regs1 <= vns_xilinxmultiregimpl6_regs0;
-end
-
-reg [31:0] mem[0:16383];
-reg [31:0] memdat;
-always @(posedge sys_clk) begin
-	memdat <= mem[soc_netsoc_rom_adr];
-end
-
-assign soc_netsoc_rom_dat_r = memdat;
-
-initial begin
-	$readmemh("mem.init", mem);
-end
-
-reg [31:0] mem_1[0:8191];
-reg [12:0] memadr;
-always @(posedge sys_clk) begin
-	if (soc_netsoc_sram_we[0])
-		mem_1[soc_netsoc_sram_adr][7:0] <= soc_netsoc_sram_dat_w[7:0];
-	if (soc_netsoc_sram_we[1])
-		mem_1[soc_netsoc_sram_adr][15:8] <= soc_netsoc_sram_dat_w[15:8];
-	if (soc_netsoc_sram_we[2])
-		mem_1[soc_netsoc_sram_adr][23:16] <= soc_netsoc_sram_dat_w[23:16];
-	if (soc_netsoc_sram_we[3])
-		mem_1[soc_netsoc_sram_adr][31:24] <= soc_netsoc_sram_dat_w[31:24];
-	memadr <= soc_netsoc_sram_adr;
-end
-
-assign soc_netsoc_sram_dat_r = mem_1[memadr];
-
-initial begin
-	$readmemh("mem_1.init", mem_1);
-end
-
-reg [9:0] storage[0:15];
-reg [9:0] memdat_1;
-reg [9:0] memdat_2;
-always @(posedge sys_clk) begin
-	if (soc_netsoc_uart_tx_fifo_wrport_we)
-		storage[soc_netsoc_uart_tx_fifo_wrport_adr] <= soc_netsoc_uart_tx_fifo_wrport_dat_w;
-	memdat_1 <= storage[soc_netsoc_uart_tx_fifo_wrport_adr];
-end
-
-always @(posedge sys_clk) begin
-	if (soc_netsoc_uart_tx_fifo_rdport_re)
-		memdat_2 <= storage[soc_netsoc_uart_tx_fifo_rdport_adr];
-end
-
-assign soc_netsoc_uart_tx_fifo_wrport_dat_r = memdat_1;
-assign soc_netsoc_uart_tx_fifo_rdport_dat_r = memdat_2;
-
-reg [9:0] storage_1[0:15];
-reg [9:0] memdat_3;
-reg [9:0] memdat_4;
-always @(posedge sys_clk) begin
-	if (soc_netsoc_uart_rx_fifo_wrport_we)
-		storage_1[soc_netsoc_uart_rx_fifo_wrport_adr] <= soc_netsoc_uart_rx_fifo_wrport_dat_w;
-	memdat_3 <= storage_1[soc_netsoc_uart_rx_fifo_wrport_adr];
-end
-
-always @(posedge sys_clk) begin
-	if (soc_netsoc_uart_rx_fifo_rdport_re)
-		memdat_4 <= storage_1[soc_netsoc_uart_rx_fifo_rdport_adr];
-end
-
-assign soc_netsoc_uart_rx_fifo_wrport_dat_r = memdat_3;
-assign soc_netsoc_uart_rx_fifo_rdport_dat_r = memdat_4;
-
-reg [7:0] mem_2[0:6];
-reg [2:0] memadr_1;
-always @(posedge sys_clk) begin
-	memadr_1 <= vns_netsoc_csrbankarray_adr;
-end
-
-assign vns_netsoc_csrbankarray_dat_r = mem_2[memadr_1];
-
-initial begin
-	$readmemh("mem_2.init", mem_2);
-end
-
-PLLE2_ADV #(
-	.CLKFBOUT_MULT(4'd12),
-	.CLKIN1_PERIOD(10.0),
-	.CLKOUT0_DIVIDE(5'd20),
-	.CLKOUT0_PHASE(1'd0),
-	.CLKOUT1_DIVIDE(3'd5),
-	.CLKOUT1_PHASE(1'd0),
-	.CLKOUT2_DIVIDE(3'd5),
-	.CLKOUT2_PHASE(90000),
-	.CLKOUT3_DIVIDE(3'd6),
-	.CLKOUT3_PHASE(1'd0),
-	.CLKOUT4_DIVIDE(6'd48),
-	.CLKOUT5_PHASE(1'd0),
-	.DIVCLK_DIVIDE(1'd1),
-	.REF_JITTER1(0.01),
-	.STARTUP_WAIT("FALSE")
-) PLLE2_ADV (
-	.CLKFBIN(soc_pll_fb),
-	.CLKIN1(clk100),
-	.CLKFBOUT(soc_pll_fb),
-	.CLKOUT0(sys_clk),
-	.CLKOUT1(sys4x_clk),
-	.CLKOUT2(sys4x_dqs_clk),
-	.CLKOUT3(clk200_clk),
-	.CLKOUT4(eth_ref_clk_obuf),
-	.LOCKED(soc_pll_locked)
-);
-
-OBUF clk_eth_buf(.I(eth_ref_clk_obuf), .O(eth_ref_clk));
-
-(* LOC="IDELAYCTRL_X1Y0" *)
-IDELAYCTRL IDELAYCTRL(
-	.REFCLK(clk200_clk),
-	.RST(soc_ic_reset),
-	.RDY(idelayctl_rdy)
-);
-
-reg [31:0] mem_3[0:4095];
-reg [11:0] memadr_2;
-always @(posedge sys_clk) begin
-	if (soc_emulator_ram_we[0])
-		mem_3[soc_emulator_ram_adr][7:0] <= soc_emulator_ram_dat_w[7:0];
-	if (soc_emulator_ram_we[1])
-		mem_3[soc_emulator_ram_adr][15:8] <= soc_emulator_ram_dat_w[15:8];
-	if (soc_emulator_ram_we[2])
-		mem_3[soc_emulator_ram_adr][23:16] <= soc_emulator_ram_dat_w[23:16];
-	if (soc_emulator_ram_we[3])
-		mem_3[soc_emulator_ram_adr][31:24] <= soc_emulator_ram_dat_w[31:24];
-	memadr_2 <= soc_emulator_ram_adr;
-end
-
-assign soc_emulator_ram_dat_r = mem_3[memadr_2];
-
-wire tq;
-
-OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
-) OSERDESE2 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(1'd0),
-	.D2(1'd1),
-	.D3(1'd0),
-	.D4(1'd1),
-	.D5(1'd0),
-	.D6(1'd1),
-	.D7(1'd0),
-	.D8(1'd1),
-	.OCE(1'd1),
-	.RST(sys_rst),
-	.OQ(soc_a7ddrphy_sd_clk_se_nodelay),
-	.TQ(tq),
-	.TCE(1'd1),
-	.T1(1'b0)
-);
-
-OBUFTDS OBUFTDS_0(
-	.I(soc_a7ddrphy_sd_clk_se_nodelay),
-	.O(ddram_clk_p),
-	.OB(ddram_clk_n),
-	.T(tq)
-);
-
-OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
-) OSERDESE2_1 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(soc_a7ddrphy_dfi_p0_address[0]),
-	.D2(soc_a7ddrphy_dfi_p0_address[0]),
-	.D3(soc_a7ddrphy_dfi_p1_address[0]),
-	.D4(soc_a7ddrphy_dfi_p1_address[0]),
-	.D5(soc_a7ddrphy_dfi_p2_address[0]),
-	.D6(soc_a7ddrphy_dfi_p2_address[0]),
-	.D7(soc_a7ddrphy_dfi_p3_address[0]),
-	.D8(soc_a7ddrphy_dfi_p3_address[0]),
-	.OCE(1'd1),
-	.RST(sys_rst),
-	.OQ(ddram_a[0])
-);
-
-OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
-) OSERDESE2_2 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(soc_a7ddrphy_dfi_p0_address[1]),
-	.D2(soc_a7ddrphy_dfi_p0_address[1]),
-	.D3(soc_a7ddrphy_dfi_p1_address[1]),
-	.D4(soc_a7ddrphy_dfi_p1_address[1]),
-	.D5(soc_a7ddrphy_dfi_p2_address[1]),
-	.D6(soc_a7ddrphy_dfi_p2_address[1]),
-	.D7(soc_a7ddrphy_dfi_p3_address[1]),
-	.D8(soc_a7ddrphy_dfi_p3_address[1]),
-	.OCE(1'd1),
-	.RST(sys_rst),
-	.OQ(ddram_a[1])
-);
-
-OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
-) OSERDESE2_3 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(soc_a7ddrphy_dfi_p0_address[2]),
-	.D2(soc_a7ddrphy_dfi_p0_address[2]),
-	.D3(soc_a7ddrphy_dfi_p1_address[2]),
-	.D4(soc_a7ddrphy_dfi_p1_address[2]),
-	.D5(soc_a7ddrphy_dfi_p2_address[2]),
-	.D6(soc_a7ddrphy_dfi_p2_address[2]),
-	.D7(soc_a7ddrphy_dfi_p3_address[2]),
-	.D8(soc_a7ddrphy_dfi_p3_address[2]),
-	.OCE(1'd1),
-	.RST(sys_rst),
-	.OQ(ddram_a[2])
-);
-
-OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
-) OSERDESE2_4 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(soc_a7ddrphy_dfi_p0_address[3]),
-	.D2(soc_a7ddrphy_dfi_p0_address[3]),
-	.D3(soc_a7ddrphy_dfi_p1_address[3]),
-	.D4(soc_a7ddrphy_dfi_p1_address[3]),
-	.D5(soc_a7ddrphy_dfi_p2_address[3]),
-	.D6(soc_a7ddrphy_dfi_p2_address[3]),
-	.D7(soc_a7ddrphy_dfi_p3_address[3]),
-	.D8(soc_a7ddrphy_dfi_p3_address[3]),
-	.OCE(1'd1),
-	.RST(sys_rst),
-	.OQ(ddram_a[3])
-);
-
-OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
-) OSERDESE2_5 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(soc_a7ddrphy_dfi_p0_address[4]),
-	.D2(soc_a7ddrphy_dfi_p0_address[4]),
-	.D3(soc_a7ddrphy_dfi_p1_address[4]),
-	.D4(soc_a7ddrphy_dfi_p1_address[4]),
-	.D5(soc_a7ddrphy_dfi_p2_address[4]),
-	.D6(soc_a7ddrphy_dfi_p2_address[4]),
-	.D7(soc_a7ddrphy_dfi_p3_address[4]),
-	.D8(soc_a7ddrphy_dfi_p3_address[4]),
-	.OCE(1'd1),
-	.RST(sys_rst),
-	.OQ(ddram_a[4])
-);
-
-OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
-) OSERDESE2_6 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(soc_a7ddrphy_dfi_p0_address[5]),
-	.D2(soc_a7ddrphy_dfi_p0_address[5]),
-	.D3(soc_a7ddrphy_dfi_p1_address[5]),
-	.D4(soc_a7ddrphy_dfi_p1_address[5]),
-	.D5(soc_a7ddrphy_dfi_p2_address[5]),
-	.D6(soc_a7ddrphy_dfi_p2_address[5]),
-	.D7(soc_a7ddrphy_dfi_p3_address[5]),
-	.D8(soc_a7ddrphy_dfi_p3_address[5]),
-	.OCE(1'd1),
-	.RST(sys_rst),
-	.OQ(ddram_a[5])
-);
-
-OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
-) OSERDESE2_7 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(soc_a7ddrphy_dfi_p0_address[6]),
-	.D2(soc_a7ddrphy_dfi_p0_address[6]),
-	.D3(soc_a7ddrphy_dfi_p1_address[6]),
-	.D4(soc_a7ddrphy_dfi_p1_address[6]),
-	.D5(soc_a7ddrphy_dfi_p2_address[6]),
-	.D6(soc_a7ddrphy_dfi_p2_address[6]),
-	.D7(soc_a7ddrphy_dfi_p3_address[6]),
-	.D8(soc_a7ddrphy_dfi_p3_address[6]),
-	.OCE(1'd1),
-	.RST(sys_rst),
-	.OQ(ddram_a[6])
-);
-
-OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
-) OSERDESE2_8 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(soc_a7ddrphy_dfi_p0_address[7]),
-	.D2(soc_a7ddrphy_dfi_p0_address[7]),
-	.D3(soc_a7ddrphy_dfi_p1_address[7]),
-	.D4(soc_a7ddrphy_dfi_p1_address[7]),
-	.D5(soc_a7ddrphy_dfi_p2_address[7]),
-	.D6(soc_a7ddrphy_dfi_p2_address[7]),
-	.D7(soc_a7ddrphy_dfi_p3_address[7]),
-	.D8(soc_a7ddrphy_dfi_p3_address[7]),
-	.OCE(1'd1),
-	.RST(sys_rst),
-	.OQ(ddram_a[7])
-);
-
-OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
-) OSERDESE2_9 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(soc_a7ddrphy_dfi_p0_address[8]),
-	.D2(soc_a7ddrphy_dfi_p0_address[8]),
-	.D3(soc_a7ddrphy_dfi_p1_address[8]),
-	.D4(soc_a7ddrphy_dfi_p1_address[8]),
-	.D5(soc_a7ddrphy_dfi_p2_address[8]),
-	.D6(soc_a7ddrphy_dfi_p2_address[8]),
-	.D7(soc_a7ddrphy_dfi_p3_address[8]),
-	.D8(soc_a7ddrphy_dfi_p3_address[8]),
-	.OCE(1'd1),
-	.RST(sys_rst),
-	.OQ(ddram_a[8])
-);
-
-OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
-) OSERDESE2_10 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(soc_a7ddrphy_dfi_p0_address[9]),
-	.D2(soc_a7ddrphy_dfi_p0_address[9]),
-	.D3(soc_a7ddrphy_dfi_p1_address[9]),
-	.D4(soc_a7ddrphy_dfi_p1_address[9]),
-	.D5(soc_a7ddrphy_dfi_p2_address[9]),
-	.D6(soc_a7ddrphy_dfi_p2_address[9]),
-	.D7(soc_a7ddrphy_dfi_p3_address[9]),
-	.D8(soc_a7ddrphy_dfi_p3_address[9]),
-	.OCE(1'd1),
-	.RST(sys_rst),
-	.OQ(ddram_a[9])
-);
-
-OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
-) OSERDESE2_11 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(soc_a7ddrphy_dfi_p0_address[10]),
-	.D2(soc_a7ddrphy_dfi_p0_address[10]),
-	.D3(soc_a7ddrphy_dfi_p1_address[10]),
-	.D4(soc_a7ddrphy_dfi_p1_address[10]),
-	.D5(soc_a7ddrphy_dfi_p2_address[10]),
-	.D6(soc_a7ddrphy_dfi_p2_address[10]),
-	.D7(soc_a7ddrphy_dfi_p3_address[10]),
-	.D8(soc_a7ddrphy_dfi_p3_address[10]),
-	.OCE(1'd1),
-	.RST(sys_rst),
-	.OQ(ddram_a[10])
-);
-
-OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
-) OSERDESE2_12 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(soc_a7ddrphy_dfi_p0_address[11]),
-	.D2(soc_a7ddrphy_dfi_p0_address[11]),
-	.D3(soc_a7ddrphy_dfi_p1_address[11]),
-	.D4(soc_a7ddrphy_dfi_p1_address[11]),
-	.D5(soc_a7ddrphy_dfi_p2_address[11]),
-	.D6(soc_a7ddrphy_dfi_p2_address[11]),
-	.D7(soc_a7ddrphy_dfi_p3_address[11]),
-	.D8(soc_a7ddrphy_dfi_p3_address[11]),
-	.OCE(1'd1),
-	.RST(sys_rst),
-	.OQ(ddram_a[11])
-);
-
-OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
-) OSERDESE2_13 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(soc_a7ddrphy_dfi_p0_address[12]),
-	.D2(soc_a7ddrphy_dfi_p0_address[12]),
-	.D3(soc_a7ddrphy_dfi_p1_address[12]),
-	.D4(soc_a7ddrphy_dfi_p1_address[12]),
-	.D5(soc_a7ddrphy_dfi_p2_address[12]),
-	.D6(soc_a7ddrphy_dfi_p2_address[12]),
-	.D7(soc_a7ddrphy_dfi_p3_address[12]),
-	.D8(soc_a7ddrphy_dfi_p3_address[12]),
-	.OCE(1'd1),
-	.RST(sys_rst),
-	.OQ(ddram_a[12])
-);
-
-OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
-) OSERDESE2_14 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(soc_a7ddrphy_dfi_p0_address[13]),
-	.D2(soc_a7ddrphy_dfi_p0_address[13]),
-	.D3(soc_a7ddrphy_dfi_p1_address[13]),
-	.D4(soc_a7ddrphy_dfi_p1_address[13]),
-	.D5(soc_a7ddrphy_dfi_p2_address[13]),
-	.D6(soc_a7ddrphy_dfi_p2_address[13]),
-	.D7(soc_a7ddrphy_dfi_p3_address[13]),
-	.D8(soc_a7ddrphy_dfi_p3_address[13]),
-	.OCE(1'd1),
-	.RST(sys_rst),
-	.OQ(ddram_a[13])
-);
-
-OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
-) OSERDESE2_15 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(soc_a7ddrphy_dfi_p0_bank[0]),
-	.D2(soc_a7ddrphy_dfi_p0_bank[0]),
-	.D3(soc_a7ddrphy_dfi_p1_bank[0]),
-	.D4(soc_a7ddrphy_dfi_p1_bank[0]),
-	.D5(soc_a7ddrphy_dfi_p2_bank[0]),
-	.D6(soc_a7ddrphy_dfi_p2_bank[0]),
-	.D7(soc_a7ddrphy_dfi_p3_bank[0]),
-	.D8(soc_a7ddrphy_dfi_p3_bank[0]),
-	.OCE(1'd1),
-	.RST(sys_rst),
-	.OQ(ddram_ba[0])
-);
-
-OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
-) OSERDESE2_16 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(soc_a7ddrphy_dfi_p0_bank[1]),
-	.D2(soc_a7ddrphy_dfi_p0_bank[1]),
-	.D3(soc_a7ddrphy_dfi_p1_bank[1]),
-	.D4(soc_a7ddrphy_dfi_p1_bank[1]),
-	.D5(soc_a7ddrphy_dfi_p2_bank[1]),
-	.D6(soc_a7ddrphy_dfi_p2_bank[1]),
-	.D7(soc_a7ddrphy_dfi_p3_bank[1]),
-	.D8(soc_a7ddrphy_dfi_p3_bank[1]),
-	.OCE(1'd1),
-	.RST(sys_rst),
-	.OQ(ddram_ba[1])
-);
-
-OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
-) OSERDESE2_17 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(soc_a7ddrphy_dfi_p0_bank[2]),
-	.D2(soc_a7ddrphy_dfi_p0_bank[2]),
-	.D3(soc_a7ddrphy_dfi_p1_bank[2]),
-	.D4(soc_a7ddrphy_dfi_p1_bank[2]),
-	.D5(soc_a7ddrphy_dfi_p2_bank[2]),
-	.D6(soc_a7ddrphy_dfi_p2_bank[2]),
-	.D7(soc_a7ddrphy_dfi_p3_bank[2]),
-	.D8(soc_a7ddrphy_dfi_p3_bank[2]),
-	.OCE(1'd1),
-	.RST(sys_rst),
-	.OQ(ddram_ba[2])
-);
-
-OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
-) OSERDESE2_18 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(soc_a7ddrphy_dfi_p0_ras_n),
-	.D2(soc_a7ddrphy_dfi_p0_ras_n),
-	.D3(soc_a7ddrphy_dfi_p1_ras_n),
-	.D4(soc_a7ddrphy_dfi_p1_ras_n),
-	.D5(soc_a7ddrphy_dfi_p2_ras_n),
-	.D6(soc_a7ddrphy_dfi_p2_ras_n),
-	.D7(soc_a7ddrphy_dfi_p3_ras_n),
-	.D8(soc_a7ddrphy_dfi_p3_ras_n),
-	.OCE(1'd1),
-	.RST(sys_rst),
-	.OQ(ddram_ras_n)
-);
-
-OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
-) OSERDESE2_19 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(soc_a7ddrphy_dfi_p0_cas_n),
-	.D2(soc_a7ddrphy_dfi_p0_cas_n),
-	.D3(soc_a7ddrphy_dfi_p1_cas_n),
-	.D4(soc_a7ddrphy_dfi_p1_cas_n),
-	.D5(soc_a7ddrphy_dfi_p2_cas_n),
-	.D6(soc_a7ddrphy_dfi_p2_cas_n),
-	.D7(soc_a7ddrphy_dfi_p3_cas_n),
-	.D8(soc_a7ddrphy_dfi_p3_cas_n),
-	.OCE(1'd1),
-	.RST(sys_rst),
-	.OQ(ddram_cas_n)
-);
-
-OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
-) OSERDESE2_20 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(soc_a7ddrphy_dfi_p0_we_n),
-	.D2(soc_a7ddrphy_dfi_p0_we_n),
-	.D3(soc_a7ddrphy_dfi_p1_we_n),
-	.D4(soc_a7ddrphy_dfi_p1_we_n),
-	.D5(soc_a7ddrphy_dfi_p2_we_n),
-	.D6(soc_a7ddrphy_dfi_p2_we_n),
-	.D7(soc_a7ddrphy_dfi_p3_we_n),
-	.D8(soc_a7ddrphy_dfi_p3_we_n),
-	.OCE(1'd1),
-	.RST(sys_rst),
-	.OQ(ddram_we_n)
-);
-
-OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
-) OSERDESE2_21 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(soc_a7ddrphy_dfi_p0_cke),
-	.D2(soc_a7ddrphy_dfi_p0_cke),
-	.D3(soc_a7ddrphy_dfi_p1_cke),
-	.D4(soc_a7ddrphy_dfi_p1_cke),
-	.D5(soc_a7ddrphy_dfi_p2_cke),
-	.D6(soc_a7ddrphy_dfi_p2_cke),
-	.D7(soc_a7ddrphy_dfi_p3_cke),
-	.D8(soc_a7ddrphy_dfi_p3_cke),
-	.OCE(1'd1),
-	.RST(sys_rst),
-	.OQ(ddram_cke)
-);
-
-OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
-) OSERDESE2_22 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(soc_a7ddrphy_dfi_p0_odt),
-	.D2(soc_a7ddrphy_dfi_p0_odt),
-	.D3(soc_a7ddrphy_dfi_p1_odt),
-	.D4(soc_a7ddrphy_dfi_p1_odt),
-	.D5(soc_a7ddrphy_dfi_p2_odt),
-	.D6(soc_a7ddrphy_dfi_p2_odt),
-	.D7(soc_a7ddrphy_dfi_p3_odt),
-	.D8(soc_a7ddrphy_dfi_p3_odt),
-	.OCE(1'd1),
-	.RST(sys_rst),
-	.OQ(ddram_odt)
-);
-
-OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
-) OSERDESE2_23 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(soc_a7ddrphy_dfi_p0_reset_n),
-	.D2(soc_a7ddrphy_dfi_p0_reset_n),
-	.D3(soc_a7ddrphy_dfi_p1_reset_n),
-	.D4(soc_a7ddrphy_dfi_p1_reset_n),
-	.D5(soc_a7ddrphy_dfi_p2_reset_n),
-	.D6(soc_a7ddrphy_dfi_p2_reset_n),
-	.D7(soc_a7ddrphy_dfi_p3_reset_n),
-	.D8(soc_a7ddrphy_dfi_p3_reset_n),
-	.OCE(1'd1),
-	.RST(sys_rst),
-	.OQ(ddram_reset_n)
-);
-
-OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
-) OSERDESE2_24 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(soc_a7ddrphy_dfi_p0_cs_n),
-	.D2(soc_a7ddrphy_dfi_p0_cs_n),
-	.D3(soc_a7ddrphy_dfi_p1_cs_n),
-	.D4(soc_a7ddrphy_dfi_p1_cs_n),
-	.D5(soc_a7ddrphy_dfi_p2_cs_n),
-	.D6(soc_a7ddrphy_dfi_p2_cs_n),
-	.D7(soc_a7ddrphy_dfi_p3_cs_n),
-	.D8(soc_a7ddrphy_dfi_p3_cs_n),
-	.OCE(1'd1),
-	.RST(sys_rst),
-	.OQ(ddram_cs_n)
-);
-
-OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
-) OSERDESE2_25 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(soc_a7ddrphy_dfi_p0_wrdata_mask[0]),
-	.D2(soc_a7ddrphy_dfi_p0_wrdata_mask[2]),
-	.D3(soc_a7ddrphy_dfi_p1_wrdata_mask[0]),
-	.D4(soc_a7ddrphy_dfi_p1_wrdata_mask[2]),
-	.D5(soc_a7ddrphy_dfi_p2_wrdata_mask[0]),
-	.D6(soc_a7ddrphy_dfi_p2_wrdata_mask[2]),
-	.D7(soc_a7ddrphy_dfi_p3_wrdata_mask[0]),
-	.D8(soc_a7ddrphy_dfi_p3_wrdata_mask[2]),
-	.OCE(1'd1),
-	.RST(sys_rst),
-	.OQ(ddram_dm[0])
-);
-
-OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
-) OSERDESE2_26 (
-	.CLK(sys4x_dqs_clk),
-	.CLKDIV(sys_clk),
-	.D1(soc_a7ddrphy_dqs_serdes_pattern[0]),
-	.D2(soc_a7ddrphy_dqs_serdes_pattern[1]),
-	.D3(soc_a7ddrphy_dqs_serdes_pattern[2]),
-	.D4(soc_a7ddrphy_dqs_serdes_pattern[3]),
-	.D5(soc_a7ddrphy_dqs_serdes_pattern[4]),
-	.D6(soc_a7ddrphy_dqs_serdes_pattern[5]),
-	.D7(soc_a7ddrphy_dqs_serdes_pattern[6]),
-	.D8(soc_a7ddrphy_dqs_serdes_pattern[7]),
-	.OCE(1'd1),
-	.RST(sys_rst),
-	.T1((~soc_a7ddrphy_oe_dqs)),
-	.TCE(1'd1),
-	.OFB(soc_a7ddrphy0),
-	.OQ(soc_a7ddrphy_dqs_nodelay0),
-	.TQ(soc_a7ddrphy_dqs_t0)
-);
-
-OBUFTDS OBUFTDS(
-	.I(soc_a7ddrphy_dqs_nodelay0),
-	.T(soc_a7ddrphy_dqs_t0),
-	.O(ddram_dqs_p[0]),
-	.OB(ddram_dqs_n[0])
-);
-
-OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
-) OSERDESE2_27 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(soc_a7ddrphy_dfi_p0_wrdata_mask[1]),
-	.D2(soc_a7ddrphy_dfi_p0_wrdata_mask[3]),
-	.D3(soc_a7ddrphy_dfi_p1_wrdata_mask[1]),
-	.D4(soc_a7ddrphy_dfi_p1_wrdata_mask[3]),
-	.D5(soc_a7ddrphy_dfi_p2_wrdata_mask[1]),
-	.D6(soc_a7ddrphy_dfi_p2_wrdata_mask[3]),
-	.D7(soc_a7ddrphy_dfi_p3_wrdata_mask[1]),
-	.D8(soc_a7ddrphy_dfi_p3_wrdata_mask[3]),
-	.OCE(1'd1),
-	.RST(sys_rst),
-	.OQ(ddram_dm[1])
-);
-
-OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
-) OSERDESE2_28 (
-	.CLK(sys4x_dqs_clk),
-	.CLKDIV(sys_clk),
-	.D1(soc_a7ddrphy_dqs_serdes_pattern[0]),
-	.D2(soc_a7ddrphy_dqs_serdes_pattern[1]),
-	.D3(soc_a7ddrphy_dqs_serdes_pattern[2]),
-	.D4(soc_a7ddrphy_dqs_serdes_pattern[3]),
-	.D5(soc_a7ddrphy_dqs_serdes_pattern[4]),
-	.D6(soc_a7ddrphy_dqs_serdes_pattern[5]),
-	.D7(soc_a7ddrphy_dqs_serdes_pattern[6]),
-	.D8(soc_a7ddrphy_dqs_serdes_pattern[7]),
-	.OCE(1'd1),
-	.RST(sys_rst),
-	.T1((~soc_a7ddrphy_oe_dqs)),
-	.TCE(1'd1),
-	.OFB(soc_a7ddrphy1),
-	.OQ(soc_a7ddrphy_dqs_nodelay1),
-	.TQ(soc_a7ddrphy_dqs_t1)
-);
-
-OBUFTDS OBUFTDS_1(
-	.I(soc_a7ddrphy_dqs_nodelay1),
-	.T(soc_a7ddrphy_dqs_t1),
-	.O(ddram_dqs_p[1]),
-	.OB(ddram_dqs_n[1])
-);
-
-OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
-) OSERDESE2_29 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(soc_a7ddrphy_dfi_p0_wrdata[0]),
-	.D2(soc_a7ddrphy_dfi_p0_wrdata[16]),
-	.D3(soc_a7ddrphy_dfi_p1_wrdata[0]),
-	.D4(soc_a7ddrphy_dfi_p1_wrdata[16]),
-	.D5(soc_a7ddrphy_dfi_p2_wrdata[0]),
-	.D6(soc_a7ddrphy_dfi_p2_wrdata[16]),
-	.D7(soc_a7ddrphy_dfi_p3_wrdata[0]),
-	.D8(soc_a7ddrphy_dfi_p3_wrdata[16]),
-	.OCE(1'd1),
-	.RST(sys_rst),
-	.T1((~soc_a7ddrphy_oe_dq)),
-	.TCE(1'd1),
-	.OQ(soc_a7ddrphy_dq_o_nodelay0),
-	.TQ(soc_a7ddrphy_dq_t0)
-);
-
-ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
-) ISERDESE2 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.DDLY(soc_a7ddrphy_dq_i_delayed0),
-	.RST(sys_rst),
-	.Q1(soc_a7ddrphy_dq_i_data0[7]),
-	.Q2(soc_a7ddrphy_dq_i_data0[6]),
-	.Q3(soc_a7ddrphy_dq_i_data0[5]),
-	.Q4(soc_a7ddrphy_dq_i_data0[4]),
-	.Q5(soc_a7ddrphy_dq_i_data0[3]),
-	.Q6(soc_a7ddrphy_dq_i_data0[2]),
-	.Q7(soc_a7ddrphy_dq_i_data0[1]),
-	.Q8(soc_a7ddrphy_dq_i_data0[0])
-);
-
-IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
-) IDELAYE2 (
-	.C(sys_clk),
-	.CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(soc_a7ddrphy_dq_i_nodelay0),
-	.INC(1'd1),
-	.LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(soc_a7ddrphy_dq_i_delayed0)
-);
-
-IOBUF IOBUF(
-	.I(soc_a7ddrphy_dq_o_nodelay0),
-	.T(soc_a7ddrphy_dq_t0),
-	.IO(ddram_dq[0]),
-	.O(soc_a7ddrphy_dq_i_nodelay0)
-);
-
-OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
-) OSERDESE2_30 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(soc_a7ddrphy_dfi_p0_wrdata[1]),
-	.D2(soc_a7ddrphy_dfi_p0_wrdata[17]),
-	.D3(soc_a7ddrphy_dfi_p1_wrdata[1]),
-	.D4(soc_a7ddrphy_dfi_p1_wrdata[17]),
-	.D5(soc_a7ddrphy_dfi_p2_wrdata[1]),
-	.D6(soc_a7ddrphy_dfi_p2_wrdata[17]),
-	.D7(soc_a7ddrphy_dfi_p3_wrdata[1]),
-	.D8(soc_a7ddrphy_dfi_p3_wrdata[17]),
-	.OCE(1'd1),
-	.RST(sys_rst),
-	.T1((~soc_a7ddrphy_oe_dq)),
-	.TCE(1'd1),
-	.OQ(soc_a7ddrphy_dq_o_nodelay1),
-	.TQ(soc_a7ddrphy_dq_t1)
-);
-
-ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
-) ISERDESE2_1 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.DDLY(soc_a7ddrphy_dq_i_delayed1),
-	.RST(sys_rst),
-	.Q1(soc_a7ddrphy_dq_i_data1[7]),
-	.Q2(soc_a7ddrphy_dq_i_data1[6]),
-	.Q3(soc_a7ddrphy_dq_i_data1[5]),
-	.Q4(soc_a7ddrphy_dq_i_data1[4]),
-	.Q5(soc_a7ddrphy_dq_i_data1[3]),
-	.Q6(soc_a7ddrphy_dq_i_data1[2]),
-	.Q7(soc_a7ddrphy_dq_i_data1[1]),
-	.Q8(soc_a7ddrphy_dq_i_data1[0])
-);
-
-IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
-) IDELAYE2_1 (
-	.C(sys_clk),
-	.CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(soc_a7ddrphy_dq_i_nodelay1),
-	.INC(1'd1),
-	.LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(soc_a7ddrphy_dq_i_delayed1)
-);
-
-IOBUF IOBUF_1(
-	.I(soc_a7ddrphy_dq_o_nodelay1),
-	.T(soc_a7ddrphy_dq_t1),
-	.IO(ddram_dq[1]),
-	.O(soc_a7ddrphy_dq_i_nodelay1)
-);
-
-OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
-) OSERDESE2_31 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(soc_a7ddrphy_dfi_p0_wrdata[2]),
-	.D2(soc_a7ddrphy_dfi_p0_wrdata[18]),
-	.D3(soc_a7ddrphy_dfi_p1_wrdata[2]),
-	.D4(soc_a7ddrphy_dfi_p1_wrdata[18]),
-	.D5(soc_a7ddrphy_dfi_p2_wrdata[2]),
-	.D6(soc_a7ddrphy_dfi_p2_wrdata[18]),
-	.D7(soc_a7ddrphy_dfi_p3_wrdata[2]),
-	.D8(soc_a7ddrphy_dfi_p3_wrdata[18]),
-	.OCE(1'd1),
-	.RST(sys_rst),
-	.T1((~soc_a7ddrphy_oe_dq)),
-	.TCE(1'd1),
-	.OQ(soc_a7ddrphy_dq_o_nodelay2),
-	.TQ(soc_a7ddrphy_dq_t2)
-);
-
-ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
-) ISERDESE2_2 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.DDLY(soc_a7ddrphy_dq_i_delayed2),
-	.RST(sys_rst),
-	.Q1(soc_a7ddrphy_dq_i_data2[7]),
-	.Q2(soc_a7ddrphy_dq_i_data2[6]),
-	.Q3(soc_a7ddrphy_dq_i_data2[5]),
-	.Q4(soc_a7ddrphy_dq_i_data2[4]),
-	.Q5(soc_a7ddrphy_dq_i_data2[3]),
-	.Q6(soc_a7ddrphy_dq_i_data2[2]),
-	.Q7(soc_a7ddrphy_dq_i_data2[1]),
-	.Q8(soc_a7ddrphy_dq_i_data2[0])
-);
-
-IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
-) IDELAYE2_2 (
-	.C(sys_clk),
-	.CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(soc_a7ddrphy_dq_i_nodelay2),
-	.INC(1'd1),
-	.LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(soc_a7ddrphy_dq_i_delayed2)
-);
-
-IOBUF IOBUF_2(
-	.I(soc_a7ddrphy_dq_o_nodelay2),
-	.T(soc_a7ddrphy_dq_t2),
-	.IO(ddram_dq[2]),
-	.O(soc_a7ddrphy_dq_i_nodelay2)
-);
-
-OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
-) OSERDESE2_32 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(soc_a7ddrphy_dfi_p0_wrdata[3]),
-	.D2(soc_a7ddrphy_dfi_p0_wrdata[19]),
-	.D3(soc_a7ddrphy_dfi_p1_wrdata[3]),
-	.D4(soc_a7ddrphy_dfi_p1_wrdata[19]),
-	.D5(soc_a7ddrphy_dfi_p2_wrdata[3]),
-	.D6(soc_a7ddrphy_dfi_p2_wrdata[19]),
-	.D7(soc_a7ddrphy_dfi_p3_wrdata[3]),
-	.D8(soc_a7ddrphy_dfi_p3_wrdata[19]),
-	.OCE(1'd1),
-	.RST(sys_rst),
-	.T1((~soc_a7ddrphy_oe_dq)),
-	.TCE(1'd1),
-	.OQ(soc_a7ddrphy_dq_o_nodelay3),
-	.TQ(soc_a7ddrphy_dq_t3)
-);
-
-ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
-) ISERDESE2_3 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.DDLY(soc_a7ddrphy_dq_i_delayed3),
-	.RST(sys_rst),
-	.Q1(soc_a7ddrphy_dq_i_data3[7]),
-	.Q2(soc_a7ddrphy_dq_i_data3[6]),
-	.Q3(soc_a7ddrphy_dq_i_data3[5]),
-	.Q4(soc_a7ddrphy_dq_i_data3[4]),
-	.Q5(soc_a7ddrphy_dq_i_data3[3]),
-	.Q6(soc_a7ddrphy_dq_i_data3[2]),
-	.Q7(soc_a7ddrphy_dq_i_data3[1]),
-	.Q8(soc_a7ddrphy_dq_i_data3[0])
-);
-
-IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
-) IDELAYE2_3 (
-	.C(sys_clk),
-	.CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(soc_a7ddrphy_dq_i_nodelay3),
-	.INC(1'd1),
-	.LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(soc_a7ddrphy_dq_i_delayed3)
-);
-
-IOBUF IOBUF_3(
-	.I(soc_a7ddrphy_dq_o_nodelay3),
-	.T(soc_a7ddrphy_dq_t3),
-	.IO(ddram_dq[3]),
-	.O(soc_a7ddrphy_dq_i_nodelay3)
-);
-
-OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
-) OSERDESE2_33 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(soc_a7ddrphy_dfi_p0_wrdata[4]),
-	.D2(soc_a7ddrphy_dfi_p0_wrdata[20]),
-	.D3(soc_a7ddrphy_dfi_p1_wrdata[4]),
-	.D4(soc_a7ddrphy_dfi_p1_wrdata[20]),
-	.D5(soc_a7ddrphy_dfi_p2_wrdata[4]),
-	.D6(soc_a7ddrphy_dfi_p2_wrdata[20]),
-	.D7(soc_a7ddrphy_dfi_p3_wrdata[4]),
-	.D8(soc_a7ddrphy_dfi_p3_wrdata[20]),
-	.OCE(1'd1),
-	.RST(sys_rst),
-	.T1((~soc_a7ddrphy_oe_dq)),
-	.TCE(1'd1),
-	.OQ(soc_a7ddrphy_dq_o_nodelay4),
-	.TQ(soc_a7ddrphy_dq_t4)
-);
-
-ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
-) ISERDESE2_4 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.DDLY(soc_a7ddrphy_dq_i_delayed4),
-	.RST(sys_rst),
-	.Q1(soc_a7ddrphy_dq_i_data4[7]),
-	.Q2(soc_a7ddrphy_dq_i_data4[6]),
-	.Q3(soc_a7ddrphy_dq_i_data4[5]),
-	.Q4(soc_a7ddrphy_dq_i_data4[4]),
-	.Q5(soc_a7ddrphy_dq_i_data4[3]),
-	.Q6(soc_a7ddrphy_dq_i_data4[2]),
-	.Q7(soc_a7ddrphy_dq_i_data4[1]),
-	.Q8(soc_a7ddrphy_dq_i_data4[0])
-);
-
-IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
-) IDELAYE2_4 (
-	.C(sys_clk),
-	.CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(soc_a7ddrphy_dq_i_nodelay4),
-	.INC(1'd1),
-	.LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(soc_a7ddrphy_dq_i_delayed4)
-);
-
-IOBUF IOBUF_4(
-	.I(soc_a7ddrphy_dq_o_nodelay4),
-	.T(soc_a7ddrphy_dq_t4),
-	.IO(ddram_dq[4]),
-	.O(soc_a7ddrphy_dq_i_nodelay4)
-);
-
-OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
-) OSERDESE2_34 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(soc_a7ddrphy_dfi_p0_wrdata[5]),
-	.D2(soc_a7ddrphy_dfi_p0_wrdata[21]),
-	.D3(soc_a7ddrphy_dfi_p1_wrdata[5]),
-	.D4(soc_a7ddrphy_dfi_p1_wrdata[21]),
-	.D5(soc_a7ddrphy_dfi_p2_wrdata[5]),
-	.D6(soc_a7ddrphy_dfi_p2_wrdata[21]),
-	.D7(soc_a7ddrphy_dfi_p3_wrdata[5]),
-	.D8(soc_a7ddrphy_dfi_p3_wrdata[21]),
-	.OCE(1'd1),
-	.RST(sys_rst),
-	.T1((~soc_a7ddrphy_oe_dq)),
-	.TCE(1'd1),
-	.OQ(soc_a7ddrphy_dq_o_nodelay5),
-	.TQ(soc_a7ddrphy_dq_t5)
-);
-
-ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
-) ISERDESE2_5 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.DDLY(soc_a7ddrphy_dq_i_delayed5),
-	.RST(sys_rst),
-	.Q1(soc_a7ddrphy_dq_i_data5[7]),
-	.Q2(soc_a7ddrphy_dq_i_data5[6]),
-	.Q3(soc_a7ddrphy_dq_i_data5[5]),
-	.Q4(soc_a7ddrphy_dq_i_data5[4]),
-	.Q5(soc_a7ddrphy_dq_i_data5[3]),
-	.Q6(soc_a7ddrphy_dq_i_data5[2]),
-	.Q7(soc_a7ddrphy_dq_i_data5[1]),
-	.Q8(soc_a7ddrphy_dq_i_data5[0])
-);
-
-IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
-) IDELAYE2_5 (
-	.C(sys_clk),
-	.CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(soc_a7ddrphy_dq_i_nodelay5),
-	.INC(1'd1),
-	.LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(soc_a7ddrphy_dq_i_delayed5)
-);
-
-IOBUF IOBUF_5(
-	.I(soc_a7ddrphy_dq_o_nodelay5),
-	.T(soc_a7ddrphy_dq_t5),
-	.IO(ddram_dq[5]),
-	.O(soc_a7ddrphy_dq_i_nodelay5)
-);
-
-OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
-) OSERDESE2_35 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(soc_a7ddrphy_dfi_p0_wrdata[6]),
-	.D2(soc_a7ddrphy_dfi_p0_wrdata[22]),
-	.D3(soc_a7ddrphy_dfi_p1_wrdata[6]),
-	.D4(soc_a7ddrphy_dfi_p1_wrdata[22]),
-	.D5(soc_a7ddrphy_dfi_p2_wrdata[6]),
-	.D6(soc_a7ddrphy_dfi_p2_wrdata[22]),
-	.D7(soc_a7ddrphy_dfi_p3_wrdata[6]),
-	.D8(soc_a7ddrphy_dfi_p3_wrdata[22]),
-	.OCE(1'd1),
-	.RST(sys_rst),
-	.T1((~soc_a7ddrphy_oe_dq)),
-	.TCE(1'd1),
-	.OQ(soc_a7ddrphy_dq_o_nodelay6),
-	.TQ(soc_a7ddrphy_dq_t6)
-);
-
-ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
-) ISERDESE2_6 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.DDLY(soc_a7ddrphy_dq_i_delayed6),
-	.RST(sys_rst),
-	.Q1(soc_a7ddrphy_dq_i_data6[7]),
-	.Q2(soc_a7ddrphy_dq_i_data6[6]),
-	.Q3(soc_a7ddrphy_dq_i_data6[5]),
-	.Q4(soc_a7ddrphy_dq_i_data6[4]),
-	.Q5(soc_a7ddrphy_dq_i_data6[3]),
-	.Q6(soc_a7ddrphy_dq_i_data6[2]),
-	.Q7(soc_a7ddrphy_dq_i_data6[1]),
-	.Q8(soc_a7ddrphy_dq_i_data6[0])
-);
-
-IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
-) IDELAYE2_6 (
-	.C(sys_clk),
-	.CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(soc_a7ddrphy_dq_i_nodelay6),
-	.INC(1'd1),
-	.LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(soc_a7ddrphy_dq_i_delayed6)
-);
-
-IOBUF IOBUF_6(
-	.I(soc_a7ddrphy_dq_o_nodelay6),
-	.T(soc_a7ddrphy_dq_t6),
-	.IO(ddram_dq[6]),
-	.O(soc_a7ddrphy_dq_i_nodelay6)
-);
-
-OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
-) OSERDESE2_36 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(soc_a7ddrphy_dfi_p0_wrdata[7]),
-	.D2(soc_a7ddrphy_dfi_p0_wrdata[23]),
-	.D3(soc_a7ddrphy_dfi_p1_wrdata[7]),
-	.D4(soc_a7ddrphy_dfi_p1_wrdata[23]),
-	.D5(soc_a7ddrphy_dfi_p2_wrdata[7]),
-	.D6(soc_a7ddrphy_dfi_p2_wrdata[23]),
-	.D7(soc_a7ddrphy_dfi_p3_wrdata[7]),
-	.D8(soc_a7ddrphy_dfi_p3_wrdata[23]),
-	.OCE(1'd1),
-	.RST(sys_rst),
-	.T1((~soc_a7ddrphy_oe_dq)),
-	.TCE(1'd1),
-	.OQ(soc_a7ddrphy_dq_o_nodelay7),
-	.TQ(soc_a7ddrphy_dq_t7)
-);
-
-ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
-) ISERDESE2_7 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.DDLY(soc_a7ddrphy_dq_i_delayed7),
-	.RST(sys_rst),
-	.Q1(soc_a7ddrphy_dq_i_data7[7]),
-	.Q2(soc_a7ddrphy_dq_i_data7[6]),
-	.Q3(soc_a7ddrphy_dq_i_data7[5]),
-	.Q4(soc_a7ddrphy_dq_i_data7[4]),
-	.Q5(soc_a7ddrphy_dq_i_data7[3]),
-	.Q6(soc_a7ddrphy_dq_i_data7[2]),
-	.Q7(soc_a7ddrphy_dq_i_data7[1]),
-	.Q8(soc_a7ddrphy_dq_i_data7[0])
-);
-
-IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
-) IDELAYE2_7 (
-	.C(sys_clk),
-	.CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(soc_a7ddrphy_dq_i_nodelay7),
-	.INC(1'd1),
-	.LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(soc_a7ddrphy_dq_i_delayed7)
-);
-
-IOBUF IOBUF_7(
-	.I(soc_a7ddrphy_dq_o_nodelay7),
-	.T(soc_a7ddrphy_dq_t7),
-	.IO(ddram_dq[7]),
-	.O(soc_a7ddrphy_dq_i_nodelay7)
-);
-
-OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
-) OSERDESE2_37 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(soc_a7ddrphy_dfi_p0_wrdata[8]),
-	.D2(soc_a7ddrphy_dfi_p0_wrdata[24]),
-	.D3(soc_a7ddrphy_dfi_p1_wrdata[8]),
-	.D4(soc_a7ddrphy_dfi_p1_wrdata[24]),
-	.D5(soc_a7ddrphy_dfi_p2_wrdata[8]),
-	.D6(soc_a7ddrphy_dfi_p2_wrdata[24]),
-	.D7(soc_a7ddrphy_dfi_p3_wrdata[8]),
-	.D8(soc_a7ddrphy_dfi_p3_wrdata[24]),
-	.OCE(1'd1),
-	.RST(sys_rst),
-	.T1((~soc_a7ddrphy_oe_dq)),
-	.TCE(1'd1),
-	.OQ(soc_a7ddrphy_dq_o_nodelay8),
-	.TQ(soc_a7ddrphy_dq_t8)
-);
-
-ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
-) ISERDESE2_8 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.DDLY(soc_a7ddrphy_dq_i_delayed8),
-	.RST(sys_rst),
-	.Q1(soc_a7ddrphy_dq_i_data8[7]),
-	.Q2(soc_a7ddrphy_dq_i_data8[6]),
-	.Q3(soc_a7ddrphy_dq_i_data8[5]),
-	.Q4(soc_a7ddrphy_dq_i_data8[4]),
-	.Q5(soc_a7ddrphy_dq_i_data8[3]),
-	.Q6(soc_a7ddrphy_dq_i_data8[2]),
-	.Q7(soc_a7ddrphy_dq_i_data8[1]),
-	.Q8(soc_a7ddrphy_dq_i_data8[0])
-);
-
-IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
-) IDELAYE2_8 (
-	.C(sys_clk),
-	.CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(soc_a7ddrphy_dq_i_nodelay8),
-	.INC(1'd1),
-	.LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(soc_a7ddrphy_dq_i_delayed8)
-);
-
-IOBUF IOBUF_8(
-	.I(soc_a7ddrphy_dq_o_nodelay8),
-	.T(soc_a7ddrphy_dq_t8),
-	.IO(ddram_dq[8]),
-	.O(soc_a7ddrphy_dq_i_nodelay8)
-);
-
-OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
-) OSERDESE2_38 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(soc_a7ddrphy_dfi_p0_wrdata[9]),
-	.D2(soc_a7ddrphy_dfi_p0_wrdata[25]),
-	.D3(soc_a7ddrphy_dfi_p1_wrdata[9]),
-	.D4(soc_a7ddrphy_dfi_p1_wrdata[25]),
-	.D5(soc_a7ddrphy_dfi_p2_wrdata[9]),
-	.D6(soc_a7ddrphy_dfi_p2_wrdata[25]),
-	.D7(soc_a7ddrphy_dfi_p3_wrdata[9]),
-	.D8(soc_a7ddrphy_dfi_p3_wrdata[25]),
-	.OCE(1'd1),
-	.RST(sys_rst),
-	.T1((~soc_a7ddrphy_oe_dq)),
-	.TCE(1'd1),
-	.OQ(soc_a7ddrphy_dq_o_nodelay9),
-	.TQ(soc_a7ddrphy_dq_t9)
-);
-
-ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
-) ISERDESE2_9 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.DDLY(soc_a7ddrphy_dq_i_delayed9),
-	.RST(sys_rst),
-	.Q1(soc_a7ddrphy_dq_i_data9[7]),
-	.Q2(soc_a7ddrphy_dq_i_data9[6]),
-	.Q3(soc_a7ddrphy_dq_i_data9[5]),
-	.Q4(soc_a7ddrphy_dq_i_data9[4]),
-	.Q5(soc_a7ddrphy_dq_i_data9[3]),
-	.Q6(soc_a7ddrphy_dq_i_data9[2]),
-	.Q7(soc_a7ddrphy_dq_i_data9[1]),
-	.Q8(soc_a7ddrphy_dq_i_data9[0])
-);
-
-IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
-) IDELAYE2_9 (
-	.C(sys_clk),
-	.CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(soc_a7ddrphy_dq_i_nodelay9),
-	.INC(1'd1),
-	.LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(soc_a7ddrphy_dq_i_delayed9)
-);
-
-IOBUF IOBUF_9(
-	.I(soc_a7ddrphy_dq_o_nodelay9),
-	.T(soc_a7ddrphy_dq_t9),
-	.IO(ddram_dq[9]),
-	.O(soc_a7ddrphy_dq_i_nodelay9)
-);
-
-OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
-) OSERDESE2_39 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(soc_a7ddrphy_dfi_p0_wrdata[10]),
-	.D2(soc_a7ddrphy_dfi_p0_wrdata[26]),
-	.D3(soc_a7ddrphy_dfi_p1_wrdata[10]),
-	.D4(soc_a7ddrphy_dfi_p1_wrdata[26]),
-	.D5(soc_a7ddrphy_dfi_p2_wrdata[10]),
-	.D6(soc_a7ddrphy_dfi_p2_wrdata[26]),
-	.D7(soc_a7ddrphy_dfi_p3_wrdata[10]),
-	.D8(soc_a7ddrphy_dfi_p3_wrdata[26]),
-	.OCE(1'd1),
-	.RST(sys_rst),
-	.T1((~soc_a7ddrphy_oe_dq)),
-	.TCE(1'd1),
-	.OQ(soc_a7ddrphy_dq_o_nodelay10),
-	.TQ(soc_a7ddrphy_dq_t10)
-);
-
-ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
-) ISERDESE2_10 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.DDLY(soc_a7ddrphy_dq_i_delayed10),
-	.RST(sys_rst),
-	.Q1(soc_a7ddrphy_dq_i_data10[7]),
-	.Q2(soc_a7ddrphy_dq_i_data10[6]),
-	.Q3(soc_a7ddrphy_dq_i_data10[5]),
-	.Q4(soc_a7ddrphy_dq_i_data10[4]),
-	.Q5(soc_a7ddrphy_dq_i_data10[3]),
-	.Q6(soc_a7ddrphy_dq_i_data10[2]),
-	.Q7(soc_a7ddrphy_dq_i_data10[1]),
-	.Q8(soc_a7ddrphy_dq_i_data10[0])
-);
-
-IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
-) IDELAYE2_10 (
-	.C(sys_clk),
-	.CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(soc_a7ddrphy_dq_i_nodelay10),
-	.INC(1'd1),
-	.LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(soc_a7ddrphy_dq_i_delayed10)
-);
-
-IOBUF IOBUF_10(
-	.I(soc_a7ddrphy_dq_o_nodelay10),
-	.T(soc_a7ddrphy_dq_t10),
-	.IO(ddram_dq[10]),
-	.O(soc_a7ddrphy_dq_i_nodelay10)
-);
-
-OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
-) OSERDESE2_40 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(soc_a7ddrphy_dfi_p0_wrdata[11]),
-	.D2(soc_a7ddrphy_dfi_p0_wrdata[27]),
-	.D3(soc_a7ddrphy_dfi_p1_wrdata[11]),
-	.D4(soc_a7ddrphy_dfi_p1_wrdata[27]),
-	.D5(soc_a7ddrphy_dfi_p2_wrdata[11]),
-	.D6(soc_a7ddrphy_dfi_p2_wrdata[27]),
-	.D7(soc_a7ddrphy_dfi_p3_wrdata[11]),
-	.D8(soc_a7ddrphy_dfi_p3_wrdata[27]),
-	.OCE(1'd1),
-	.RST(sys_rst),
-	.T1((~soc_a7ddrphy_oe_dq)),
-	.TCE(1'd1),
-	.OQ(soc_a7ddrphy_dq_o_nodelay11),
-	.TQ(soc_a7ddrphy_dq_t11)
-);
-
-ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
-) ISERDESE2_11 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.DDLY(soc_a7ddrphy_dq_i_delayed11),
-	.RST(sys_rst),
-	.Q1(soc_a7ddrphy_dq_i_data11[7]),
-	.Q2(soc_a7ddrphy_dq_i_data11[6]),
-	.Q3(soc_a7ddrphy_dq_i_data11[5]),
-	.Q4(soc_a7ddrphy_dq_i_data11[4]),
-	.Q5(soc_a7ddrphy_dq_i_data11[3]),
-	.Q6(soc_a7ddrphy_dq_i_data11[2]),
-	.Q7(soc_a7ddrphy_dq_i_data11[1]),
-	.Q8(soc_a7ddrphy_dq_i_data11[0])
-);
-
-IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
-) IDELAYE2_11 (
-	.C(sys_clk),
-	.CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(soc_a7ddrphy_dq_i_nodelay11),
-	.INC(1'd1),
-	.LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(soc_a7ddrphy_dq_i_delayed11)
-);
-
-IOBUF IOBUF_11(
-	.I(soc_a7ddrphy_dq_o_nodelay11),
-	.T(soc_a7ddrphy_dq_t11),
-	.IO(ddram_dq[11]),
-	.O(soc_a7ddrphy_dq_i_nodelay11)
-);
-
-OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
-) OSERDESE2_41 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(soc_a7ddrphy_dfi_p0_wrdata[12]),
-	.D2(soc_a7ddrphy_dfi_p0_wrdata[28]),
-	.D3(soc_a7ddrphy_dfi_p1_wrdata[12]),
-	.D4(soc_a7ddrphy_dfi_p1_wrdata[28]),
-	.D5(soc_a7ddrphy_dfi_p2_wrdata[12]),
-	.D6(soc_a7ddrphy_dfi_p2_wrdata[28]),
-	.D7(soc_a7ddrphy_dfi_p3_wrdata[12]),
-	.D8(soc_a7ddrphy_dfi_p3_wrdata[28]),
-	.OCE(1'd1),
-	.RST(sys_rst),
-	.T1((~soc_a7ddrphy_oe_dq)),
-	.TCE(1'd1),
-	.OQ(soc_a7ddrphy_dq_o_nodelay12),
-	.TQ(soc_a7ddrphy_dq_t12)
-);
-
-ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
-) ISERDESE2_12 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.DDLY(soc_a7ddrphy_dq_i_delayed12),
-	.RST(sys_rst),
-	.Q1(soc_a7ddrphy_dq_i_data12[7]),
-	.Q2(soc_a7ddrphy_dq_i_data12[6]),
-	.Q3(soc_a7ddrphy_dq_i_data12[5]),
-	.Q4(soc_a7ddrphy_dq_i_data12[4]),
-	.Q5(soc_a7ddrphy_dq_i_data12[3]),
-	.Q6(soc_a7ddrphy_dq_i_data12[2]),
-	.Q7(soc_a7ddrphy_dq_i_data12[1]),
-	.Q8(soc_a7ddrphy_dq_i_data12[0])
-);
-
-IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
-) IDELAYE2_12 (
-	.C(sys_clk),
-	.CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(soc_a7ddrphy_dq_i_nodelay12),
-	.INC(1'd1),
-	.LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(soc_a7ddrphy_dq_i_delayed12)
-);
-
-IOBUF IOBUF_12(
-	.I(soc_a7ddrphy_dq_o_nodelay12),
-	.T(soc_a7ddrphy_dq_t12),
-	.IO(ddram_dq[12]),
-	.O(soc_a7ddrphy_dq_i_nodelay12)
-);
-
-OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
-) OSERDESE2_42 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(soc_a7ddrphy_dfi_p0_wrdata[13]),
-	.D2(soc_a7ddrphy_dfi_p0_wrdata[29]),
-	.D3(soc_a7ddrphy_dfi_p1_wrdata[13]),
-	.D4(soc_a7ddrphy_dfi_p1_wrdata[29]),
-	.D5(soc_a7ddrphy_dfi_p2_wrdata[13]),
-	.D6(soc_a7ddrphy_dfi_p2_wrdata[29]),
-	.D7(soc_a7ddrphy_dfi_p3_wrdata[13]),
-	.D8(soc_a7ddrphy_dfi_p3_wrdata[29]),
-	.OCE(1'd1),
-	.RST(sys_rst),
-	.T1((~soc_a7ddrphy_oe_dq)),
-	.TCE(1'd1),
-	.OQ(soc_a7ddrphy_dq_o_nodelay13),
-	.TQ(soc_a7ddrphy_dq_t13)
-);
-
-ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
-) ISERDESE2_13 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.DDLY(soc_a7ddrphy_dq_i_delayed13),
-	.RST(sys_rst),
-	.Q1(soc_a7ddrphy_dq_i_data13[7]),
-	.Q2(soc_a7ddrphy_dq_i_data13[6]),
-	.Q3(soc_a7ddrphy_dq_i_data13[5]),
-	.Q4(soc_a7ddrphy_dq_i_data13[4]),
-	.Q5(soc_a7ddrphy_dq_i_data13[3]),
-	.Q6(soc_a7ddrphy_dq_i_data13[2]),
-	.Q7(soc_a7ddrphy_dq_i_data13[1]),
-	.Q8(soc_a7ddrphy_dq_i_data13[0])
-);
-
-IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
-) IDELAYE2_13 (
-	.C(sys_clk),
-	.CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(soc_a7ddrphy_dq_i_nodelay13),
-	.INC(1'd1),
-	.LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(soc_a7ddrphy_dq_i_delayed13)
-);
-
-IOBUF IOBUF_13(
-	.I(soc_a7ddrphy_dq_o_nodelay13),
-	.T(soc_a7ddrphy_dq_t13),
-	.IO(ddram_dq[13]),
-	.O(soc_a7ddrphy_dq_i_nodelay13)
-);
-
-OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
-) OSERDESE2_43 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(soc_a7ddrphy_dfi_p0_wrdata[14]),
-	.D2(soc_a7ddrphy_dfi_p0_wrdata[30]),
-	.D3(soc_a7ddrphy_dfi_p1_wrdata[14]),
-	.D4(soc_a7ddrphy_dfi_p1_wrdata[30]),
-	.D5(soc_a7ddrphy_dfi_p2_wrdata[14]),
-	.D6(soc_a7ddrphy_dfi_p2_wrdata[30]),
-	.D7(soc_a7ddrphy_dfi_p3_wrdata[14]),
-	.D8(soc_a7ddrphy_dfi_p3_wrdata[30]),
-	.OCE(1'd1),
-	.RST(sys_rst),
-	.T1((~soc_a7ddrphy_oe_dq)),
-	.TCE(1'd1),
-	.OQ(soc_a7ddrphy_dq_o_nodelay14),
-	.TQ(soc_a7ddrphy_dq_t14)
-);
-
-ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
-) ISERDESE2_14 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.DDLY(soc_a7ddrphy_dq_i_delayed14),
-	.RST(sys_rst),
-	.Q1(soc_a7ddrphy_dq_i_data14[7]),
-	.Q2(soc_a7ddrphy_dq_i_data14[6]),
-	.Q3(soc_a7ddrphy_dq_i_data14[5]),
-	.Q4(soc_a7ddrphy_dq_i_data14[4]),
-	.Q5(soc_a7ddrphy_dq_i_data14[3]),
-	.Q6(soc_a7ddrphy_dq_i_data14[2]),
-	.Q7(soc_a7ddrphy_dq_i_data14[1]),
-	.Q8(soc_a7ddrphy_dq_i_data14[0])
-);
-
-IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
-) IDELAYE2_14 (
-	.C(sys_clk),
-	.CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(soc_a7ddrphy_dq_i_nodelay14),
-	.INC(1'd1),
-	.LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(soc_a7ddrphy_dq_i_delayed14)
-);
-
-IOBUF IOBUF_14(
-	.I(soc_a7ddrphy_dq_o_nodelay14),
-	.T(soc_a7ddrphy_dq_t14),
-	.IO(ddram_dq[14]),
-	.O(soc_a7ddrphy_dq_i_nodelay14)
-);
-
-OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
-) OSERDESE2_44 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(soc_a7ddrphy_dfi_p0_wrdata[15]),
-	.D2(soc_a7ddrphy_dfi_p0_wrdata[31]),
-	.D3(soc_a7ddrphy_dfi_p1_wrdata[15]),
-	.D4(soc_a7ddrphy_dfi_p1_wrdata[31]),
-	.D5(soc_a7ddrphy_dfi_p2_wrdata[15]),
-	.D6(soc_a7ddrphy_dfi_p2_wrdata[31]),
-	.D7(soc_a7ddrphy_dfi_p3_wrdata[15]),
-	.D8(soc_a7ddrphy_dfi_p3_wrdata[31]),
-	.OCE(1'd1),
-	.RST(sys_rst),
-	.T1((~soc_a7ddrphy_oe_dq)),
-	.TCE(1'd1),
-	.OQ(soc_a7ddrphy_dq_o_nodelay15),
-	.TQ(soc_a7ddrphy_dq_t15)
-);
-
-ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
-) ISERDESE2_15 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.DDLY(soc_a7ddrphy_dq_i_delayed15),
-	.RST(sys_rst),
-	.Q1(soc_a7ddrphy_dq_i_data15[7]),
-	.Q2(soc_a7ddrphy_dq_i_data15[6]),
-	.Q3(soc_a7ddrphy_dq_i_data15[5]),
-	.Q4(soc_a7ddrphy_dq_i_data15[4]),
-	.Q5(soc_a7ddrphy_dq_i_data15[3]),
-	.Q6(soc_a7ddrphy_dq_i_data15[2]),
-	.Q7(soc_a7ddrphy_dq_i_data15[1]),
-	.Q8(soc_a7ddrphy_dq_i_data15[0])
-);
-
-IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
-) IDELAYE2_15 (
-	.C(sys_clk),
-	.CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(soc_a7ddrphy_dq_i_nodelay15),
-	.INC(1'd1),
-	.LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(soc_a7ddrphy_dq_i_delayed15)
-);
-
-IOBUF IOBUF_15(
-	.I(soc_a7ddrphy_dq_o_nodelay15),
-	.T(soc_a7ddrphy_dq_t15),
-	.IO(ddram_dq[15]),
-	.O(soc_a7ddrphy_dq_i_nodelay15)
-);
-
-reg [23:0] storage_2[0:7];
-reg [23:0] memdat_5;
-always @(posedge sys_clk) begin
-	if (soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we)
-		storage_2[soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
-	memdat_5 <= storage_2[soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr];
-end
-
-always @(posedge sys_clk) begin
-end
-
-assign soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat_5;
-assign soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage_2[soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr];
-
-reg [23:0] storage_3[0:7];
-reg [23:0] memdat_6;
-always @(posedge sys_clk) begin
-	if (soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we)
-		storage_3[soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
-	memdat_6 <= storage_3[soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr];
-end
-
-always @(posedge sys_clk) begin
-end
-
-assign soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_6;
-assign soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_3[soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr];
-
-reg [23:0] storage_4[0:7];
-reg [23:0] memdat_7;
-always @(posedge sys_clk) begin
-	if (soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we)
-		storage_4[soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
-	memdat_7 <= storage_4[soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr];
-end
-
-always @(posedge sys_clk) begin
-end
-
-assign soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_7;
-assign soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_4[soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr];
-
-reg [23:0] storage_5[0:7];
-reg [23:0] memdat_8;
-always @(posedge sys_clk) begin
-	if (soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we)
-		storage_5[soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
-	memdat_8 <= storage_5[soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr];
-end
-
-always @(posedge sys_clk) begin
-end
-
-assign soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_8;
-assign soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_5[soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr];
-
-reg [23:0] storage_6[0:7];
-reg [23:0] memdat_9;
-always @(posedge sys_clk) begin
-	if (soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_we)
-		storage_6[soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
-	memdat_9 <= storage_6[soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr];
-end
-
-always @(posedge sys_clk) begin
-end
-
-assign soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = memdat_9;
-assign soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_6[soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_adr];
-
-reg [23:0] storage_7[0:7];
-reg [23:0] memdat_10;
-always @(posedge sys_clk) begin
-	if (soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_we)
-		storage_7[soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
-	memdat_10 <= storage_7[soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr];
-end
-
-always @(posedge sys_clk) begin
-end
-
-assign soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = memdat_10;
-assign soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_7[soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_adr];
-
-reg [23:0] storage_8[0:7];
-reg [23:0] memdat_11;
-always @(posedge sys_clk) begin
-	if (soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_we)
-		storage_8[soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
-	memdat_11 <= storage_8[soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr];
-end
-
-always @(posedge sys_clk) begin
-end
-
-assign soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = memdat_11;
-assign soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_8[soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_adr];
-
-reg [23:0] storage_9[0:7];
-reg [23:0] memdat_12;
-always @(posedge sys_clk) begin
-	if (soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_we)
-		storage_9[soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
-	memdat_12 <= storage_9[soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr];
-end
-
-always @(posedge sys_clk) begin
-end
-
-assign soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = memdat_12;
-assign soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_9[soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_adr];
-
-reg [23:0] tag_mem[0:511];
-reg [8:0] memadr_3;
-always @(posedge sys_clk) begin
-	if (soc_netsoc_tag_port_we)
-		tag_mem[soc_netsoc_tag_port_adr] <= soc_netsoc_tag_port_dat_w;
-	memadr_3 <= soc_netsoc_tag_port_adr;
-end
-
-assign soc_netsoc_tag_port_dat_r = tag_mem[memadr_3];
-
-assign eth_mdio = soc_data_oe ? soc_data_w : 1'bz;
-assign soc_data_r = eth_mdio;
-
-reg [11:0] storage_10[0:4];
-reg [11:0] memdat_13;
-always @(posedge eth_rx_clk) begin
-	if (soc_crc32_checker_syncfifo_wrport_we)
-		storage_10[soc_crc32_checker_syncfifo_wrport_adr] <= soc_crc32_checker_syncfifo_wrport_dat_w;
-	memdat_13 <= storage_10[soc_crc32_checker_syncfifo_wrport_adr];
-end
-
-always @(posedge eth_rx_clk) begin
-end
-
-assign soc_crc32_checker_syncfifo_wrport_dat_r = memdat_13;
-assign soc_crc32_checker_syncfifo_rdport_dat_r = storage_10[soc_crc32_checker_syncfifo_rdport_adr];
-
-reg [41:0] storage_11[0:63];
-reg [5:0] memadr_4;
-reg [5:0] memadr_5;
-always @(posedge sys_clk) begin
-	if (soc_tx_cdc_wrport_we)
-		storage_11[soc_tx_cdc_wrport_adr] <= soc_tx_cdc_wrport_dat_w;
-	memadr_4 <= soc_tx_cdc_wrport_adr;
-end
-
-always @(posedge eth_tx_clk) begin
-	memadr_5 <= soc_tx_cdc_rdport_adr;
-end
-
-assign soc_tx_cdc_wrport_dat_r = storage_11[memadr_4];
-assign soc_tx_cdc_rdport_dat_r = storage_11[memadr_5];
-
-reg [41:0] storage_12[0:63];
-reg [5:0] memadr_6;
-reg [5:0] memadr_7;
-always @(posedge eth_rx_clk) begin
-	if (soc_rx_cdc_wrport_we)
-		storage_12[soc_rx_cdc_wrport_adr] <= soc_rx_cdc_wrport_dat_w;
-	memadr_6 <= soc_rx_cdc_wrport_adr;
-end
-
-always @(posedge sys_clk) begin
-	memadr_7 <= soc_rx_cdc_rdport_adr;
-end
-
-assign soc_rx_cdc_wrport_dat_r = storage_12[memadr_6];
-assign soc_rx_cdc_rdport_dat_r = storage_12[memadr_7];
-
-reg [34:0] storage_13[0:1];
-reg [34:0] memdat_14;
-always @(posedge sys_clk) begin
-	if (soc_writer_fifo_wrport_we)
-		storage_13[soc_writer_fifo_wrport_adr] <= soc_writer_fifo_wrport_dat_w;
-	memdat_14 <= storage_13[soc_writer_fifo_wrport_adr];
-end
-
-always @(posedge sys_clk) begin
-end
-
-assign soc_writer_fifo_wrport_dat_r = memdat_14;
-assign soc_writer_fifo_rdport_dat_r = storage_13[soc_writer_fifo_rdport_adr];
-
-reg [31:0] mem_4[0:381];
-reg [8:0] memadr_8;
-reg [31:0] memdat_15;
-always @(posedge sys_clk) begin
-	if (soc_writer_memory0_we)
-		mem_4[soc_writer_memory0_adr] <= soc_writer_memory0_dat_w;
-	memadr_8 <= soc_writer_memory0_adr;
-end
-
-always @(posedge sys_clk) begin
-	memdat_15 <= mem_4[soc_sram0_adr0];
-end
-
-assign soc_writer_memory0_dat_r = mem_4[memadr_8];
-assign soc_sram0_dat_r0 = memdat_15;
-
-reg [31:0] mem_5[0:381];
-reg [8:0] memadr_9;
-reg [31:0] memdat_16;
-always @(posedge sys_clk) begin
-	if (soc_writer_memory1_we)
-		mem_5[soc_writer_memory1_adr] <= soc_writer_memory1_dat_w;
-	memadr_9 <= soc_writer_memory1_adr;
-end
-
-always @(posedge sys_clk) begin
-	memdat_16 <= mem_5[soc_sram1_adr0];
-end
-
-assign soc_writer_memory1_dat_r = mem_5[memadr_9];
-assign soc_sram1_dat_r0 = memdat_16;
-
-reg [13:0] storage_14[0:1];
-reg [13:0] memdat_17;
-always @(posedge sys_clk) begin
-	if (soc_reader_fifo_wrport_we)
-		storage_14[soc_reader_fifo_wrport_adr] <= soc_reader_fifo_wrport_dat_w;
-	memdat_17 <= storage_14[soc_reader_fifo_wrport_adr];
-end
-
-always @(posedge sys_clk) begin
-end
-
-assign soc_reader_fifo_wrport_dat_r = memdat_17;
-assign soc_reader_fifo_rdport_dat_r = storage_14[soc_reader_fifo_rdport_adr];
-
-reg [31:0] mem_6[0:381];
-reg [8:0] memadr_10;
-reg [8:0] memadr_11;
-always @(posedge sys_clk) begin
-	memadr_10 <= soc_reader_memory0_adr;
-end
-
-always @(posedge sys_clk) begin
-	if (soc_sram0_we[0])
-		mem_6[soc_sram0_adr1][7:0] <= soc_sram0_dat_w[7:0];
-	if (soc_sram0_we[1])
-		mem_6[soc_sram0_adr1][15:8] <= soc_sram0_dat_w[15:8];
-	if (soc_sram0_we[2])
-		mem_6[soc_sram0_adr1][23:16] <= soc_sram0_dat_w[23:16];
-	if (soc_sram0_we[3])
-		mem_6[soc_sram0_adr1][31:24] <= soc_sram0_dat_w[31:24];
-	memadr_11 <= soc_sram0_adr1;
-end
-
-assign soc_reader_memory0_dat_r = mem_6[memadr_10];
-assign soc_sram0_dat_r1 = mem_6[memadr_11];
-
-reg [31:0] mem_7[0:381];
-reg [8:0] memadr_12;
-reg [8:0] memadr_13;
-always @(posedge sys_clk) begin
-	memadr_12 <= soc_reader_memory1_adr;
-end
-
-always @(posedge sys_clk) begin
-	if (soc_sram1_we[0])
-		mem_7[soc_sram1_adr1][7:0] <= soc_sram1_dat_w[7:0];
-	if (soc_sram1_we[1])
-		mem_7[soc_sram1_adr1][15:8] <= soc_sram1_dat_w[15:8];
-	if (soc_sram1_we[2])
-		mem_7[soc_sram1_adr1][23:16] <= soc_sram1_dat_w[23:16];
-	if (soc_sram1_we[3])
-		mem_7[soc_sram1_adr1][31:24] <= soc_sram1_dat_w[31:24];
-	memadr_13 <= soc_sram1_adr1;
-end
-
-assign soc_reader_memory1_dat_r = mem_7[memadr_12];
-assign soc_sram1_dat_r1 = mem_7[memadr_13];
-
-VexRiscv VexRiscv(
-	.clk(sys_clk),
-	.dBusWishbone_ACK(soc_netsoc_cpu_dbus_ack),
-	.dBusWishbone_DAT_MISO(soc_netsoc_cpu_dbus_dat_r),
-	.dBusWishbone_ERR(soc_netsoc_cpu_dbus_err),
-	.externalInterruptArray(soc_netsoc_cpu_interrupt0),
-	.externalResetVector(1'd0),
-	.iBusWishbone_ACK(soc_netsoc_cpu_ibus_ack),
-	.iBusWishbone_DAT_MISO(soc_netsoc_cpu_ibus_dat_r),
-	.iBusWishbone_ERR(soc_netsoc_cpu_ibus_err),
-	.reset((sys_rst | soc_netsoc_cpu_reset)),
-	.softwareInterrupt(1'd0),
-	.timerInterrupt(soc_netsoc_cpu_interrupt1),
-	.dBusWishbone_ADR(soc_netsoc_cpu_dbus_adr),
-	.dBusWishbone_BTE(soc_netsoc_cpu_dbus_bte),
-	.dBusWishbone_CTI(soc_netsoc_cpu_dbus_cti),
-	.dBusWishbone_CYC(soc_netsoc_cpu_dbus_cyc),
-	.dBusWishbone_DAT_MOSI(soc_netsoc_cpu_dbus_dat_w),
-	.dBusWishbone_SEL(soc_netsoc_cpu_dbus_sel),
-	.dBusWishbone_STB(soc_netsoc_cpu_dbus_stb),
-	.dBusWishbone_WE(soc_netsoc_cpu_dbus_we),
-	.iBusWishbone_ADR(soc_netsoc_cpu_ibus_adr),
-	.iBusWishbone_BTE(soc_netsoc_cpu_ibus_bte),
-	.iBusWishbone_CTI(soc_netsoc_cpu_ibus_cti),
-	.iBusWishbone_CYC(soc_netsoc_cpu_ibus_cyc),
-	.iBusWishbone_DAT_MOSI(soc_netsoc_cpu_ibus_dat_w),
-	.iBusWishbone_SEL(soc_netsoc_cpu_ibus_sel),
-	.iBusWishbone_STB(soc_netsoc_cpu_ibus_stb),
-	.iBusWishbone_WE(soc_netsoc_cpu_ibus_we)
-);
-
-reg [7:0] data_mem_grain0[0:511];
-reg [8:0] memadr_14;
-always @(posedge sys_clk) begin
-	if (soc_netsoc_data_port_we[0])
-		data_mem_grain0[soc_netsoc_data_port_adr] <= soc_netsoc_data_port_dat_w[7:0];
-	memadr_14 <= soc_netsoc_data_port_adr;
-end
-
-assign soc_netsoc_data_port_dat_r[7:0] = data_mem_grain0[memadr_14];
-
-reg [7:0] data_mem_grain1[0:511];
-reg [8:0] memadr_15;
-always @(posedge sys_clk) begin
-	if (soc_netsoc_data_port_we[1])
-		data_mem_grain1[soc_netsoc_data_port_adr] <= soc_netsoc_data_port_dat_w[15:8];
-	memadr_15 <= soc_netsoc_data_port_adr;
-end
-
-assign soc_netsoc_data_port_dat_r[15:8] = data_mem_grain1[memadr_15];
-
-reg [7:0] data_mem_grain2[0:511];
-reg [8:0] memadr_16;
-always @(posedge sys_clk) begin
-	if (soc_netsoc_data_port_we[2])
-		data_mem_grain2[soc_netsoc_data_port_adr] <= soc_netsoc_data_port_dat_w[23:16];
-	memadr_16 <= soc_netsoc_data_port_adr;
-end
-
-assign soc_netsoc_data_port_dat_r[23:16] = data_mem_grain2[memadr_16];
-
-reg [7:0] data_mem_grain3[0:511];
-reg [8:0] memadr_17;
-always @(posedge sys_clk) begin
-	if (soc_netsoc_data_port_we[3])
-		data_mem_grain3[soc_netsoc_data_port_adr] <= soc_netsoc_data_port_dat_w[31:24];
-	memadr_17 <= soc_netsoc_data_port_adr;
-end
-
-assign soc_netsoc_data_port_dat_r[31:24] = data_mem_grain3[memadr_17];
-
-reg [7:0] data_mem_grain4[0:511];
-reg [8:0] memadr_18;
-always @(posedge sys_clk) begin
-	if (soc_netsoc_data_port_we[4])
-		data_mem_grain4[soc_netsoc_data_port_adr] <= soc_netsoc_data_port_dat_w[39:32];
-	memadr_18 <= soc_netsoc_data_port_adr;
-end
-
-assign soc_netsoc_data_port_dat_r[39:32] = data_mem_grain4[memadr_18];
-
-reg [7:0] data_mem_grain5[0:511];
-reg [8:0] memadr_19;
-always @(posedge sys_clk) begin
-	if (soc_netsoc_data_port_we[5])
-		data_mem_grain5[soc_netsoc_data_port_adr] <= soc_netsoc_data_port_dat_w[47:40];
-	memadr_19 <= soc_netsoc_data_port_adr;
-end
-
-assign soc_netsoc_data_port_dat_r[47:40] = data_mem_grain5[memadr_19];
-
-reg [7:0] data_mem_grain6[0:511];
-reg [8:0] memadr_20;
-always @(posedge sys_clk) begin
-	if (soc_netsoc_data_port_we[6])
-		data_mem_grain6[soc_netsoc_data_port_adr] <= soc_netsoc_data_port_dat_w[55:48];
-	memadr_20 <= soc_netsoc_data_port_adr;
-end
-
-assign soc_netsoc_data_port_dat_r[55:48] = data_mem_grain6[memadr_20];
-
-reg [7:0] data_mem_grain7[0:511];
-reg [8:0] memadr_21;
-always @(posedge sys_clk) begin
-	if (soc_netsoc_data_port_we[7])
-		data_mem_grain7[soc_netsoc_data_port_adr] <= soc_netsoc_data_port_dat_w[63:56];
-	memadr_21 <= soc_netsoc_data_port_adr;
-end
-
-assign soc_netsoc_data_port_dat_r[63:56] = data_mem_grain7[memadr_21];
-
-reg [7:0] data_mem_grain8[0:511];
-reg [8:0] memadr_22;
-always @(posedge sys_clk) begin
-	if (soc_netsoc_data_port_we[8])
-		data_mem_grain8[soc_netsoc_data_port_adr] <= soc_netsoc_data_port_dat_w[71:64];
-	memadr_22 <= soc_netsoc_data_port_adr;
-end
-
-assign soc_netsoc_data_port_dat_r[71:64] = data_mem_grain8[memadr_22];
-
-reg [7:0] data_mem_grain9[0:511];
-reg [8:0] memadr_23;
-always @(posedge sys_clk) begin
-	if (soc_netsoc_data_port_we[9])
-		data_mem_grain9[soc_netsoc_data_port_adr] <= soc_netsoc_data_port_dat_w[79:72];
-	memadr_23 <= soc_netsoc_data_port_adr;
-end
-
-assign soc_netsoc_data_port_dat_r[79:72] = data_mem_grain9[memadr_23];
-
-reg [7:0] data_mem_grain10[0:511];
-reg [8:0] memadr_24;
-always @(posedge sys_clk) begin
-	if (soc_netsoc_data_port_we[10])
-		data_mem_grain10[soc_netsoc_data_port_adr] <= soc_netsoc_data_port_dat_w[87:80];
-	memadr_24 <= soc_netsoc_data_port_adr;
-end
-
-assign soc_netsoc_data_port_dat_r[87:80] = data_mem_grain10[memadr_24];
-
-reg [7:0] data_mem_grain11[0:511];
-reg [8:0] memadr_25;
-always @(posedge sys_clk) begin
-	if (soc_netsoc_data_port_we[11])
-		data_mem_grain11[soc_netsoc_data_port_adr] <= soc_netsoc_data_port_dat_w[95:88];
-	memadr_25 <= soc_netsoc_data_port_adr;
-end
-
-assign soc_netsoc_data_port_dat_r[95:88] = data_mem_grain11[memadr_25];
-
-reg [7:0] data_mem_grain12[0:511];
-reg [8:0] memadr_26;
-always @(posedge sys_clk) begin
-	if (soc_netsoc_data_port_we[12])
-		data_mem_grain12[soc_netsoc_data_port_adr] <= soc_netsoc_data_port_dat_w[103:96];
-	memadr_26 <= soc_netsoc_data_port_adr;
-end
-
-assign soc_netsoc_data_port_dat_r[103:96] = data_mem_grain12[memadr_26];
-
-reg [7:0] data_mem_grain13[0:511];
-reg [8:0] memadr_27;
-always @(posedge sys_clk) begin
-	if (soc_netsoc_data_port_we[13])
-		data_mem_grain13[soc_netsoc_data_port_adr] <= soc_netsoc_data_port_dat_w[111:104];
-	memadr_27 <= soc_netsoc_data_port_adr;
-end
-
-assign soc_netsoc_data_port_dat_r[111:104] = data_mem_grain13[memadr_27];
-
-reg [7:0] data_mem_grain14[0:511];
-reg [8:0] memadr_28;
-always @(posedge sys_clk) begin
-	if (soc_netsoc_data_port_we[14])
-		data_mem_grain14[soc_netsoc_data_port_adr] <= soc_netsoc_data_port_dat_w[119:112];
-	memadr_28 <= soc_netsoc_data_port_adr;
-end
-
-assign soc_netsoc_data_port_dat_r[119:112] = data_mem_grain14[memadr_28];
-
-reg [7:0] data_mem_grain15[0:511];
-reg [8:0] memadr_29;
-always @(posedge sys_clk) begin
-	if (soc_netsoc_data_port_we[15])
-		data_mem_grain15[soc_netsoc_data_port_adr] <= soc_netsoc_data_port_dat_w[127:120];
-	memadr_29 <= soc_netsoc_data_port_adr;
-end
-
-assign soc_netsoc_data_port_dat_r[127:120] = data_mem_grain15[memadr_29];
-
-(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
-	.INIT(1'd1)
-) FDPE (
-	.C(sys_clk),
-	.CE(1'd1),
-	.D(1'd0),
-	.PRE(vns_xilinxasyncresetsynchronizerimpl0),
-	.Q(vns_xilinxasyncresetsynchronizerimpl0_rst_meta)
-);
-
-(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
-	.INIT(1'd1)
-) FDPE_1 (
-	.C(sys_clk),
-	.CE(1'd1),
-	.D(vns_xilinxasyncresetsynchronizerimpl0_rst_meta),
-	.PRE(vns_xilinxasyncresetsynchronizerimpl0),
-	.Q(sys_rst)
-);
-
-(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
-	.INIT(1'd1)
-) FDPE_2 (
-	.C(clk200_clk),
-	.CE(1'd1),
-	.D(1'd0),
-	.PRE(vns_xilinxasyncresetsynchronizerimpl1),
-	.Q(vns_xilinxasyncresetsynchronizerimpl1_rst_meta)
-);
-
-(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
-	.INIT(1'd1)
-) FDPE_3 (
-	.C(clk200_clk),
-	.CE(1'd1),
-	.D(vns_xilinxasyncresetsynchronizerimpl1_rst_meta),
-	.PRE(vns_xilinxasyncresetsynchronizerimpl1),
-	.Q(clk200_rst)
-);
-
-(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
-	.INIT(1'd1)
-) FDPE_4 (
-	.C(eth_tx_clk),
-	.CE(1'd1),
-	.D(1'd0),
-	.PRE(soc_reset0),
-	.Q(vns_xilinxasyncresetsynchronizerimpl2_rst_meta)
-);
-
-(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
-	.INIT(1'd1)
-) FDPE_5 (
-	.C(eth_tx_clk),
-	.CE(1'd1),
-	.D(vns_xilinxasyncresetsynchronizerimpl2_rst_meta),
-	.PRE(soc_reset0),
-	.Q(eth_tx_rst)
-);
-
-(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
-	.INIT(1'd1)
-) FDPE_6 (
-	.C(eth_rx_clk),
-	.CE(1'd1),
-	.D(1'd0),
-	.PRE(soc_reset0),
-	.Q(vns_xilinxasyncresetsynchronizerimpl3_rst_meta)
-);
-
-(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
-	.INIT(1'd1)
-) FDPE_7 (
-	.C(eth_rx_clk),
-	.CE(1'd1),
-	.D(vns_xilinxasyncresetsynchronizerimpl3_rst_meta),
-	.PRE(soc_reset0),
-	.Q(eth_rx_rst)
-);
-
-endmodule
diff --git a/sdc-plugin/tests/base_litex/base_litex.xdc b/sdc-plugin/tests/base_litex/base_litex.xdc
deleted file mode 100644
index 0fd7ee9..0000000
--- a/sdc-plugin/tests/base_litex/base_litex.xdc
+++ /dev/null
@@ -1,273 +0,0 @@
-### serial:0.tx
-set_property LOC D10 [get_ports serial_tx]
-set_property IOSTANDARD LVCMOS33 [get_ports serial_tx]
-### serial:0.rx
-set_property LOC A9 [get_ports serial_rx]
-set_property IOSTANDARD LVCMOS33 [get_ports serial_rx]
-### clk100:0
-set_property LOC E3 [get_ports clk100]
-set_property IOSTANDARD LVCMOS33 [get_ports clk100]
-### eth_ref_clk:0
-set_property LOC G18 [get_ports eth_ref_clk]
-set_property IOSTANDARD LVCMOS33 [get_ports eth_ref_clk]
-### cpu_reset:0
-set_property LOC C2 [get_ports cpu_reset]
-set_property IOSTANDARD LVCMOS33 [get_ports cpu_reset]
-### ddram:0.a
-set_property LOC R2 [get_ports {ddram_a[0]} ]
-set_property SLEW FAST [get_ports {ddram_a[0]} ]
-set_property IOSTANDARD SSTL135 [get_ports {ddram_a[0]} ]
-### ddram:0.a
-set_property LOC M6 [get_ports {ddram_a[1]} ]
-set_property SLEW FAST [get_ports {ddram_a[1]} ]
-set_property IOSTANDARD SSTL135 [get_ports {ddram_a[1]} ]
-### ddram:0.a
-set_property LOC N4 [get_ports {ddram_a[2]} ]
-set_property SLEW FAST [get_ports {ddram_a[2]} ]
-set_property IOSTANDARD SSTL135 [get_ports {ddram_a[2]} ]
-### ddram:0.a
-set_property LOC T1 [get_ports {ddram_a[3]} ]
-set_property SLEW FAST [get_ports {ddram_a[3]} ]
-set_property IOSTANDARD SSTL135 [get_ports {ddram_a[3]} ]
-### ddram:0.a
-set_property LOC N6 [get_ports {ddram_a[4]} ]
-set_property SLEW FAST [get_ports {ddram_a[4]} ]
-set_property IOSTANDARD SSTL135 [get_ports {ddram_a[4]} ]
-### ddram:0.a
-set_property LOC R7 [get_ports {ddram_a[5]} ]
-set_property SLEW FAST [get_ports {ddram_a[5]} ]
-set_property IOSTANDARD SSTL135 [get_ports {ddram_a[5]} ]
-### ddram:0.a
-set_property LOC V6 [get_ports {ddram_a[6]} ]
-set_property SLEW FAST [get_ports {ddram_a[6]} ]
-set_property IOSTANDARD SSTL135 [get_ports {ddram_a[6]} ]
-### ddram:0.a
-set_property LOC U7 [get_ports {ddram_a[7]} ]
-set_property SLEW FAST [get_ports {ddram_a[7]} ]
-set_property IOSTANDARD SSTL135 [get_ports {ddram_a[7]} ]
-### ddram:0.a
-set_property LOC R8 [get_ports {ddram_a[8]} ]
-set_property SLEW FAST [get_ports {ddram_a[8]} ]
-set_property IOSTANDARD SSTL135 [get_ports {ddram_a[8]} ]
-### ddram:0.a
-set_property LOC V7 [get_ports {ddram_a[9]} ]
-set_property SLEW FAST [get_ports {ddram_a[9]} ]
-set_property IOSTANDARD SSTL135 [get_ports {ddram_a[9]} ]
-### ddram:0.a
-set_property LOC R6 [get_ports {ddram_a[10]} ]
-set_property SLEW FAST [get_ports {ddram_a[10]} ]
-set_property IOSTANDARD SSTL135 [get_ports {ddram_a[10]} ]
-### ddram:0.a
-set_property LOC U6 [get_ports {ddram_a[11]} ]
-set_property SLEW FAST [get_ports {ddram_a[11]} ]
-set_property IOSTANDARD SSTL135 [get_ports {ddram_a[11]} ]
-### ddram:0.a
-set_property LOC T6 [get_ports {ddram_a[12]} ]
-set_property SLEW FAST [get_ports {ddram_a[12]} ]
-set_property IOSTANDARD SSTL135 [get_ports {ddram_a[12]} ]
-### ddram:0.a
-set_property LOC T8 [get_ports {ddram_a[13]} ]
-set_property SLEW FAST [get_ports {ddram_a[13]} ]
-set_property IOSTANDARD SSTL135 [get_ports {ddram_a[13]} ]
-### ddram:0.ba
-set_property LOC R1 [get_ports {ddram_ba[0]} ]
-set_property SLEW FAST [get_ports {ddram_ba[0]} ]
-set_property IOSTANDARD SSTL135 [get_ports {ddram_ba[0]} ]
-### ddram:0.ba
-set_property LOC P4 [get_ports {ddram_ba[1]} ]
-set_property SLEW FAST [get_ports {ddram_ba[1]} ]
-set_property IOSTANDARD SSTL135 [get_ports {ddram_ba[1]} ]
-### ddram:0.ba
-set_property LOC P2 [get_ports {ddram_ba[2]} ]
-set_property SLEW FAST [get_ports {ddram_ba[2]} ]
-set_property IOSTANDARD SSTL135 [get_ports {ddram_ba[2]} ]
-### ddram:0.ras_n
-set_property LOC P3 [get_ports ddram_ras_n]
-set_property SLEW FAST [get_ports ddram_ras_n]
-set_property IOSTANDARD SSTL135 [get_ports ddram_ras_n]
-### ddram:0.cas_n
-set_property LOC M4 [get_ports ddram_cas_n]
-set_property SLEW FAST [get_ports ddram_cas_n]
-set_property IOSTANDARD SSTL135 [get_ports ddram_cas_n]
-### ddram:0.we_n
-set_property LOC P5 [get_ports ddram_we_n]
-set_property SLEW FAST [get_ports ddram_we_n]
-set_property IOSTANDARD SSTL135 [get_ports ddram_we_n]
-### ddram:0.cs_n
-set_property LOC U8 [get_ports ddram_cs_n]
-set_property SLEW FAST [get_ports ddram_cs_n]
-set_property IOSTANDARD SSTL135 [get_ports ddram_cs_n]
-### ddram:0.dm
-set_property LOC L1 [get_ports {ddram_dm[0]} ]
-set_property SLEW FAST [get_ports {ddram_dm[0]} ]
-set_property IOSTANDARD SSTL135 [get_ports {ddram_dm[0]} ]
-### ddram:0.dm
-set_property LOC U1 [get_ports {ddram_dm[1]} ]
-set_property SLEW FAST [get_ports {ddram_dm[1]} ]
-set_property IOSTANDARD SSTL135 [get_ports {ddram_dm[1]} ]
-### ddram:0.dq
-set_property LOC K5 [get_ports {ddram_dq[0]} ]
-set_property SLEW FAST [get_ports {ddram_dq[0]} ]
-set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[0]} ]
-set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[0]} ]
-### ddram:0.dq
-set_property LOC L3 [get_ports {ddram_dq[1]} ]
-set_property SLEW FAST [get_ports {ddram_dq[1]} ]
-set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[1]} ]
-set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[1]} ]
-### ddram:0.dq
-set_property LOC K3 [get_ports {ddram_dq[2]} ]
-set_property SLEW FAST [get_ports {ddram_dq[2]} ]
-set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[2]} ]
-set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[2]} ]
-### ddram:0.dq
-set_property LOC L6 [get_ports {ddram_dq[3]} ]
-set_property SLEW FAST [get_ports {ddram_dq[3]} ]
-set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[3]} ]
-set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[3]} ]
-### ddram:0.dq
-set_property LOC M3 [get_ports {ddram_dq[4]} ]
-set_property SLEW FAST [get_ports {ddram_dq[4]} ]
-set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[4]} ]
-set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[4]} ]
-### ddram:0.dq
-set_property LOC M1 [get_ports {ddram_dq[5]} ]
-set_property SLEW FAST [get_ports {ddram_dq[5]} ]
-set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[5]} ]
-set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[5]} ]
-### ddram:0.dq
-set_property LOC L4 [get_ports {ddram_dq[6]} ]
-set_property SLEW FAST [get_ports {ddram_dq[6]} ]
-set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[6]} ]
-set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[6]} ]
-### ddram:0.dq
-set_property LOC M2 [get_ports {ddram_dq[7]} ]
-set_property SLEW FAST [get_ports {ddram_dq[7]} ]
-set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[7]} ]
-set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[7]} ]
-### ddram:0.dq
-set_property LOC V4 [get_ports {ddram_dq[8]} ]
-set_property SLEW FAST [get_ports {ddram_dq[8]} ]
-set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[8]} ]
-set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[8]} ]
-### ddram:0.dq
-set_property LOC T5 [get_ports {ddram_dq[9]} ]
-set_property SLEW FAST [get_ports {ddram_dq[9]} ]
-set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[9]} ]
-set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[9]} ]
-### ddram:0.dq
-set_property LOC U4 [get_ports {ddram_dq[10]} ]
-set_property SLEW FAST [get_ports {ddram_dq[10]} ]
-set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[10]} ]
-set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[10]} ]
-### ddram:0.dq
-set_property LOC V5 [get_ports {ddram_dq[11]} ]
-set_property SLEW FAST [get_ports {ddram_dq[11]} ]
-set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[11]} ]
-set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[11]} ]
-### ddram:0.dq
-set_property LOC V1 [get_ports {ddram_dq[12]} ]
-set_property SLEW FAST [get_ports {ddram_dq[12]} ]
-set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[12]} ]
-set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[12]} ]
-### ddram:0.dq
-set_property LOC T3 [get_ports {ddram_dq[13]} ]
-set_property SLEW FAST [get_ports {ddram_dq[13]} ]
-set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[13]} ]
-set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[13]} ]
-### ddram:0.dq
-set_property LOC U3 [get_ports {ddram_dq[14]} ]
-set_property SLEW FAST [get_ports {ddram_dq[14]} ]
-set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[14]} ]
-set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[14]} ]
-### ddram:0.dq
-set_property LOC R3 [get_ports {ddram_dq[15]} ]
-set_property SLEW FAST [get_ports {ddram_dq[15]} ]
-set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[15]} ]
-set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[15]} ]
-### ddram:0.dqs_p
-set_property LOC N2 [get_ports {ddram_dqs_p[0]} ]
-set_property SLEW FAST [get_ports {ddram_dqs_p[0]} ]
-set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_dqs_p[0]} ]
-### ddram:0.dqs_p
-set_property LOC U2 [get_ports {ddram_dqs_p[1]} ]
-set_property SLEW FAST [get_ports {ddram_dqs_p[1]} ]
-set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_dqs_p[1]} ]
-### ddram:0.dqs_n
-set_property LOC N1 [get_ports {ddram_dqs_n[0]} ]
-set_property SLEW FAST [get_ports {ddram_dqs_n[0]} ]
-set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_dqs_n[0]} ]
-### ddram:0.dqs_n
-set_property LOC V2 [get_ports {ddram_dqs_n[1]} ]
-set_property SLEW FAST [get_ports {ddram_dqs_n[1]} ]
-set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_dqs_n[1]} ]
-### ddram:0.clk_p
-set_property LOC U9 [get_ports ddram_clk_p]
-set_property SLEW FAST [get_ports ddram_clk_p]
-set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_clk_p]
-### ddram:0.clk_n
-set_property LOC V9 [get_ports ddram_clk_n]
-set_property SLEW FAST [get_ports ddram_clk_n]
-set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_clk_n]
-### ddram:0.cke
-set_property LOC N5 [get_ports ddram_cke]
-set_property SLEW FAST [get_ports ddram_cke]
-set_property IOSTANDARD SSTL135 [get_ports ddram_cke]
-### ddram:0.odt
-set_property LOC R5 [get_ports ddram_odt]
-set_property SLEW FAST [get_ports ddram_odt]
-set_property IOSTANDARD SSTL135 [get_ports ddram_odt]
-### ddram:0.reset_n
-set_property LOC K6 [get_ports ddram_reset_n]
-set_property SLEW FAST [get_ports ddram_reset_n]
-set_property IOSTANDARD SSTL135 [get_ports ddram_reset_n]
-### eth:0.rst_n
-set_property LOC C16 [get_ports eth_rst_n]
-set_property IOSTANDARD LVCMOS33 [get_ports eth_rst_n]
-### eth:0.mdio
-set_property LOC K13 [get_ports eth_mdio]
-set_property IOSTANDARD LVCMOS33 [get_ports eth_mdio]
-### eth:0.mdc
-set_property LOC F16 [get_ports eth_mdc]
-set_property IOSTANDARD LVCMOS33 [get_ports eth_mdc]
-### eth:0.rx_dv
-set_property LOC G16 [get_ports eth_rx_dv]
-set_property IOSTANDARD LVCMOS33 [get_ports eth_rx_dv]
-### eth:0.rx_er
-set_property LOC C17 [get_ports eth_rx_er]
-set_property IOSTANDARD LVCMOS33 [get_ports eth_rx_er]
-### eth:0.rx_data
-set_property LOC D18 [get_ports {eth_rx_data[0]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[0]}]
-### eth:0.rx_data
-set_property LOC E17 [get_ports {eth_rx_data[1]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[1]}]
-### eth:0.rx_data
-set_property LOC E18 [get_ports {eth_rx_data[2]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[2]}]
-### eth:0.rx_data
-set_property LOC G17 [get_ports {eth_rx_data[3]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[3]}]
-### eth:0.tx_en
-set_property LOC H15 [get_ports eth_tx_en]
-set_property IOSTANDARD LVCMOS33 [get_ports eth_tx_en]
-### eth:0.tx_data
-set_property LOC H14 [get_ports {eth_tx_data[0]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[0]}]
-### eth:0.tx_data
-set_property LOC J14 [get_ports {eth_tx_data[1]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[1]}]
-### eth:0.tx_data
-set_property LOC J13 [get_ports {eth_tx_data[2]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[2]}]
-### eth:0.tx_data
-set_property LOC H17 [get_ports {eth_tx_data[3]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[3]}]
-### eth:0.col
-set_property LOC D17 [get_ports eth_col]
-set_property IOSTANDARD LVCMOS33 [get_ports eth_col]
-### eth:0.crs
-set_property LOC G14 [get_ports eth_crs]
-set_property IOSTANDARD LVCMOS33 [get_ports eth_crs]
-
-set_property INTERNAL_VREF 0.750 [get_iobanks 34]
diff --git a/sdc-plugin/tests/base_litex/mem.init b/sdc-plugin/tests/base_litex/mem.init
deleted file mode 100644
index ec98d98..0000000
--- a/sdc-plugin/tests/base_litex/mem.init
+++ /dev/null
@@ -1,6479 +0,0 @@
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diff --git a/sdc-plugin/tests/base_litex/mem_1.init b/sdc-plugin/tests/base_litex/mem_1.init
deleted file mode 100644
index e69de29..0000000
--- a/sdc-plugin/tests/base_litex/mem_1.init
+++ /dev/null
diff --git a/sdc-plugin/tests/base_litex/mem_2.init b/sdc-plugin/tests/base_litex/mem_2.init
deleted file mode 100644
index 3158a57..0000000
--- a/sdc-plugin/tests/base_litex/mem_2.init
+++ /dev/null
@@ -1,7 +0,0 @@
-4e
-65
-74
-53
-6f
-43
-0
diff --git a/sdc-plugin/tests/compare_output_json.py b/sdc-plugin/tests/compare_output_json.py
deleted file mode 100644
index 3b437e8..0000000
--- a/sdc-plugin/tests/compare_output_json.py
+++ /dev/null
@@ -1,53 +0,0 @@
-#!/usr/bin/env python3
-"""
-
-This script extracts the top module cells and their corresponding parameters
-from json files produced by Yosys.
-The return code of this script is used to check if the output is equivalent.
-"""
-
-import sys
-import json
-import argparse
-
-parameters = ["CLKFBOUT_CLKOUT1_HIGH_TIME"]
-
-def read_cells(json_file):
-    with open(json_file) as f:
-        data = json.load(f)
-    f.close()
-    cells = data['modules']['top']['cells']
-    cells_parameters = dict()
-    for cell, opts in cells.items():
-        attributes = opts['parameters']
-        if len(attributes.keys()):
-            if any([x in parameters for x in attributes.keys()]):
-                cells_parameters[cell] = attributes
-    return cells_parameters
-
-
-def main(args):
-    cells = read_cells(args.json)
-    if args.update:
-        with open(args.golden, 'w') as f:
-            json.dump(cells, f, indent=2)
-    else:
-        with open(args.golden) as f:
-            cells_golden = json.load(f)
-            if cells == cells_golden:
-                exit(0)
-            else:
-                print(json.dumps(cells, indent=4))
-                json.dump(cells, open(args.json + ".fail", 'w'), indent=2)
-                print("VS")
-                print(json.dumps(cells_golden, indent=4))
-                exit(1)
-    f.close()
-
-if __name__ == "__main__":
-    parser = argparse.ArgumentParser()
-    parser.add_argument('--json', help = 'JSON to compare', required = True)
-    parser.add_argument('--golden', help = 'Golden JSON file', required = True)
-    parser.add_argument('--update', action = 'store_true', help = 'Update golden reference')
-    args = parser.parse_args()
-    main(args)
diff --git a/sdc-plugin/tests/counter/counter.golden.sdc b/sdc-plugin/tests/counter/counter.golden.sdc
new file mode 100644
index 0000000..0ab3ac8
--- /dev/null
+++ b/sdc-plugin/tests/counter/counter.golden.sdc
@@ -0,0 +1,5 @@
+create_clock -period 10 -name clk_int_1 -waveform {0 5} clk_int_1 clk_int_2 ibuf_out middle_inst_1.clk middle_inst_1.clk_int middle_inst_2.clk middle_inst_2.clk_int middle_inst_3.clk middle_inst_3.clk_int
+create_clock -period 10 -name clk -waveform {0 5} clk clk2
+create_clock -period 10 -waveform {1 6} ibuf_proxy_out
+create_clock -period 10 -waveform {2 7} $auto$clkbufmap.cc:247:execute$1918
+create_clock -period 10 -waveform {1 6} $auto$clkbufmap.cc:247:execute$1920
diff --git a/sdc-plugin/tests/counter/counter.golden.txt b/sdc-plugin/tests/counter/counter.golden.txt
new file mode 100644
index 0000000..2f3dfce
--- /dev/null
+++ b/sdc-plugin/tests/counter/counter.golden.txt
@@ -0,0 +1 @@
+clk_int_1 clk ibuf_proxy_out {$auto$clkbufmap.cc:247:execute$1918} {$auto$clkbufmap.cc:247:execute$1920}
diff --git a/sdc-plugin/tests/counter/counter.sdc b/sdc-plugin/tests/counter/counter.input.sdc
similarity index 100%
rename from sdc-plugin/tests/counter/counter.sdc
rename to sdc-plugin/tests/counter/counter.input.sdc
diff --git a/sdc-plugin/tests/counter/counter.tcl b/sdc-plugin/tests/counter/counter.tcl
index 4471078..a27caf9 100644
--- a/sdc-plugin/tests/counter/counter.tcl
+++ b/sdc-plugin/tests/counter/counter.tcl
@@ -1,5 +1,4 @@
 yosys -import
-plugin -i xdc
 plugin -i sdc
 # Import the commands from the plugins to the tcl interpreter
 yosys -import
@@ -10,33 +9,18 @@
 hierarchy -check -auto-top
 # Start flow after library reading
 synth_xilinx -vpr -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check
-# Read the design's timing constraints
-set ::env(INPUT_SDC_FILE) counter.sdc
-read_sdc $::env(INPUT_SDC_FILE)
-set clocks [get_clocks]
-puts $clocks
-propagate_clocks
-get_clocks
-stop
-#select top/w:clk %a
 
-#return
-#
-##Read the design constraints
-#read_xdc -part_json $::env(PART_JSON) $::env(INPUT_XDC_FILE)
-#
-## Map Xilinx tech library to 7-series VPR tech library.
-#read_verilog -lib ../techmaps/cells_sim.v
-#techmap -map  ../techmaps/cells_map.v
-#
-## opt_expr -undriven makes sure all nets are driven, if only by the $undef
-## net.
-#opt_expr -undriven
-#opt_clean
-#
-#setundef -zero -params
-#stat
-#
-## Write the design in JSON format.
-#write_json $::env(OUT_JSON)
-#write_blif -attr -param -cname -conn $::env(OUT_EBLIF)
+# Read the design's timing constraints
+read_sdc $::env(INPUT_SDC_FILE)
+
+# Propagate the clocks
+propagate_clocks
+
+# Write the clocks to file
+set fh [open counter.txt w]
+set clocks [get_clocks]
+puts $fh $clocks
+close $fh
+
+# Write out the SDC file after the clock propagation step
+write_sdc $::env(OUTPUT_SDC_FILE)
diff --git a/sdc-plugin/tests/counter/counter.v b/sdc-plugin/tests/counter/counter.v
index 2b671bb..564fae5 100644
--- a/sdc-plugin/tests/counter/counter.v
+++ b/sdc-plugin/tests/counter/counter.v
@@ -34,21 +34,3 @@
 
 assign out = cnt[0];
 endmodule
-/*
-module dut();
-reg clk;
-wire [1:0] out;
-
-top dut(.clk(clk), .in(2'b11), .out(out));
-initial begin
-	$dumpfile("test.vcd");
-	$dumpvars(0,dut);
-	clk = 0;
-end
-
-always
-begin
-	clk = #5 !clk;
-end
-endmodule
-*/
diff --git a/sdc-plugin/tests/counter/counter.xdc b/sdc-plugin/tests/counter/counter.xdc
deleted file mode 100644
index 327fb51..0000000
--- a/sdc-plugin/tests/counter/counter.xdc
+++ /dev/null
@@ -1,15 +0,0 @@
-set_property LOC E3 [get_ports clk]
-set_property IOSTANDARD LVCMOS33 [get_ports clk]
-
-set_property LOC J13 [get_ports {in[0]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {in[0]}]
-
-set_property LOC J14 [get_ports {in[1]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {in[1]}]
-
-set_property LOC K15 [get_ports {out[0]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {out[0]}]
-
-set_property LOC K16 [get_ports {out[1]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {out[1]}]
-
diff --git a/sdc-plugin/tests/pll/pll.golden.sdc b/sdc-plugin/tests/pll/pll.golden.sdc
new file mode 100644
index 0000000..72d68b1
--- /dev/null
+++ b/sdc-plugin/tests/pll/pll.golden.sdc
@@ -0,0 +1,7 @@
+create_clock -period 10 -waveform {0 5} clk
+create_clock -period 10 -waveform {0 5} $auto$clkbufmap.cc:247:execute$1829
+create_clock -period 2.5 -waveform {0 1.25} $auto$clkbufmap.cc:247:execute$1831
+create_clock -period 10 -waveform {1 6} $auto$clkbufmap.cc:247:execute$1827
+create_clock -period 10 -waveform {1 6} main_clkout0
+create_clock -period 2.5 -waveform {1 2.25} main_clkout1
+create_clock -period 10 -waveform {2 7} $techmap1716\FDCE_0.C
diff --git a/sdc-plugin/tests/pll/pll.input.sdc b/sdc-plugin/tests/pll/pll.input.sdc
new file mode 100644
index 0000000..00354d7
--- /dev/null
+++ b/sdc-plugin/tests/pll/pll.input.sdc
@@ -0,0 +1 @@
+create_clock -period 10 -waveform {0 5} clk
diff --git a/sdc-plugin/tests/pll/pll.tcl b/sdc-plugin/tests/pll/pll.tcl
index 237381f..e103a53 100644
--- a/sdc-plugin/tests/pll/pll.tcl
+++ b/sdc-plugin/tests/pll/pll.tcl
@@ -1,5 +1,4 @@
 yosys -import
-plugin -i xdc
 plugin -i sdc
 # Import the commands from the plugins to the tcl interpreter
 yosys -import
@@ -11,29 +10,14 @@
 
 # Start flow after library reading
 synth_xilinx -vpr -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check
-#
-#Read the design timing constraints
-set ::env(INPUT_SDC_FILE) pll.sdc
+
+# Read the design timing constraints
 read_sdc $::env(INPUT_SDC_FILE)
+
+# Propagate the clocks
 propagate_clocks
-get_clocks
-#return
-#
-##Read the design constraints
-#read_xdc -part_json $::env(PART_JSON) $::env(INPUT_XDC_FILE)
-#
-## Map Xilinx tech library to 7-series VPR tech library.
-#read_verilog -lib ../techmaps/cells_sim.v
-#techmap -map  ../techmaps/cells_map.v
-#
-## opt_expr -undriven makes sure all nets are driven, if only by the $undef
-## net.
-opt_expr -undriven
-opt_clean
-#
-setundef -zero -params
-stat
-#
-## Write the design in JSON format.
-write_json $::env(OUT_JSON)
-write_blif -attr -param -cname -conn $::env(OUT_EBLIF)
+propagate_clocks
+propagate_clocks
+
+# Write out the SDC file after the clock propagation step
+write_sdc $::env(OUTPUT_SDC_FILE)
diff --git a/sdc-plugin/tests/pll/pll.xdc b/sdc-plugin/tests/pll/pll.xdc
deleted file mode 100644
index 2f4eba3..0000000
--- a/sdc-plugin/tests/pll/pll.xdc
+++ /dev/null
@@ -1,9 +0,0 @@
-# ## clk100:0
-set_property LOC E3 [get_ports clk100]
-set_property IOSTANDARD LVCMOS33 [get_ports clk100]
-# ## cpu_reset:0
-set_property LOC C2 [get_ports cpu_reset]
-set_property IOSTANDARD LVCMOS33 [get_ports cpu_reset]
-set_property LOC H5 [get_ports {led[0]}]
-set_property LOC J5 [get_ports {led[1]}]
-set_property LOC T9 [get_ports {led[2]}]
diff --git a/sdc-plugin/tests/techmaps/cells_map.v b/sdc-plugin/tests/techmaps/cells_map.v
deleted file mode 100644
index 772f588..0000000
--- a/sdc-plugin/tests/techmaps/cells_map.v
+++ /dev/null
@@ -1,866 +0,0 @@
-// ============================================================================
-// CMT
-
-`define PLL_FRAC_PRECISION  10
-`define PLL_FIXED_WIDTH     32
-
-// Rounds a fixed point number to a given precision
-function [`PLL_FIXED_WIDTH:1] pll_round_frac
-(
-input [`PLL_FIXED_WIDTH:1] decimal,
-input [`PLL_FIXED_WIDTH:1] precision
-);
-
- if (decimal[(`PLL_FRAC_PRECISION - precision)] == 1'b1) begin
-   pll_round_frac = decimal + (1'b1 << (`PLL_FRAC_PRECISION - precision));
- end else begin
-   pll_round_frac = decimal;
- end
-
-endfunction
-
-// Computes content of the PLLs divider registers
-function [13:0] pll_divider_regs
-(
-input [ 7:0] divide,      // Max divide is 128
-input [31:0] duty_cycle   // Duty cycle is multiplied by 100,000
-);
-
-  reg [`PLL_FIXED_WIDTH:1] duty_cycle_fix;
-  reg [`PLL_FIXED_WIDTH:1] duty_cycle_min;
-  reg [`PLL_FIXED_WIDTH:1] duty_cycle_max;
-
-  reg [6:0] high_time;
-  reg [6:0] low_time;
-  reg       w_edge;
-  reg       no_count;
-
-  reg [`PLL_FIXED_WIDTH:1] temp;
-
-  if (divide >= 64) begin
-      duty_cycle_min = ((divide - 64) * 100_000) / divide;
-      duty_cycle_max = (645 / divide) * 100_00;
-      if (duty_cycle > duty_cycle_max)
-        duty_cycle = duty_cycle_max;
-      if (duty_cycle < duty_cycle_min)
-        duty_cycle = duty_cycle_min;
-  end
-
-  duty_cycle_fix = (duty_cycle << `PLL_FRAC_PRECISION) / 100_000;
-
-  if (divide == 7'h01) begin
-      high_time = 7'h01;
-      w_edge    = 1'b0;
-      low_time  = 7'h01;
-      no_count  = 1'b1;
-
-  end else begin
-      temp = pll_round_frac(duty_cycle_fix*divide, 1);
-
-      high_time = temp[`PLL_FRAC_PRECISION+7:`PLL_FRAC_PRECISION+1];
-      w_edge    = temp[`PLL_FRAC_PRECISION];
-
-      if (high_time == 7'h00) begin
-         high_time = 7'h01;
-         w_edge    = 1'b0;
-      end
-
-      if (high_time == divide) begin
-         high_time = divide - 1;
-         w_edge    = 1'b1;
-      end
-
-      low_time = divide - high_time;
-      no_count = 1'b0;
-  end
-
-  pll_divider_regs = {w_edge, no_count, high_time[5:0], low_time[5:0]};
-endfunction
-
-// Computes the PLLs phase shift registers
-function [10:0] pll_phase_regs
-(
-input        [ 7:0] divide,
-input signed [31:0] phase
-);
-
-  reg [`PLL_FIXED_WIDTH:1] phase_in_cycles;
-  reg [`PLL_FIXED_WIDTH:1] phase_fixed;
-  reg [1:0] mx;
-  reg [5:0] delay_time;
-  reg [2:0] phase_mux;
-
-  reg [`PLL_FIXED_WIDTH:1] temp;
-
-  if(phase < 0) begin
-      phase_fixed = ((phase + 360000) << `PLL_FRAC_PRECISION) / 1000;
-  end else begin
-      phase_fixed = (phase << `PLL_FRAC_PRECISION) / 1000;
-  end
-
- phase_in_cycles = (phase_fixed * divide) / 360;
- temp = pll_round_frac(phase_in_cycles, 3);
-
- mx         =  2'b00;
- phase_mux  =  temp[`PLL_FRAC_PRECISION:`PLL_FRAC_PRECISION-2];
- delay_time =  temp[`PLL_FRAC_PRECISION+6:`PLL_FRAC_PRECISION+1];
-
- pll_phase_regs = {mx, phase_mux, delay_time};
-endfunction
-
-
-// Given PLL/MMCM divide, duty_cycle and phase calculates content of the
-// CLKREG1 and CLKREG2.
-function [37:0] pll_clkregs
-(
-input [7:0]         divide,     // Max divide is 128
-input [31:0]        duty_cycle, // Multiplied by 100,000
-input signed [31:0] phase       // Phase is given in degrees (-360,000 to 360,000)
-);
-
-  reg [13:0] pll_div;   // EDGE, NO_COUNT, HIGH_TIME[5:0], LOW_TIME[5:0]
-  reg [10:0] pll_phase; // MX, PHASE_MUX[2:0], DELAY_TIME[5:0]
-
-  pll_div = pll_divider_regs(divide, duty_cycle);
-  pll_phase = pll_phase_regs(divide, phase);
-
-  pll_clkregs = {
-    // CLKREG2: RESERVED[6:0], MX[1:0], EDGE, NO_COUNT, DELAY_TIME[5:0]
-    6'h00, pll_phase[10:9], pll_div[13:12], pll_phase[5:0],
-    // CLKREG1: PHASE_MUX[3:0], RESERVED, HIGH_TIME[5:0], LOW_TIME[5:0]
-    pll_phase[8:6], 1'b0, pll_div[11:0]
-  };
-
-endfunction
-
-// This function takes the divide value and outputs the necessary lock values
-function [39:0] pll_lktable_lookup
-(
-input [6:0] divide // Max divide is 64
-);
-
-  reg [2559:0] lookup;
-
-  lookup = {
-    // This table is composed of:
-    // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
-    40'b00110_00110_1111101000_1111101001_0000000001,
-    40'b00110_00110_1111101000_1111101001_0000000001,
-    40'b01000_01000_1111101000_1111101001_0000000001,
-    40'b01011_01011_1111101000_1111101001_0000000001,
-    40'b01110_01110_1111101000_1111101001_0000000001,
-    40'b10001_10001_1111101000_1111101001_0000000001,
-    40'b10011_10011_1111101000_1111101001_0000000001,
-    40'b10110_10110_1111101000_1111101001_0000000001,
-    40'b11001_11001_1111101000_1111101001_0000000001,
-    40'b11100_11100_1111101000_1111101001_0000000001,
-    40'b11111_11111_1110000100_1111101001_0000000001,
-    40'b11111_11111_1100111001_1111101001_0000000001,
-    40'b11111_11111_1011101110_1111101001_0000000001,
-    40'b11111_11111_1010111100_1111101001_0000000001,
-    40'b11111_11111_1010001010_1111101001_0000000001,
-    40'b11111_11111_1001110001_1111101001_0000000001,
-    40'b11111_11111_1000111111_1111101001_0000000001,
-    40'b11111_11111_1000100110_1111101001_0000000001,
-    40'b11111_11111_1000001101_1111101001_0000000001,
-    40'b11111_11111_0111110100_1111101001_0000000001,
-    40'b11111_11111_0111011011_1111101001_0000000001,
-    40'b11111_11111_0111000010_1111101001_0000000001,
-    40'b11111_11111_0110101001_1111101001_0000000001,
-    40'b11111_11111_0110010000_1111101001_0000000001,
-    40'b11111_11111_0110010000_1111101001_0000000001,
-    40'b11111_11111_0101110111_1111101001_0000000001,
-    40'b11111_11111_0101011110_1111101001_0000000001,
-    40'b11111_11111_0101011110_1111101001_0000000001,
-    40'b11111_11111_0101000101_1111101001_0000000001,
-    40'b11111_11111_0101000101_1111101001_0000000001,
-    40'b11111_11111_0100101100_1111101001_0000000001,
-    40'b11111_11111_0100101100_1111101001_0000000001,
-    40'b11111_11111_0100101100_1111101001_0000000001,
-    40'b11111_11111_0100010011_1111101001_0000000001,
-    40'b11111_11111_0100010011_1111101001_0000000001,
-    40'b11111_11111_0100010011_1111101001_0000000001,
-    40'b11111_11111_0011111010_1111101001_0000000001,
-    40'b11111_11111_0011111010_1111101001_0000000001,
-    40'b11111_11111_0011111010_1111101001_0000000001,
-    40'b11111_11111_0011111010_1111101001_0000000001,
-    40'b11111_11111_0011111010_1111101001_0000000001,
-    40'b11111_11111_0011111010_1111101001_0000000001,
-    40'b11111_11111_0011111010_1111101001_0000000001,
-    40'b11111_11111_0011111010_1111101001_0000000001,
-    40'b11111_11111_0011111010_1111101001_0000000001,
-    40'b11111_11111_0011111010_1111101001_0000000001,
-    40'b11111_11111_0011111010_1111101001_0000000001,
-    40'b11111_11111_0011111010_1111101001_0000000001,
-    40'b11111_11111_0011111010_1111101001_0000000001,
-    40'b11111_11111_0011111010_1111101001_0000000001,
-    40'b11111_11111_0011111010_1111101001_0000000001,
-    40'b11111_11111_0011111010_1111101001_0000000001,
-    40'b11111_11111_0011111010_1111101001_0000000001,
-    40'b11111_11111_0011111010_1111101001_0000000001,
-    40'b11111_11111_0011111010_1111101001_0000000001,
-    40'b11111_11111_0011111010_1111101001_0000000001,
-    40'b11111_11111_0011111010_1111101001_0000000001,
-    40'b11111_11111_0011111010_1111101001_0000000001,
-    40'b11111_11111_0011111010_1111101001_0000000001,
-    40'b11111_11111_0011111010_1111101001_0000000001,
-    40'b11111_11111_0011111010_1111101001_0000000001,
-    40'b11111_11111_0011111010_1111101001_0000000001,
-    40'b11111_11111_0011111010_1111101001_0000000001,
-    40'b11111_11111_0011111010_1111101001_0000000001
-    };
-
-  pll_lktable_lookup = lookup[ ((64-divide)*40) +: 40];
-endfunction
-
-// This function takes the divide value and the bandwidth setting of the PLL
-// and outputs the digital filter settings necessary.
-function [9:0] pll_table_lookup
-(
-input [6:0]   divide, // Max divide is 64
-input [8*9:0] BANDWIDTH
-);
-
-  reg [639:0] lookup_low;
-  reg [639:0] lookup_high;
-  reg [639:0] lookup_optimized;
-
-  reg [9:0] lookup_entry;
-
-  lookup_low = {
-    // CP_RES_LFHF
-    10'b0010_1111_00,
-    10'b0010_1111_00,
-    10'b0010_0111_00,
-    10'b0010_1101_00,
-    10'b0010_0101_00,
-    10'b0010_0101_00,
-    10'b0010_1001_00,
-    10'b0010_1110_00,
-    10'b0010_1110_00,
-    10'b0010_0001_00,
-    10'b0010_0001_00,
-    10'b0010_0110_00,
-    10'b0010_0110_00,
-    10'b0010_0110_00,
-    10'b0010_0110_00,
-    10'b0010_1010_00,
-    10'b0010_1010_00,
-    10'b0010_1010_00,
-    10'b0010_1010_00,
-    10'b0010_1100_00,
-    10'b0010_1100_00,
-    10'b0010_1100_00,
-    10'b0010_1100_00,
-    10'b0010_1100_00,
-    10'b0010_1100_00,
-    10'b0010_1100_00,
-    10'b0010_1100_00,
-    10'b0010_1100_00,
-    10'b0010_1100_00,
-    10'b0010_1100_00,
-    10'b0010_0010_00,
-    10'b0010_0010_00,
-    10'b0010_0010_00,
-    10'b0010_0010_00,
-    10'b0010_0010_00,
-    10'b0010_0010_00,
-    10'b0010_0010_00,
-    10'b0010_0010_00,
-    10'b0010_0010_00,
-    10'b0010_0010_00,
-    10'b0011_1100_00,
-    10'b0011_1100_00,
-    10'b0011_1100_00,
-    10'b0011_1100_00,
-    10'b0011_1100_00,
-    10'b0011_1100_00,
-    10'b0011_1100_00,
-    10'b0010_0100_00,
-    10'b0010_0100_00,
-    10'b0010_0100_00,
-    10'b0010_0100_00,
-    10'b0010_0100_00,
-    10'b0010_0100_00,
-    10'b0010_0100_00,
-    10'b0010_0100_00,
-    10'b0010_0100_00,
-    10'b0010_0100_00,
-    10'b0010_0100_00,
-    10'b0010_0100_00,
-    10'b0010_0100_00,
-    10'b0010_0100_00,
-    10'b0010_0100_00,
-    10'b0010_0100_00,
-    10'b0010_0100_00
-  };
-
-  lookup_high = {
-    // CP_RES_LFHF
-    10'b0011_0111_00,
-    10'b0011_0111_00,
-    10'b0101_1111_00,
-    10'b0111_1111_00,
-    10'b0111_1011_00,
-    10'b1101_0111_00,
-    10'b1110_1011_00,
-    10'b1110_1101_00,
-    10'b1111_1101_00,
-    10'b1111_0111_00,
-    10'b1111_1011_00,
-    10'b1111_1101_00,
-    10'b1111_0011_00,
-    10'b1110_0101_00,
-    10'b1111_0101_00,
-    10'b1111_0101_00,
-    10'b1111_0101_00,
-    10'b1111_0101_00,
-    10'b0111_0110_00,
-    10'b0111_0110_00,
-    10'b0111_0110_00,
-    10'b0111_0110_00,
-    10'b0101_1100_00,
-    10'b0101_1100_00,
-    10'b0101_1100_00,
-    10'b1100_0001_00,
-    10'b1100_0001_00,
-    10'b1100_0001_00,
-    10'b1100_0001_00,
-    10'b1100_0001_00,
-    10'b1100_0001_00,
-    10'b1100_0001_00,
-    10'b1100_0001_00,
-    10'b0100_0010_00,
-    10'b0100_0010_00,
-    10'b0100_0010_00,
-    10'b0010_1000_00,
-    10'b0010_1000_00,
-    10'b0010_1000_00,
-    10'b0011_0100_00,
-    10'b0010_1000_00,
-    10'b0010_1000_00,
-    10'b0010_1000_00,
-    10'b0010_1000_00,
-    10'b0010_1000_00,
-    10'b0010_1000_00,
-    10'b0010_1000_00,
-    10'b0010_1000_00,
-    10'b0010_1000_00,
-    10'b0010_1000_00,
-    10'b0010_1000_00,
-    10'b0010_1000_00,
-    10'b0010_1000_00,
-    10'b0100_1100_00,
-    10'b0100_1100_00,
-    10'b0100_1100_00,
-    10'b0100_1100_00,
-    10'b0100_1100_00,
-    10'b0100_1100_00,
-    10'b0100_1100_00,
-    10'b0010_0100_00,
-    10'b0010_0100_00,
-    10'b0010_0100_00,
-    10'b0010_0100_00
-  };
-
-  lookup_optimized = {
-    // CP_RES_LFHF
-    10'b0011_0111_00,
-    10'b0011_0111_00,
-    10'b0101_1111_00,
-    10'b0111_1111_00,
-    10'b0111_1011_00,
-    10'b1101_0111_00,
-    10'b1110_1011_00,
-    10'b1110_1101_00,
-    10'b1111_1101_00,
-    10'b1111_0111_00,
-    10'b1111_1011_00,
-    10'b1111_1101_00,
-    10'b1111_0011_00,
-    10'b1110_0101_00,
-    10'b1111_0101_00,
-    10'b1111_0101_00,
-    10'b1111_0101_00,
-    10'b1111_0101_00,
-    10'b0111_0110_00,
-    10'b0111_0110_00,
-    10'b0111_0110_00,
-    10'b0111_0110_00,
-    10'b0101_1100_00,
-    10'b0101_1100_00,
-    10'b0101_1100_00,
-    10'b1100_0001_00,
-    10'b1100_0001_00,
-    10'b1100_0001_00,
-    10'b1100_0001_00,
-    10'b1100_0001_00,
-    10'b1100_0001_00,
-    10'b1100_0001_00,
-    10'b1100_0001_00,
-    10'b0100_0010_00,
-    10'b0100_0010_00,
-    10'b0100_0010_00,
-    10'b0010_1000_00,
-    10'b0010_1000_00,
-    10'b0010_1000_00,
-    10'b0011_0100_00,
-    10'b0010_1000_00,
-    10'b0010_1000_00,
-    10'b0010_1000_00,
-    10'b0010_1000_00,
-    10'b0010_1000_00,
-    10'b0010_1000_00,
-    10'b0010_1000_00,
-    10'b0010_1000_00,
-    10'b0010_1000_00,
-    10'b0010_1000_00,
-    10'b0010_1000_00,
-    10'b0010_1000_00,
-    10'b0010_1000_00,
-    10'b0100_1100_00,
-    10'b0100_1100_00,
-    10'b0100_1100_00,
-    10'b0100_1100_00,
-    10'b0100_1100_00,
-    10'b0100_1100_00,
-    10'b0100_1100_00,
-    10'b0010_0100_00,
-    10'b0010_0100_00,
-    10'b0010_0100_00,
-    10'b0010_0100_00
-  };
-
-  if (BANDWIDTH == "LOW") begin
-    pll_table_lookup = lookup_low[((64-divide)*10) +: 10];
-  end else if (BANDWIDTH == "HIGH") begin
-    pll_table_lookup = lookup_high[((64-divide)*10) +: 10];
-  end else if (BANDWIDTH == "OPTIMIZED") begin
-    pll_table_lookup = lookup_optimized[((64-divide)*10) +: 10];
-  end
-
-endfunction
-
-// ............................................................................
-// IMPORTANT NOTE: Due to lack of support for real type parameters in Yosys
-// the PLL parameters that define duty cycles and phase shifts have to be
-// provided as integers! The DUTY_CYCLE is expressed as % of high time times
-// 1000 whereas the PHASE is expressed in degrees times 1000.
-
-// PLLE2_ADV
-module PLLE2_ADV
-(
-input         CLKFBIN,
-input         CLKIN1,
-input         CLKIN2,
-input         CLKINSEL,
-
-output        CLKFBOUT,
-output        CLKOUT0,
-output        CLKOUT1,
-output        CLKOUT2,
-output        CLKOUT3,
-output        CLKOUT4,
-output        CLKOUT5,
-
-input         PWRDWN,
-input         RST,
-output        LOCKED,
-
-input         DCLK,
-input         DEN,
-input         DWE,
-output        DRDY,
-input  [ 6:0] DADDR,
-input  [15:0] DI,
-output [15:0] DO
-);
-
-  parameter _TECHMAP_CONSTMSK_CLKINSEL_ = 0;
-  parameter _TECHMAP_CONSTVAL_CLKINSEL_ = 0;
-
-  parameter _TECHMAP_CONSTMSK_RST_      = 0;
-  parameter _TECHMAP_CONSTVAL_RST_      = 0;
-  parameter _TECHMAP_CONSTMSK_PWRDWN_   = 0;
-  parameter _TECHMAP_CONSTVAL_PWRDWN_   = 0;
-
-  parameter _TECHMAP_CONSTMSK_CLKFBOUT_ = 0;
-  parameter _TECHMAP_CONSTVAL_CLKFBOUT_ = 0;
-  parameter _TECHMAP_CONSTMSK_CLKOUT0_  = 0;
-  parameter _TECHMAP_CONSTVAL_CLKOUT0_  = 0;
-  parameter _TECHMAP_CONSTMSK_CLKOUT1_  = 0;
-  parameter _TECHMAP_CONSTVAL_CLKOUT1_  = 0;
-  parameter _TECHMAP_CONSTMSK_CLKOUT2_  = 0;
-  parameter _TECHMAP_CONSTVAL_CLKOUT2_  = 0;
-  parameter _TECHMAP_CONSTMSK_CLKOUT3_  = 0;
-  parameter _TECHMAP_CONSTVAL_CLKOUT3_  = 0;
-  parameter _TECHMAP_CONSTMSK_CLKOUT4_  = 0;
-  parameter _TECHMAP_CONSTVAL_CLKOUT4_  = 0;
-  parameter _TECHMAP_CONSTMSK_CLKOUT5_  = 0;
-  parameter _TECHMAP_CONSTVAL_CLKOUT5_  = 0;
-
-  parameter _TECHMAP_CONSTMSK_DCLK_     = 0;
-  parameter _TECHMAP_CONSTVAL_DCLK_     = 0;
-  parameter _TECHMAP_CONSTMSK_DEN_      = 0;
-  parameter _TECHMAP_CONSTVAL_DEN_      = 0;
-  parameter _TECHMAP_CONSTMSK_DWE_      = 0;
-  parameter _TECHMAP_CONSTVAL_DWE_      = 0;
-
-  parameter IS_CLKINSEL_INVERTED = 1'b0;
-  parameter IS_RST_INVERTED = 1'b0;
-  parameter IS_PWRDWN_INVERTED = 1'b0;
-
-  parameter BANDWIDTH = "OPTIMIZED";
-  parameter STARTUP_WAIT = "FALSE";
-  parameter COMPENSATION = "ZHOLD";
-
-  parameter CLKIN1_PERIOD = 0.0;
-  parameter REF_JITTER1 = 0.01;
-  parameter CLKIN2_PERIOD = 0.0;
-  parameter REF_JITTER2 = 0.01;
-
-  parameter [5:0] DIVCLK_DIVIDE = 1;
-
-  parameter [5:0] CLKFBOUT_MULT = 1;
-  parameter CLKFBOUT_PHASE = 0;
-
-  parameter [6:0] CLKOUT0_DIVIDE = 1;
-  parameter CLKOUT0_DUTY_CYCLE = 50000;
-  parameter signed CLKOUT0_PHASE = 0;
-
-  parameter [6:0] CLKOUT1_DIVIDE = 1;
-  parameter CLKOUT1_DUTY_CYCLE = 50000;
-  parameter signed CLKOUT1_PHASE = 0;
-
-  parameter [6:0] CLKOUT2_DIVIDE = 1;
-  parameter CLKOUT2_DUTY_CYCLE = 50000;
-  parameter signed CLKOUT2_PHASE = 0;
-
-  parameter [6:0] CLKOUT3_DIVIDE = 1;
-  parameter CLKOUT3_DUTY_CYCLE = 50000;
-  parameter signed CLKOUT3_PHASE = 0;
-
-  parameter [6:0] CLKOUT4_DIVIDE = 1;
-  parameter CLKOUT4_DUTY_CYCLE = 50000;
-  parameter signed CLKOUT4_PHASE = 0;
-
-  parameter [6:0] CLKOUT5_DIVIDE = 1;
-  parameter CLKOUT5_DUTY_CYCLE = 50000;
-  parameter signed CLKOUT5_PHASE = 0;
-
-  // Compute PLL's registers content
-  localparam CLKFBOUT_REGS = pll_clkregs(CLKFBOUT_MULT, 50000, CLKFBOUT_PHASE);
-  localparam DIVCLK_REGS   = pll_clkregs(DIVCLK_DIVIDE, 50000, 0);
-
-  localparam CLKOUT0_REGS  = pll_clkregs(CLKOUT0_DIVIDE, CLKOUT0_DUTY_CYCLE, CLKOUT0_PHASE);
-  localparam CLKOUT1_REGS  = pll_clkregs(CLKOUT1_DIVIDE, CLKOUT1_DUTY_CYCLE, CLKOUT1_PHASE);
-  localparam CLKOUT2_REGS  = pll_clkregs(CLKOUT2_DIVIDE, CLKOUT2_DUTY_CYCLE, CLKOUT2_PHASE);
-  localparam CLKOUT3_REGS  = pll_clkregs(CLKOUT3_DIVIDE, CLKOUT3_DUTY_CYCLE, CLKOUT3_PHASE);
-  localparam CLKOUT4_REGS  = pll_clkregs(CLKOUT4_DIVIDE, CLKOUT4_DUTY_CYCLE, CLKOUT4_PHASE);
-  localparam CLKOUT5_REGS  = pll_clkregs(CLKOUT5_DIVIDE, CLKOUT5_DUTY_CYCLE, CLKOUT5_PHASE);
-
-  // Handle inputs that should have certain logic levels when left unconnected
-  generate if (_TECHMAP_CONSTMSK_CLKINSEL_ == 1) begin
-    localparam INV_CLKINSEL = !_TECHMAP_CONSTVAL_CLKINSEL_;
-    wire clkinsel = 1'b1;
-  end else if (_TECHMAP_CONSTVAL_CLKINSEL_ == 0) begin
-    localparam INV_CLKINSEL = IS_CLKINSEL_INVERTED;
-    wire clkinsel = 1'b1;
-  end else begin
-    localparam INV_CLKINSEL = IS_CLKINSEL_INVERTED;
-    wire clkinsel = CLKINSEL;
-  end endgenerate
-
-  generate if (_TECHMAP_CONSTMSK_PWRDWN_ == 1) begin
-    localparam INV_PWRDWN =  !_TECHMAP_CONSTVAL_PWRDWN_;
-    wire pwrdwn = 1'b1;
-  end else if (_TECHMAP_CONSTVAL_PWRDWN_ == 0) begin
-    localparam INV_PWRDWN = ~IS_PWRDWN_INVERTED;
-    wire pwrdwn = 1'b1;
-  end else begin
-    localparam INV_PWRDWN =  IS_PWRDWN_INVERTED;
-    wire pwrdwn = PWRDWN;
-  end endgenerate
-
-  generate if (_TECHMAP_CONSTMSK_RST_ == 1) begin
-    localparam INV_RST =  !_TECHMAP_CONSTVAL_PWRDWN_;
-    wire rst = 1'b1;
-  end else if (_TECHMAP_CONSTVAL_RST_ == 0) begin
-    localparam INV_RST = ~IS_RST_INVERTED;
-    wire rst = 1'b1;
-  end else begin
-    localparam INV_RST =  IS_RST_INVERTED;
-    wire rst = RST;
-  end endgenerate
-
-  generate if (_TECHMAP_CONSTMSK_DCLK_ == 1)
-    wire dclk = _TECHMAP_CONSTVAL_DCLK_;
-  else if (_TECHMAP_CONSTVAL_DCLK_ == 0)
-    wire dclk = 1'b0;
-  else
-    wire dclk = DCLK;
-  endgenerate
-  
-  generate if (_TECHMAP_CONSTMSK_DEN_ == 1)
-    wire den = _TECHMAP_CONSTVAL_DEN_;
-  else if (_TECHMAP_CONSTVAL_DEN_ == 0)
-    wire den = 1'b0;
-  else
-    wire den = DEN;
-  endgenerate
-
-  generate if (_TECHMAP_CONSTMSK_DWE_ == 1)
-    wire dwe = _TECHMAP_CONSTVAL_DWE_;
-  else if (_TECHMAP_CONSTVAL_DWE_ == 0)
-    wire dwe = 1'b0;
-  else
-    wire dwe = DWE;
-  endgenerate
-
-  // The substituted cell
-  PLLE2_ADV_VPR #
-  (
-  // Inverters
-  .INV_CLKINSEL(INV_CLKINSEL),
-  .ZINV_PWRDWN (INV_PWRDWN),
-  .ZINV_RST    (INV_RST),
-
-  // Straight mapped parameters
-  .STARTUP_WAIT(STARTUP_WAIT == "TRUE"),
-
-  // Lookup tables
-  .LKTABLE(pll_lktable_lookup(CLKFBOUT_MULT)),
-  .TABLE(pll_table_lookup(CLKFBOUT_MULT, BANDWIDTH)),
-
-  // FIXME: How to compute values the two below ?
-  .FILTREG1_RESERVED(12'b0000_00001000),
-  .LOCKREG3_RESERVED(1'b1),
-
-  // Clock feedback settings
-  .CLKFBOUT_CLKOUT1_HIGH_TIME   (CLKFBOUT_REGS[11:6]),
-  .CLKFBOUT_CLKOUT1_LOW_TIME    (CLKFBOUT_REGS[5:0]),
-  .CLKFBOUT_CLKOUT1_PHASE_MUX   (CLKFBOUT_REGS[15:13]),
-  .CLKFBOUT_CLKOUT2_DELAY_TIME  (CLKFBOUT_REGS[21:16]),
-  .CLKFBOUT_CLKOUT2_EDGE        (CLKFBOUT_REGS[23]),
-  .CLKFBOUT_CLKOUT2_NO_COUNT    (CLKFBOUT_REGS[22]),
-
-  // Internal VCO divider settings
-  .DIVCLK_DIVCLK_HIGH_TIME      (DIVCLK_REGS[11:6]),
-  .DIVCLK_DIVCLK_LOW_TIME       (DIVCLK_REGS[5:0]),
-  .DIVCLK_DIVCLK_NO_COUNT       (DIVCLK_REGS[22]),
-  .DIVCLK_DIVCLK_EDGE           (DIVCLK_REGS[23]),
-
-  // CLKOUT0
-  .CLKOUT0_CLKOUT1_HIGH_TIME    (CLKOUT0_REGS[11:6]),
-  .CLKOUT0_CLKOUT1_LOW_TIME     (CLKOUT0_REGS[5:0]),
-  .CLKOUT0_CLKOUT1_PHASE_MUX    (CLKOUT0_REGS[15:13]),
-  .CLKOUT0_CLKOUT2_DELAY_TIME   (CLKOUT0_REGS[21:16]),
-  .CLKOUT0_CLKOUT2_EDGE         (CLKOUT0_REGS[23]),
-  .CLKOUT0_CLKOUT2_NO_COUNT     (CLKOUT0_REGS[22]),
-
-  // CLKOUT1
-  .CLKOUT1_CLKOUT1_HIGH_TIME    (CLKOUT1_REGS[11:6]),
-  .CLKOUT1_CLKOUT1_LOW_TIME     (CLKOUT1_REGS[5:0]),
-  .CLKOUT1_CLKOUT1_PHASE_MUX    (CLKOUT1_REGS[15:13]),
-  .CLKOUT1_CLKOUT2_DELAY_TIME   (CLKOUT1_REGS[21:16]),
-  .CLKOUT1_CLKOUT2_EDGE         (CLKOUT1_REGS[23]),
-  .CLKOUT1_CLKOUT2_NO_COUNT     (CLKOUT1_REGS[22]),
-
-  // CLKOUT2
-  .CLKOUT2_CLKOUT1_HIGH_TIME    (CLKOUT2_REGS[11:6]),
-  .CLKOUT2_CLKOUT1_LOW_TIME     (CLKOUT2_REGS[5:0]),
-  .CLKOUT2_CLKOUT1_PHASE_MUX    (CLKOUT2_REGS[15:13]),
-  .CLKOUT2_CLKOUT2_DELAY_TIME   (CLKOUT2_REGS[21:16]),
-  .CLKOUT2_CLKOUT2_EDGE         (CLKOUT2_REGS[23]),
-  .CLKOUT2_CLKOUT2_NO_COUNT     (CLKOUT2_REGS[22]),
-
-  // CLKOUT3
-  .CLKOUT3_CLKOUT1_HIGH_TIME    (CLKOUT3_REGS[11:6]),
-  .CLKOUT3_CLKOUT1_LOW_TIME     (CLKOUT3_REGS[5:0]),
-  .CLKOUT3_CLKOUT1_PHASE_MUX    (CLKOUT3_REGS[15:13]),
-  .CLKOUT3_CLKOUT2_DELAY_TIME   (CLKOUT3_REGS[21:16]),
-  .CLKOUT3_CLKOUT2_EDGE         (CLKOUT3_REGS[23]),
-  .CLKOUT3_CLKOUT2_NO_COUNT     (CLKOUT3_REGS[22]),
-
-  // CLKOUT4
-  .CLKOUT4_CLKOUT1_HIGH_TIME    (CLKOUT4_REGS[11:6]),
-  .CLKOUT4_CLKOUT1_LOW_TIME     (CLKOUT4_REGS[5:0]),
-  .CLKOUT4_CLKOUT1_PHASE_MUX    (CLKOUT4_REGS[15:13]),
-  .CLKOUT4_CLKOUT2_DELAY_TIME   (CLKOUT4_REGS[21:16]),
-  .CLKOUT4_CLKOUT2_EDGE         (CLKOUT4_REGS[23]),
-  .CLKOUT4_CLKOUT2_NO_COUNT     (CLKOUT4_REGS[22]),
-
-  // CLKOUT5
-  .CLKOUT5_CLKOUT1_HIGH_TIME    (CLKOUT5_REGS[11:6]),
-  .CLKOUT5_CLKOUT1_LOW_TIME     (CLKOUT5_REGS[5:0]),
-  .CLKOUT5_CLKOUT1_PHASE_MUX    (CLKOUT5_REGS[15:13]),
-  .CLKOUT5_CLKOUT2_DELAY_TIME   (CLKOUT5_REGS[21:16]),
-  .CLKOUT5_CLKOUT2_EDGE         (CLKOUT5_REGS[23]),
-  .CLKOUT5_CLKOUT2_NO_COUNT     (CLKOUT5_REGS[22]),
-
-  // Clock output enable controls
-  .CLKFBOUT_CLKOUT1_OUTPUT_ENABLE(_TECHMAP_CONSTVAL_CLKFBOUT_ === 1'bX),
-
-  .CLKOUT0_CLKOUT1_OUTPUT_ENABLE(_TECHMAP_CONSTVAL_CLKOUT0_ === 1'bX),
-  .CLKOUT1_CLKOUT1_OUTPUT_ENABLE(_TECHMAP_CONSTVAL_CLKOUT1_ === 1'bX),
-  .CLKOUT2_CLKOUT1_OUTPUT_ENABLE(_TECHMAP_CONSTVAL_CLKOUT2_ === 1'bX),
-  .CLKOUT3_CLKOUT1_OUTPUT_ENABLE(_TECHMAP_CONSTVAL_CLKOUT3_ === 1'bX),
-  .CLKOUT4_CLKOUT1_OUTPUT_ENABLE(_TECHMAP_CONSTVAL_CLKOUT4_ === 1'bX),
-  .CLKOUT5_CLKOUT1_OUTPUT_ENABLE(_TECHMAP_CONSTVAL_CLKOUT5_ === 1'bX)
-  )
-  _TECHMAP_REPLACE_
-  (
-  .CLKFBIN(CLKFBIN),
-  .CLKIN1(CLKIN1),
-  .CLKIN2(CLKIN2),
-  .CLKFBOUT(CLKFBOUT),
-  .CLKOUT0(CLKOUT0),
-  .CLKOUT1(CLKOUT1),
-  .CLKOUT2(CLKOUT2),
-  .CLKOUT3(CLKOUT3),
-  .CLKOUT4(CLKOUT4),
-  .CLKOUT5(CLKOUT5),
-
-  .CLKINSEL (clkinsel),
-
-  .PWRDWN   (pwrdwn),
-  .RST      (rst),
-  .LOCKED   (LOCKED),
-
-  .DCLK (dclk),
-  .DEN  (den),
-  .DWE  (dwe),
-  .DRDY (DRDY),
-  .DADDR(DADDR),
-  .DI   (DI),
-  .DO   (DO)
-  );
-
-endmodule
-
-// PLLE2_BASE
-module PLLE2_BASE
-(
-input         CLKFBIN,
-input         CLKIN,
-
-output        CLKFBOUT,
-output        CLKOUT0,
-output        CLKOUT1,
-output        CLKOUT2,
-output        CLKOUT3,
-output        CLKOUT4,
-output        CLKOUT5,
-
-input         RST,
-output        LOCKED
-);
-
-  parameter IS_CLKINSEL_INVERTED = 1'b0;
-  parameter IS_RST_INVERTED = 1'b0;
-
-  parameter BANDWIDTH = "OPTIMIZED";
-  parameter STARTUP_WAIT = "FALSE";
-
-  parameter CLKIN1_PERIOD = 0.0;
-  parameter REF_JITTER1 = 0.1;
-
-  parameter [5:0] DIVCLK_DIVIDE = 1;
-
-  parameter [5:0] CLKFBOUT_MULT = 1;
-  parameter signed CLKFBOUT_PHASE = 0;
-
-  parameter [6:0] CLKOUT0_DIVIDE = 1;
-  parameter CLKOUT0_DUTY_CYCLE = 50000;
-  parameter signed CLKOUT0_PHASE = 0;
-
-  parameter [6:0] CLKOUT1_DIVIDE = 1;
-  parameter CLKOUT1_DUTY_CYCLE = 50000;
-  parameter signed CLKOUT1_PHASE = 0;
-
-  parameter [6:0] CLKOUT2_DIVIDE = 1;
-  parameter CLKOUT2_DUTY_CYCLE = 50000;
-  parameter signed CLKOUT2_PHASE = 0;
-
-  parameter [6:0] CLKOUT3_DIVIDE = 1;
-  parameter CLKOUT3_DUTY_CYCLE = 50000;
-  parameter signed CLKOUT3_PHASE = 0;
-
-  parameter [6:0] CLKOUT4_DIVIDE = 1;
-  parameter CLKOUT4_DUTY_CYCLE = 50000;
-  parameter signed CLKOUT4_PHASE = 0;
-
-  parameter [6:0] CLKOUT5_DIVIDE = 1;
-  parameter CLKOUT5_DUTY_CYCLE = 50000;
-  parameter signed CLKOUT5_PHASE = 0;
-
-  // The substituted cell
-  PLLE2_ADV #
-  (
-  .IS_CLKINSEL_INVERTED(IS_CLKINSEL_INVERTED),
-  .IS_RST_INVERTED(IS_RST_INVERTED),
-  .IS_PWRDWN_INVERTED(1'b0),
-
-  .BANDWIDTH(BANDWIDTH),
-  .STARTUP_WAIT(STARTUP_WAIT),
-
-  .CLKIN1_PERIOD(CLKIN1_PERIOD),
-  .REF_JITTER1(REF_JITTER1),
-
-  .DIVCLK_DIVIDE(DIVCLK_DIVIDE),
-
-  .CLKFBOUT_MULT(CLKFBOUT_MULT),
-  .CLKFBOUT_PHASE(CLKFBOUT_PHASE),
-
-  .CLKOUT0_DIVIDE(CLKOUT0_DIVIDE),
-  .CLKOUT0_DUTY_CYCLE(CLKOUT0_DUTY_CYCLE),
-  .CLKOUT0_PHASE(CLKOUT0_PHASE),
-
-  .CLKOUT1_DIVIDE(CLKOUT1_DIVIDE),
-  .CLKOUT1_DUTY_CYCLE(CLKOUT1_DUTY_CYCLE),
-  .CLKOUT1_PHASE(CLKOUT1_PHASE),
-
-  .CLKOUT2_DIVIDE(CLKOUT2_DIVIDE),
-  .CLKOUT2_DUTY_CYCLE(CLKOUT2_DUTY_CYCLE),
-  .CLKOUT2_PHASE(CLKOUT2_PHASE),
-
-  .CLKOUT3_DIVIDE(CLKOUT3_DIVIDE),
-  .CLKOUT3_DUTY_CYCLE(CLKOUT3_DUTY_CYCLE),
-  .CLKOUT3_PHASE(CLKOUT3_PHASE),
-
-  .CLKOUT4_DIVIDE(CLKOUT4_DIVIDE),
-  .CLKOUT4_DUTY_CYCLE(CLKOUT4_DUTY_CYCLE),
-  .CLKOUT4_PHASE(CLKOUT4_PHASE),
-
-  .CLKOUT5_DIVIDE(CLKOUT5_DIVIDE),
-  .CLKOUT5_DUTY_CYCLE(CLKOUT5_DUTY_CYCLE),
-  .CLKOUT5_PHASE(CLKOUT5_PHASE)
-  )
-  _TECHMAP_REPLACE_
-  (
-  .CLKFBIN(CLKFBIN),
-  .CLKIN1(CLKIN),
-  .CLKINSEL(1'b1),
-
-  .CLKFBOUT(CLKFBOUT),
-  .CLKOUT0(CLKOUT0),
-  .CLKOUT1(CLKOUT1),
-  .CLKOUT2(CLKOUT2),
-  .CLKOUT3(CLKOUT3),
-  .CLKOUT4(CLKOUT4),
-  .CLKOUT5(CLKOUT5),
-
-  .PWRDWN(1'b0),
-  .RST(RST),
-  .LOCKED(LOCKED),
-
-  .DCLK(1'b0),
-  .DEN(1'b0),
-  .DWE(1'b0),
-  .DRDY(),
-  .DADDR(7'd0),
-  .DI(16'd0),
-  .DO()
-  );
-
-endmodule
diff --git a/sdc-plugin/tests/techmaps/cells_sim.v b/sdc-plugin/tests/techmaps/cells_sim.v
deleted file mode 100644
index 607f98b..0000000
--- a/sdc-plugin/tests/techmaps/cells_sim.v
+++ /dev/null
@@ -1,145 +0,0 @@
-// ============================================================================
-// CMT
-
-// PLLE2_ADV_VPR
-(* blackbox *)
-module PLLE2_ADV_VPR
-(
-input         CLKFBIN,
-input         CLKIN1,
-input         CLKIN2,
-input         CLKINSEL,
-
-output        CLKFBOUT,
-output        CLKOUT0,
-output        CLKOUT1,
-output        CLKOUT2,
-output        CLKOUT3,
-output        CLKOUT4,
-output        CLKOUT5,
-
-input         PWRDWN,
-input         RST,
-output        LOCKED,
-
-input         DCLK,
-input         DEN,
-input         DWE,
-output        DRDY,
-input  [ 6:0] DADDR,
-input  [15:0] DI,
-output [15:0] DO
-);
-
-  parameter [0:0] INV_CLKINSEL = 1'd0;
-  parameter [0:0] ZINV_PWRDWN = 1'd0;
-  parameter [0:0] ZINV_RST = 1'd1;
-
-  parameter [0:0] STARTUP_WAIT = 1'd0;
-
-  // Tables
-  parameter [9:0] TABLE = 10'd0;
-  parameter [39:0] LKTABLE = 40'd0;
-  parameter [15:0] POWER_REG = 16'd0;
-  parameter [11:0] FILTREG1_RESERVED = 12'd0;
-  parameter [9:0] FILTREG2_RESERVED = 10'd0;
-  parameter [5:0] LOCKREG1_RESERVED = 6'd0;
-  parameter [0:0] LOCKREG2_RESERVED = 1'b0;
-  parameter [0:0] LOCKREG3_RESERVED = 1'b0;
-
-  // DIVCLK
-  parameter [5:0] DIVCLK_DIVCLK_HIGH_TIME = 6'd0;
-  parameter [5:0] DIVCLK_DIVCLK_LOW_TIME = 6'd0;
-  parameter [0:0] DIVCLK_DIVCLK_NO_COUNT = 1'b1;
-  parameter [0:0] DIVCLK_DIVCLK_EDGE = 1'b0;
-
-  // CLKFBOUT
-  parameter [5:0] CLKFBOUT_CLKOUT1_HIGH_TIME = 6'd0;
-  parameter [5:0] CLKFBOUT_CLKOUT1_LOW_TIME = 6'd0;
-  parameter [0:0] CLKFBOUT_CLKOUT1_OUTPUT_ENABLE = 1'b0;
-  parameter [2:0] CLKFBOUT_CLKOUT1_PHASE_MUX = 3'd0;
-  parameter [5:0] CLKFBOUT_CLKOUT2_DELAY_TIME = 6'd0;
-  parameter [0:0] CLKFBOUT_CLKOUT2_EDGE = 1'b0;
-  parameter [2:0] CLKFBOUT_CLKOUT2_FRAC = 3'd0;
-  parameter [0:0] CLKFBOUT_CLKOUT2_FRAC_EN = 1'b0;
-  parameter [0:0] CLKFBOUT_CLKOUT2_FRAC_WF_R = 1'b0;
-  parameter [0:0] CLKFBOUT_CLKOUT2_NO_COUNT = 1'b1;
-
-  // CLKOUT0
-  parameter [5:0] CLKOUT0_CLKOUT1_HIGH_TIME = 6'd0;
-  parameter [5:0] CLKOUT0_CLKOUT1_LOW_TIME = 6'd0;
-  parameter [0:0] CLKOUT0_CLKOUT1_OUTPUT_ENABLE = 1'b0;
-  parameter [2:0] CLKOUT0_CLKOUT1_PHASE_MUX = 3'd0;
-  parameter [5:0] CLKOUT0_CLKOUT2_DELAY_TIME = 6'd0;
-  parameter [0:0] CLKOUT0_CLKOUT2_EDGE = 1'b0;
-  parameter [2:0] CLKOUT0_CLKOUT2_FRAC = 3'd0;
-  parameter [0:0] CLKOUT0_CLKOUT2_FRAC_EN = 1'b0;
-  parameter [0:0] CLKOUT0_CLKOUT2_FRAC_WF_R = 1'b0;
-  parameter [0:0] CLKOUT0_CLKOUT2_NO_COUNT = 1'b1;
-
-  // CLKOUT1
-  parameter [5:0] CLKOUT1_CLKOUT1_HIGH_TIME = 6'd0;
-  parameter [5:0] CLKOUT1_CLKOUT1_LOW_TIME = 6'd0;
-  parameter [0:0] CLKOUT1_CLKOUT1_OUTPUT_ENABLE = 1'b0;
-  parameter [2:0] CLKOUT1_CLKOUT1_PHASE_MUX = 3'd0;
-  parameter [5:0] CLKOUT1_CLKOUT2_DELAY_TIME = 6'd0;
-  parameter [0:0] CLKOUT1_CLKOUT2_EDGE = 1'b0;
-  parameter [2:0] CLKOUT1_CLKOUT2_FRAC = 3'd0;
-  parameter [0:0] CLKOUT1_CLKOUT2_FRAC_EN = 1'b0;
-  parameter [0:0] CLKOUT1_CLKOUT2_FRAC_WF_R = 1'b0;
-  parameter [0:0] CLKOUT1_CLKOUT2_NO_COUNT = 1'b1;
-
-  // CLKOUT2
-  parameter [5:0] CLKOUT2_CLKOUT1_HIGH_TIME = 6'd0;
-  parameter [5:0] CLKOUT2_CLKOUT1_LOW_TIME = 6'd0;
-  parameter [0:0] CLKOUT2_CLKOUT1_OUTPUT_ENABLE = 1'b0;
-  parameter [2:0] CLKOUT2_CLKOUT1_PHASE_MUX = 3'd0;
-  parameter [5:0] CLKOUT2_CLKOUT2_DELAY_TIME = 6'd0;
-  parameter [0:0] CLKOUT2_CLKOUT2_EDGE = 1'b0;
-  parameter [2:0] CLKOUT2_CLKOUT2_FRAC = 3'd0;
-  parameter [0:0] CLKOUT2_CLKOUT2_FRAC_EN = 1'b0;
-  parameter [0:0] CLKOUT2_CLKOUT2_FRAC_WF_R = 1'b0;
-  parameter [0:0] CLKOUT2_CLKOUT2_NO_COUNT = 1'b1;
-
-  // CLKOUT3
-  parameter [5:0] CLKOUT3_CLKOUT1_HIGH_TIME = 6'd0;
-  parameter [5:0] CLKOUT3_CLKOUT1_LOW_TIME = 6'd0;
-  parameter [0:0] CLKOUT3_CLKOUT1_OUTPUT_ENABLE = 1'b0;
-  parameter [2:0] CLKOUT3_CLKOUT1_PHASE_MUX = 3'd0;
-  parameter [5:0] CLKOUT3_CLKOUT2_DELAY_TIME = 6'd0;
-  parameter [0:0] CLKOUT3_CLKOUT2_EDGE = 1'b0;
-  parameter [2:0] CLKOUT3_CLKOUT2_FRAC = 3'd0;
-  parameter [0:0] CLKOUT3_CLKOUT2_FRAC_EN = 1'b0;
-  parameter [0:0] CLKOUT3_CLKOUT2_FRAC_WF_R = 1'b0;
-  parameter [0:0] CLKOUT3_CLKOUT2_NO_COUNT = 1'b1;
-
-  // CLKOUT4
-  parameter [5:0] CLKOUT4_CLKOUT1_HIGH_TIME = 6'd0;
-  parameter [5:0] CLKOUT4_CLKOUT1_LOW_TIME = 6'd0;
-  parameter [0:0] CLKOUT4_CLKOUT1_OUTPUT_ENABLE = 1'b0;
-  parameter [2:0] CLKOUT4_CLKOUT1_PHASE_MUX = 3'd0;
-  parameter [5:0] CLKOUT4_CLKOUT2_DELAY_TIME = 6'd0;
-  parameter [0:0] CLKOUT4_CLKOUT2_EDGE = 1'b0;
-  parameter [2:0] CLKOUT4_CLKOUT2_FRAC = 3'd0;
-  parameter [0:0] CLKOUT4_CLKOUT2_FRAC_EN = 1'b0;
-  parameter [0:0] CLKOUT4_CLKOUT2_FRAC_WF_R = 1'b0;
-  parameter [0:0] CLKOUT4_CLKOUT2_NO_COUNT = 1'b1;
-
-  // CLKOUT5
-  parameter [5:0] CLKOUT5_CLKOUT1_HIGH_TIME = 6'd0;
-  parameter [5:0] CLKOUT5_CLKOUT1_LOW_TIME = 6'd0;
-  parameter [0:0] CLKOUT5_CLKOUT1_OUTPUT_ENABLE = 1'b0;
-  parameter [2:0] CLKOUT5_CLKOUT1_PHASE_MUX = 3'd0;
-  parameter [5:0] CLKOUT5_CLKOUT2_DELAY_TIME = 6'd0;
-  parameter [0:0] CLKOUT5_CLKOUT2_EDGE = 1'b0;
-  parameter [2:0] CLKOUT5_CLKOUT2_FRAC = 3'd0;
-  parameter [0:0] CLKOUT5_CLKOUT2_FRAC_EN = 1'b0;
-  parameter [0:0] CLKOUT5_CLKOUT2_FRAC_WF_R = 1'b0;
-  parameter [0:0] CLKOUT5_CLKOUT2_NO_COUNT = 1'b1;
-
-
-  // TODO: Compensation parameters
-
-  // TODO: How to simulate a PLL in verilog (i.e. the VCO) ???
-
-endmodule
diff --git a/sdc-plugin/tests/xc7a35tcsg324-1.json b/sdc-plugin/tests/xc7a35tcsg324-1.json
deleted file mode 100644
index 602b949..0000000
--- a/sdc-plugin/tests/xc7a35tcsg324-1.json
+++ /dev/null
@@ -1,10 +0,0 @@
-{
-    "iobanks": {
-        "0": "X1Y78",
-        "14": "X1Y26",
-        "15": "X1Y78",
-        "16": "X1Y130",
-        "34": "X113Y26",
-        "35": "X113Y78"
-    }
-}