)]}'
{
  "commit": "83ad47a6182082ce7c05b897a31470c2afa867a9",
  "tree": "c770247b40090f7239aa25557d3d05e6c4cfd104",
  "parents": [
    "f84b823fe14aa8d6e33622c6ec3b25acbf7c0174"
  ],
  "author": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Mon Mar 13 11:29:49 2023 +0100"
  },
  "committer": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Mon Mar 13 11:29:49 2023 +0100"
  },
  "message": "systemverilog-plugin: add assert\n\nSigned-off-by: Kamil Rakoczy \u003ckrakoczy@antmicro.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "f9d0b71fbb7a0e257eb64134636db7e7723aed9d",
      "old_mode": 33188,
      "old_path": "systemverilog-plugin/UhdmAst.cc",
      "new_id": "42cd001ddd3ca11433f6c728cdb91d87dc2a4835",
      "new_mode": 33188,
      "new_path": "systemverilog-plugin/UhdmAst.cc"
    }
  ]
}