)]}'
{
  "commit": "8430e6469f44993a53cfc5ac80952d50d8d946bf",
  "tree": "d3d868d88b9e8c0f8bfd4dd95bc13a923594e0ec",
  "parents": [
    "ae92491a67fdbf77fb0c870b032edc6d3eded467"
  ],
  "author": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Thu Feb 23 10:45:44 2023 +0100"
  },
  "committer": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Tue Feb 28 11:09:21 2023 +0100"
  },
  "message": "systemverilog-plugin: fix wires not starting from 0\n\nSigned-off-by: Kamil Rakoczy \u003ckrakoczy@antmicro.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "38c42a7fe09c772d93a42ecc59292590f0acdec5",
      "old_mode": 33188,
      "old_path": "systemverilog-plugin/UhdmAst.cc",
      "new_id": "471816b46bd18cc5933733a04b04884974079495",
      "new_mode": 33188,
      "new_path": "systemverilog-plugin/UhdmAst.cc"
    }
  ]
}