commit 8cda05162b2110fb1fa34b5242adbb86d99c6c66
author Rafal Kapuscik <rkapuscik@antmicro.com> Mon May 09 12:20:46 2022 +0200
committer Rafal Kapuscik <rkapuscik@antmicro.com> Mon May 09 12:21:06 2022 +0200
tree 44257d7adf75d6e0a40aedb8483b15aee01caf23
parent e9ce130bf456e4e7fe736c8cda9c5706be747a63

Update typespec sizes

Signed-off-by: Rafal Kapuscik <rkapuscik@antmicro.com>

systemverilog-plugin/UhdmAst.cc

diff --git a/systemverilog-plugin/UhdmAst.cc b/systemverilog-plugin/UhdmAst.cc
index 70dea66..04d3206 100644
--- a/systemverilog-plugin/UhdmAst.cc
+++ b/systemverilog-plugin/UhdmAst.cc
@@ -3404,7 +3404,10 @@
     std::vector<AST::AstNode *> packed_ranges;   // comes before wire name
     std::vector<AST::AstNode *> unpacked_ranges; // comes after wire name
     current_node = make_ast_node(AST::AST_WIRE);
-    packed_ranges.push_back(make_range(16, 0));
+    packed_ranges.push_back(make_range(15, 0));
+    add_multirange_wire(current_node, packed_ranges, unpacked_ranges);
+    current_node->is_signed = true;
+}
 
 void UhdmAst::process_byte_typespec()
 {
@@ -3421,7 +3424,7 @@
     std::vector<AST::AstNode *> packed_ranges;   // comes before wire name
     std::vector<AST::AstNode *> unpacked_ranges; // comes after wire name
     current_node = make_ast_node(AST::AST_WIRE);
-    packed_ranges.push_back(make_range(64, 0));
+    packed_ranges.push_back(make_range(63, 0));
     add_multirange_wire(current_node, packed_ranges, unpacked_ranges);
     current_node->is_signed = false;
 }