)]}'
{
  "commit": "8e5d56f222cd4ebcf2fe61232056233275ad36cb",
  "tree": "5e7f3f2bdb680f6105c6e567fc74cc97ab38b9fd",
  "parents": [
    "aa22df7e19747932e055a00a073e502f58d0d305"
  ],
  "author": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Mon Apr 03 17:02:16 2023 +0200"
  },
  "committer": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Mon Apr 03 17:02:16 2023 +0200"
  },
  "message": "systemverilog-plugin: delete children when changing wire to id in process_assignment\n\nSigned-off-by: Kamil Rakoczy \u003ckrakoczy@antmicro.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "23d72c091d7282cba04e9157f32a7323cb1d763c",
      "old_mode": 33188,
      "old_path": "systemverilog-plugin/UhdmAst.cc",
      "new_id": "a3484d62577c1c66c0ae366d67b2ad49d51a664e",
      "new_mode": 33188,
      "new_path": "systemverilog-plugin/UhdmAst.cc"
    }
  ]
}