)]}'
{
  "commit": "8edc027cdc484f86c5ac8698c696c74d04e6f92e",
  "tree": "56a5d6bf281166db59b79a54208514cfb335d700",
  "parents": [
    "56f957caa573658015cc4256cd9ebf2a0cc70a19",
    "cb6c85575bda3d06d6e798d11010957d39391ce1"
  ],
  "author": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Tue Jun 06 07:40:47 2023 +0200"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Tue Jun 06 07:40:47 2023 +0200"
  },
  "message": "Merge pull request #523 from antmicro/kr/fix_anonymous_enum\n\nsystemverilog-plugin: fix anonymous enum when declared in submodules",
  "tree_diff": []
}