| commit | 914679b3c5e732def4037e755c8ed4e86ef91266 | [log] [tgz] |
|---|---|---|
| author | rakeshm <rakeshm@quicklogic.com> | Tue Dec 20 04:56:38 2022 -0800 |
| committer | rakeshm <rakeshm@quicklogic.com> | Tue Dec 20 04:56:38 2022 -0800 |
| tree | fe47e4beba9616e9fb7c116370af382e2fef7837 | |
| parent | 2df3c42694d74542adb7e3b05ce9c5fa6a2e09cd [diff] |
added primitives_sim.v to the VERILOG_MODULES list in Makefile
diff --git a/ql-qlf-plugin/Makefile b/ql-qlf-plugin/Makefile index d754156..d546b16 100644 --- a/ql-qlf-plugin/Makefile +++ b/ql-qlf-plugin/Makefile
@@ -55,6 +55,7 @@ $(QLF_K6N10F_DIR)/brams.txt \ $(QLF_K6N10F_DIR)/cells_sim.v \ $(QLF_K6N10F_DIR)/dsp_sim.v \ + $(QLF_K6N10F_DIR)/primitives_sim.v \ $(QLF_K6N10F_DIR)/brams_sim.v \ $(QLF_K6N10F_DIR)/sram1024x18.v \ $(QLF_K6N10F_DIR)/TDP18K_FIFO.v \