)]}'
{
  "commit": "914679b3c5e732def4037e755c8ed4e86ef91266",
  "tree": "fe47e4beba9616e9fb7c116370af382e2fef7837",
  "parents": [
    "2df3c42694d74542adb7e3b05ce9c5fa6a2e09cd"
  ],
  "author": {
    "name": "rakeshm",
    "email": "rakeshm@quicklogic.com",
    "time": "Tue Dec 20 04:56:38 2022 -0800"
  },
  "committer": {
    "name": "rakeshm",
    "email": "rakeshm@quicklogic.com",
    "time": "Tue Dec 20 04:56:38 2022 -0800"
  },
  "message": "added primitives_sim.v to the VERILOG_MODULES list in Makefile\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "d75415667854ed80c4db8ee8d5e5267fa1d2f433",
      "old_mode": 33188,
      "old_path": "ql-qlf-plugin/Makefile",
      "new_id": "d546b164ed6209811bb13dac7a5a464af8ac52b8",
      "new_mode": 33188,
      "new_path": "ql-qlf-plugin/Makefile"
    }
  ]
}