tree fe47e4beba9616e9fb7c116370af382e2fef7837
parent 2df3c42694d74542adb7e3b05ce9c5fa6a2e09cd
author rakeshm <rakeshm@quicklogic.com> 1671540998 -0800
committer rakeshm <rakeshm@quicklogic.com> 1671540998 -0800

added primitives_sim.v to the VERILOG_MODULES list in Makefile