SDC: Remove Clocks storage
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
diff --git a/sdc-plugin/clocks.cc b/sdc-plugin/clocks.cc
index bbad62c..d1804b7 100644
--- a/sdc-plugin/clocks.cc
+++ b/sdc-plugin/clocks.cc
@@ -55,23 +55,6 @@
return clock_wires;
}
-std::vector<std::string> Clocks::GetClockNames() {
- std::vector<std::string> res;
- for (auto clock : clocks_) {
- res.push_back(clock.Name());
-#ifdef SDC_DEBUG
- std::stringstream ss;
- for (auto clock_wire : clock.GetClockWires()) {
- ss << RTLIL::unescape_id(clock_wire->name) << " ";
- }
- log("create_clock -period %f -name %s -waveform {%f %f} %s\n",
- clock.Period(), clock.Name().c_str(), clock.RisingEdge(),
- clock.FallingEdge(), ss.str().c_str());
-#endif
- }
- return res;
-}
-
void Clocks::Propagate(RTLIL::Design* design, NaturalPropagation* pass) {
#ifdef SDC_DEBUG
log("Start natural clock propagation\n");
diff --git a/sdc-plugin/clocks.h b/sdc-plugin/clocks.h
index 114cee3..c074649 100644
--- a/sdc-plugin/clocks.h
+++ b/sdc-plugin/clocks.h
@@ -67,17 +67,12 @@
void AddClock(const std::string& name, RTLIL::Wire* wire, float period,
float rising_edge, float falling_edge);
void AddClock(Clock& clock);
- std::vector<std::string> GetClockNames();
void Propagate(RTLIL::Design* design, NaturalPropagation* pass);
void Propagate(RTLIL::Design* design, BufferPropagation* pass);
void Propagate(RTLIL::Design* design, ClockDividerPropagation* pass);
- const std::vector<Clock> GetClocks() {
- return std::vector<Clock>();
- }
static const std::vector<RTLIL::Wire*> GetClocks(RTLIL::Design* design);
private:
- std::vector<Clock> clocks_;
void PropagateThroughBuffer(Propagation* pass, RTLIL::Design* design, Clock& clock,
Buffer buffer);
};
diff --git a/sdc-plugin/sdc_writer.cc b/sdc-plugin/sdc_writer.cc
index 6998097..6826d01 100644
--- a/sdc-plugin/sdc_writer.cc
+++ b/sdc-plugin/sdc_writer.cc
@@ -58,27 +58,6 @@
}
}
-void SdcWriter::WriteClocks(Clocks& clocks, std::ostream& file) {
- for (auto clock : clocks.GetClocks()) {
- auto clock_wires = clock.GetClockWires();
- // FIXME: Input port nets are not found in VPR
- if (std::all_of(clock_wires.begin(), clock_wires.end(),
- [&](RTLIL::Wire* wire) { return wire->port_input; })) {
- continue;
- }
- file << "create_clock -period " << clock.Period();
- file << " -waveform {" << clock.RisingEdge() << " "
- << clock.FallingEdge() << "}";
- for (auto clock_wire : clock_wires) {
- if (clock_wire->port_input) {
- continue;
- }
- file << " " << Clock::ClockWireName(clock_wire);
- }
- file << std::endl;
- }
-}
-
void SdcWriter::WriteFalsePaths(std::ostream& file) {
for (auto path : false_paths_) {
file << "set_false_path";
diff --git a/sdc-plugin/sdc_writer.h b/sdc-plugin/sdc_writer.h
index c6ea149..5cdf8a2 100644
--- a/sdc-plugin/sdc_writer.h
+++ b/sdc-plugin/sdc_writer.h
@@ -64,7 +64,6 @@
void WriteSdc(RTLIL::Design* design, std::ostream& file);
private:
- void WriteClocks(Clocks& clocks, std::ostream& file);
void WriteClocks(RTLIL::Design* design, std::ostream& file);
void WriteFalsePaths(std::ostream& file);
void WriteMaxDelay(std::ostream& file);
