commit 93f80095a6b0498877d5e564ce12928ab9fd2bee
author Kamil Rakoczy <krakoczy@antmicro.com> Tue Feb 21 11:15:17 2023 +0100
committer GitHub <noreply@github.com> Tue Feb 21 11:15:17 2023 +0100
tree e064786d0415787897a849b97b7a9ac2925c1cf9
parent 43308c14324f88f59df758a575c12f55df90987f
parent 72e32103b4476d33fc8c9e6dd5081a5bb0a4df3c

Merge pull request #458 from antmicro/kr/memory_slice

systemverilog-plugin: convert memory when accessing slice

systemverilog-plugin/UhdmAst.cc

diff --git a/systemverilog-plugin/UhdmAst.cc b/systemverilog-plugin/UhdmAst.cc
index 425c8dc..0525f35 100644
--- a/systemverilog-plugin/UhdmAst.cc
+++ b/systemverilog-plugin/UhdmAst.cc
@@ -311,7 +311,6 @@
     // return range from *current* selected range
     // in the end, it results in whole selected range
     id->basic_prep = true;
-    result->dumpAst(NULL, "> ");
     return result;
 }
 
@@ -3854,6 +3853,7 @@
     // calls another function that is not imported in the calling scope.
     if (vpiHandle function_h = vpi_handle(vpiFunction, obj_h)) {
         current_node->str = get_name(function_h, true);
+        vpi_release_handle(function_h);
     }
 }