)]}'
{
  "commit": "93f80095a6b0498877d5e564ce12928ab9fd2bee",
  "tree": "e064786d0415787897a849b97b7a9ac2925c1cf9",
  "parents": [
    "43308c14324f88f59df758a575c12f55df90987f",
    "72e32103b4476d33fc8c9e6dd5081a5bb0a4df3c"
  ],
  "author": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Tue Feb 21 11:15:17 2023 +0100"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Tue Feb 21 11:15:17 2023 +0100"
  },
  "message": "Merge pull request #458 from antmicro/kr/memory_slice\n\nsystemverilog-plugin: convert memory when accessing slice",
  "tree_diff": []
}