)]}'
{
  "commit": "94d267daca1eb0cc80c97c420f3138144d2490b8",
  "tree": "87a4e6ea3d8cb73b2fb17c1548641b77a150c4c5",
  "parents": [
    "794ff73e432515eabe95a73e127f45cf7db0a04c"
  ],
  "author": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Wed Apr 05 13:59:38 2023 +0200"
  },
  "committer": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Tue Apr 11 10:37:43 2023 +0200"
  },
  "message": "systemverilog-plugin: fix sometimes missing typedef in port wire\n\nSigned-off-by: Kamil Rakoczy \u003ckrakoczy@antmicro.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "9d2abeb488a626cac45fa232dc8a2e5e7bdf5b56",
      "old_mode": 33188,
      "old_path": "systemverilog-plugin/UhdmAst.cc",
      "new_id": "febcb9d154a05b41b615d7278609d5701258e29f",
      "new_mode": 33188,
      "new_path": "systemverilog-plugin/UhdmAst.cc"
    }
  ]
}