)]}'
{
  "commit": "96a0853eba5691f54a5e0bfc044d847743e09cef",
  "tree": "777152a4d163681d8835fb18e4fd6fec0a772b3e",
  "parents": [
    "8b80abceaaa1eb34c0a78cb9a4ac59c884ff10c3",
    "82f3d4a37a59555c1cb8b1695d6dbe0d4cef1d03"
  ],
  "author": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Mon Apr 17 15:14:17 2023 +0200"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Mon Apr 17 15:14:17 2023 +0200"
  },
  "message": "Merge pull request #479 from antmicro/kr/module_input_type\n\nsystemverilog-plugin: fix size of struct used as I/O wire",
  "tree_diff": []
}