)]}'
{
  "commit": "99a6411280ad3796a6c60b33f2d84439b2545097",
  "tree": "b3ccc5251d182a8b42c8db8a25bd8c167f682759",
  "parents": [
    "3e8721b11be3db188018314de9b18dd4263e20dc"
  ],
  "author": {
    "name": "Mariusz Glebocki",
    "email": "mglebocki@antmicro.com",
    "time": "Wed Dec 14 13:47:52 2022 +0100"
  },
  "committer": {
    "name": "Mariusz Glebocki",
    "email": "mglebocki@antmicro.com",
    "time": "Wed Dec 14 14:32:55 2022 +0100"
  },
  "message": "Put all systemverilog plugin code in `systemverilog_plugin` namespace.\n\nMoves the code from Yosys namespace to our own. This will prevent any\nunexpected symbol conflicts in the future.\n",
  "tree_diff": [
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}