)]}'
{
  "commit": "99b6b6e4f6c093d1b228ce45a7ad73febb41aa46",
  "tree": "75d04a64065a138637cb7f9140d54ee3ccb4d430",
  "parents": [
    "6f384227e77b70dbc5c23e4d467da964606f452f",
    "503b9e76f36e9786297ecf4c39c2cf2ffc3d397c"
  ],
  "author": {
    "name": "Mariusz Glebocki",
    "email": "mglebocki@antmicro.com",
    "time": "Tue Dec 06 10:56:06 2022 +0100"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Tue Dec 06 10:56:06 2022 +0100"
  },
  "message": "Merge pull request #411 from antmicro/mglb/UhdmSurelogAstFrontendRTTI\n\nsystemverilog: use RTTI for resource management in UhdmSurelogAstFrontend",
  "tree_diff": []
}