systemverilog-plugin: Skip visiting vpiPort, vpiInterface, vpiTaskFunc, vpiAssertion, vpiClockingBlock, vpiGenScopeArray in uhdmallmodules
Signed-off-by: Magdalena Andrys <mandrys@antmicro.com>
diff --git a/systemverilog-plugin/UhdmAst.cc b/systemverilog-plugin/UhdmAst.cc
index ee19809..9586f97 100644
--- a/systemverilog-plugin/UhdmAst.cc
+++ b/systemverilog-plugin/UhdmAst.cc
@@ -1726,15 +1726,13 @@
move_type_to_new_typedef(current_node, node);
}
});
- visit_one_to_many({vpiModule, vpiInterface, vpiTaskFunc, vpiParameter, vpiParamAssign, vpiPort, vpiNet, vpiArrayNet, vpiGenScopeArray,
- vpiProcess, vpiClockingBlock, vpiAssertion},
- obj_h, [&](AST::AstNode *node) {
- if (node) {
- if (node->type == AST::AST_ASSIGN && node->children.size() < 2)
- return;
- add_or_replace_child(current_node, node);
- }
- });
+ visit_one_to_many({vpiModule, vpiParameter, vpiParamAssign, vpiNet, vpiArrayNet, vpiProcess}, obj_h, [&](AST::AstNode *node) {
+ if (node) {
+ if (node->type == AST::AST_ASSIGN && node->children.size() < 2)
+ return;
+ add_or_replace_child(current_node, node);
+ }
+ });
}
} else {
// Not a top module, create instance
