diff --git a/dsp_ff-plugin/tests/Makefile b/dsp_ff-plugin/tests/Makefile
new file mode 100644
index 0000000..76ffd64
--- /dev/null
+++ b/dsp_ff-plugin/tests/Makefile
@@ -0,0 +1,14 @@
+# Copyright (C) 2020-2022  The SymbiFlow Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier:ISC
+
+TESTS = \
+    nexus_mult
+
+include $(shell pwd)/../../Makefile_test.common
+
+nexus_mult_verify = true
diff --git a/dsp_ff-plugin/tests/nexus_mult/README.md b/dsp_ff-plugin/tests/nexus_mult/README.md
new file mode 100644
index 0000000..f72e27c
--- /dev/null
+++ b/dsp_ff-plugin/tests/nexus_mult/README.md
@@ -0,0 +1 @@
+Simple DSP register inference
diff --git a/dsp_ff-plugin/tests/nexus_mult/nexus_mult.tcl b/dsp_ff-plugin/tests/nexus_mult/nexus_mult.tcl
new file mode 100644
index 0000000..437fe9e
--- /dev/null
+++ b/dsp_ff-plugin/tests/nexus_mult/nexus_mult.tcl
@@ -0,0 +1,43 @@
+yosys -import
+if { [info procs dsp_ff] == {} } { plugin -i dsp-ff }
+yosys -import  ;# ingest plugin commands
+
+read_verilog $::env(DESIGN_TOP).v
+design -save read
+
+set TOP "mult_ireg"
+design -load read
+hierarchy -top ${TOP}
+synth_nexus -flatten
+techmap -map +/nexus/cells_sim.v t:VLO t:VHI %u ;# Unmap VHI and VLO
+equiv_opt -assert -async2sync -map +/nexus/cells_sim.v debug dsp_ff -rules ../../nexus-dsp_rules.txt
+design -load postopt
+yosys cd ${TOP}
+stat
+select -assert-count MULT9X9 1
+select -assert-count FD1P3IX 0
+
+set TOP "mult_oreg"
+design -load read
+hierarchy -top ${TOP}
+synth_nexus -flatten
+techmap -map +/nexus/cells_sim.v t:VLO t:VHI %u ;# Unmap VHI and VLO
+equiv_opt -assert -async2sync -map +/nexus/cells_sim.v debug dsp_ff -rules ../../nexus-dsp_rules.txt
+design -load postopt
+yosys cd ${TOP}
+stat
+select -assert-count MULT9X9 1
+select -assert-count FD1P3IX 0
+
+set TOP "mult_all"
+design -load read
+hierarchy -top ${TOP}
+synth_nexus -flatten
+techmap -map +/nexus/cells_sim.v t:VLO t:VHI %u ;# Unmap VHI and VLO
+equiv_opt -assert -async2sync -map +/nexus/cells_sim.v debug dsp_ff -rules ../../nexus-dsp_rules.txt
+design -load postopt
+yosys cd ${TOP}
+stat
+select -assert-count MULT9X9 1
+select -assert-count FD1P3IX 0
+
diff --git a/dsp_ff-plugin/tests/nexus_mult/nexus_mult.v b/dsp_ff-plugin/tests/nexus_mult/nexus_mult.v
new file mode 100644
index 0000000..4b7bda4
--- /dev/null
+++ b/dsp_ff-plugin/tests/nexus_mult/nexus_mult.v
@@ -0,0 +1,76 @@
+module mult_ireg (
+    input  wire        CLK,
+    input  wire [ 8:0] A,
+    input  wire [ 8:0] B,
+    output wire [17:0] Z
+);
+
+    reg [8:0] ra;
+    always @(posedge CLK)
+        ra <= A;
+
+    MULT9X9 # (
+        .REGINPUTA("BYPASS"),
+        .REGINPUTB("BYPASS"),
+        .REGOUTPUT("BYPASS")
+    ) mult (
+        .A (ra),
+        .B (B),
+        .Z (Z)
+    );
+
+endmodule
+
+module mult_oreg (
+    input  wire        CLK,
+    input  wire [ 8:0] A,
+    input  wire [ 8:0] B,
+    output reg  [17:0] Z
+);
+
+    reg [17:0] z;
+    always @(posedge CLK)
+        Z <= z;
+
+    MULT9X9 # (
+        .REGINPUTA("BYPASS"),
+        .REGINPUTB("BYPASS"),
+        .REGOUTPUT("BYPASS")
+    ) mult (
+        .A (A),
+        .B (B),
+        .Z (z)
+    );
+
+endmodule
+
+module mult_all (
+    input  wire        CLK,
+    input  wire [ 8:0] A,
+    input  wire [ 8:0] B,
+    output reg  [17:0] Z
+);
+
+    reg [8:0] ra;
+    always @(posedge CLK)
+        ra <= A;
+
+    reg [8:0] rb;
+    always @(posedge CLK)
+        rb <= B;
+
+    reg [17:0] z;
+    always @(posedge CLK)
+        Z <= z;
+
+    MULT9X9 # (
+        .REGINPUTA("BYPASS"),
+        .REGINPUTB("BYPASS"),
+        .REGOUTPUT("BYPASS")
+    ) mult (
+        .A (ra),
+        .B (rb),
+        .Z (z)
+    );
+
+endmodule