diff --git a/ql-qlf-plugin/tests/consts/consts.tcl b/ql-qlf-plugin/tests/consts/consts.tcl
index 71ca0ad..270f679 100644
--- a/ql-qlf-plugin/tests/consts/consts.tcl
+++ b/ql-qlf-plugin/tests/consts/consts.tcl
@@ -1,5 +1,5 @@
 yosys -import
-if { [info procs synth_quicklogic] == {} } { plugin -i ql-qlf }
+if { [info procs quicklogic_eqn] == {} } { plugin -i ql-qlf }
 yosys -import  ;# ingest plugin commands
 
 read_verilog $::env(DESIGN_TOP).v
diff --git a/ql-qlf-plugin/tests/dffs/dffs.tcl b/ql-qlf-plugin/tests/dffs/dffs.tcl
index d96b3e6..2626215 100644
--- a/ql-qlf-plugin/tests/dffs/dffs.tcl
+++ b/ql-qlf-plugin/tests/dffs/dffs.tcl
@@ -1,5 +1,5 @@
 yosys -import
-if { [info procs synth_quicklogic] == {} } { plugin -i ql-qlf }
+if { [info procs quicklogic_eqn] == {} } { plugin -i ql-qlf }
 yosys -import  ;# ingest plugin commands
 
 read_verilog $::env(DESIGN_TOP).v
diff --git a/ql-qlf-plugin/tests/fsm/fsm.tcl b/ql-qlf-plugin/tests/fsm/fsm.tcl
index 2e09677..61a1e10 100644
--- a/ql-qlf-plugin/tests/fsm/fsm.tcl
+++ b/ql-qlf-plugin/tests/fsm/fsm.tcl
@@ -1,5 +1,5 @@
 yosys -import
-if { [info procs synth_quicklogic] == {} } { plugin -i ql-qlf }
+if { [info procs quicklogic_eqn] == {} } { plugin -i ql-qlf }
 yosys -import  ;# ingest plugin commands
 
 read_verilog $::env(DESIGN_TOP).v
diff --git a/ql-qlf-plugin/tests/full_adder/full_adder.tcl b/ql-qlf-plugin/tests/full_adder/full_adder.tcl
index 9c5a402..9fe651f 100644
--- a/ql-qlf-plugin/tests/full_adder/full_adder.tcl
+++ b/ql-qlf-plugin/tests/full_adder/full_adder.tcl
@@ -1,5 +1,5 @@
 yosys -import
-if { [info procs synth_quicklogic] == {} } { plugin -i ql-qlf }
+if { [info procs quicklogic_eqn] == {} } { plugin -i ql-qlf }
 yosys -import  ;# ingest plugin commands
 
 # Equivalence check for adder synthesis for qlf-k4n8
diff --git a/ql-qlf-plugin/tests/iob_no_flatten/iob_no_flatten.tcl b/ql-qlf-plugin/tests/iob_no_flatten/iob_no_flatten.tcl
index 9ab802a..a18c03a 100644
--- a/ql-qlf-plugin/tests/iob_no_flatten/iob_no_flatten.tcl
+++ b/ql-qlf-plugin/tests/iob_no_flatten/iob_no_flatten.tcl
@@ -1,5 +1,5 @@
 yosys -import
-if { [info procs synth_quicklogic] == {} } { plugin -i ql-qlf}
+if { [info procs quicklogic_eqn] == {} } { plugin -i ql-qlf}
 yosys -import  ;# ingest plugin commands
 
 read_verilog $::env(DESIGN_TOP).v
diff --git a/ql-qlf-plugin/tests/latches/latches.tcl b/ql-qlf-plugin/tests/latches/latches.tcl
index 864876c..72b31d8 100644
--- a/ql-qlf-plugin/tests/latches/latches.tcl
+++ b/ql-qlf-plugin/tests/latches/latches.tcl
@@ -1,5 +1,5 @@
 yosys -import
-if { [info procs synth_quicklogic] == {} } { plugin -i ql-qlf }
+if { [info procs quicklogic_eqn] == {} } { plugin -i ql-qlf }
 yosys -import  ;# ingest plugin commands
 
 read_verilog $::env(DESIGN_TOP).v
diff --git a/ql-qlf-plugin/tests/logic/logic.tcl b/ql-qlf-plugin/tests/logic/logic.tcl
index 0e10db5..b1de9f7 100644
--- a/ql-qlf-plugin/tests/logic/logic.tcl
+++ b/ql-qlf-plugin/tests/logic/logic.tcl
@@ -1,5 +1,5 @@
 yosys -import
-if { [info procs synth_quicklogic] == {} } { plugin -i ql-qlf }
+if { [info procs quicklogic_eqn] == {} } { plugin -i ql-qlf }
 yosys -import  ;# ingest plugin commands
 
 #Logic test for qlf_k4n8 device
diff --git a/ql-qlf-plugin/tests/mac_unit/mac_unit.tcl b/ql-qlf-plugin/tests/mac_unit/mac_unit.tcl
index 5028d41..0db32a9 100644
--- a/ql-qlf-plugin/tests/mac_unit/mac_unit.tcl
+++ b/ql-qlf-plugin/tests/mac_unit/mac_unit.tcl
@@ -1,5 +1,5 @@
 yosys -import
-if { [info procs synth_quicklogic] == {} } { plugin -i ql-qlf}
+if { [info procs quicklogic_eqn] == {} } { plugin -i ql-qlf}
 yosys -import  ;# ingest plugin commands
 
 set TOP "mac_unit"
diff --git a/ql-qlf-plugin/tests/multiplier/multiplier.tcl b/ql-qlf-plugin/tests/multiplier/multiplier.tcl
index 762bac6..5c783c2 100644
--- a/ql-qlf-plugin/tests/multiplier/multiplier.tcl
+++ b/ql-qlf-plugin/tests/multiplier/multiplier.tcl
@@ -1,5 +1,5 @@
 yosys -import
-if { [info procs synth_quicklogic] == {} } { plugin -i ql-qlf}
+if { [info procs quicklogic_eqn] == {} } { plugin -i ql-qlf}
 yosys -import  ;# ingest plugin commands
 
 set TOP "mult16x16"
diff --git a/ql-qlf-plugin/tests/mux/mux.tcl b/ql-qlf-plugin/tests/mux/mux.tcl
index 47a1e1b..3d0f949 100644
--- a/ql-qlf-plugin/tests/mux/mux.tcl
+++ b/ql-qlf-plugin/tests/mux/mux.tcl
@@ -1,5 +1,5 @@
 yosys -import
-if { [info procs synth_quicklogic] == {} } { plugin -i ql-qlf }
+if { [info procs quicklogic_eqn] == {} } { plugin -i ql-qlf }
 yosys -import  ;# ingest plugin commands
 
 read_verilog $::env(DESIGN_TOP).v
diff --git a/ql-qlf-plugin/tests/pp3_bram/pp3_bram.tcl b/ql-qlf-plugin/tests/pp3_bram/pp3_bram.tcl
index 8c9dde1..eadfda3 100644
--- a/ql-qlf-plugin/tests/pp3_bram/pp3_bram.tcl
+++ b/ql-qlf-plugin/tests/pp3_bram/pp3_bram.tcl
@@ -1,5 +1,5 @@
 yosys -import
-if { [info procs synth_quicklogic] == {} } { plugin -i ql-qlf }
+if { [info procs quicklogic_eqn] == {} } { plugin -i ql-qlf }
 yosys -import  ;# ingest plugin commands
 
 read_verilog $::env(DESIGN_TOP).v
diff --git a/ql-qlf-plugin/tests/qlf_k6n10_bram/bram.tcl b/ql-qlf-plugin/tests/qlf_k6n10_bram/bram.tcl
index 989b2d5..5275fa5 100644
--- a/ql-qlf-plugin/tests/qlf_k6n10_bram/bram.tcl
+++ b/ql-qlf-plugin/tests/qlf_k6n10_bram/bram.tcl
@@ -1,5 +1,5 @@
 yosys -import
-if { [info procs synth_quicklogic] == {} } { plugin -i ql-qlf }
+if { [info procs quicklogic_eqn] == {} } { plugin -i ql-qlf }
 yosys -import  ;# ingest plugin commands
 
 read_verilog $::env(DESIGN_TOP).v
diff --git a/ql-qlf-plugin/tests/shreg/shreg.tcl b/ql-qlf-plugin/tests/shreg/shreg.tcl
index 9be1ca3..dba736c 100644
--- a/ql-qlf-plugin/tests/shreg/shreg.tcl
+++ b/ql-qlf-plugin/tests/shreg/shreg.tcl
@@ -1,5 +1,5 @@
 yosys -import
-if { [info procs synth_quicklogic] == {} } { plugin -i ql-qlf }
+if { [info procs quicklogic_eqn] == {} } { plugin -i ql-qlf }
 yosys -import ;# ingest plugin commands
 
 read_verilog $::env(DESIGN_TOP).v
diff --git a/ql-qlf-plugin/tests/tribuf/tribuf.tcl b/ql-qlf-plugin/tests/tribuf/tribuf.tcl
index acee086..0d759b5 100644
--- a/ql-qlf-plugin/tests/tribuf/tribuf.tcl
+++ b/ql-qlf-plugin/tests/tribuf/tribuf.tcl
@@ -1,5 +1,5 @@
 yosys -import
-if { [info procs synth_quicklogic] == {} } { plugin -i ql-qlf }
+if { [info procs quicklogic_eqn] == {} } { plugin -i ql-qlf }
 yosys -import  ;# ingest plugin commands
 
 read_verilog $::env(DESIGN_TOP).v