)]}'
{
  "commit": "a4e48ee88d1c5d2a69cc5d97caccff0d67223106",
  "tree": "26d18443f2e71d8b66f4708617aecb289df875c9",
  "parents": [
    "ff70a90fc36cc968618c5b47f7ba4f322af9b71e"
  ],
  "author": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Thu Apr 14 15:20:06 2022 +0200"
  },
  "committer": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Thu Apr 14 15:20:06 2022 +0200"
  },
  "message": "systemverilog: abort when Surelog report error in design\n\nSigned-off-by: Kamil Rakoczy \u003ckrakoczy@antmicro.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "82f04e4056a7a0965dd796353623174feac4efd2",
      "old_mode": 33188,
      "old_path": "systemverilog-plugin/uhdmsurelogastfrontend.cc",
      "new_id": "1f8472ae281db697f8313cc8affffc3ed40da1f6",
      "new_mode": 33188,
      "new_path": "systemverilog-plugin/uhdmsurelogastfrontend.cc"
    }
  ]
}