)]}'
{
  "commit": "a5a59ed95f5473d049d232b8ee93186b4ae8c8c8",
  "tree": "368d72e1733265398bc08a71dba0be57ec7538a3",
  "parents": [
    "a20c6a96d9fd4b8989940a6608501784e02e78b1",
    "67deb91dfd4e77f084102669db67d6d88d9d491a"
  ],
  "author": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Wed Feb 08 14:01:17 2023 +0100"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Wed Feb 08 14:01:17 2023 +0100"
  },
  "message": "Merge pull request #450 from antmicro/kr/add_list_op\n\nsystemverilog: add support for list op with low and high bound",
  "tree_diff": []
}