)]}'
{
  "commit": "aa22df7e19747932e055a00a073e502f58d0d305",
  "tree": "bb6060172a1e1768af60eea762d13a9507c154ce",
  "parents": [
    "652f82d692b6353ecd4357b27426400eda37c7a8"
  ],
  "author": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Wed Mar 22 11:49:16 2023 +0100"
  },
  "committer": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Mon Apr 03 11:05:04 2023 +0200"
  },
  "message": "systemverilog-plugin: fix assignments to wire\n\nSigned-off-by: Kamil Rakoczy \u003ckrakoczy@antmicro.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "681741cd1bdbd83d90e435a00ca3fd156efc81a9",
      "old_mode": 33188,
      "old_path": "systemverilog-plugin/UhdmAst.cc",
      "new_id": "23d72c091d7282cba04e9157f32a7323cb1d763c",
      "new_mode": 33188,
      "new_path": "systemverilog-plugin/UhdmAst.cc"
    }
  ]
}