Merge pull request #306 from antmicro/install-destdir
Added support for overriding installation path via DESTDIR
diff --git a/ql-qlf-plugin/qlf_k6n10f/cells_sim.v b/ql-qlf-plugin/qlf_k6n10f/cells_sim.v
index c9c881e..a77f76c 100644
--- a/ql-qlf-plugin/qlf_k6n10f/cells_sim.v
+++ b/ql-qlf-plugin/qlf_k6n10f/cells_sim.v
@@ -14,12 +14,14 @@
//
// SPDX-License-Identifier: Apache-2.0
+`default_nettype none
+
(* abc9_flop, lib_whitebox *)
module sh_dff(
output reg Q,
- input D,
+ input wire D,
(* clkbuf_sink *)
- input C
+ input wire C
);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
@@ -30,11 +32,11 @@
(* abc9_box, lib_blackbox *)
module adder_carry(
- output sumout,
- output cout,
- input p,
- input g,
- input cin
+ output wire sumout,
+ output wire cout,
+ input wire p,
+ input wire g,
+ input wire cin
);
assign sumout = p ^ cin;
assign cout = p ? cin : g;
@@ -43,12 +45,12 @@
(* abc9_box, lib_whitebox *)
module adder_lut5(
- output lut5_out,
+ output wire lut5_out,
(* abc9_carry *)
- output cout,
- input [0:4] in,
+ output wire cout,
+ input wire [0:4] in,
(* abc9_carry *)
- input cin
+ input wire cin
);
parameter [0:15] LUT=0;
parameter IN2_IS_CIN = 0;
@@ -77,10 +79,10 @@
(* abc9_lut=1, lib_whitebox *)
module frac_lut6(
- input [0:5] in,
- output [0:3] lut4_out,
- output [0:1] lut5_out,
- output lut6_out
+ input wire [0:5] in,
+ output wire [0:3] lut4_out,
+ output wire [0:1] lut5_out,
+ output wire lut6_out
);
parameter [0:63] LUT = 0;
// Effective LUT input
@@ -127,10 +129,10 @@
(* abc9_flop, lib_whitebox *)
module dff(
output reg Q,
- input D,
+ input wire D,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
- input C
+ input wire C
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
@@ -148,11 +150,11 @@
(* abc9_flop, lib_whitebox *)
module dffr(
output reg Q,
- input D,
- input R,
+ input wire D,
+ input wire R,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
- input C
+ input wire C
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
@@ -176,12 +178,12 @@
(* abc9_flop, lib_whitebox *)
module dffre(
output reg Q,
- input D,
- input R,
- input E,
+ input wire D,
+ input wire R,
+ input wire E,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
- input C
+ input wire C
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
@@ -204,11 +206,11 @@
module dffs(
output reg Q,
- input D,
+ input wire D,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
- input C,
- input S
+ input wire C,
+ input wire S
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
@@ -231,12 +233,12 @@
module dffse(
output reg Q,
- input D,
+ input wire D,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
- input C,
- input S,
- input E
+ input wire C,
+ input wire S,
+ input wire E
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
@@ -259,12 +261,12 @@
module dffsr(
output reg Q,
- input D,
+ input wire D,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
- input C,
- input R,
- input S
+ input wire C,
+ input wire R,
+ input wire S
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
@@ -291,12 +293,12 @@
module dffsre(
output reg Q,
- input D,
+ input wire D,
(* clkbuf_sink *)
- input C,
- input E,
- input R,
- input S
+ input wire C,
+ input wire E,
+ input wire R,
+ input wire S
);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
@@ -313,12 +315,12 @@
module dffnsre(
output reg Q,
- input D,
+ input wire D,
(* clkbuf_sink *)
- input C,
- input E,
- input R,
- input S
+ input wire C,
+ input wire E,
+ input wire R,
+ input wire S
);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
@@ -336,11 +338,11 @@
(* abc9_flop, lib_whitebox *)
module latchsre (
output reg Q,
- input S,
- input R,
- input D,
- input G,
- input E
+ input wire S,
+ input wire R,
+ input wire D,
+ input wire G,
+ input wire E
);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
@@ -358,11 +360,11 @@
(* abc9_flop, lib_whitebox *)
module latchnsre (
output reg Q,
- input S,
- input R,
- input D,
- input G,
- input E
+ input wire S,
+ input wire R,
+ input wire D,
+ input wire G,
+ input wire E
);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
@@ -380,8 +382,8 @@
(* abc9_flop, lib_whitebox *)
module scff(
output reg Q,
- input D,
- input clk
+ input wire D,
+ input wire clk
);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
@@ -392,29 +394,29 @@
module TDP_BRAM18 (
(* clkbuf_sink *)
- input CLOCKA,
+ input wire CLOCKA,
(* clkbuf_sink *)
- input CLOCKB,
- input READENABLEA,
- input READENABLEB,
- input [13:0] ADDRA,
- input [13:0] ADDRB,
- input [15:0] WRITEDATAA,
- input [15:0] WRITEDATAB,
- input [1:0] WRITEDATAAP,
- input [1:0] WRITEDATABP,
- input WRITEENABLEA,
- input WRITEENABLEB,
- input [1:0] BYTEENABLEA,
- input [1:0] BYTEENABLEB,
- //input [2:0] WRITEDATAWIDTHA,
- //input [2:0] WRITEDATAWIDTHB,
- //input [2:0] READDATAWIDTHA,
- //input [2:0] READDATAWIDTHB,
- output [15:0] READDATAA,
- output [15:0] READDATAB,
- output [1:0] READDATAAP,
- output [1:0] READDATABP
+ input wire CLOCKB,
+ input wire READENABLEA,
+ input wire READENABLEB,
+ input wire [13:0] ADDRA,
+ input wire [13:0] ADDRB,
+ input wire [15:0] WRITEDATAA,
+ input wire [15:0] WRITEDATAB,
+ input wire [1:0] WRITEDATAAP,
+ input wire [1:0] WRITEDATABP,
+ input wire WRITEENABLEA,
+ input wire WRITEENABLEB,
+ input wire [1:0] BYTEENABLEA,
+ input wire [1:0] BYTEENABLEB,
+ //input wire [2:0] WRITEDATAWIDTHA,
+ //input wire [2:0] WRITEDATAWIDTHB,
+ //input wire [2:0] READDATAWIDTHA,
+ //input wire [2:0] READDATAWIDTHB,
+ output wire [15:0] READDATAA,
+ output wire [15:0] READDATAB,
+ output wire [1:0] READDATAAP,
+ output wire [1:0] READDATABP
);
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
@@ -495,7 +497,6 @@
endmodule
-`default_nettype wire
module TDP36K (
RESET_ni,
WEN_A1_i,
@@ -705,7 +706,7 @@
parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- input RESET_ni;
+ input wire RESET_ni;
input wire WEN_A1_i;
input wire WEN_B1_i;
input wire REN_A1_i;
@@ -1153,50 +1154,49 @@
.FMODE_i(ram_fmode2)
);
endmodule
-`default_nettype none
(* blackbox *)
module QL_DSP1 (
- input [19:0] a,
- input [17:0] b,
+ input wire [19:0] a,
+ input wire [17:0] b,
(* clkbuf_sink *)
- input clk0,
+ input wire clk0,
(* clkbuf_sink *)
- input clk1,
- input [ 1:0] feedback0,
- input [ 1:0] feedback1,
- input load_acc0,
- input load_acc1,
- input reset0,
- input reset1,
+ input wire clk1,
+ input wire [ 1:0] feedback0,
+ input wire [ 1:0] feedback1,
+ input wire load_acc0,
+ input wire load_acc1,
+ input wire reset0,
+ input wire reset1,
output reg [37:0] z
);
parameter MODE_BITS = 27'b00000000000000000000000000;
endmodule /* QL_DSP1 */
module QL_DSP2 ( // TODO: Name subject to change
- input [19:0] a,
- input [17:0] b,
- input [ 5:0] acc_fir,
- output [37:0] z,
- output [17:0] dly_b,
+ input wire [19:0] a,
+ input wire [17:0] b,
+ input wire [ 5:0] acc_fir,
+ output wire [37:0] z,
+ output wire [17:0] dly_b,
(* clkbuf_sink *)
- input clk,
- input reset,
+ input wire clk,
+ input wire reset,
- input [2:0] feedback,
- input load_acc,
- input unsigned_a,
- input unsigned_b,
+ input wire [2:0] feedback,
+ input wire load_acc,
+ input wire unsigned_a,
+ input wire unsigned_b,
- input f_mode,
- input [2:0] output_select,
- input saturate_enable,
- input [5:0] shift_right,
- input round,
- input subtract,
- input register_inputs
+ input wire f_mode,
+ input wire [2:0] output_select,
+ input wire saturate_enable,
+ input wire [5:0] shift_right,
+ input wire round,
+ input wire subtract,
+ input wire register_inputs
);
parameter [79:0] MODE_BITS = 80'd0;
@@ -1331,31 +1331,31 @@
parameter NBITS_B = 18,
parameter NBITS_Z = 38
)(
- input [NBITS_A-1:0] a_i,
- input [NBITS_B-1:0] b_i,
- output [NBITS_Z-1:0] z_o,
- output reg [NBITS_B-1:0] dly_b_o,
+ input wire [NBITS_A-1:0] a_i,
+ input wire [NBITS_B-1:0] b_i,
+ output wire [NBITS_Z-1:0] z_o,
+ output reg [NBITS_B-1:0] dly_b_o,
- input [5:0] acc_fir_i,
- input [2:0] feedback_i,
- input load_acc_i,
+ input wire [5:0] acc_fir_i,
+ input wire [2:0] feedback_i,
+ input wire load_acc_i,
- input unsigned_a_i,
- input unsigned_b_i,
+ input wire unsigned_a_i,
+ input wire unsigned_b_i,
- input clock_i,
- input s_reset,
+ input wire clock_i,
+ input wire s_reset,
- input saturate_enable_i,
- input [2:0] output_select_i,
- input round_i,
- input [5:0] shift_right_i,
- input subtract_i,
- input register_inputs_i,
- input [NBITS_A-1:0] coef_0_i,
- input [NBITS_A-1:0] coef_1_i,
- input [NBITS_A-1:0] coef_2_i,
- input [NBITS_A-1:0] coef_3_i
+ input wire saturate_enable_i,
+ input wire [2:0] output_select_i,
+ input wire round_i,
+ input wire [5:0] shift_right_i,
+ input wire subtract_i,
+ input wire register_inputs_i,
+ input wire [NBITS_A-1:0] coef_0_i,
+ input wire [NBITS_A-1:0] coef_1_i,
+ input wire [NBITS_A-1:0] coef_2_i,
+ input wire [NBITS_A-1:0] coef_3_i
);
// FIXME: The version of Icarus Verilog from Conda seems not to recognize the
@@ -1559,27 +1559,27 @@
endmodule
module dsp_t1_20x18x64 (
- input [19:0] a_i,
- input [17:0] b_i,
- input [ 5:0] acc_fir_i,
- output [37:0] z_o,
- output [17:0] dly_b_o,
+ input wire [19:0] a_i,
+ input wire [17:0] b_i,
+ input wire [ 5:0] acc_fir_i,
+ output wire [37:0] z_o,
+ output wire [17:0] dly_b_o,
(* clkbuf_sink *)
- input clock_i,
- input reset_i,
+ input wire clock_i,
+ input wire reset_i,
- input [2:0] feedback_i,
- input load_acc_i,
- input unsigned_a_i,
- input unsigned_b_i,
+ input wire [ 2:0] feedback_i,
+ input wire load_acc_i,
+ input wire unsigned_a_i,
+ input wire unsigned_b_i,
- input [2:0] output_select_i,
- input saturate_enable_i,
- input [5:0] shift_right_i,
- input round_i,
- input subtract_i,
- input register_inputs_i
+ input wire [ 2:0] output_select_i,
+ input wire saturate_enable_i,
+ input wire [ 5:0] shift_right_i,
+ input wire round_i,
+ input wire subtract_i,
+ input wire register_inputs_i
);
parameter [19:0] COEFF_0 = 20'd0;
@@ -1617,27 +1617,27 @@
endmodule
module dsp_t1_10x9x32 (
- input [ 9:0] a_i,
- input [ 8:0] b_i,
- input [ 5:0] acc_fir_i,
- output [18:0] z_o,
- output [ 8:0] dly_b_o,
+ input wire [ 9:0] a_i,
+ input wire [ 8:0] b_i,
+ input wire [ 5:0] acc_fir_i,
+ output wire [18:0] z_o,
+ output wire [ 8:0] dly_b_o,
(* clkbuf_sink *)
- input clock_i,
- input reset_i,
+ input wire clock_i,
+ input wire reset_i,
- input [2:0] feedback_i,
- input load_acc_i,
- input unsigned_a_i,
- input unsigned_b_i,
+ input wire [ 2:0] feedback_i,
+ input wire load_acc_i,
+ input wire unsigned_a_i,
+ input wire unsigned_b_i,
- input [2:0] output_select_i,
- input saturate_enable_i,
- input [5:0] shift_right_i,
- input round_i,
- input subtract_i,
- input register_inputs_i
+ input wire [ 2:0] output_select_i,
+ input wire saturate_enable_i,
+ input wire [ 5:0] shift_right_i,
+ input wire round_i,
+ input wire subtract_i,
+ input wire register_inputs_i
);
parameter [9:0] COEFF_0 = 10'd0;
diff --git a/systemverilog-plugin/UhdmAst.cc b/systemverilog-plugin/UhdmAst.cc
index 5d08bb7..978fde5 100644
--- a/systemverilog-plugin/UhdmAst.cc
+++ b/systemverilog-plugin/UhdmAst.cc
@@ -972,7 +972,7 @@
AST_INTERNAL::current_ast_mod = nullptr;
}
-static void mark_as_unsigned(AST::AstNode *node)
+static void mark_as_unsigned(AST::AstNode *node, const UHDM::BaseClass *object)
{
if (node->children.empty() || node->children.size() == 1) {
node->is_signed = false;
@@ -980,7 +980,7 @@
node->children[0]->is_signed = false;
node->children[1]->is_signed = false;
} else {
- log_error("Unsupported expression in mark_as_unsigned!\n");
+ log_error("%s:%d: Unsupported expression in mark_as_unsigned!\n", object->VpiFile().c_str(), object->VpiLineNo());
}
}
@@ -1717,6 +1717,18 @@
shared.report.mark_handled(typespec_h);
break;
}
+ case vpiByteTypespec: {
+ current_node->is_signed = true;
+ packed_ranges.push_back(make_range(7, 0));
+ shared.report.mark_handled(typespec_h);
+ break;
+ }
+ case vpiShortIntTypespec: {
+ current_node->is_signed = true;
+ packed_ranges.push_back(make_range(15, 0));
+ shared.report.mark_handled(typespec_h);
+ break;
+ }
case vpiIntTypespec:
case vpiIntegerTypespec: {
current_node->is_signed = true;
@@ -2166,7 +2178,7 @@
add_multirange_wire(current_node, packed_ranges, unpacked_ranges);
}
-void UhdmAst::process_array_net()
+void UhdmAst::process_array_net(const UHDM::BaseClass *object)
{
current_node = make_ast_node(AST::AST_WIRE);
vpiHandle itr = vpi_iterate(vpiNet, obj_h);
@@ -2177,7 +2189,16 @@
if (net_type == vpiLogicNet) {
current_node->is_logic = true;
current_node->is_signed = vpi_get(vpiSigned, net_h);
- visit_one_to_many({vpiRange}, net_h, [&](AST::AstNode *node) { packed_ranges.push_back(node); });
+ vpiHandle typespec_h = vpi_handle(vpiTypespec, net_h);
+ if (!typespec_h) {
+ typespec_h = vpi_handle(vpiTypespec, obj_h);
+ }
+ if (typespec_h) {
+ visit_one_to_many({vpiRange}, typespec_h, [&](AST::AstNode *node) { packed_ranges.push_back(node); });
+ vpi_release_handle(typespec_h);
+ } else {
+ visit_one_to_many({vpiRange}, net_h, [&](AST::AstNode *node) { packed_ranges.push_back(node); });
+ }
shared.report.mark_handled(net_h);
} else if (net_type == vpiStructNet) {
visit_one_to_one({vpiTypespec}, net_h, [&](AST::AstNode *node) {
@@ -2417,7 +2438,7 @@
});
}
-void UhdmAst::process_operation()
+void UhdmAst::process_operation(const UHDM::BaseClass *object)
{
auto operation = vpi_get(vpiOpType, obj_h);
switch (operation) {
@@ -2437,6 +2458,11 @@
case vpiAssignmentPatternOp:
process_assignment_pattern_op();
break;
+ case vpiWildEqOp:
+ case vpiWildNeqOp: {
+ report_error("%s:%d: Wildcard operators are not supported yet\n", object->VpiFile().c_str(), object->VpiLineNo());
+ break;
+ }
default: {
current_node = make_ast_node(AST::AST_NONE);
visit_one_to_many({vpiOperand}, obj_h, [&](AST::AstNode *node) {
@@ -2499,12 +2525,12 @@
case vpiLShiftOp:
current_node->type = AST::AST_SHIFT_LEFT;
log_assert(current_node->children.size() == 2);
- mark_as_unsigned(current_node->children[1]);
+ mark_as_unsigned(current_node->children[1], object);
break;
case vpiRShiftOp:
current_node->type = AST::AST_SHIFT_RIGHT;
log_assert(current_node->children.size() == 2);
- mark_as_unsigned(current_node->children[1]);
+ mark_as_unsigned(current_node->children[1], object);
break;
case vpiNotOp:
current_node->type = AST::AST_LOGIC_NOT;
@@ -2560,17 +2586,21 @@
case vpiArithLShiftOp:
current_node->type = AST::AST_SHIFT_SLEFT;
log_assert(current_node->children.size() == 2);
- mark_as_unsigned(current_node->children[1]);
+ mark_as_unsigned(current_node->children[1], object);
break;
case vpiArithRShiftOp:
current_node->type = AST::AST_SHIFT_SRIGHT;
log_assert(current_node->children.size() == 2);
- mark_as_unsigned(current_node->children[1]);
+ mark_as_unsigned(current_node->children[1], object);
break;
case vpiPowerOp:
current_node->type = AST::AST_POW;
break;
- case vpiPostIncOp: // TODO: Make this an actual post-increment op (currently it's a pre-increment)
+ case vpiPostIncOp: {
+ // TODO: Make this an actual post-increment op (currently it's a pre-increment)
+ log_warning("%s:%d: Post-incrementation operations are handled as pre-incrementation.\n", object->VpiFile().c_str(), object->VpiLineNo());
+ [[fallthrough]];
+ }
case vpiPreIncOp: {
current_node->type = AST::AST_ASSIGN_EQ;
auto id = current_node->children[0]->clone();
@@ -2580,7 +2610,11 @@
current_node->children.push_back(add_node);
break;
}
- case vpiPostDecOp: // TODO: Make this an actual post-decrement op (currently it's a pre-decrement)
+ case vpiPostDecOp: {
+ // TODO: Make this an actual post-decrement op (currently it's a pre-decrement)
+ log_warning("%s:%d: Post-decrementation operations are handled as pre-decrementation.\n", object->VpiFile().c_str(), object->VpiLineNo());
+ [[fallthrough]];
+ }
case vpiPreDecOp: {
current_node->type = AST::AST_ASSIGN_EQ;
auto id = current_node->children[0]->clone();
@@ -2628,8 +2662,6 @@
default: {
delete current_node;
current_node = nullptr;
- const uhdm_handle *const handle = (const uhdm_handle *)obj_h;
- const UHDM::BaseClass *const object = (const UHDM::BaseClass *)handle->object;
report_error("%s:%d: Encountered unhandled operation type %d\n", object->VpiFile().c_str(), object->VpiLineNo(), operation);
}
}
@@ -3005,16 +3037,17 @@
}
});
- visit_one_to_many({vpiParamAssign, vpiParameter, vpiNet, vpiArrayNet, vpiVariables, vpiContAssign, vpiProcess, vpiModule, vpiGenScopeArray},
- obj_h, [&](AST::AstNode *node) {
- if (node) {
- if ((node->type == AST::AST_PARAMETER || node->type == AST::AST_LOCALPARAM) && node->children.empty()) {
- delete node; // skip parameters without any children
- } else {
- current_node->children.push_back(node);
- }
- }
- });
+ visit_one_to_many(
+ {vpiParamAssign, vpiParameter, vpiNet, vpiArrayNet, vpiVariables, vpiContAssign, vpiProcess, vpiModule, vpiGenScopeArray, vpiTaskFunc}, obj_h,
+ [&](AST::AstNode *node) {
+ if (node) {
+ if ((node->type == AST::AST_PARAMETER || node->type == AST::AST_LOCALPARAM) && node->children.empty()) {
+ delete node; // skip parameters without any children
+ } else {
+ current_node->children.push_back(node);
+ }
+ }
+ });
}
void UhdmAst::process_case()
@@ -3027,11 +3060,28 @@
void UhdmAst::process_case_item()
{
current_node = make_ast_node(AST::AST_COND);
- visit_one_to_many({vpiExpr}, obj_h, [&](AST::AstNode *node) {
- if (node) {
- current_node->children.push_back(node);
+ vpiHandle itr = vpi_iterate(vpiExpr, obj_h);
+ while (vpiHandle expr_h = vpi_scan(itr)) {
+ // case ... inside statement, the operation is stored in UHDM inside case items
+ // Retrieve just the InsideOp arguments here, we don't add any special handling
+ // TODO: handle inside range (list operations) properly here
+ if (vpi_get(vpiType, expr_h) == vpiOperation && vpi_get(vpiOpType, expr_h) == vpiInsideOp) {
+ visit_one_to_many({vpiOperand}, expr_h, [&](AST::AstNode *node) {
+ if (node) {
+ current_node->children.push_back(node);
+ }
+ });
+ } else {
+ UhdmAst uhdm_ast(this, shared, indent + " ");
+ auto *node = uhdm_ast.process_object(expr_h);
+ if (node) {
+ current_node->children.push_back(node);
+ }
}
- });
+ // FIXME: If we release the handle here, visiting vpiStmt fails for some reason
+ // vpi_release_handle(expr_h);
+ }
+ vpi_release_handle(itr);
if (current_node->children.empty()) {
current_node->children.push_back(new AST::AstNode(AST::AST_DEFAULT));
}
@@ -3232,7 +3282,13 @@
}
delete node;
});
- visit_one_to_many({vpiRange}, obj_h, [&](AST::AstNode *node) { packed_ranges.push_back(node); });
+ // TODO: Handling below seems similar to other typespec accesses for range. Candidate for extraction to a function.
+ if (auto typespec_h = vpi_handle(vpiTypespec, obj_h)) {
+ visit_one_to_many({vpiRange}, typespec_h, [&](AST::AstNode *node) { packed_ranges.push_back(node); });
+ vpi_release_handle(typespec_h);
+ } else {
+ visit_one_to_many({vpiRange}, obj_h, [&](AST::AstNode *node) { packed_ranges.push_back(node); });
+ }
visit_default_expr(obj_h);
add_multirange_wire(current_node, packed_ranges, unpacked_ranges);
}
@@ -3344,14 +3400,41 @@
std::vector<AST::AstNode *> packed_ranges; // comes before wire name
std::vector<AST::AstNode *> unpacked_ranges; // comes after wire name
current_node = make_ast_node(AST::AST_WIRE);
- auto left_const = AST::AstNode::mkconst_int(31, true);
- auto right_const = AST::AstNode::mkconst_int(0, true);
- auto range = new AST::AstNode(AST::AST_RANGE, left_const, right_const);
- packed_ranges.push_back(range);
+ packed_ranges.push_back(make_range(31, 0));
add_multirange_wire(current_node, packed_ranges, unpacked_ranges);
current_node->is_signed = true;
}
+void UhdmAst::process_shortint_typespec()
+{
+ std::vector<AST::AstNode *> packed_ranges; // comes before wire name
+ std::vector<AST::AstNode *> unpacked_ranges; // comes after wire name
+ current_node = make_ast_node(AST::AST_WIRE);
+ packed_ranges.push_back(make_range(15, 0));
+ add_multirange_wire(current_node, packed_ranges, unpacked_ranges);
+ current_node->is_signed = true;
+}
+
+void UhdmAst::process_byte_typespec()
+{
+ std::vector<AST::AstNode *> packed_ranges; // comes before wire name
+ std::vector<AST::AstNode *> unpacked_ranges; // comes after wire name
+ current_node = make_ast_node(AST::AST_WIRE);
+ packed_ranges.push_back(make_range(7, 0));
+ add_multirange_wire(current_node, packed_ranges, unpacked_ranges);
+ current_node->is_signed = true;
+}
+
+void UhdmAst::process_time_typespec()
+{
+ std::vector<AST::AstNode *> packed_ranges; // comes before wire name
+ std::vector<AST::AstNode *> unpacked_ranges; // comes after wire name
+ current_node = make_ast_node(AST::AST_WIRE);
+ packed_ranges.push_back(make_range(63, 0));
+ add_multirange_wire(current_node, packed_ranges, unpacked_ranges);
+ current_node->is_signed = false;
+}
+
void UhdmAst::process_string_var()
{
current_node = make_ast_node(AST::AST_WIRE);
@@ -3577,7 +3660,7 @@
current_node->is_logic = !current_node->is_reg;
current_node->is_signed = vpi_get(vpiSigned, obj_h);
visit_one_to_one({vpiTypespec}, obj_h, [&](AST::AstNode *node) {
- if (node) {
+ if (node && !node->str.empty()) {
auto wiretype_node = new AST::AstNode(AST::AST_WIRETYPE);
wiretype_node->str = node->str;
// wiretype needs to be 1st node
@@ -3585,7 +3668,10 @@
current_node->is_custom_type = true;
}
});
- visit_one_to_many({vpiRange}, obj_h, [&](AST::AstNode *node) { packed_ranges.push_back(node); });
+ if (vpiHandle typespec_h = vpi_handle(vpiTypespec, obj_h)) {
+ visit_one_to_many({vpiRange}, typespec_h, [&](AST::AstNode *node) { packed_ranges.push_back(node); });
+ vpi_release_handle(typespec_h);
+ }
add_multirange_wire(current_node, packed_ranges, unpacked_ranges);
}
@@ -3611,6 +3697,11 @@
shared.report.mark_handled(typespec_h);
break;
}
+ case vpiByteTypespec: {
+ packed_ranges.push_back(make_range(7, 0));
+ shared.report.mark_handled(typespec_h);
+ break;
+ }
case vpiEnumTypespec:
case vpiRealTypespec:
case vpiStringTypespec: {
@@ -3625,9 +3716,11 @@
}
case vpiStructTypespec: {
visit_one_to_one({vpiTypespec}, obj_h, [&](AST::AstNode *node) {
- auto wiretype_node = make_ast_node(AST::AST_WIRETYPE);
- wiretype_node->str = node->str;
- current_node->children.push_back(wiretype_node);
+ if (node && !node->str.empty()) {
+ auto wiretype_node = make_ast_node(AST::AST_WIRETYPE);
+ wiretype_node->str = node->str;
+ current_node->children.push_back(wiretype_node);
+ }
current_node->is_custom_type = true;
auto it = shared.param_types.find(current_node->str);
if (it == shared.param_types.end())
@@ -3635,6 +3728,7 @@
});
break;
}
+ case vpiPackedArrayTypespec:
case vpiArrayTypespec: {
shared.report.mark_handled(typespec_h);
visit_one_to_one({vpiElemTypespec}, typespec_h, [&](AST::AstNode *node) {
@@ -3859,7 +3953,7 @@
process_net();
break;
case vpiArrayNet:
- process_array_net();
+ process_array_net(object);
break;
case vpiPackedArrayNet:
process_packed_array_net();
@@ -3895,7 +3989,7 @@
break;
case vpiCondition:
case vpiOperation:
- process_operation();
+ process_operation(object);
break;
case vpiTaggedPattern:
process_tagged_pattern();
@@ -3968,7 +4062,7 @@
case vpiHierPath:
process_hier_path();
break;
- case UHDM::uhdmimport:
+ case UHDM::uhdmimport_typespec:
break;
case vpiDelayControl:
process_nonsynthesizable(object);
@@ -3980,9 +4074,18 @@
case vpiIntegerTypespec:
process_int_typespec();
break;
+ case vpiShortIntTypespec:
+ process_shortint_typespec();
+ break;
+ case vpiTimeTypespec:
+ process_time_typespec();
+ break;
case vpiBitTypespec:
process_bit_typespec();
break;
+ case vpiByteTypespec:
+ process_byte_typespec();
+ break;
case vpiStringVar:
process_string_var();
break;
diff --git a/systemverilog-plugin/UhdmAst.h b/systemverilog-plugin/UhdmAst.h
index 8cc5338..0314369 100644
--- a/systemverilog-plugin/UhdmAst.h
+++ b/systemverilog-plugin/UhdmAst.h
@@ -90,7 +90,7 @@
void process_assignment();
void process_net();
void process_packed_array_net();
- void process_array_net();
+ void process_array_net(const UHDM::BaseClass *object);
void process_package();
void process_interface();
void process_modport();
@@ -99,7 +99,7 @@
void process_event_control(const UHDM::BaseClass *object);
void process_initial();
void process_begin(bool is_named);
- void process_operation();
+ void process_operation(const UHDM::BaseClass *object);
void process_stream_op();
void process_list_op();
void process_cast_op();
@@ -126,11 +126,14 @@
void process_hier_path();
void process_logic_typespec();
void process_int_typespec();
+ void process_shortint_typespec();
+ void process_time_typespec();
void process_bit_typespec();
void process_string_var();
void process_string_typespec();
void process_repeat();
void process_byte_var();
+ void process_byte_typespec();
void process_long_int_var();
void process_immediate_cover();
void process_immediate_assume();
diff --git a/systemverilog-plugin/uhdmsurelogastfrontend.cc b/systemverilog-plugin/uhdmsurelogastfrontend.cc
index bec697f..4a450be 100644
--- a/systemverilog-plugin/uhdmsurelogastfrontend.cc
+++ b/systemverilog-plugin/uhdmsurelogastfrontend.cc
@@ -30,8 +30,8 @@
#include <unistd.h>
#endif
-#include "ErrorReporting/Report.h"
-#include "surelog.h"
+#include "Surelog/ErrorReporting/Report.h"
+#include "Surelog/surelog.h"
namespace UHDM
{
